JP2013222960A - Structure of via hole of electrical circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a structure of a via hole of an electrical circuit board.SOLUTION: A structure of a via hole of an electrical circuit board comprises: an adhesive layer and a conductor layer that are formed after wiring is formed on a carrier board. At least one through hole extends in a vertical direction through the carrier board, the wiring, the adhesive layer, and the conductor layer and forms a hole wall surface. The conductor layer shows a height difference with respect to an exposed zone of a circuit trace in the vertical direction. A conductive cover section covers the conductor layer and the hole wall surface of the through hole. The carrier board is a single-sided board, a double-sided board, a multi-layered board, or a combination thereof, and the single-sided board, the double-sided board, and the multi-layered board can be flexible boards, rigid boards, or composite boards combining flexible and rigid boards.

Description

  The present invention relates to the field of via holes in electrical circuit boards, and more particularly to the structure of via holes in electrical circuit boards.

  A printed circuit board (PCB) is an indispensable electronic component, is also a support body for the electronic device and the component, and plays a role of providing connection of wiring of the electronic component. A conventional circuit board is called a printed board or a printed wiring board because a circuit wiring and a pattern are produced by applying a process of printing an etching resist. Electronics products are becoming smaller and more sophisticated, and most of today's circuit boards are made by applying a resist (thin film or coating), then exposed and developed, then etched, The production of the substrate is completed.

  A process conventionally employed for producing a via hole in a circuit board is to first provide a carrier substrate having upper and lower copper foil layers and an adhesive layer. Next, drilling is performed and the conductive cover portion is electroplated. The carrier substrate is then coated with dry film, exposed, developed and etched to form a plurality of etched regions. Finally, a thin film is applied to the etched carrier substrate.

However, in a conventional process for producing a via hole in a circuit board, first a hole is drilled and then electroplating and etching are performed. The flow of processing is simple, but often suffers from the following disadvantages.
(1) The thickness of the carrier substrate is not uniform, and therefore the yield rate of fine wiring processing is deteriorated.
(2) Impurities may be generated in the electroplating process, which decreases the yield rate of image transfer and etching.
(3) The size stability of the carrier substrate is deteriorated, so that the alignment of exposure becomes inaccurate.
(4) The structure of the carrier substrate can be changed, and the flexibility tends to decrease.
As a result, further improvements can be made to the known processes for making circuit board via hole structures.

  In view of the above, a first object of the present invention is to provide a via hole structure of an electric circuit board.

Compared with the conventional manufacturing process related to the via hole of the electric circuit board, the present invention has the following advantages.
(1) Since the etching is directly performed on the raw material, the yield rate is greatly improved.
(2) The problem of impurities does not occur at all in the manufacturing process.
(3) The material used is excellent in stability.
(4) Except for the structural change of the via hole plating region, the material of the substrate is not significantly changed.
(5) The density of circuit traces on the substrate is increased.

It is sectional drawing which shows the structure of the via hole of the electric circuit board | substrate by 1st Embodiment of this invention in a different step of a manufacturing process. It is sectional drawing which shows the structure of the via hole of the electric circuit board | substrate by 1st Embodiment of this invention in a different step of a manufacturing process. It is sectional drawing which shows the structure of the via hole of the electric circuit board | substrate by 1st Embodiment of this invention in a different step of a manufacturing process. It is sectional drawing which shows the structure of the via hole of the electric circuit board | substrate by 1st Embodiment of this invention in a different step of a manufacturing process. It is sectional drawing which shows the structure of the via hole of the electric circuit board | substrate by 1st Embodiment of this invention in a different step of a manufacturing process. 1 is a cross-sectional view of a first embodiment of the present invention after fully assembled. FIG. It is sectional drawing which shows the carrier substrate by 2nd Embodiment of this invention. It is sectional drawing which shows the carrier substrate by 2nd Embodiment of this invention. It is sectional drawing which shows the carrier substrate by 2nd Embodiment of this invention. It is sectional drawing which shows the carrier substrate by 2nd Embodiment of this invention. It is sectional drawing which shows the carrier substrate by 2nd Embodiment of this invention. FIG. 6 is a cross-sectional view of a second embodiment of the present invention after it has been fully assembled. FIG. 6 is another cross-sectional view showing a second embodiment of the present invention after it is fully assembled. It is sectional drawing of the exploded form which shows the carrier substrate by 3rd Embodiment of this invention. FIG. 7 is an exploded sectional view showing a carrier substrate according to a fourth embodiment of the present invention. FIG. 7 is an exploded sectional view showing a carrier substrate according to a fifth embodiment of the present invention. It is sectional drawing of the exploded form which shows the carrier substrate by 6th Embodiment of this invention. It is sectional drawing of the exploded form which shows the carrier substrate by 7th Embodiment of this invention. FIG. 9 is a cross-sectional view showing a seventh embodiment of the present invention after it is fully assembled. It is sectional drawing of the exploded form which shows the carrier substrate by 8th Embodiment of this invention. It is sectional drawing of the exploded form which shows the carrier substrate by 9th Embodiment of this invention. It is sectional drawing of the exploded form which shows the carrier substrate by 10th Embodiment of this invention.

  With reference to the drawings, in particular FIGS. 1 to 6, the carrier substrate according to the first embodiment of the present invention, generally denoted by reference numeral 100, is a single-sided substrate. The first substrate 11 has a first substrate upper surface 11a and a first substrate lower surface 11b. At least one upper circuit trace 21 is formed on the first substrate upper surface 11a. Upper circuit traces 21 are separated by a separation area 210.

  The upper adhesive layer 31 is formed on the surface of the upper circuit trace 21. The upper adhesive layer 31 may completely cover the surface of the upper circuit trace 21 or may partially cover a partial region of the upper adhesive layer 31. The surface of the upper circuit trace 21 that is not covered by the upper adhesive layer 31 is defined as an upper circuit trace exposure area 211 and serves as an exposed contact for a surface mount device (SMD) or gold finger.

  The upper conductor layer 41 is formed on the surface of the upper adhesive layer 31. The upper conductor layer 41 shows a first height difference h1 (as shown in FIG. 3) in the vertical direction I with respect to the upper circuit trace exposure area 211 of the upper circuit trace 21. The lower conductor layer 42 is formed on the first substrate lower surface 11 b of the first substrate 11.

  As shown in FIG. 4, at least one through hole 5 extends in the vertical direction I through the upper conductor layer 41, the upper adhesive layer 31, the upper circuit trace 21, the first substrate 11, and the lower conductor layer 42. The through-hole wall surface 51 is formed.

  As shown in FIG. 5, the conductive cover 6 covers the upper surface of the upper conductor layer 41, the lower surface of the lower conductor layer 42, and the through hole wall surface 51 of the through hole 5. The conductive cover portion 6 may be formed by a process including dry film coating, exposure, development, and etching. The conductive cover portion 6 includes a conductive material selected from copper, silver, gold, or a combination thereof.

  As shown in FIG. 6, the portion of the conductive cover portion 6 excluding the portion adjacent to the through hole 5, the portion of the upper conductor layer 41 excluding the portion adjacent to the through hole 5, and the portion adjacent to the through hole 5 are excluded. The portion of the lower conductor layer 42 is removed by a known etching technique or left partially.

  The upper conductor layer 41, the upper circuit trace 21, and the lower conductor layer 42 are electrically connected to each other through the conductive cover portion 6.

  In the present embodiment, the first substrate 11 is a single-sided substrate that serves as a carrier substrate. Instead, the carrier substrate is a combination of a single-sided substrate and a single-sided substrate, a combination of a single-sided substrate and a double-sided substrate, a double-sided substrate, It can be realized with a combination of double-sided substrates and multilayer substrates.

  Please refer to FIG. 7 to FIG. The carrier substrate according to the second embodiment of the present invention, generally represented by reference numeral 200, is a double-sided substrate.

  As shown in FIG. 7, the first double-sided board 12 has a double-sided board upper surface 12a and a double-sided board lower surface 12b, and each forms at least one upper circuit trace 21 and at least one lower circuit trace 22. To do. Upper circuit trace 21 is spaced apart by spaced area 210 and lower circuit trace 22 is spaced by spaced area 220. Upper circuit trace 21 includes at least one upper circuit trace exposure area 211, and lower circuit trace 22 optionally includes at least one lower circuit trace exposure area 221.

  As shown in FIGS. 8 and 9, the upper adhesive layer 31 is formed on the surface of the upper circuit trace 21. The lower adhesive layer 32 is formed on the surface of the lower circuit trace 22. The upper conductor layer 41 is formed on the surface of the upper adhesive layer 31. The upper conductor layer 41 exhibits a first height difference h <b> 1 in the vertical direction I with respect to the upper circuit trace exposure area 211 of the upper circuit trace 21.

  The lower conductor layer 42 is formed on the surface of the lower adhesive layer 32. The lower conductor layer 42 exhibits a second height difference h <b> 2 in the vertical direction I with respect to the lower circuit trace exposure area 221 of the lower circuit trace 22.

  As shown in FIG. 10, at least one through hole 5 has an upper conductor layer 41, an upper adhesive layer 31, an upper circuit trace 21, a first double-sided substrate 12, a lower circuit trace 22, and a lower adhesive layer in the vertical direction I. 32, extending through the lower conductor layer 42. The through hole 5 forms a through hole wall surface 51.

  As shown in FIG. 11, the conductive cover 6 covers the upper surface of the upper conductor layer 41, the lower surface of the lower conductor layer 42, and the through hole wall surface 51 of the through hole 5.

  As shown in FIG. 12, the portion of the conductive cover portion 6 excluding the portion adjacent to the through hole 5 and the portion of the upper conductor layer 41 excluding the portion adjacent to the through hole 5 are removed by a known etching technique. Or partially remains.

  As shown in FIG. 13, the portion of the conductive cover portion 6 excluding the portion adjacent to the through hole 5 and the portion of the lower conductor layer 42 excluding the portion adjacent to the through hole 5 are removed by a known etching technique. Or partially remains.

FIG. 14 is a cross-sectional view illustrating a carrier substrate according to a third embodiment of the present invention, including two single-sided substrates, generally indicated by reference numeral 300. As shown in the drawing, the carrier substrate 300 includes at least one first substrate 11 having a first substrate upper surface 11a and a first substrate lower surface 11b, and at least one upper circuit trace 21 is formed on the first substrate upper surface 11a. Formed on top. At least one second substrate 13 has a second substrate upper surface 13a and a second substrate lower surface 13b, and the second substrate upper surface 13a is bonded to the first substrate lower surface 11b of the first substrate 11 by an adhesive layer 71. The At least one lower circuit trace 22 is formed on the second substrate lower surface 13b. The adhesive layer 71 exhibits physical properties of adhesion and insulation.
The carrier substrate 300 of the third embodiment can be replaced with the carrier substrate 100 of the first embodiment, and the manufacturing processes described in FIGS. 2 to 6 are applied to the carrier substrate of the third embodiment and 2 It is possible to form an electric circuit board via-hole structure composed of a single-sided board.

  FIG. 15 is a cross-sectional view illustrating a carrier substrate according to a fourth embodiment of the present invention that includes three single-sided substrates, generally designated by the reference numeral 400. The general structure of the fourth embodiment is the same as that of FIG. 14, but at least one third substrate 14 and adhesive layers 71 and 72 are formed on the second substrate upper surface 13 a of the second substrate 13 and the first substrate 13. The substrate 11 is disposed between the first substrate lower surface 11b. The third substrate 14 has a surface on which at least one intermediate circuit trace 23 is formed.

FIG. 16 is a cross-sectional view illustrating a carrier substrate according to a fifth embodiment of the present invention, including two single-sided substrates and one double-sided substrate, generally designated by the reference numeral 500.
The carrier substrate of the fifth embodiment includes a first substrate 11 having a first substrate upper surface 11a and a first substrate lower surface 11b, and at least one upper circuit trace 21 is formed on the first substrate upper surface 11a. The second substrate 13 has a second substrate upper surface 13a and a second substrate lower surface 13b, and at least one lower circuit trace 22 is formed on the second substrate lower surface 13b.

  At least one first double-sided substrate 12 is disposed between the second substrate upper surface 13 a of the second substrate 13 and the first substrate lower surface 11 b of the first substrate 11. The first double-sided substrate 12 has a double-sided substrate upper surface 12a and a double-sided substrate lower surface 12b, and at least one intermediate circuit trace 23a, 23b is formed on each of these surfaces. The double-sided substrate upper surface 12a is bonded to the first substrate lower surface 11b of the first substrate 11 by the adhesive layer 71, and the first double-sided substrate 12b is bonded to the second substrate upper surface 13a of the second substrate 13 by the adhesive layer 72. The

FIG. 17 is a cross-sectional view illustrating a carrier substrate according to a sixth embodiment of the present invention, including a single-sided substrate and a single-sided double-sided substrate, generally designated by the reference numeral 600. The carrier substrate of the sixth embodiment includes a first substrate 11 having a first substrate upper surface 11a and a first substrate lower surface 11b, and at least one upper circuit trace 21 is formed on the first substrate upper surface 11a.
At least one first double-sided substrate 12 has a double-sided substrate upper surface 12a and a double-sided substrate lower surface 12b. The double-sided substrate upper surface 12 a is bonded to the first substrate lower surface 11 b of the first substrate 11 by the adhesive layer 71. At least one lower circuit trace 22 is formed on the double-sided board lower surface 12b. At least one intermediate circuit trace 23 is formed on the double-sided board upper surface 12 a of the first double-sided board 12.

FIG. 18 is a cross-sectional view illustrating a carrier substrate according to a seventh embodiment of the present invention, including two double-sided substrates, generally designated by the reference numeral 700, and FIG. 19 is the first view after fully assembled. It is sectional drawing which shows 7 embodiment. The carrier substrate 700 includes a first double-sided substrate 12 having a double-sided substrate upper surface 12a and a double-sided substrate lower surface 12b, and at least one upper circuit trace 21 is formed on the double-sided substrate upper surface 12a. At least one second double-sided substrate 15 has a double-sided substrate upper surface 15a and a double-sided substrate lower surface 15b. The second double-sided substrate upper surface 15 a is bonded to the double-sided substrate lower surface 12 b of the first double-sided substrate 12 by the adhesive layer 71.
At least one lower circuit trace 22 is formed on the double-sided board lower surface 15 b of the second double-sided board 15. At least one first double-sided board intermediate circuit trace 23 c is formed on the double-sided board lower surface 12 b of the first double-sided board 12. At least one second double-sided board intermediate circuit trace 23 d is formed on the double-sided board upper surface 15 a of the second double-sided board 15.

  Refer to FIG. After the assembly, the upper adhesive layer 31 is formed on at least a partial region of the upper circuit trace 21 of the first double-sided substrate 12, and the portion of the upper circuit trace 21 that is not covered by the upper adhesive layer 31 is defined as the upper circuit trace exposure area 211. It is prescribed. The upper conductor layer 41 is formed on the upper surface of the upper adhesive layer 31. The upper conductor layer 41 exhibits a first height difference h <b> 1 in the vertical direction I with respect to the upper circuit trace exposure area 211.

  The lower adhesive layer 32 is formed on at least a partial region of the lower circuit trace 22 of the second double-sided substrate 15, and the portion of the lower circuit trace 22 that is not covered by the lower adhesive layer 32 is defined as the lower circuit trace exposure area 221. . The lower conductor layer 42 is formed on the lower surface of the lower adhesive layer 32. The lower conductor layer 42 exhibits a second height difference h <b> 2 with respect to the lower circuit trace exposure area 221 in the vertical direction I.

At least one through hole 5 is formed in the vertical direction I in the upper conductor layer 41, the upper adhesive layer 31, the upper circuit trace 21, the first double-sided board 12, the intermediate circuit trace 23c of the first double-sided board, the adhesive layer 71, the second layer. The through-hole wall surface 51 is formed by extending through the intermediate circuit trace 23d of the double-sided substrate, the second double-sided substrate 15, the lower circuit trace 22, the lower adhesive layer 32, and the lower conductor layer 42.
The conductive cover portion 6 includes a through hole wall surface 51 of the through hole 5, a partial region of the upper conductor layer 41 of the first double-sided substrate 12 adjacent to the through hole 5, and a lower conductor of the second double-sided substrate 15 adjacent to the through hole 5. A partial region of layer 42 is covered.

  In practical use, the through-hole 5 is selectively used as an upper circuit trace 21, a lower circuit trace 22, an intermediate circuit trace 23c on the first double-sided board, and an intermediate circuit trace 23d on the second double-sided board as desired. Can be electrically connected.

FIG. 20 is a cross-sectional view illustrating a carrier substrate according to an eighth embodiment of the present invention, including a single-sided substrate and a double-sided substrate, generally designated by the reference numeral 800. As shown in the drawings, the carrier substrate of the eighth embodiment includes at least one first substrate 11 and one first double-sided substrate 12. The first double-sided substrate 12 includes a buried hole 8.
The buried hole 8 has a structure similar to the structure of the through hole 5 shown in FIG. 13, but the buried hole 8 is formed in advance before bonding the first substrate 11 and the first double-sided substrate 12. Is done. The first double-sided substrate 12 has an upper surface that forms an upper circuit trace that serves as an intermediate circuit trace 24. The first double-sided substrate 12 has a lower surface that forms at least one lower circuit trace 22. The first substrate 11 has an upper surface 11 a that forms at least one upper circuit trace 21. The first double-sided substrate 12 and the first substrate 11 are bonded to each other by an adhesive layer 73.

  After the first substrate 11 and the first double-sided substrate 12 are bonded together by the adhesive layer 73, the manufacturing process as described above is performed at a position shifted from the embedded hole 8 in order to produce a through hole. Is done. As a result, the structure of the three-layer electric circuit board including the buried hole and the intermediate circuit trace layer is completed, and functions as a carrier substrate according to the present invention.

  In the present embodiment, in order to form the carrier substrate 800, the single-sided substrate is bonded to the double-sided substrate in which the embedded holes 8 are formed in advance by the adhesive layer 73. Therefore, the carrier substrate 800 may be replaced with the carrier substrate 100 of the first embodiment, and the manufacturing process described in FIGS. 2 to 6 may be performed at a position shifted from the embedded hole 8 of the first double-sided substrate 12. Good. Thereby, the structure of the via hole of the electric circuit board including the buried hole and the intermediate circuit trace layer is completed.

FIG. 21 is a cross-sectional view illustrating a carrier substrate according to a ninth embodiment of the present invention that includes two double-sided substrates, generally designated by the reference numeral 900. As shown in the drawings, the carrier substrate of the ninth embodiment includes at least two double-sided substrates 12 and 15 in which embedded holes 8a and 8b are previously formed, respectively.
The first double-sided board 12 has a double-sided board upper surface 12 a that forms at least one intermediate circuit trace 24. The double-sided board has a double-sided board lower surface 12 b that forms at least one lower circuit trace 22. The second double-sided substrate 15 has a double-sided substrate lower surface 15 b that forms at least one intermediate circuit trace 25 and a double-sided substrate upper surface 15 a that forms at least one upper circuit trace 21. The two double-sided substrates 12 and 15 are bonded to each other by the adhesive layer 74.

After the two double-sided boards 12 and 15 are bonded together by the adhesive layer 74, the manufacturing process relating to the through hole described above completes the structure of a four-layer electric circuit board having a buried hole and an intermediate circuit trace layer. In order to function as the carrier substrate of the present invention, it can be performed.
In the present embodiment, the two double-sided substrates 12 and 15 in which the embedding holes are formed in advance are bonded together by the adhesive layer 74 to form the carrier substrate 900. Accordingly, the carrier substrate 900 is replaced with the carrier substrate 100 of the first embodiment, and the manufacturing process described with reference to FIGS. 2 to 6 is completed to complete the via hole structure of the electric circuit substrate including the buried hole and the intermediate circuit trace layer. Thus, the position of the buried hole may be avoided.

  FIG. 22 is a cross-sectional view illustrating a carrier substrate according to a tenth embodiment of the present invention, including one double-sided substrate and two single-sided substrates, generally designated by reference numeral 901. As shown in the drawings, the carrier substrate of the tenth embodiment includes at least one first double-sided substrate 12 including a pre-formed buried hole 8. The first double-sided board 12 has a double-sided board upper surface 12 a and a double-sided board lower surface 12 b, and at least one intermediate circuit trace 24, 26 is formed on each of these surfaces, and the adhesive layers 75, 76 respectively. The first substrate 11 and the second substrate 13 are bonded. Both the first substrate 11 and the second substrate 13 are single-sided substrates. The first substrate 11 has an upper surface 11 a that forms at least one upper circuit trace 21, and the second substrate 13 has a lower surface 13 b that forms at least one lower circuit trace 22.

  After the first double-sided substrate 12 and the first substrate 11 and the second substrate 13 are bonded to each other by the adhesive layers 75 and 76, the manufacturing process described with reference to FIGS. In order to complete the structure of the four-layer electric circuit board including and to function as a carrier substrate according to the present invention, it is performed at a position avoiding the buried hole 8 of the first double-sided board 12.

  The following is understood from the above embodiment. In the present invention, one or a plurality of single-sided substrates and double-sided substrates or multilayer substrates are combined to form carrier substrates having various structures. The single-sided substrates, double-sided substrates, and multilayer substrates are flexible circuit boards, rigid circuit boards, In addition, a circuit board having different characteristics such as a composite board of a flexible board and a rigid board can be obtained. Various embodiments can also be made in accordance with the present invention, combining via hole structures and manufacturing processes.

Claims (19)

A first substrate comprising a single-sided substrate having a first substrate upper surface and a first substrate lower surface;
At least one upper circuit trace formed on the top surface of the first substrate;
An upper adhesive layer formed on at least a partial region of the upper circuit trace, wherein a portion of the upper circuit trace not covered by the upper adhesive layer forms an upper circuit trace exposure area; and
An upper conductor layer formed on the upper adhesive layer, wherein the upper conductor layer shows a first height difference with respect to the upper circuit trace exposure area in the longitudinal direction; and
A lower conductor layer formed on the lower surface of the first substrate;
At least one through hole extending in the vertical direction through the upper conductor layer, the upper adhesive layer, the upper circuit trace, the first substrate, the lower conductor layer, and forming a through hole wall surface;
A conductive cover portion covering the through hole wall surface of the through hole, a partial region of the upper conductor layer adjacent to the through hole, and a partial region of the lower conductor layer adjacent to the through hole;
Electric circuit board.   The lower conductor layer and the lower surface of the first substrate have a second substrate upper surface and a second substrate lower surface between them, and the second substrate upper surface is in the vertical direction, the first substrate of the first substrate. A second substrate bonded to a lower surface; at least one lower circuit trace formed on the lower surface of the second substrate; a lower adhesive layer formed on at least a partial region of the lower circuit trace; The lower conductor layer formed under the adhesive layer, the second substrate, the lower circuit trace, the lower adhesive layer, the through hole extending through the lower conductor layer, and the conductive cover portion The electric circuit board according to claim 1, further comprising: the through hole further covering a partial region of the lower conductor layer adjacent to the through hole.   The portion of the lower circuit trace not covered by the lower adhesive layer forms a lower circuit trace exposure area, and the lower conductor layer exhibits a second height difference with respect to the lower circuit trace exposure area in the longitudinal direction. The electric circuit board according to claim 2.   The lower surface of the first substrate of the first substrate and the upper surface of the second substrate of the second substrate include at least one third substrate including at least one intermediate circuit trace therebetween. The electric circuit board according to 1.   The electric circuit board according to claim 4, wherein the first board, the second board, and the third board are a flexible board, a rigid board, or a composite board in which a flexible board and a rigid board are combined.   The lower surface of the first substrate of the first substrate and the upper surface of the second substrate of the second substrate further include at least one first double-sided substrate therebetween, and the first double-sided substrate is a double-sided substrate. The electric circuit board according to claim 2, wherein the electric circuit board has an upper surface and a lower surface of the double-sided substrate, each of which forms an intermediate circuit trace, and the through hole extends through the first double-sided substrate.   The electric circuit board according to claim 6, wherein at least one embedded hole is formed in the first double-sided board at a position shifted from the through hole.   The first substrate lower surface of the first substrate is bonded to at least one double-sided substrate, the first double-sided substrate has a double-sided substrate upper surface and a double-sided substrate lower surface, and the lower circuit trace is the double-sided substrate lower surface. The electrical circuit board according to claim 1, wherein the electrical circuit board is formed on the upper surface of the double-sided board, wherein at least one intermediate circuit trace is formed, and the through-hole extends through the first double-sided board.   The electric circuit board according to claim 8, wherein at least one embedded hole is formed in the first double-sided board at a position shifted from the through hole.   The electric circuit board according to claim 8, wherein the first double-sided board is a flexible board, a rigid board, or a composite board in which a flexible board and a rigid board are combined. A first double-sided substrate having a first double-sided substrate upper surface and a first double-sided substrate lower surface;
At least one upper circuit trace formed on the upper surface of the first double-sided substrate;
An upper adhesive layer formed on at least a partial region of the upper circuit trace, wherein a portion of the upper circuit trace not covered by the upper adhesive layer forms an upper circuit trace exposure area; and
An upper conductor layer formed on the upper adhesive layer, wherein the upper conductor layer shows a first height difference with respect to the upper circuit trace exposure area in the longitudinal direction; and
At least one lower circuit trace formed on the lower surface of the first double-sided substrate;
A lower adhesive layer formed on at least a partial region of the lower circuit trace;
A lower conductor layer formed on the lower adhesive layer;
Extending in the vertical direction through the upper conductor layer, the adhesive layer, the upper circuit trace, the first double-sided substrate, the lower circuit trace, the lower adhesive layer, and the lower conductor layer to form a through-hole wall surface At least one through hole;
A conductive cover portion covering the through hole wall surface of the through hole, a partial region of the upper conductor layer adjacent to the through hole, and a partial region of the lower conductor layer adjacent to the through hole;
Electric circuit board.   The lower surface of the lower conductor layer of the first double-sided board is bonded to at least one second double-sided board by an adhesive layer, and each of the second double-sided boards has at least one upper circuit trace and one lower circuit trace. A double-sided board upper surface and a double-sided board lower surface forming a circuit trace, and an upper adhesive layer is formed on at least a partial region of the upper circuit trace, and a portion of the upper circuit trace not covered by the upper adhesive layer is Forming a circuit trace exposure area, the lower adhesive layer being formed on at least a partial region of the lower circuit trace, the upper conductor layer being formed on the upper adhesive layer, and the upper conductor layer being in the longitudinal direction; , Showing a first height difference with respect to the upper circuit trace exposure area, a lower conductor layer is formed on the lower adhesive layer, and the through hole is formed on the upper conductor layer of the second double-sided substrate, the upper Adhesive layer, said The circuit trace, the second double-sided board, the lower circuit trace, the lower adhesive layer, and the lower conductor layer extend through the conductive cover portion of the second double-sided board adjacent to the through hole. The electric circuit board according to claim 11, further covering a partial region of the lower conductor layer.   The electric circuit board according to claim 12, wherein at least one embedded hole is formed in the second double-sided board at a position shifted from the through hole.   The portion of the lower circuit trace of the second double-sided substrate not covered by the lower adhesive layer forms a lower circuit trace exposure area, and the lower conductor layer of the second double-sided substrate extends in the vertical direction in the lower circuit. The electric circuit board according to claim 12, wherein the electric circuit board exhibits a second height difference with respect to the trace exposure area.   The electric circuit board according to claim 12, wherein the first double-sided board and the second double-sided board are a flexible board, a rigid board, or a composite board in which a flexible board and a rigid board are combined. A first double-sided substrate having a first double-sided substrate upper surface and a first double-sided substrate lower surface;
At least one upper circuit trace formed on the upper surface of the first double-sided substrate;
An upper adhesive layer formed on at least a partial region of the upper circuit trace, wherein a portion of the upper circuit trace not covered by the upper adhesive layer forms an upper circuit trace exposure area; and
An upper conductor layer formed on the upper adhesive layer, wherein the upper conductor layer shows a first height difference with respect to the upper circuit trace exposure area in the longitudinal direction; and
At least one first double-sided intermediate circuit trace formed on the lower surface of the first double-sided substrate;
A second double-sided substrate having a second double-sided substrate upper surface and a second double-sided substrate lower surface;
At least one lower circuit trace formed on the lower surface of the second double-sided substrate;
A lower adhesive layer formed on at least a partial region of the lower circuit trace, wherein a portion of the lower circuit trace not covered by the lower adhesive layer forms a lower circuit trace exposure area; and
A lower conductor layer formed on the lower adhesive layer, the lower conductor layer showing a second height difference with respect to the lower circuit trace exposure area in the longitudinal direction; and
An intermediate circuit trace of at least one second double-sided substrate formed on the top surface of the second double-sided substrate;
An adhesive layer inserted between the lower surface of the first double-sided substrate and the upper surface of the second double-sided substrate;
In the vertical direction, the upper conductor layer, the upper adhesive layer, the upper circuit trace, the adhesive layer, the lower circuit trace, the lower adhesive layer, and the lower conductor layer are extended to form a through-hole wall surface. At least one through hole;
Covers the through hole wall surface of the through hole, the partial region of the upper conductor layer of the first double-sided substrate adjacent to the through hole, and the partial region of the lower conductor layer of the second double-sided substrate adjacent to the through hole. Including a conductive cover portion,
Electric circuit board.   The electric circuit board according to claim 16, wherein at least one embedded hole is formed in the first double-sided board at a position shifted from the through hole.   The electric circuit board according to claim 16, wherein at least one embedded hole is formed in the second double-sided board at a position shifted from the through hole.   The electric circuit board according to claim 16, wherein the first double-sided board and the second double-sided board are a flexible board, a rigid board, or a composite board in which a flexible board and a rigid board are combined.

Images