JP2013222100A - Reticle, exposure method and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reticle that minimizes an area of multiple exposure regions generated on a wafer.SOLUTION: The reticle includes: a transparent substrate; an element region that is surrounded with a first scribe region having a first width; a most outer periphery scribe region that surrounds the first scribe region; and a light shield zone that surrounds the most outer periphery scribe region. The most outer periphery scribe region has a second width narrower than the first width and includes a marker pattern region. The light shield zone passes a center of an effective pattern region including the element region, the first scribe region and the most outer periphery scribe region and includes a light shield pattern region at a linear symmetry position to the marker pattern region with respect to a center line of the effective pattern region extending in a first direction or a second direction orthogonal to the first direction. The marker pattern region is formed such that its center line coincides with a boundary between the first scribe region and the most outer periphery scribe region, and a width of the marker pattern region exceeds two times the second width.

Description

  The present invention relates to a reticle, an exposure method using the reticle, a method of manufacturing a semiconductor device using the exposure method, and a wafer exposed using the exposure method.

  In manufacturing a semiconductor device, various patterns are exposed on a semiconductor wafer using a reticle.

  A general reticle includes a glass substrate in which a plurality of exposure patterns each corresponding to one chip pattern are formed in a matrix, and the plurality of exposure patterns are formed on a semiconductor wafer by one exposure. The film is exposed. Since a predetermined exposure pattern cannot be formed on the entire surface of the semiconductor wafer by a single exposure, such exposure is usually repeatedly performed while shifting the exposure position on the wafer by a predetermined amount of movement (hereinafter, steps). Called exposure). As a result of such step exposure, a predetermined chip pattern is formed in a matrix form on the semiconductor wafer across the entire surface with predetermined scribe lines used for dicing being separated.

For example, FIG. 1 shows exposure data 11A corresponding to one chip area, a reticle pattern 11B formed on the reticle 10 corresponding to the exposure data 11A, and a positive resist film corresponding to the reticle pattern 11B. and an example is shown of a resist pattern 11C and 11D formed in the negative resist film, exposure data 11A and the device region 11A ₁ a device pattern shown schematically by the letter "F" is formed, around which and a scribe region 11A ₂ of, whereas the reticle pattern 11B is in correspondence with the exposure data 11A, is composed of a scribe region 11B ₂ surrounding it and the device region 11B ₁ is formed on a glass substrate constituting a reticle ing.

Scribe region 11B ₂ on the reticle 10 has a transparent area, when the reticle pattern 11B exposed on the positive resist film by the reticle 10 is the same as the device region 11B ₁ and the scribe region 11B ₂ resist pattern 11C having a device region 11C ₁ and the scribe region 11C ₂ is formed. On the other hand when the reticle pattern 11B is exposed by a reticle 10 onto a negative resist film, the resist pattern 11D is formed with the device region 11B ₁ and the scribe region 11B ₂ the same device area 11D and ₁ and the scribe region 11D ₂ The That is, when the exposure was performed on the positive resist film of FIG 11C uses the reticle 10 in FIG. 1, the in scribe region 11C ₂ exposure results, while the resist film is removed, the same reticle when 10 was exposed on the negative resist film in FIG. 11D using, the scribe region 11D ₂ results of exposure in the resist film is left.

  FIG. 2 is a plan view showing a more specific example of the reticle pattern 11B included in the reticle 10.

Referring to FIG. 2, the reticle 10 is formed by arranging the reticle pattern 11B of FIG. 1 on a glass substrate 10A in a 2 × 2 matrix form in the illustrated example, and each scribe region 11B _2. Are connected to form a grid-like scribe pattern 11BS. The lattice-shaped scribe pattern device pattern 11B ₁ at a 11BS are formed in a matrix, surrounds the outermost scribe pattern BS are light-shielding band 10B is formed, during said scribing pattern 11BS of outermost, A marker pattern 11B ₃ used for mask alignment or the like is formed.

  FIG. 3 shows a positive type while moving the center of the reticle 10 in FIG. 2 from point A to point B, and further from point C and point D to distance X or distance Y, as indicated by an arrow in FIG. It is a top view which shows the example of a resist pattern at the time of carrying out the step exposure of the reticle pattern of the said FIG. 2 on the surface of the wafer W in which the resist film was formed. However, the distance X and the distance Y are the widths of the reticle pattern exposed by one exposure, more precisely, the outermost scribes facing each other in the reticle pattern formed on the positive resist by one exposure. This corresponds to the distance between the centers of the pattern 11BS.

JP 2002-246281 A JP 2002-23344 A

When step exposure using such a reticle is performed on a semiconductor wafer, special care is required at the joint between the previous exposure area and the next exposure area. That is, the joint between adjacent exposure regions is generally formed so as to correspond to the scribe line on the semiconductor wafer. For example, the scribe region 11C ₂ D and the scribe region 11C ₂ Q in FIG. Thus, in such a joint, an area that is exposed in an overlapping manner occurs in the previous exposure area and the next exposure area. In this case, in the overlappingly exposed region, as shown in FIG. 4, the resist opening width increases as the integrated exposure amount to the resist film increases. Therefore, the line width of the scribe line is enlarged at such a joint, and there may be a problem that the exposure pattern around the reticle is deformed.

  According to one aspect, a reticle includes a transparent substrate, a region on the transparent substrate, a device region formed with a semiconductor device pattern, and surrounded by a first scribe region having a first width; A region on the transparent substrate, the outermost scribe region surrounding the first scribe region, and a light shielding band formed on the transparent substrate and surrounding the outermost scribe region, wherein the outermost scribe region is The outermost scribe region includes a marker pattern region, and the shading band includes the element region, the first scribe region, and the outermost scribe. The marker pattern region with respect to the effective pattern region center line extending in the first direction or the second direction perpendicular to the first direction through the center of the effective pattern region including the region A light-shielding pattern region corresponding to the marker pattern region is provided at a line-symmetric position, and the marker pattern region is formed by matching the center line with the boundary between the first scribe region and the outermost peripheral scribe region. The width of the marker pattern region exceeds twice the second width.

  According to another aspect, an exposure method and a method for manufacturing a semiconductor device include a step of forming a film to be exposed on a semiconductor substrate, and the effective pattern region using the reticle in a first exposure region of the film to be exposed. A first exposure step of exposing a first effective pattern corresponding to the first exposure pattern, and moving the reticle relative to the wafer, and using the reticle in a second exposure region adjacent to the first exposure region. A second exposure step of exposing a second effective pattern corresponding to the effective pattern region, wherein the first exposure step includes the outermost peripheral scribe region and the first exposure pattern in the first effective pattern. A step of exposing a first scribe line corresponding to one scribe region, wherein the second exposure step includes the outermost peripheral scribe region and the first scrubbing region in the second effective pattern. And a step of exposing the second scribe lines corresponding to the blanking area, at least a portion of the second scribe line overlaps with the first scribe line.

  According to the above-described embodiment, when performing step exposure while moving the exposure position on the wafer, the double exposure region generated in the scribe region at the boundary between one exposure region and the next exposure region is minimized. This makes it possible to avoid deformation of the formed chip pattern and improve the yield of the semiconductor device.

It is a figure explaining exposure of a positive resist film or a negative resist film using a reticle. It is a top view which shows the example of the conventional reticle. It is a top view which shows the example which exposed on the wafer using the reticle of FIG. It is a figure which shows the example of the photosensitive characteristic of a resist film. It is a top view explaining the conventional subject. It is a top view which shows the example of another conventional reticle. 1 is a plan view showing a reticle according to a first embodiment. FIG. 8 is an enlarged plan view showing a part of the reticle of FIG. 7. It is a top view which shows the wafer which exposed using the reticle of FIG. 7, FIG. (A), (B) is sectional drawing which shows the mode of exposure of FIG. FIG. 10 is a sectional view taken along line A-A ′ in FIG. 9. FIG. 6 is an enlarged plan view showing a reticle according to a modification of the first embodiment. (A), (B) is sectional drawing which shows the mode of the exposure performed using the reticle of FIG. It is a top view which shows the reticle by a comparative example. (A), (B) is a top view which shows the reticle by another modification. It is a top view which shows the wafer by 2nd Embodiment. FIG. 17 is an enlarged plan view when the wafer of FIG. 16 is exposed using the reticle of FIG. 8. FIG. 17 is an enlarged plan view when the wafer of FIG. 16 is exposed using the reticle of FIG. 12.

[First Embodiment]
FIG. 7 is a plan view showing the reticle 20 according to the first embodiment.

  Referring to FIG. 7, the reticle 20 includes an effective patterning region 20C defined by a light shielding band 20B such as Cr on a glass substrate 20A made of quartz glass or the like, and each of the effective patterning regions 20C includes a semiconductor chip. A plurality of chip regions 20D schematically indicated by the letter “F” corresponding to the element pattern are formed in a matrix with a scribe region 20E having a width D therebetween. Further, the array of the plurality of chip regions 20D in the effective patterning region 20C is the innermost side of the light shielding band 20B, and is formed with a width d (d <D) smaller than the width D connected to the scribe region 20E. Surrounded by an outer peripheral scribe region 20F. In FIG. 7, the chip sizes Cx and Cy for one chip area 20D are between the pair of scribe areas 20E and the outermost peripheral scribe area 20F which are opposed to each other across the chip area 20D as shown in FIG. The distances are defined in the x direction, that is, the row direction, and the y direction, that is, the column direction, respectively.

Further, in the outermost peripheral scribe region 20F, a marker region 20G used for alignment at the time of exposure or process control at the time of etching, etc., is a chip region opposite to the light shielding band 20B whose center line is indicated by a one-dot chain line. The effective patterning region 20C is formed so as to coincide with the center line of the scribe region 20E running at a position D / 2 from the outer edge of 20D, and the center line C ₁ extending in the row direction or the column direction is formed in the effective patterning region 20C. the position of the relative C ₂ marker pattern 20G axisymmetrical, the light-shielding band 20B similar shielding pattern 20H is formed in the corresponding shape and dimensions to the marker pattern 20G. The alternate long and short dash line corresponds to a cutting line that is actually cut by the dicing blade when the pattern on the reticle 20 is exposed on the wafer W.

  In this embodiment, it should be noted that the front edge of the light shielding band 20B is close to the chip area 20D in the outermost peripheral scribe area 20F, and a part of the marker pattern 20G bites into the light shielding band 20B. is there. That is, in the reticle 20 of FIG. 7, not only the width of the outer portion 20Eout of the cutting line indicated by the alternate long and short dash line in the outermost peripheral scribe region 20F is simply narrower than the width of the inner portion 20Ein, but also the width of the outer portion 20Eout It is narrower than the width PW / 2 of the pattern 20G.

  FIG. 8 is an enlarged view of the vicinity of the marker pattern 20G or the light shielding pattern 20H in the reticle 20 of FIG.

  Referring to FIG. 8, the marker pattern 20G has a pattern width PW, and the half value PW / 2 of the pattern width PW is indicated by a one-dot chain line from the front edge 20b of the light shielding band 20B facing the chip region 20D. It can be seen that it is larger than the distance Δ to the center line. For this reason, the front edge 20b of the shading band 20B exceeds the rear edge 20j of the marker pattern 20G at a distance D / 2 + PW / 2 from the front edge 20d of the chip region 20D, and is close to the front edge 20d. Yes. The shading band 20B is formed with a notch 20hA, and the marker pattern 20G forms a gap having a width of 20k with the shading band 20B in the notch 20hA. In the marker pattern 20G, a slit pattern 20g corresponding to the pattern to be exposed is formed in a predetermined shape.

  On the other hand, regarding the light shielding pattern 20H, the light shielding pattern 20H has a pattern width PX that is slightly larger than the pattern width PW of the marker pattern 20G, and the rear edge 20e of the light shielding band 20B is the rear edge 20f of the chip region 20D. Is beyond the rear edge 20l of the light-shielding pattern 20H at a distance D / 2 + PX / 2, and is close to the rear edge 20f. The shading band 20B is formed with a notch 20hB, and the shading pattern 20H forms a gap having a width of 20 m with the shading band 20B in the notch 20hB.

  In FIG. 8, an arrow connecting the upper chip region 20D and the lower chip region 20D means that these chip regions 20D are continuous.

  9 shows that the reticle 20 of FIGS. 7 and 8 is placed on the wafer W from the point A to the point B, from the point B to the point C, from the point C to the point D, as shown in FIG. It is a top view which shows the example which performed step exposure, moving as shown by the arrow.

  Referring to FIG. 9, as a result of the step exposure on the wafer W, a plurality of chip area exposure patterns 40D corresponding to the chip areas 20D each have a grid-like scribe line exposure area corresponding to the scribe area 20E. 40E is formed in a matrix separated by a distance of 40W, and in the illustrated example, a chip area exposure pattern 40D exposed at a time in 2 rows and 2 columns is surrounded, and a one-dot chain line corresponding to the outermost peripheral scribe area 20F is attached. The outermost peripheral scribe line exposure region 40F is formed, and in the outermost peripheral scribe line exposure region 40F, a marker pattern 40G corresponding to the marker pattern 20G has a two-row and two-column configuration in which the center line is indicated by a one-dot chain line 40W / 2 from the outer edge of the chip area exposure pattern 40D arranged in the above-described manner, that is, a scrubber It is formed to coincide with the center line of the brine exposure area 40E. The outermost peripheral scribe line exposure area 40F has a width 40w that is smaller than the width 40W corresponding to the width d of the outermost peripheral scribe line 20F on the reticle 20, so that the marker pattern 40G The outermost scribe line exposure region 40F is formed closer to the outer side than the center.

According to the present embodiment, the reticle 20 of FIG. 7 is step-exposed on the wafer W while shifting the exposure position of the center C as shown by arrows A, B, C, and D in FIG. As a result, the outermost scribe region 20F at each position is double-exposed in the region 40f indicated by hatching in FIG. 9, and the region 40g where the region 40f intersects is subjected to quadruple exposure. However, in the present embodiment, in the reticle 20 of FIG. 7, the width d of the outermost peripheral scribe region 20F is formed narrower than the width D of the normal scribe region 20E. Is smaller than the width 40W of the scribe line exposure region 40E. As a result, the double exposure is the region 40f from the outer periphery of the chip region exposure pattern 40D, the distance (40W-40w) / 2 only be formed separately. The same applies to the quadruple exposure region 40g.

  As described above, in the present embodiment, the area of the double exposure region generated in the scribe line on the wafer W is formed on the reticle 20 so that the light shielding band 20B is close to the center of the scribe region. Even if it exists, the influence with respect to exposure of the marker pattern 20G is excluded by forming the marker pattern 20G in the notch part 20hA formed in the light-shielding band 20B as schematically shown in FIG. In addition, double exposure of the marker pattern 20G is avoided by forming the light-shielding pattern 20H in a line-symmetrical position with respect to the reticle center line corresponding to the marker pattern 20G.

  As described above, according to the present embodiment, the region where double exposure occurs is limited to the region 40f at the center of the outermost peripheral scribe line exposure region 40F shown by hatching in FIG. 9, and the double exposure is performed on the marker pattern 40G. In the reticle shown in FIG. 7, the area of the double-exposed region 40f is increased by making the light shielding band 20B close to the chip region 20D and reducing the width of the outermost peripheral scribe region 20F. Thus, the problem of deformation of the scribe area due to double exposure can be solved.

  Further, as described above, in the present embodiment, after the marker pattern 40G formed in such a double exposure region 40f is exposed in the first exposure and then in the next exposure, FIG. In the reticle 20, the region on the wafer W is covered with the light-shielding pattern 20H because it is covered with the light-shielding pattern 20H formed in a line-symmetric position with respect to the marker pattern 20G. Since the exposure is performed by the marker pattern 20G only at the time of the next exposure, the marker pattern 20G is exposed only once, and the size change of the marker pattern due to multiple exposure is suppressed. There is no error in alignment using patterns and process control.

  In the wafer plan view of FIG. 9, a light shielding pattern 40H represents a region on the wafer W where the exposure is blocked by the light shielding pattern 20H of the reticle 20 in the first exposure. When the movement range of the reticle 20 in FIG. 9 is expanded, the same double exposure occurs in the outermost scribe line exposure region 40F other than the outermost scribe line exposure region 40F hatched in FIG. Even in such a case, in the light shielding pattern 40H, the exposure of the marker pattern 40G is blocked first, so that even if the marker pattern 40G is exposed for the second time, double exposure does not occur.

  FIGS. 10A and 10B show exposure of a region including the marker pattern 40G in the semiconductor device 50 formed on the wafer W along the line AA ′ in the plan view of FIG. FIG. 9 is a cross-sectional view illustrating a state corresponding to the reticle enlarged view of FIG. 8 for the first exposure and the next exposure, respectively.

  Referring to FIG. 10A, for example, the semiconductor device 50 includes a silicon substrate 51 on which an active element (not shown) is formed, an interlayer insulating film 52 formed on the silicon substrate 51, and the interlayer insulation. And a conductive film 53 made of Al or the like formed on the film 52, and a positive resist film 54 is applied on the conductive film 53.

  Further, a reticle 20 having the glass substrate 20A above the semiconductor device 50 and having the chip region 20D, the marker pattern 20G, and the light shielding band 20B formed by a metal film 21 such as Cr is disposed. Exposure light from a light source is patterned on the reticle 20 and then irradiated onto the resist film 54. As a result of the exposure, the chip region exposure pattern 40D is exposed corresponding to the chip region 20D in the left region 54P of the resist film 54, and the regions 54A and 54B of the resist film 54 are further exposed. , 54C and 54D are exposed, and the marker pattern 40G is exposed in the resist film 54. 10A, it should be noted that the vicinity of the light-shielding pattern 20B at the right end portion of the reticle 20 in FIG. 7 is shown. In FIG. 10A, “PWmax” is the maximum value of the width PW of the marker pattern 20G.

  Next, referring to FIG. 10B, in the illustrated example, the reticle 20 is moved to the right with respect to the wafer W, and a chip region exposure pattern in the region 54Q on the right side of the drawing of the resist film 54. 40D is exposed. At that time, the region of the resist film 54 where the marker pattern 40G is formed is covered with the light-shielding pattern 20H formed at the left end of the reticle 20, so that double exposure of the marker pattern 40G does not occur. . Further, the region 54P where the chip region exposure pattern 40D is exposed by the exposure shown in FIG. 10A is also covered with the light shielding band 20B at the left end portion of the reticle 20, and is not double-exposed. Thus, according to the present embodiment, even when the step exposure is performed, the marker pattern 40G and its immediate area, for example, the area between the marker pattern 40G and the double exposure area 54E in FIG. The area between the marker pattern 40G and the double exposure area 54F is not subjected to double exposure, and therefore process control such as alignment and etching performed using such a marker pattern is not affected.

  On the other hand, in the exposure process of FIG. 10B, a portion of the resist film 54 corresponding to the gap between the light shielding band 20B and the light shielding pattern 20H and between the light shielding pattern 20H and the chip region 20D is exposed. Accordingly, the part 54E of the previously exposed area 54A is double-exposed, and the area 54D previously exposed is enlarged, and double exposure occurs in the part 54F. However, these double exposure regions are separated from the regions 54P and 54Q in the resist film 54 where the chip region exposure pattern 40D is exposed by a distance (40W-40w) / 2, and in these regions, two double exposure regions are formed. Even if the double exposure occurs, the chip area exposure pattern 40D formed in the areas 54P and 54Q is not affected. The same applies to the quadruple exposure region 40g in FIG.

  10A and 10B, the exposure light is blocked by a masking blade (not shown) provided in the exposure apparatus in a region outside the light shielding band 20B of the reticle 20 in the exposure process of FIGS. Therefore, unnecessary exposure does not occur.

  FIG. 11 is a cross-sectional view corresponding to FIGS. 10A and 10B, showing a scribe line on a wafer together with a part of a pair of semiconductor chip patterns formed with the scribe line interposed therebetween. FIG. 11 shows a state in which the metal film 53 is further patterned after the exposure shown in FIG. 10B, and the resist film 54 has already been removed.

  Referring to FIG. 11, a first chip region 50A and a second chip region 50B are defined on a silicon substrate 51 by a STI type element isolation region 51I via a scribe line 50C. On the silicon substrate 51, the first to fifth interlayer insulating films 52A to 52E and the last include the scribe line 50C from the first chip region 50A to the second chip region 50B over the entire surface of the wafer W. An interlayer insulating film 52F is sequentially stacked corresponding to the interlayer insulating film 52 in FIGS. 10 (A) and 10 (B).

  In the interlayer insulating film 52A, in contact with the surface of the silicon substrate 51, the first metal pattern 52Aa in the first chip region 50A and the second metal pattern in the second chip region 50B. 52Ab is formed on the first interlayer insulating film 52A, the third metal pattern 52Ac in contact with the first metal pattern 52Aa in the first chip region 50A, and the second metal pattern 52Ac. In the chip region 50B, a fourth metal pattern 52Ad is formed in contact with the second metal pattern 52Ab.

  On the interlayer insulating film 52A, the next interlayer insulating film 52B covers the third metal pattern 52Ac in the first chip region 50A, and the fourth chip in the second chip region 50B. The fifth metal pattern 52Ae is in contact with the third metal pattern 52Ac in the first chip region 50A, and the second metal pattern 52Ad is formed in the interlayer insulating film 52B. In the chip region 50B, a sixth metal pattern 52Af is formed in contact with the fourth metal pattern 52Ad.

  On the interlayer insulating film 52B, a seventh metal pattern 52Ag is in contact with the fifth metal pattern 52Ae in the first chip region 50A, and the sixth metal is formed in the second chip region 50B. An eighth metal pattern 52Ah is formed in contact with the pattern 52Af, and the next interlayer insulating film 52C covers the seventh metal pattern 52Ag in the first chip region 50A on the interlayer insulating film 52B. Further, the second chip region 50B is formed so as to cover the eighth metal pattern 52Ah, and the seventh metal pattern 52Ag is formed in the interlayer insulating film 52C in the first chip region 50A. The ninth metal pattern 52Ai is in contact with the eighth metal pattern 52 in the second chip region 50B. Tenth metal pattern 52Aj in contact with h are formed.

  An eleventh metal pattern 52Ak is in contact with the ninth metal pattern 52Ai in the first chip region 50A and the tenth metal in the second chip region 50B on the interlayer insulating film 52C. A twelfth metal pattern 52Al is formed in contact with the pattern 52Aj, and the next interlayer insulating film 52D covers the eleventh metal pattern 52Ak in the first chip region 50A on the interlayer insulating film 52C. Further, the second chip region 50B is formed to cover the twelfth metal pattern 52Al, and the interlayer insulating film 52D has the eleventh metal pattern 52Ak in the first chip region 50A. The thirteenth metal pattern 52Am is in contact therewith, and the twelfth metal pattern 52B is in the second chip region 50B. 14 metal pattern 52An against the genus pattern 52Al are formed.

  On the interlayer insulating film 52D, a fifteenth metal pattern 52Ao is in contact with the thirteenth metal pattern 52Am in the first chip region 50A, and the fourteenth metal in the second chip region 50B. A sixteenth metal pattern 52Ap is formed in contact with the pattern 52An, and the next interlayer insulating film 52E covers the fifteenth metal pattern 52Ao in the first chip region 50A on the interlayer insulating film 52D. In addition, the second chip region 50B is formed so as to cover the sixteenth metal pattern 52Ap, and in the interlayer insulating film 52E, the fifteenth metal pattern 52Ao is formed in the first chip region 50A. The seventeenth metal pattern 52Aq is in contact therewith, and the sixteenth metal pattern 52Aq in the second chip region 50B. 18 metal pattern 52Ar in contact with the metal pattern 52Ap are formed.

  On the interlayer insulating film 52E, a nineteenth metal pattern 52As is in contact with the seventeenth metal pattern 52Aq in the first chip region 50A, and the eighteenth metal in the second chip region 50B. A twentieth metal pattern 52At is formed in contact with the pattern 52Ar, and the last interlayer insulating film 52F is formed on the interlayer insulating film 52E so as to cover the nineteenth metal pattern 52As in the first chip region 50A. In addition, the second chip region 50B is formed so as to cover the twentieth metal pattern 52At.

  Further, the marker pattern 40G is formed on the interlayer insulating film 52E so as to be covered with the interlayer insulating film 52F in the scribe line 50C, and the protective film 63 made of polyimide or the like is formed on the interlayer insulating film 52F. In the protective film 63, an opening 63A corresponding to the marker pattern 40G is formed.

  The metal patterns 52Aa, 52Ab, 52Ae, 52Af, 52Ai, 52Aj, 52Am, 52An, 52Aq, 52Ar are made of, for example, a CVD deposited film such as tungsten, while the metal patterns 52Ac, 52Ad, 52Ag, 52Ah, 52Ak, 52Al, The 52Ao, 52Ap, 52As, 52At and the marker pattern 40G are made of, for example, an Al film, which faces the scribe line and constitutes a moisture-resistant ring 51R in each of the semiconductor chip regions 50A, 50B. The metal patterns 52As and 52At and the marker pattern 40G correspond to the conductive film 53 in FIGS. 10A and 10B.

Referring now to FIG. 11, the region I has a kerf width of 40 μm or 45 μm, for example, and corresponds to the width of the blade used for dicing. On the other hand, the region II is a processing width with a predetermined margin, for example, about 55 μm to 60 μm. Further region III is the width PW of the marker pattern 40G, for example, 80μm approximately, whereas area IV is the maximum width PW _M ax marker pattern 40G.

  According to the present embodiment, the double exposure described above in the cross section of FIG. 11 occurs only in the region II having a width of 55 μm to 60 μm, for example, when the reticle of FIG. 8 is used. On the other hand, as shown in FIG. 12, when the extension line of the rear edge 20j of the marker pattern 20G coincides with the front edge 20b of the light shielding band 20B, double exposure is performed in the region III in the cross-sectional view of FIG. Occurs in the corresponding region 40f ′.

  As described above, according to the present embodiment, the double exposure region on the wafer W is limited to the range of the regions 40f ′ to 40f. For this reason, for example, the moisture-resistant ring formed in the semiconductor chip regions 50A and 50B is double exposed. As a result, problems such as deformation can be avoided, and the reliability of the manufactured semiconductor device can be improved.

  FIG. 12 is an enlarged view similar to FIG. 8, showing a reticle 60 according to a modification of the reticle of FIG.

  Referring to FIG. 12, in the reticle 60, the front edge 20b of the marker pattern 20G is close to the opposing chip region 20D, and the marker pattern 20G is continuous with the light shielding band 20B. As a result, the gaps 20hA and 20hB in FIG. 8 disappear, the marker pattern 20G is formed on the protrusion formed on the front edge 20b of the light shielding band 20B, and the light shielding pattern 20H is behind the light shielding band 20B. It is in the form of a protrusion formed on the edge 20e. In FIG. 12, the parts described above are denoted by the same reference numerals and description thereof is omitted.

  FIGS. 13A and 13B show the exposure performed using the reticle 60 of FIG. 12 in association with the reticle 60 of FIG. It is similar sectional drawing. In the figure, the parts described above are denoted by corresponding reference numerals, and the description thereof is omitted.

  Referring to FIGS. 13A and 13B, in this embodiment, the double exposure regions 54E and 54F immediately adjacent to the marker pattern 40G generated in the example of FIGS. 10A and 10B disappear, Deformation due to double exposure of the marker pattern 40G can be avoided more reliably.

  According to the present embodiment, the area of the effective patterning region 20C on the reticle is reduced by reducing the width of the outermost peripheral scribe region 20F on the reticle 20 or 60 as compared with the conventional example, as shown in FIG. It becomes possible to reduce compared with the reticle 80 by. However, in FIG. 14, the parts described above are denoted by corresponding reference numerals, and description thereof is omitted.

  In this embodiment, the area of the effective patterning region 20C on the reticle is reduced with respect to the array of chip regions thus provided, but this also has an array including a larger number of chip regions. It shows that even when a reticle is used, an increase in the area of the effective patterning region 20C can be suppressed. Therefore, it is conceivable to improve the exposure throughput by using a reticle having such an array including a large number of chip areas in an exposure machine with a limited maximum exposure range.

  For example, a predetermined maximum exposure possible range is 8.640 mm in the X-axis direction when projected onto the wafer W on an exposure machine having a predetermined maximum exposure range of 26.000 mm in the X-axis direction and 33.000 mm in the Y-axis direction. When exposure is performed by combining a reticle having a chip area of 8.230 mm in the Y-axis direction, when three of these chip areas are arranged on the reticle in the X-axis direction and four in the Y-axis direction, If the width of the portion 20Eout outside the cutting line indicated by the alternate long and short dash line in the outer peripheral scribe region 20F is set to 60 μm on one side and 120 μm on both sides, the required exposure area is 8 in the X-axis direction. .640 × 3 + 0.120 = 26.04 mm, and 8.230 × 4 + 0.120 = 33.04 mm in the Y-axis direction, which exceeds the maximum exposure range of the exposure machine. Therefore, in such a case, it is necessary to reduce the number of chip regions on the reticle to two in the X-axis direction and three in the Y-axis direction. However, in such a case, the exposure area formed in one shot is 8.640 × 2 + 0.120 = 17.40 mm in the X-axis direction and 8.230 × 3 + 0.120 = 24.81 mm in the Y-axis direction. Thus, considering the capability of the exposure machine, there is a lot of waste.

  On the other hand, in the present embodiment, the width of the portion 20Eout outside the cutting line indicated by the alternate long and short dash line in the outermost peripheral scribe region 20F is set to 40 μm on one side in a size projected onto the wafer W, and is set to 80 μm in total. As a result, even when three identical chip areas are arranged in the X-axis direction and four in the Y-axis direction, the necessary exposure area is 26.00 mm in the X-axis direction and 33.00 mm in the Y-axis direction. Enter the exposure range.

  In this way, by increasing the number of chip regions 20D carried on the reticle, the number of exposures required to expose one wafer W is reduced from, for example, 162 times in the comparative example to, for example, 85 times, and accordingly, It is possible to greatly improve the throughput of exposure by using the performance of the exposure machine to the limit.

  In the enlarged view of FIG. 10 or FIG. 12, the front edge 20b of the shading band 20B approaches the chip area 20D beyond the center line of the marker pattern 20G corresponding to the center of the scribe area 20E. Since an unexposed area is generated at the center portion, it is desirable not to exceed the area obtained by adding the machining width II / 2 corresponding to the blade width used for dicing shown in FIG.

  In the present embodiment, the arrangement of the marker pattern 20G and the light shielding pattern 20H is not limited to that described above with reference to FIG. 7, and for example, the arrangement shown in FIGS. 15A and 15B is also possible. is there. In FIGS. 15A and 15B, the same reference numerals are given to the portions described above, and description thereof is omitted.

FIG. 15 (A), the even in the embodiment of (B), wherein the marker pattern 20G and the light-shielding pattern 20H is formed on the line symmetry with respect to the center line _{C 1} or _{C 2} of the effective patterning region 20C relationship Yes.

  Although the reticle in which a plurality of element regions are arranged has been described in the present embodiment, the number of element regions arranged in the reticle is not limited to a plurality, and only one may be arranged. .

[Second Embodiment]
FIG. 16 is a plan view showing a silicon wafer W having a so-called frame layout according to the second embodiment exposed by the first embodiment. However, the exposure method according to the present embodiment is not limited to a silicon wafer having such a frame layout.

  Referring to FIG. 16, the silicon wafer W is exposed to the reticle 20 or 60, followed by development, etching, ion implantation, and the like. As a result, a large number of chip area exposure patterns 40D are formed in a matrix. In the outermost chip region of W, no exposure is performed, and the conductive film 53 in FIGS. 10A and 10B and the metal film M such as the Al patterns 52As, 40G, and 52At in FIG. 11 remain. A so-called frame region is formed.

  FIG. 17 is an enlarged plan view showing a portion surrounded by a frame 17F in FIG.

Referring to FIG. 17, in the present embodiment, as a result of applying the reticle 20 described in FIG. 8, the frame region is shielded when exposing the chip region exposure patterns 40D ₁ and 40D ₂ closest to the outermost peripheral chip region. As a result, the marker pattern 40G and the light shielding pattern 40H adjacent to the metal film M constituting the frame region are covered with the band 20B, and the distance d (d) is smaller than the half value D / 2 of the width D of the scribe region. It can be seen that it is formed in <D / 2). However, the distance d represents the distance between the front edge Me corresponding to the front edge 20b of the light shielding band 20B and the center line of the marker pattern 40G or the light shielding pattern 40H that coincides with the center line of the scribe region.

  FIG. 18 is also an enlarged plan view showing a portion surrounded by a frame 17F in FIG.

Referring to FIG. 18, in the present embodiment, as a result of applying the reticle 60 described in FIG. 12, the frame region is shielded when exposing the chip region exposure patterns 40D ₁ and 40D ₂ closest to the outermost peripheral chip region. As a result, the marker pattern 40G and the light shielding pattern 40H adjacent to the metal film M constituting the frame region are covered with the band 20B. The distance d ′ (d ′ <d <D / It can be seen that it is formed in 2). Here again, the distance d represents the distance between the front edge Me corresponding to the front edge 20b of the light shielding band 20B and the center line of the marker pattern 40G or the light shielding pattern 40H coinciding with the center line of the scribe region.

  As described above, in the wafer having the frame layout, the traces to which the reticle 20 of FIG. 8 or the reticle 60 of FIG. 12 is applied are marked with the front edge Me of the metal film M and the marker pattern 40G or the light shielding pattern 40H adjacent thereto. It is possible to find out from the positional relationship.

  The case where the present invention is applied to a positive resist film has been described above as an example. However, the present invention is not limited to the positive resist film, and as shown in FIG. 6 as long as the scribe region is exposed. The present invention can also be applied to such a negative resist film.

As mentioned above, although this invention was described about preferable embodiment, this invention is not limited to this specific embodiment, A various deformation | transformation and change are possible within the summary described in the claim.
(Appendix 1)
A transparent substrate;
A region on the transparent substrate, a device region formed with a semiconductor device pattern and surrounded by a first scribe region having a first width;
A region on the transparent substrate, the outermost peripheral scribe region surrounding the first scribe region;
A light-shielding band formed on the transparent substrate and surrounding the outermost peripheral scribe region;
Including
The outermost peripheral scribe region has a second width narrower than the first width;
The outermost scribe region includes a marker pattern region,
The shading band passes through the center of an effective pattern region including the element region, the first scribe region, and the outermost peripheral scribe region in a first direction or a second direction perpendicular to the first direction. A light shielding pattern region corresponding to the marker pattern region at a position symmetrical to the marker pattern region with respect to the extending effective pattern region center line,
The marker pattern region is formed with its center line coincident with the boundary between the first scribe region and the outermost peripheral scribe region, and the width of the marker pattern region is twice the second width. A reticle characterized by exceeding.
(Appendix 2)
A plurality of the element regions are formed in the effective pattern region,
The reticle according to appendix 1, wherein the plurality of element regions are arranged with a second scribe region having a third width larger than the first width interposed therebetween.
(Appendix 3)
The reticle according to appendix 2, wherein the third width is twice as wide as the first width.
(Appendix 4)
The effective pattern area has a first notch between the light shielding band and the marker pattern area, and has a second notch between the light shielding band and the light shielding pattern. The reticle according to any one of appendices 1 to 3.
(Appendix 5)
The shading band has a first projecting portion and a second projecting portion, the marker pattern region is formed in the first projecting portion, and the shading pattern region is formed by the second projecting portion. The reticle according to any one of appendices 1 to 3, wherein:
(Appendix 6)
6. The reticle according to claim 1, wherein the light-shielding pattern region has a larger shape and size than the marker pattern region.
(Appendix 7)
An exposure method using the reticle according to any one of appendices 1 to 6,
Forming a film to be exposed on a semiconductor substrate;
A first exposure step of exposing a first effective pattern corresponding to the effective pattern region using the reticle in the first exposure region of the film to be exposed;
The reticle is moved relative to the wafer, and a second effective pattern corresponding to the effective pattern area is exposed using the reticle in a second exposure area adjacent to the first exposure area. Exposure process,
Including
The first exposure step includes a step of exposing a first scribe line corresponding to the outermost peripheral scribe region and the first scribe region in the first effective pattern,
The second exposure step includes a step of exposing a second scribe line corresponding to the outermost peripheral scribe region and the first scribe region in the second effective pattern,
An exposure method, wherein at least a part of the second scribe line overlaps with the first scribe line.
(Appendix 8)
In the first exposure step, a marker pattern corresponding to the marker pattern region of the reticle is exposed to the first scribe line, and in the second exposure step, the marker pattern is placed on the reticle. The exposure method according to appendix 7, wherein the exposure method is performed while being covered with a light shielding pattern region.
(Appendix 9)
A manufacturing method of a semiconductor device including the exposure method according to appendix 7 or 8.
(Appendix 10)
A semiconductor substrate;
A plurality of chip regions formed in a matrix form on the semiconductor substrate via a lattice-like scribe region;
A metal film covering the outermost chip region of the plurality of chip regions;
Including
In the scribe region, a marker pattern and a light-shielding pattern having a predetermined width are formed by matching a center line with a center line of the scribe region,
The scribe area between the outermost chip area and the chip area closest thereto is narrower than the other scribe area on the side of the outermost chip area,
In the scribe area between the outermost chip area and the chip area closest thereto, the marker pattern or the light shielding pattern is arranged closer to the outermost chip area than the nearest scribe area. A wafer characterized by that.
(Appendix 11)
The marker pattern or the light shielding pattern is formed by biting into a metal film covering the outermost chip region in a scribe region between the outermost chip region and a chip region closest thereto. The wafer according to appendix 10.

20, 60 Reticle 20A Glass substrate 20B Shading band 20b Shading band leading edge 20e Shading band trailing edge 20C Effective patterning area 20D Chip area 20d Chip area leading edge 20f Chip area trailing edge 20E Scribe area 20F Outermost scribe area 20G Marker pattern 20g Slit pattern 20H shielding pattern 20j marker pattern trailing edge 20l shielding pattern trailing edge 20k, 20 m gap 21 metal film _40D, 40D _1, 40D ₂ chip area exposure pattern 40E scribe line exposure region 40F outermost scribe line exposure region 40f double exposure region 40G Marker pattern 40g Quadruple exposure area 40H Light shielding pattern 50 Semiconductor device 50A First chip area 50B Second chip area 50C Scribe line 51 Silicon substrate 1I Element isolation region 51R Moisture resistant ring 52 Interlayer insulation film 52A-52E Interlayer insulation film 52Aa-52At Metal pattern 52F Top layer interlayer insulation film 53 Conductive film 54 Resist film 54P, 54Q Chip pattern exposure area 54A-54D Marker pattern exposure area 54E, 54F Double exposure area 63 Protective film 63A Opening 80 Reticle of comparative example

Claims (9)

A transparent substrate;
A region on the transparent substrate, a device region formed with a semiconductor device pattern and surrounded by a first scribe region having a first width;
A region on the transparent substrate, the outermost peripheral scribe region surrounding the first scribe region;
A light-shielding band formed on the transparent substrate and surrounding the outermost peripheral scribe region;
Including
The outermost peripheral scribe region has a second width narrower than the first width;
The outermost scribe region includes a marker pattern region,
The shading band passes through the center of an effective pattern region including the element region, the first scribe region, and the outermost peripheral scribe region in a first direction or a second direction perpendicular to the first direction. A light shielding pattern region corresponding to the marker pattern region at a position symmetrical to the marker pattern region with respect to the extending effective pattern region center line,
The marker pattern region is formed with its center line coincident with the boundary between the first scribe region and the outermost peripheral scribe region, and the width of the marker pattern region is twice the second width. A reticle characterized by exceeding. A plurality of the element regions are formed in the effective pattern region,
2. The reticle according to claim 1, wherein the plurality of element regions are arranged with a second scribe region having a third width larger than the first width interposed therebetween.   The reticle according to claim 2, wherein the third width is twice the first width.   The effective pattern area has a first notch between the light shielding band and the marker pattern area, and has a second notch between the light shielding band and the light shielding pattern. The reticle according to any one of claims 1 to 3.   The shading band has a first projecting portion and a second projecting portion, the marker pattern region is formed in the first projecting portion, and the shading pattern region is formed by the second projecting portion. The reticle according to any one of claims 1 to 3, wherein:   The reticle according to any one of claims 1 to 5, wherein the light shielding pattern region has a larger shape and size than the marker pattern region. An exposure method using the reticle according to any one of claims 1 to 6,
Forming a film to be exposed on a semiconductor substrate;
A first exposure step of exposing a first effective pattern corresponding to the effective pattern region using the reticle in the first exposure region of the film to be exposed;
The reticle is moved relative to the wafer, and a second effective pattern corresponding to the effective pattern area is exposed using the reticle in a second exposure area adjacent to the first exposure area. Exposure process,
Including
The first exposure step includes a step of exposing a first scribe line corresponding to the outermost peripheral scribe region and the first scribe region in the first effective pattern,
The second exposure step includes a step of exposing a second scribe line corresponding to the outermost peripheral scribe region and the first scribe region in the second effective pattern,
An exposure method, wherein at least a part of the second scribe line overlaps with the first scribe line.   In the first exposure step, a marker pattern corresponding to the marker pattern region of the reticle is exposed to the first scribe line, and in the second exposure step, the marker pattern is placed on the reticle. 8. The exposure method according to claim 7, wherein the exposure method is performed while being covered with a light shielding pattern region.   A method for manufacturing a semiconductor device, comprising the exposure method according to claim 7.