JP2013220962A - Manufacturing method for silicon wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To establish a feedback method of control related to distribution/generation states of RIE defects.SOLUTION: A manufacturing method for a silicon wafer includes: a defect identifying and evaluating step S04 of identifying a Pv area and detecting a defect distribution by a defect identifying and evaluating method; an RIE defect distribution estimating step S05 of estimating the state of RIE defects on the basis of the result of the defect identifying and evaluating step; and a determination step S06 of determining whether or not to perform feedback to a pulling condition so as to control the RIE defect distribution from the result.

Description

  The present invention relates to a method for manufacturing a silicon wafer, and in particular, a technique suitable for use in a method for manufacturing a silicon wafer sliced from a silicon single crystal grown by the Czochralski method (CZ method) and used for a substrate of a semiconductor device. About.

When a silicon single crystal is grown by the Czochralski method, the type and distribution of defects included in the crystal depend on the ratio V / G of the crystal pulling speed V and the temperature gradient G in the growth direction in the silicon single crystal. . When this V / G is large, vacancies become excessive, and microvoids (defects called COPs) that are aggregates of vacancies are generated. On the other hand, when V / G is small, interstitial silicon atoms become excessive, and dislocation clusters, which are aggregates of interstitial silicon, are generated. Therefore, in order to produce a crystal containing neither COP nor dislocation clusters, V / G must be controlled to fall within an appropriate range. Since the temperature gradient G depends on the structure of the high temperature portion (hot zone) in the CZ furnace, the crystal growth direction is adjusted by changing V. Currently, even a silicon single crystal having a diameter of 300 mm is mass-produced without controlling C / N and dislocation clusters by controlling V / G.
As described above, COPs pulled by controlling V / G and silicon wafers that do not contain dislocation clusters are mass-produced and used for manufacturing electronic devices.

  Between the region where COP is generated and the region where dislocation clusters are generated, there are three regions in order from the largest V / G: the OSF region, the Pv region, and the Pi region. The OSF region contains plate-like oxygen precipitates (OSF nuclei) in an as-grown state (a state in which no heat treatment is performed after crystal growth), and at a high temperature (generally 1000 ° C. to 1200 ° C.). This is a region where an OSF (Oxidation Induced Stacking Fault) occurs when thermal oxidation occurs. The Pv region is an area where oxygen precipitate nuclei are contained in an as-grown state, and oxygen precipitates are likely to be generated when two-stage heat treatment is performed at low and high temperatures (for example, 800 ° C. and 1000 ° C.). . The Pi region is a region that hardly contains oxygen precipitation nuclei in an as-grown state and hardly generates oxygen precipitates even when heat treatment is performed. Since the difference between V / G at which COP begins to occur and V / G at which dislocation clusters begin to occur is very small, strict control of V is required to produce a crystal that does not contain COPs or dislocation clusters. Further, even in a region containing neither COP nor dislocation clusters, finer RIE defects existed.

  The RIE defect is a defect detected by a method using reactive ion etching (RIE) in an as-grown state, and is caused by a fine crystal that cannot be detected by an infrared tomography method ( grown-in) defects.

Evaluation methods based on various principles have been proposed as a method for detecting crystal defects in a silicon single crystal. However, in Patent Document 1, after making oxygen precipitates such as BMD appear by heat treatment, Si / SiO _A method is described in which RIE is performed on a sample under conditions with a high selectivity ratio of ₂ . As a result, oxygen precipitates (SiO ₂ ) are not etched but are manifested as protrusions. It has been reported that if conditions with a high Si / SiO ₂ selection ratio are selected, defect evaluation with higher sensitivity than infrared tomography is possible.

  Patent Document 2 describes the detection of defects in the as-grown state by the RIE method, not after the heat treatment.

JP 2000-58509 A JP 2010-100507 A

As described in the patent literature, the RIE method can detect fine defects in the as-grown state, but in order to detect RIE defects, it is necessary to polish a sample cut from a single crystal. It becomes. This is to reduce the influence of processing damage on detection. Therefore, even if an attempt is made to change the pulling speed V, which is a control condition for a fine defect that is detected as an RIE defect, at the stage where the RIE defect is detected, the next pulling has already started, and the pulling speed V or The temperature gradient G cannot be fed back. Alternatively, if feedback regarding the RIE defect is performed, the next pulling cannot be started until the RIE defect detection result is obtained.
For this reason, there has been a demand for establishing a control feedback method regarding the distribution and generation state of RIE defects without using the RIE method so as not to cause such a decrease in productivity.

The present invention has been made in view of the above circumstances, and intends to achieve the following object.
1. To establish a control feedback method for the distribution and generation state of RIE defects.
2. Enable feedback of RIE defects without reducing productivity.
3. Enable feedback of RIE defect density distribution while preventing increase in manufacturing cost.
4). To improve the characteristics of silicon wafers.

The silicon wafer manufacturing method of the present invention is a silicon wafer manufacturing method capable of controlling the distribution and density of RIE defects,
A pulling step of pulling the silicon single crystal by the CZ method;
Cutting the pulled single crystal into an ingot of a predetermined length in the pulling axial direction, and slicing a wafer-like slag sample from its end; and
A defect revealing evaluation step of detecting a defect distribution by revealing a defect region by a defect revealing evaluation method in the slag sample;
RIE defect distribution estimation step for estimating the state of the RIE defect based on the result of the defect manifestation evaluation step;
A determination step of determining whether feedback to the pulling condition is necessary so as to control the RIE defect distribution from the result of the RIE defect distribution estimation step;
By solving this problem, the above-mentioned problems were solved.
In the present invention, the defect revealing evaluation step detects an outer peripheral diameter S1 and an inner peripheral diameter S2 of a defect non-detection region that is annular in the slag sample, and the RIE defect is determined based on a difference between these values (S1-S2). More preferably, the density is estimated.
According to the present invention, in the RIE defect distribution estimation step, the outer peripheral diameter R1 of the non-RIE defect region without the RIE defect and the inner peripheral diameter are formed by the outer peripheral diameter S1 and the inner peripheral diameter S2 of the defect undetected region. R2 can be estimated.
Further, in the RIE defect distribution estimation step, the RIE defect maximum density RM1 on the outer peripheral side from the RIE defect-free non-RIE defect region having an annular shape by the outer peripheral diameter S1 and the inner peripheral diameter S2 of the defect undetected region; The RIE defect maximum density RM2 can be estimated on the center side from the non-RIE defect region.
Further, in the present invention, in the RIE defect distribution estimation step, the outer peripheral diameter R1 of the non-RIE defect region without the RIE defect, which is annular, is determined by the outer peripheral diameter S1 and the inner peripheral diameter S2 of the defect undetected region, The peripheral diameter R2 is estimated, and the necessity of feedback to the pulling condition is determined based on the outer peripheral diameter R1 and the inner peripheral diameter R2 of the non-RIE defect region. In the RIE defect distribution estimating step, The outer peripheral diameter S1 and the inner peripheral diameter S2 of the defect-undetected region are the RIE defect maximum density RM1 on the outer peripheral side of the RIE defect-free RIE defect region that is annular, and the RIE defect on the central side of the non-RIE defect region. The maximum density RM2 is estimated, and the feed rate to the pulling condition is determined based on the RIE defect maximum density RM1 and the RIE defect maximum density RM2 inside and outside the non-RIE defect region. It is also possible to adopt a means for judging the back necessity.
In the present invention, when it is determined that feedback is performed in the determination step, based on the estimated R1, R2, RM1, and RM2, the ratio V / G of the pulling speed V and the temperature gradient G in the pulling condition is It is desirable to change the value.
The silicon wafer of the present invention is preferably manufactured by any one of the manufacturing methods described above.

  In the present invention, the RIE defect is manifested as a protrusion on the etched surface by performing reactive ion etching (RIE) on a sample in an as-grown state, and observed by an optical microscope. This means a defect caused by a crystal containing silicon oxide (grown-in defect), and in the as-grown state, a defect that is so fine that it cannot be detected by means other than RIE evaluation methods such as infrared tomography. Is also included.

  In the present invention, an ingot means a cylindrical silicon single crystal lump obtained by performing cylindrical grinding on a pulled silicon single crystal and cutting it to a predetermined length in the crystal growth axis direction.

  In the present invention, the slag sample means a sample sliced to a predetermined thickness from the end of the crystal growth axis of the ingot. The slag sample is sliced from the end of the ingot for the purpose of collecting the sample, and the ingot is entirely processed into a wafer and polished, and is different from the wafer selected therefrom.

In the present invention, the defect revealing evaluation method is, for example, a slag sample etched with HF / HNO ₃ , washed with HF / H ₂ O, and evaluated in an inert gas or oxygen atmosphere (400 to 800 ° C.). / (3 hr to 5 hr) +900 to 1100 ° C./(10 hr to 14 hr)), washed with HF / H ₂ O, decorated with Cu at a temperature of 700 to 900 ° C. after immersion in a copper nitrate aqueous solution, and HF / HNO ₃ After removing Cu adhering to the surface by etching, precipitates are made more obvious by selective etching, the surface defect distribution is visually observed, and the defect occurrence state of the crystal is evaluated based on the distribution.

  Estimating the state of RIE defects means that in the as-grown state, the distribution and density of fine defects that can only be detected by the RIE method can be processed in a short time, and no mirror polishing is required. It means to estimate from the result of cheap defect manifestation processing.

  In the present invention, the defect non-detection region is a region where no defect is detected as a result of the defect manifestation evaluation.

  In the present invention, the term “annular” means that the outer periphery or inner periphery of the defect-undetected region or the non-RIE defect region may be formed, such as a circular shape or a state where the outer periphery coincides with the outer periphery of the slab sample. Is also included. In this case, when the shape is a circle, the inner diameter S2 and the like are zero, and when the outer periphery coincides with the outer edge of the slab sample, the outer diameter S1 and the like are regarded as the slag sample diameter.

In the present invention, the slow pulling speed means that it is close to the pulling speed V on the side where defects due to interstitial silicon occur in the Pi region.
In the present invention, the high pulling speed means that it is close to the pulling speed V on the side where defects due to vacancies occur in the Pi region.

The silicon wafer manufacturing method of the present invention is a silicon wafer manufacturing method capable of controlling the density distribution of RIE defects,
A pulling step of pulling the silicon single crystal by the CZ method;
Cutting the pulled single crystal into an ingot of a predetermined length in the pulling axial direction, and slicing a wafer-like slag sample from its end; and
A defect revealing evaluation step of detecting a defect distribution by revealing a defect region by a defect revealing evaluation method in the slag sample;
RIE defect distribution estimation step for estimating the state of the RIE defect based on the result of the defect manifestation evaluation step;
A determination step of determining whether to feed back to the pulling condition so as to control the RIE defect distribution from the result of the RIE defect distribution estimation step;
As a result, it was possible to establish a method for controlling REI defects without using the RIE method, which was not established conventionally. In addition, wafer pass / fail judgment can be made by estimating the RIE defect density distribution using the slag sample obtained at the same time in the ingot cutting process, which is an upstream process of the manufacturing process, so that feedback can be performed quickly. .

  In the present invention, the defect revealing evaluation step detects an outer peripheral diameter S1 and an inner peripheral diameter S2 of a defect non-detection region that is annular in the slag sample, and the RIE defect is determined based on a difference between these values (S1-S2). By estimating the density, feedback can be promptly performed by a defect revealing method that produces results in a short time without using an RIE evaluation method that requires an RIE apparatus and requires time for measurement preprocessing.

  According to the present invention, in the RIE defect distribution estimation step, the outer peripheral diameter R1 of the non-RIE defect region without the RIE defect and the inner peripheral diameter are formed by the outer peripheral diameter S1 and the inner peripheral diameter S2 of the defect undetected region. R2 can be estimated, and this makes it possible to easily estimate the radial dimension (width dimension in the case of an annular shape) of a region free of RIE defects that could only be evaluated by the RIE evaluation method. Become.

  Further, in the RIE defect distribution estimation step, the RIE defect maximum density RM1 on the outer peripheral side from the RIE defect-free non-RIE defect region having an annular shape by the outer peripheral diameter S1 and the inner peripheral diameter S2 of the defect undetected region; The RIE defect maximum density RM2 can be estimated on the center side of the non-RIE defect region, and the density distribution of the RIE defect that could only be evaluated by the RIE method can be obtained from the defect undetected region by the defect manifestation evaluation. It is possible to easily estimate the outer peripheral diameter S1 and the inner peripheral diameter S2.

  Further, in the present invention, in the RIE defect distribution estimation step, the outer peripheral diameter R1 of the non-RIE defect region without the RIE defect, which is annular, is determined by the outer peripheral diameter S1 and the inner peripheral diameter S2 of the defect undetected region, The peripheral diameter R2 is estimated, and the necessity of feedback to the pulling condition is determined based on the outer peripheral diameter R1 and the inner peripheral diameter R2 of the non-RIE defect region. In the RIE defect distribution estimating step, The outer peripheral diameter S1 and the inner peripheral diameter S2 of the defect-undetected region are the RIE defect maximum density RM1 on the outer peripheral side of the RIE defect-free RIE defect region that is annular, and the RIE defect on the central side of the non-RIE defect region. The maximum density RM2 is estimated, and the feed rate to the pulling condition is determined based on the RIE defect maximum density RM1 and the RIE defect maximum density RM2 inside and outside the non-RIE defect region. By adopting a means for judging the back necessity, it is possible to quick feedback to pulling conditions during pulling the next crystal.

  In the present invention, when it is determined that feedback is performed in the determination step, based on the estimated R1, R2, RM1, and RM2, the ratio V / G of the pulling speed V and the temperature gradient G in the pulling condition is By changing the value, the crystal characteristics to be pulled can be changed to pull up a silicon single crystal having a desired RIE defect distribution state, whereby a silicon wafer having a desired RIE defect distribution state can be manufactured. it can.

In the present invention, when the estimated (R1-R2) is smaller than a required value, the value of (R1-R2) is increased by performing feedback that V / G in the pulling condition is decreased, The non-RIE defect region can be expanded.
In the present invention, when (R1-R2) is larger than a necessary value, feedback of increasing V / G in the pulling condition is performed to reduce the value of (R1-R2), thereby reducing the RIE defect. The area can be narrowed.
As a result, a method for controlling the RIE defect density distribution could be established.

In the present invention, when the estimated RM1 or RM2 is larger than a necessary value, the feedback of reducing V / G in the pulling condition is performed to maintain the RIE defects at a low density over the entire wafer surface. it can.
As a result, a method for controlling the RIE defect density distribution could be established.

  When the estimated result of R1-R2, RM1, or RM2 is used to feed back to the pulling condition, each result can be judged and fed back independently or can be fed back by judging in combination. .

The silicon wafer of the present invention is preferably manufactured by any one of the manufacturing methods described above.
In the silicon wafer of the present invention, it is preferable that the Pi region is secured, and in particular, a wafer having a low density of RIE defects over the entire surface can be manufactured.

  According to the present invention, it is possible to establish a control feedback method related to the distribution / generation state of RIE defects without using the RIE method, and it is possible to feed back RIE defects without reducing productivity. In addition, while preventing an increase in manufacturing cost, it is possible to provide feedback of the RIE defect density distribution and improve the characteristics of the silicon wafer.

It is a flowchart which shows the process in 1st Embodiment of the manufacturing method of the silicon wafer which concerns on this invention. It is a schematic diagram which shows the silicon single crystal pulling apparatus applicable to 1st Embodiment of the manufacturing method of the silicon wafer which concerns on this invention. It is a figure which shows an example of the relationship between the pulling speed V of a silicon single crystal, and the kind and distribution of a defect. It is the graph (a) which shows the RIE defect distribution state in 1st Embodiment of the manufacturing method of the silicon wafer which concerns on this invention, and the graph (b) which shows the result of defect manifestation evaluation. It is the graph (b) which shows the image (a) which shows the RIE defect distribution state by RIE evaluation method in 1st Embodiment of the manufacturing method of the silicon wafer which concerns on this invention, and the result of corresponding defect manifestation evaluation. It is a graph which shows the relationship between the inner periphery diameter S2 of the defect undetected area | region and the inner periphery diameter R2 of a non-RIE defect area | region in 1st Embodiment of the manufacturing method of the silicon wafer which concerns on this invention. It is a graph which shows the relationship between the outer periphery diameter S1 of the defect non-detection area | region and the outer periphery diameter R1 of a non-RIE defect area | region in 1st Embodiment of the manufacturing method of the silicon wafer which concerns on this invention. It is a graph (a) which shows the RIE defect distribution state in 2nd Embodiment of the manufacturing method of the silicon wafer which concerns on this invention, and a graph (b) which shows the result of defect manifestation evaluation. It is the graph (b) which shows the image (a) which shows the RIE defect distribution state by RIE evaluation method in 2nd Embodiment of the manufacturing method of the silicon wafer which concerns on this invention, and the result of corresponding defect manifestation evaluation. It is a graph which shows the relationship between the inner peripheral diameter S2 of the defect undetected area | region and inner side RIE defect maximum density RM2 in 2nd Embodiment of the manufacturing method of the silicon wafer which concerns on this invention. It is a graph which shows the relationship between the outer periphery diameter S1 of the defect undetected area | region and outer side RIE defect maximum density RM1 in 2nd Embodiment of the manufacturing method of the silicon wafer which concerns on this invention.

Hereinafter, a first embodiment of a method for producing a silicon wafer according to the present invention will be described with reference to the drawings.
FIG. 1 is a flowchart showing a method for manufacturing a silicon wafer in the present embodiment.

  As shown in FIG. 1, the silicon wafer manufacturing method of this embodiment includes a pulling condition setting step S01, a pulling step S02, an ingot cutting / slag sample obtaining step S03, a defect revealing evaluation step S04, and an RIE defect distribution estimating step S05. , Determination step S06, wafer slicing step S07, and wafer polishing step S08.

The silicon wafer manufactured by the silicon wafer manufacturing method of the present embodiment has at least a Pi region, and RIE defects have a low density over the entire surface.
The silicon wafer manufacturing method of the present embodiment is based on the standard of the wafer to be manufactured as the pulling condition setting step S01 shown in FIG. 1, and the pulling speed V, temperature gradient G, applied magnetic field state, crystal and crucible rotation speed, pulling atmosphere Set the dopant concentration. This condition setting includes, in particular, setting what the RIE defect distribution state is, and other pulling conditions are also set in order to realize this characteristic.

  Next, as a pulling step S02 shown in FIG. 1, the silicon single crystal is pulled according to the conditions set in the pulling condition setting step S01.

FIG. 2 is a schematic diagram showing a silicon single crystal pulling apparatus applicable to the method for manufacturing a silicon wafer in the present embodiment.
The silicon single crystal pulling apparatus 10 includes a chamber 11, a support rotary shaft 12 penetrating through the center of the bottom of the chamber 11, a graphite susceptor 13 fixed to the upper end of the support rotary shaft 12, a graphite A quartz crucible 14 accommodated in the susceptor 13, a heater 15 provided around the graphite susceptor 13, a support shaft rotation drive mechanism 16 for moving the support rotation shaft 12 up and down, and a seed for holding a seed crystal While preventing the heating of the silicon single crystal 20 due to the radiant heat from the chuck 17, the pulling wire 18 for suspending the seed chuck 17, the wire winding mechanism 19 for winding the wire 18, and the heater 15 and the quartz crucible 14. The heat shielding member 22 for suppressing the temperature fluctuation of the silicon melt 21 and each part And a Gosuru controller 23.

  A gas inlet 24 for introducing Ar gas into the chamber 11 is provided in the upper part of the chamber 11. Ar gas is introduced into the chamber 11 from the gas introduction port 24 through the gas pipe 25, and the introduction amount is controlled by the conductance valve 26.

  A gas discharge port 27 for exhausting Ar gas in the chamber 11 is provided at the bottom of the chamber 11. Ar gas in the sealed chamber 11 is discharged from the gas outlet 27 through the exhaust pipe 28 to the outside. A conductance valve 29 and a vacuum pump 30 are installed in the middle of the exhaust gas pipe 28, and the pressure in the chamber 11 is reduced by controlling the pressure with the conductance valve 29 while sucking the Ar gas in the chamber 11 with the vacuum pump 30. Is maintained.

  Further, a magnetic field supply device 31 is provided outside the chamber 11. The magnetic field supplied from the magnetic field supply device 31 may be a horizontal magnetic field or a cusp magnetic field.

  Next, as the ingot cutting / slag sample acquisition step S03 shown in FIG. 1, the pulled silicon single crystal is cut to a predetermined length in the crystal growth axis direction set to an arbitrary length of 10 to 3000 mm, and cylindrical grinding is performed. The cylindrical ingot is formed. At this time, as a slag sample sliced from both ends of the ingot, a wafer-like plate having a thickness substantially equal to the wafer to be manufactured is obtained.

Next, as a defect revealing evaluation step S04 shown in FIG. 1, the slag sample is subjected to HF / HNO ₃ etching, washed with HF / H ₂ O, and evaluated heat treatment (400 to 800 ° C ./ ( 3 hr to 5 hr) +900 to 1100 ° C./(10 hr to 14 hr)), washed with HF / H ₂ O, decorated with Cu nitrate at a temperature of 700 to 900 ° C. after immersion in an aqueous copper nitrate solution, and HF / HNO ₃ etched After removing Cu adhering to the surface, precipitates are made more obvious by selective etching using a Wright solution (etching amount: 1 to 8 μm / one side), and the defect distribution on the surface is visually observed.

FIG. 4 is a graph (a) showing the RIE defect distribution state in this embodiment and a graph (b) showing the result of the defect manifestation evaluation, and FIG. 5 is an RIE defect according to the RIE evaluation method in this embodiment. It is a graph (b) which shows the image (a) which shows a distribution state, and the result of corresponding defect manifestation evaluation.
As shown in FIGS. 4 and 5, the defect revealing evaluation detects the outer peripheral diameter S1 and the inner peripheral diameter S2 of the defect non-detection region that is annular in the slag sample SS, and the difference (S1−S2) is detected. Ask. At this time, the outer peripheral diameter S1 and the inner peripheral diameter S2 are detected by observation under a condensing lamp. However, detection is also possible by measuring a lifetime map using a lifetime measuring instrument using the μ-PCD method. is there.

  In FIG. 4, the black circles indicate the distribution of RIE defects in the as-grown state by the RIE method.

Next, as the RIE defect distribution estimation step S05 shown in FIG. 1, the RIE defect density distribution is estimated based on the value of (S1-S2) calculated in the defect revealing evaluation step S04.
Specifically, in the RIE defect distribution estimation step S05, as shown in FIG. 4A, the outer peripheral diameter R1 and the inner peripheral diameter R2 of the non-RIE defect region without the RIE defect are shown in FIG. 4B. As described above, since the outer peripheral diameter S1 and the inner peripheral diameter S2 of the defect undetected region can be regarded as substantially equal to each other, the difference between the outer peripheral diameter S1 and the inner peripheral diameter S2 of the defect undetected region (S1−S2) The radial dimension TPi = (R1-R2) between the outer peripheral diameter R1 and the inner peripheral diameter R2 of the non-RIE defect region without the RIE defect is estimated.

  Next, as a determination step S06 shown in FIG. 1, it is determined whether the radial width dimension TPi = (R1-R2) of the non-RIE defect region estimated in the RIE defect distribution estimation step S05 is in a predetermined state, and there is no problem. In such a case, the process proceeds to the next wafer slicing step S07, and when it is out of the predetermined state, feedback is performed to change the pulling condition in the pulling condition setting step S01.

  When it is determined in the determination step S08 that feedback is performed, the value of the ratio V / G of the pulling speed V and the temperature gradient G in the pulling condition is changed, thereby changing the crystal characteristics to be pulled and a desired RIE. A silicon single crystal having a defect distribution state can be pulled up, whereby a silicon wafer having a desired RIE defect distribution state can be manufactured.

Specifically, in the present embodiment, when the estimated (R1-R2) is smaller than a necessary value, feedback (R1-R2) is performed by reducing V / G in the pulling condition. The value of can be increased and the non-RIE defect region can be expanded.
In the present embodiment, when (R1-R2) is larger than a necessary value, feedback of increasing V / G in the pulling condition is performed, so that the value of (R1-R2) is reduced and no RIE is performed. The defect area can be narrowed.

  In the wafer slicing step S07 and wafer polishing step S08 shown in FIG. 1, a silicon wafer is manufactured by performing necessary processes such as slicing, etching, cleaning, grinding, polishing, beveling, and heat treatment in a normal wafer manufacturing process.

  FIG. 3 is a diagram showing the relationship between the pulling rate V of the silicon single crystal and the type and distribution of defects, and the left side of the drawing shows the silicon single crystal SC in which the pulling rate is changed with different temperature gradients G. It is sectional drawing of a growth axis direction, and the right side of FIG. 3 is sectional drawing of the broken line shown to (a)-(c), respectively, and is equivalent to the surface of slag sample SS of each state.

The pulling condition in FIG. 3C is a pulling condition in which the OSF region appears in a disk shape, and is a case where V / G near the center is larger (G is smaller) than the outer peripheral portion of the crystal.
When the pulling speed V is set to a speed corresponding to the broken line in the drawing under the pulling conditions in FIG. 3C, a Pv region appears at the center of the cut silicon wafer as shown in FIG. Pi area appears outside of the area. When the pulling speed V is changed to a side larger than the broken line in the drawing (upper position in the drawing) under the pulling condition in FIG. 3C, an OSF region appears in a disk shape at the center of the wafer.

The pulling condition in FIG. 3A is a pulling condition in which the Pv region appears in a disk shape and a ring shape, and in the case where V / G is large (G is small) at the outer periphery of the crystal as compared with FIG. is there.
When the pulling speed V is set to a speed corresponding to the broken line in the drawing under the pulling condition of FIG. 3A, a Pv region appears at the center of the cut silicon wafer, and a Pi region is formed concentrically on the outside thereof. , Pv regions appear in this order.

The pulling condition in FIG. 3B is a pulling condition in which the Pv region appears in a disk shape and a ring shape, and in the case where V / G is large (G is small) at the outer periphery of the crystal as compared with FIG. is there.
When the pulling speed V is set to a speed corresponding to the broken line in the drawing under the pulling condition of FIG. 3B, a Pi region appears at the center of the cut silicon wafer, and a concentric Pv region appears outside the Pi region. Appears.

  When pulling up under such different conditions, the Pv region and the Pi region are distributed circularly and annularly in the slag sample SS or the corresponding silicon wafer surface. The silicon wafer to be manufactured in the present embodiment or the slag sample SS to be determined during the manufacturing corresponds to these states, as shown in FIGS. 3A to 3C, in the radial direction of each non-RIE defect region. It has a width dimension TPi = (R1-R2) in the as-grown state.

  Here, an example having the non-RIE defect region shown in FIG. 3A, that is, an example in which the Pv region, the Pi region, and the Pv region are distributed from the center toward the radially outer side will be described.

Specifically, as shown in FIG. 6, the inner peripheral diameter R2 of the non-RIE defect region without RIE, which is an annular Pi region, which is information of the as-grown state desired to be obtained in the present embodiment, is made apparent. It is substantially equal to the inner peripheral diameter S2 of the defect undetected area after the evaluation.
Further, as shown in FIG. 7, the outer peripheral diameter R1 of the RIE defect-free RIE defect region, which is an annular Pi region, which is information of the as-grown state desired to be obtained in this embodiment, is the defect after the defect manifestation evaluation. It is almost equal to the outer diameter S1 of the undetected area.
Therefore, in order to estimate the radial dimension TPi = (R1-R2) between the outer peripheral diameter R1 and the inner peripheral diameter R2 of the RIE defect-free RIE defect region that is annular in the as-grown state, the defect manifestation is performed. The difference (S1−S2) between the outer peripheral diameter S1 and the inner peripheral diameter S2 of the defect undetected region after the evaluation can be used.

  Further, as shown in FIG. 3C, when the outer diameter R1 of the Pi region (non-RIE defect region without RIE defect) is constant with the outer edge of the wafer, or as shown in FIG. 3B. Even if the inner diameter R2 of the Pi region (non-RIE defect region without RIE defect) is constant with the center of the wafer, as in the example shown in FIG. In order to estimate the radial dimension TPi = (R1−R2) between the outer peripheral diameter R1 of the non-RIE defect region and the inner peripheral diameter R2, the difference between the outer peripheral diameter S1 and the inner peripheral diameter S2 of the defect-undetected region (S1-S2) can be used.

  In the present embodiment, as shown in FIG. 5 (a), in the actual RIE evaluation, other than the RIE defect, such as a processing cause, is detected, but the RIE method is not required and it is cheaper. The radial dimension TPi of the outer peripheral diameter R1 and the inner peripheral diameter R2 of the RIE defect-free non-RIE area that is annular in the as-grown state by using the defect manifestation evaluation that can be completed in a short time. By estimating (R1-R2), the RIE defect density distribution can be evaluated in a short time and at a low cost, and a technique for manufacturing a silicon wafer in which the RIE defect density distribution is controlled by feeding back to the pulling conditions can be established. It was.

  Here, a method for observing the position and width of the Pi region by RIE evaluation will be described.

  The position and width of the Pi region can be observed by revealing crystal-grown-in defects including silicon oxide as protrusions on the etched surface by the RIE method. Specifically, a silicon single crystal that does not contain COP and dislocation clusters is grown by the Czochralski method, a silicon wafer is processed from the silicon single crystal, and reactive ion etching is performed on the silicon wafer in an as-grown state. As a result, a grown-in defect containing silicon oxide is revealed as a protrusion on the etched surface. Thereby, the position and the width of the Pi region can be observed. Actually, a region where fine grown-in defects including silicon oxide are present, that is, a Pv region is observed, and the Pi region is observed as a portion other than the Pv region.

In order to make silicon oxide appear as protrusions by RIE, it is necessary to perform RIE under a condition that Si is more easily etched than SiO ₂ , that is, a condition with a higher Si / SiO ₂ selection ratio. Thereby, SiO ₂ is hardly etched and becomes apparent as a protrusion.

FIG. 5 (a) is an actual sample surface image obtained by optical photography of the SiO ₂ that has been exposed as described above, and in FIG. 5 (a), the white portion is a protrusion generation region detected by RIE evaluation. The black portion (corresponding to the Pv region) is a non-RIE defect distribution region (corresponding to the Pi region).

  The protrusion generation region is a composite region of the OSF region and the Pv region shown on the left side of FIGS. That is, when RIE is performed on a silicon wafer in the as-grown state, protrusions are generated in the OSF region and the Pv region, and almost no protrusions are generated in the Pi region. The OSF region is a region containing plate-like oxygen precipitates in an as-grown state, and this plate-like oxygen precipitate becomes apparent when thermally oxidized at a high temperature of about 1000 ° C. to 1200 ° C. .

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

Hereinafter, a second embodiment of a method for producing a silicon wafer according to the present invention will be described with reference to the drawings.
In the present embodiment, the difference from the first embodiment described above is the point related to the RIE defect distribution estimation step S05 shown in FIG. 1 and its related parts, and other corresponding components are denoted by the same reference numerals. Therefore, the description is omitted.

  In the present embodiment, in the RIE defect distribution estimation step S05 shown in FIG. 1, the outer RIE defect maximum density RM1 on the outer periphery side of the annular RIE defect-free RIE defect region and the center side of the non-RIE defect region. The inner RIE defect maximum density RM2 can be regarded as having a correlation with the outer peripheral diameter S1 and the inner peripheral diameter S2 of the defect non-detection region. And the value of the inner RIE defect maximum density RM2 is estimated from the inner peripheral diameter S2 of the defect undetected region.

  Next, as a determination step S06 shown in FIG. 1, whether the outer RIE defect maximum density RM1 inside and outside the non-RIE defect region estimated in the RIE defect distribution estimation step S05 and the inner RIE defect maximum density RM2 are in a predetermined state. If there is no problem, the process proceeds to the next wafer slicing step S07. If it is out of the predetermined state, feedback is performed to change the pulling condition in the pulling condition setting step S01.

  Here, an example having the non-RIE defect region shown in FIG. 4A, that is, an example in which the Pv region, the Pi region, and the Pv region are distributed from the center toward the radially outer side will be described.

Specifically, as shown in FIG. 10, the inner RIE defect maximum density RM2 on the center side from the non-RIE defect region which is the annular Pi region, which is information of the as-grown state desired to be obtained in the present embodiment, is the defect manifestation. It has a correlation with the inner peripheral diameter S2 of the defect undetected area after the evaluation.
Further, as shown in FIG. 11, the outer RIE defect maximum density RM1 on the outer peripheral side from the RIE defect-free non-RIE defect region which is an annular Pi region which is information of the as-grown state desired to be obtained in the present embodiment is It has a correlation with the outer peripheral diameter S1 of the defect-undetected region after the revealing evaluation.
Therefore, the outer RIE defect maximum density RM1 on the outer peripheral side of the RIE defect-free RIE defect region that is annular in the as-grown state and the inner RIE defect maximum density RM2 on the center side of the non-RIE defect region are estimated. Therefore, it is possible to use the outer peripheral diameter S1 and the inner peripheral diameter S2 of the defect undetected region after the defect manifestation evaluation.

  Similarly to the example shown in FIG. 3A, as shown in FIG. 3C, the outer diameter R1 of the Pi region (non-RIE defect region having no RIE defect) is constant with the outer edge of the wafer. In this case, the inner RIE defect maximum density RM2 on the center side from the non-RIE defect region is estimated, and as shown in FIG. 3B, the inner diameter R2 of the Pi region (non-RIE defect region without RIE defect) is the wafer. In order to estimate the outer RIE defect maximum density RM1 on the outer peripheral side from the non-RIE defect region, the outer peripheral diameter S1 or the inner peripheral diameter S2 of the defect non-detection region can be used, respectively.

  In this embodiment, as shown in FIGS. 8 and 9, the density distribution of RIE defects that could only be evaluated by the RIE evaluation method is a defect that uses defect manifestation evaluation that allows the processing to be completed in a short time at a lower cost. By estimating the inner RIE defect maximum density RM2 on the center side from the non-RIE defect region and the outer RIE defect maximum density RM1 on the outer periphery side from the non-RIE defect region by the outer peripheral diameter S1 or the inner peripheral diameter S2 of the undetected region, It was possible to establish a method for manufacturing a silicon wafer in which the RIE defect density distribution was evaluated in a short time at low cost and fed back to control the RIE defect density distribution.

In this embodiment, when the estimated RM1 or RM2 is larger than a necessary value, the feedback is performed to reduce the V / G in the pulling condition, thereby maintaining the RIE defects at a low density over the entire surface of the wafer. Can do.
As a result, a method for controlling the RIE defect density distribution could be established.

  In the present embodiment, the outer peripheral diameter R1 and the inner peripheral diameter R2 of the RIE defect-free area without the RIE defect that is annular as in the first embodiment described above are estimated, and at the same time the center side from the non-RIE defect-free area. The inner RIE defect maximum density RM2 and the outer RIE defect maximum density RM1 on the outer peripheral side of the non-RIE defect region can also be estimated. As a result, it is possible to estimate a more accurate RIE defect density distribution based on the outer peripheral diameter S1 and the inner peripheral diameter S2 of the defect undetected region using the defect manifestation evaluation.

  Further, in the present embodiment, in the RIE defect distribution estimation step, the outer peripheral diameter R1 of the non-RIE defect region without the RIE defect, which is annular, is determined by the outer peripheral diameter S1 and the inner peripheral diameter S2 of the defect undetected region. The inner peripheral diameter R2 is estimated, and the necessity of feedback to the pulling condition is determined based on the outer peripheral diameter R1 and the inner peripheral diameter R2 of the non-RIE defect region. In the RIE defect distribution estimating step, The outer peripheral RIE defect density RM1 on the outer peripheral side from the RIE defect-free RIE defect region that is annular and the center side from the non-RIE defect region by the outer peripheral diameter S1 and the inner peripheral diameter S2 of the defect-undetected region The inner RIE defect maximum density RM2 is estimated, and the inner RIE defect maximum density RM2 and the inner RIE defect maximum density RM2 inside and outside the non-RIE defect region are estimated. There are also possible to judge the feedback necessity to pulling conditions.

This embodiment can be implemented alone or together with the first embodiment.
As a result, a method for controlling the RIE defect density distribution could be established.

S1 ... Outer diameter of defect-undetected area S2 ... Inner diameter R1 of defect-undetected area ... Outer diameter of non-RIE defect area R2 ... Inner diameter of non-RIE defect area RM1 ... Outer RIE on the outer side of the non-RIE defect area Defect maximum density RM2 ... Inner RIE defect maximum density on the center side from the non-RIE defect region

Claims (6)

A silicon wafer manufacturing method capable of controlling the distribution and density of RIE defects,
A pulling step of pulling the silicon single crystal by the CZ method;
Cutting the pulled single crystal into an ingot of a predetermined length in the pulling axial direction, and slicing a wafer-like slag sample from its end; and
A defect revealing evaluation step of detecting a defect distribution by revealing a defect region by a defect revealing evaluation method in the slag sample;
RIE defect distribution estimation step for estimating the state of the RIE defect based on the result of the defect manifestation evaluation step;
A determination step of determining whether feedback to the pulling condition is necessary so as to control the RIE defect distribution from the result of the RIE defect distribution estimation step;
A method for producing a silicon wafer, comprising:   In the defect manifestation evaluation step, the outer peripheral diameter S1 and the inner peripheral diameter S2 of the annular defect-undetected region in the slag sample are detected, and the RIE defect density is estimated from the difference (S1-S2). The method for producing a silicon wafer according to claim 1.   In the RIE defect distribution estimation step, an outer peripheral diameter R1 and an inner peripheral diameter R2 of the non-RIE defect area without the RIE defect that are annular are determined by the outer peripheral diameter S1 and the inner peripheral diameter S2 of the defect undetected area. The method for producing a silicon wafer according to claim 2, wherein the estimation is performed.   In the RIE defect distribution estimating step, the outer peripheral RIE defect maximum density RM1 on the outer peripheral side of the non-RIE defect region without the RIE defect, which is annular, is determined by the outer peripheral diameter S1 and the inner peripheral diameter S2 of the defect undetected region; 3. The method of manufacturing a silicon wafer according to claim 2, wherein the inner RIE defect maximum density RM2 closer to the center side than the non-RIE defect region is estimated.   The value of the ratio V / G of the pulling speed V and the temperature gradient G in the pulling condition is changed when it is determined that feedback is performed in the determination step. Silicon wafer manufacturing method. A silicon wafer manufactured by the manufacturing method according to claim 1.