JP2013214560A - Manufacturing method of integrated circuit board including ferroelectric capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of an integrated circuit board including a ferroelectric capacitor.SOLUTION: A manufacturing method of an integrated circuit board 11 including a ferroelectric capacitor comprises: a first step of sequentially forming a first electrode layer 12, a ferroelectric thin film 23a and a second electrode 12c on a semiconductor substrate 21; a second step of forming take-out electrodes 11a-11d on a top face of the integrated circuit board 11; a third step of coating, for example, a bonding resin material 14 from above the take-out electrodes of the integrated circuit board 11; a fourth step of bonding the semiconductor substrate 21 upside down on the integrated circuit board 11 in an overlapping manner; a fifth step of removing only the semiconductor substrate 21 with the ferroelectric thin film 23a and electrodes 12c, d of the ferroelectric thin film 23a left on the integrated circuit board 11; a sixth step of patterning the first electrode layer 12 on the ferroelectric thin film 23a to form a first electrode 12d; and a seventh step of forming electrode connection parts 12a, b for connecting the electrode 12c on the ferroelectric thin film 23a with the take-out electrodes 11a, b on the integrated circuit board 11.

Description

  The present invention relates to a ferroelectric capacitor used as a variable capacitance diode (varactor) or the like, and a method of manufacturing an integrated circuit board provided with an inductor.

  In manufacturing a semiconductor device, Patent Document 1 discloses a step of forming an insulating film made of a resin on a semiconductor substrate having a plurality of connection pads on the upper surface, and a lower layer wiring including a lower electrode on the insulating film. Forming a ferroelectric film formed using a dielectric film forming substrate different from the semiconductor substrate, and transferring the patterned ferroelectric film to a film. And a technique of disposing the ferroelectric film from the film on the lower electrode and forming an upper electrode on the ferroelectric film.

Non-Patent Document 1 discloses the structure of a device (integrated circuit, hereinafter referred to as IC) in which a BST capacitor structure made of barium strontium titanate (hereinafter referred to as BST) is integrated. That is, the device according to Non-Patent Document 1 is manufactured as follows.
First, a ferroelectric thin film and a lower electrode are sequentially formed on a semiconductor substrate, a circuit is formed on a separately prepared substrate to form an integrated circuit substrate, and a bonding resin material is applied to the upper surface of the integrated circuit substrate. A base film necessary for the growth of the ferroelectric thin film may be provided on the semiconductor substrate.

Next, the semiconductor substrate is turned upside down and superimposed on the integrated circuit substrate, and the ferroelectric thin film and the lower electrode on the semiconductor substrate are bonded to the integrated circuit substrate.
Subsequently, after removing the semiconductor substrate while leaving only the ferroelectric thin film and the lower electrode on the integrated circuit substrate, a via hole is formed in the bonding resin material and an electrode is formed on the bonding resin material. Thus, the ferroelectric thin film is electrically connected to the circuit of the circuit board through the electrode.
In this way, a circuit board having a ferroelectric capacitor is manufactured.

JP 2006-310419 A

Masahito Moriwaki, Masayoshi Esashi, Hideharu Tanaka, “Development of transfer process of barium strontium titanate thin film on LSI”, Proceedings of the 72nd JSAP Academic Lecture Meeting (2011 Autumn Yamagata University), p.22-005 2011 Masahito Moriwaki, Masayoshi Esashi, Hideharu Tanaka, “Development of hetero-integration technology for barium strontium titanate thin film devices”, 59th Joint Conference on Applied Physics (Spring 2012, Waseda University), p.22 -051, 2012

  By the way, in the method of manufacturing a semiconductor device according to Patent Document 1, a lower electrode of a ferroelectric thin film is formed on another semiconductor substrate, and the ferroelectric thin film is transferred (transferred) thereon. For this reason, the bonding property between the ferroelectric film and the lower electrode is not so good. Therefore, the performance of the ferroelectric capacitor is deteriorated. In addition, if this bondability is poor, not only an electrical problem of deterioration of the performance of the ferroelectric capacitor, but also a structural problem such as peeling, the transfer process yield is lowered. Furthermore, the process of forming the upper electrode on the transferred ferroelectric thin film also deteriorates the performance of the ferroelectric capacitor.

  Further, in the device manufactured according to Non-Patent Document 1, a ferroelectric thin film and a lower electrode are formed in order to sequentially transfer a ferroelectric thin film and a lower electrode on a semiconductor substrate to an integrated circuit substrate. The bondability between is good. However, the ferroelectric thin film exposed during the transfer process is damaged, and the performance of the dielectric capacitor is deteriorated. Similarly to the manufacturing method according to Patent Document 1, when the upper electrode is formed on the transferred ferroelectric thin film, the performance of the ferroelectric capacitor deteriorates due to process damage.

  In view of the above problems, the present invention has a ferroelectric capacitor that has good bonding properties between a ferroelectric thin film and an electrode and that does not cause damage to the ferroelectric thin film during the transfer process of the ferroelectric thin film. An object is to provide an integrated circuit board.

  In order to achieve the above object, a method of manufacturing an integrated circuit substrate having a ferroelectric capacitor according to the present invention includes a first electrode layer, a ferroelectric thin film, and a second electrode sequentially formed on a semiconductor substrate. A second step of forming an extraction electrode on the upper surface of the integrated circuit substrate in which an integrated circuit is configured; and a bonding resin material is applied on the integrated circuit substrate from above the extraction electrode, or a semiconductor substrate 3. Integration with the third stage, either by applying the bonding resin material from above the first electrode layer, the ferroelectric thin film and the second electrode or by applying the bonding resin material on both substrates A fourth stage in which the semiconductor substrate is turned upside down on the circuit board and bonded together; and the first electrode layer, the ferroelectric thin film, and the second electrode are left on the integrated circuit board, and only the conductive substrate is removed. Step 5 and patterning the first electrode layer on the ferroelectric thin film A sixth step of forming the first electrode and a seventh step of forming an electrode connection for connecting the electrode on the ferroelectric thin film to the extraction electrode on the integrated circuit substrate. Features.

In the above configuration, a bonding resin material may be applied on the semiconductor substrate from above the first electrode layer, the ferroelectric thin film, and the second electrode before the fourth stage.
Preferably, in the seventh stage, an inductor is formed on the integrated circuit substrate together with the electrode connection portion.
Preferably, in the first stage, the ferroelectric thin film is a BST thin film.
Preferably, after the seventh stage, the bonding resin material is removed.

According to the above configuration, the ferroelectric thin film preferably made of BST is formed on the semiconductor substrate in a state of being laminated with the first electrode layer and the second electrode, and is transferred onto the integrated circuit substrate. The bonding state between the body thin film and the electrode is good.
In addition, since the first electrode layer, the ferroelectric thin film, and the second electrode are bonded to the upper surface of the integrated circuit substrate through the bonding resin material, the first electrode layer, the ferroelectric thin film, and the second electrode are integrated. The transfer is performed without causing a peeling portion or the like with respect to the upper surface of the circuit board, and the yield in the transfer process is improved.
Furthermore, the ferroelectric thin film is transferred to the upper surface of the integrated circuit substrate together with the first electrode layer, and when the semiconductor substrate is removed, the first electrode layer remains without being removed. For this reason, since the ferroelectric thin film is covered with the first electrode layer, it is possible to effectively prevent damage to the ferroelectric thin film due to etching for removing the semiconductor substrate.
When the inductor is formed adjacent to the bonded ferroelectric thin film on the integrated circuit board, the ferroelectric capacitor and the inductor by the ferroelectric thin film are arranged side by side with respect to the integrated circuit board. The integrated circuit board can be provided with various functions.

  In the seventh stage, when the inductor is formed on the integrated circuit substrate together with the electrode connection portion, the electrode connection portion for electrically connecting the ferroelectric thin film electrode and the collective circuit substrate is formed. At the same time, since the inductor can be formed at the same time, the inductor can be formed adjacent to the ferroelectric capacitor at a low cost without increasing the number of steps.

  In this way, according to the present invention, the bondability between the ferroelectric thin film and the electrode is good, the ferroelectric thin film is not damaged, and the yield of the transfer process of the ferroelectric thin film is further improved. It is possible to configure an integrated circuit substrate having a ferroelectric capacitor and a method for manufacturing the integrated circuit substrate.

The structure of embodiment of the integrated circuit board provided with the ferroelectric capacitor by this invention is shown, (A) is a top view, (B) is sectional drawing. FIG. 2 is a cross-sectional view sequentially showing manufacturing steps of a semiconductor substrate having a ferroelectric thin film in the integrated circuit substrate of FIG. 1. FIG. 2 is a cross-sectional view sequentially showing manufacturing steps of the integrated circuit board in the integrated circuit board of FIG. FIGS. 2A and 2B are a cross-sectional view of a bonding process, and FIG. 3B is a cross-sectional view of a semiconductor substrate removing process. FIGS. FIG. 5 is a cross-sectional view sequentially showing steps for electrical connection of a ferroelectric thin film on the integrated circuit substrates joined in FIG. 4. FIG. 5 is a cross-sectional view sequentially showing subsequent steps for electrical connection of a ferroelectric thin film on the integrated circuit substrates joined in FIG. 4. 1A and 1B show a prototype example of the device of FIG. 1, in which FIG. 1A is a cross-sectional view, and FIG. 8 is a graph showing changes in dielectric constant and tan δ before and after transfer of a ferroelectric thin film in the prototype of FIG.

Hereinafter, the present invention will be described in detail based on the embodiments shown in the drawings.
FIG. 1 shows a configuration of a first embodiment of an integrated circuit board 10 (hereinafter referred to as a device) having a ferroelectric capacitor according to the present invention.
In FIG. 1, a device 10 includes an integrated circuit board 11, and a ferroelectric capacitor 12 and an inductor 13 that are arranged side by side on the integrated circuit board 11, for example.

  The integrated circuit board 11 has a known configuration, and includes an integrated circuit such as an IC or LSI that is configured inside, that is, for example, a single-layer or multi-layer wiring layer, and in these wiring layers or between wiring layers. And various configured elements. Further, the integrated circuit board 11 is provided with metal pads 11a, 11b, 11c and 11d as extraction electrodes from the integrated circuit on the upper surface thereof.

  The varactor 12 is a variable-capacitance diode using a ferroelectric, and is composed of a ferroelectric thin film 23a. The varactor 12 is formed on the integrated circuit board 11 by a bonding resin material 14 disposed on the integrated circuit board 11. It is joined.

  Further, the varactor 12 is connected to the metal pads 11a and 11b on the integrated circuit substrate 11 through two electrode connection portions 12a and 12b formed at both ends thereof.

  Thereby, the varactor 12 is electrically connected to the integrated circuit in the integrated circuit substrate 11. In the varactor 12, the capacitance of the ferroelectric substance changes depending on the voltage applied to the metal pads 11a and 11b. That is, the ferroelectric capacitor becomes a variable capacitor.

  Here, the ferroelectric thin film 23a constituting the varactor 12 is formed on the supporting semiconductor substrate 21 together with the base metal layer 12c and the electrode 12d in a manufacturing process to be described later, and then is applied to the upper surface of the integrated circuit substrate 11. Are transferred onto the integrated circuit substrate 11.

  The inductor 13 is a coil disposed adjacent to the varactor 12 on the integrated circuit substrate 11, and is formed as a thin film on the surface of the bonding resin material 14 by plating or the like.

  Further, the inductor 13 is connected to the metal pads 11c and 11d on the integrated circuit substrate 11 through the two electrode connection portions 13a and 13b formed at both ends in the same manner as the varactor 12.

  As a result, the inductor 13 is electrically connected to the integrated circuit in the integrated circuit substrate 11.

The device 10 according to the embodiment of the present invention is configured as described above, and is manufactured according to the manufacturing method shown in FIGS.
FIG. 2 is a cross-sectional view sequentially showing manufacturing steps of the semiconductor substrate 21 having the ferroelectric thin film 23 in the integrated circuit substrate 11 of FIG.
In FIG. 2A, first, a semiconductor substrate 21, specifically, a silicon (Si) substrate having a thickness of 500 μm, for example, is prepared, and the silicon (Si) substrate 21 is thermally oxidized to thereby obtain an upper surface of the silicon substrate 21. Then, the lower surface is oxidized by a thickness of 50 nm to produce oxide films (SiO ₂ ) 21a and 21b. Further, a TiO _x layer having a thickness of 10 nm is formed on the upper surface as a base film.

  Next, as shown in FIG. 2B, the first electrode layer 22 is formed on the upper surface of the silicon substrate 21 from above the oxide film 21a, and then the BST layer 23 is formed. Here, the first electrode layer 22 is specifically a Pt layer having a thickness of 100 nm, for example.

Specifically, the BST layer 23 is made of, for example, a barium strontium titanate ((Ba _x Sr _1-x ) TiO ₃ ) thin film having a thickness of 100 to 200 nm, and is formed at a temperature of 600 to 700 ° C., for example. .

  Thereafter, as shown in FIG. 2C, the alignment marks 21c and 21d are formed on the lower surface of the silicon substrate 21 by, for example, RIE etching using photoresist patterning.

  Subsequently, as shown in FIG. 2D, the BST layer 23 on the upper surface of the silicon substrate 21 is shaped by wet etching, for example, by patterning a photoresist, leaving only the region corresponding to the varactor 12. The ferroelectric thin film 23a is used.

  Next, as shown in FIG. 2E, the second electrode 23b is formed on the ferroelectric thin film 23a by metal vapor deposition, for example, by patterning a photoresist. Here, the second electrode 23b is made of, for example, a Pt layer having a thickness of 100 nm.

  Subsequently, as shown in FIG. 2F, the bonding resin material 24 is applied over the entire upper surface of the silicon substrate 21 by a spin coating method. Here, the bonding resin material 24 is made of, for example, polyimide or BCB having a thickness of 4 μm, preferably UR-3100E.

  In order to prevent the bonding resin material 24 from rising at the substrate edge during spin coating, first, the spin coating treatment is performed at a thickness of 2 μm, and then the bonding resin material is formed at the substrate edge. 24 may be removed and spin coating may be performed again.

  As a result, the thickness of the bonding resin material 24 is reduced only at the edge of the substrate as shown in FIG.

FIG. 3 is a cross-sectional view sequentially showing the manufacturing steps of the integrated circuit board in the integrated circuit board 11 of FIG.
As shown in FIG. 3A, an integrated circuit substrate 31 into which a ferroelectric capacitor is to be incorporated is prepared separately from the silicon substrate 21 described above. The integrated circuit board 31 has a known configuration, and an integrated circuit (not shown) such as an IC or LSI is formed inside.
Then, the extraction electrodes 31a, 31b, 31c, and 31d are formed on the upper surface of the integrated circuit substrate 31, for example, by metal deposition by patterning a photoresist. Here, the extraction electrodes 31a to 31d are composed of, for example, an Au layer having a thickness of 100 nm, a Pt layer having a thickness of 10 nm, and a Cr layer having a thickness of 10 nm.

  Subsequently, as illustrated in FIG. 3B, the bonding resin material 32 is applied by spin coating over the entire upper surface of the integrated circuit substrate 31. Here, the bonding resin material 32 is applied in the same manner as the spin coating of the bonding resin material 24 to the silicon substrate 21.

  In the above process, the bonding resin material 32 is applied on the integrated circuit substrate 31 over the entire upper surface of the integrated circuit substrate 31, but the first electrode layer 22, the ferroelectric thin film 23a, The bonding resin material 32 may be applied from above the two electrodes 23b, or the bonding resin material 32 may be applied to both the semiconductor substrate 21 and the integrated circuit substrate 31.

4A and 4B are cross-sectional views of the semiconductor substrate 21 in FIG. 2 and the integrated circuit substrate 31 in FIG. 3. FIG. 4A shows a bonding process of the semiconductor substrate 21, and FIG. 4B shows a removal process of the semiconductor substrate 21. Is shown.
As shown in FIG. 4A, a silicon substrate 21 (on which an adhesive resin material 24 is spin-coated on an integrated circuit substrate 31 (see FIG. 3B) on which an adhesive resin material 32 is spin-coated). 2F) is turned upside down, positioned with reference to the alignment marks 21c and 21d, and joined by being heated and pressed.

Next, as shown in FIG. 4B, the silicon substrate 21 is removed by, for example, RIE etching and XeF ₂ etching, and the oxide film 21a and the TiO _x layer are removed by, for example, RIE.
In this way, the ferroelectric thin film 23a and the second electrode 23b made of the first electrode layer 22 and the BST layer 23 are transferred onto the integrated circuit substrate 31 (hereinafter referred to as transfer).

FIG. 5 is a cross-sectional view sequentially showing steps for electrical connection of the ferroelectric thin film 23a in the integrated circuit substrate 31 bonded in FIG.
As shown in FIG. 5A, the integrated circuit substrate 31 to which the ferroelectric thin film 23a has been transferred in this way is formed by shaping the first electrode layer 22 by RIE etching, for example, by patterning a photoresist. Let it be electrode 22a.

  Subsequently, as shown in FIG. 5B, via holes 25a, 25b, 25c, and 25d that penetrate from the upper surface to the lower surface and reach the extraction electrodes 31a to 31d are formed in the bonding resin materials 24 and 32.

The via holes 25a to 25d are formed, for example, by forming a metal mask made of Al or the like having a thickness of, for example, 200 nm over the entire upper surface of the bonding resin material 32, and patterning the photoresist, for example, O ₂ / After removing the bonding resin materials 24 and 32 in the regions of the via holes 25a to 25d by RIE etching using CF ₄ gas, the metal mask is removed.

  Thereafter, as shown in FIG. 5C, a seed layer 26 for plating is formed on the surface of the bonding resin material 32 and the inner surfaces of the via holes 25a to 25d, for example, by sputtering. The seed layer 26 is constituted by a Cu layer having a thickness of 100 nm, for example.

  Next, as shown in FIG. 5D, a plating mold 27 is formed on the upper surface of the bonding resin material 32 by patterning a photoresist. The plating mold 27 is for forming electrode connecting portions 11 and 12 and an inductor 13 which will be described later.

FIG. 6 is a cross-sectional view sequentially showing subsequent steps for electrical connection of the ferroelectric thin film 23a in the integrated circuit substrate 31 bonded in FIG.
Subsequently, as shown in FIG. 6A, a plating layer 28 made of, for example, an Au layer having a thickness of 8 μm is formed on the upper surface of the bonding resin material 32 from above the plating mold 27. At this time, the spiral portion of the plating layer 28 constitutes the inductor 28a, and a part of the plating layer 28 extends into the via holes 25a to 25d, thereby constituting the electrode connection portions 28, respectively. Each electrode connection portion 28 formed by this plating becomes each electrode connection portion 12a, 12b, 13a, 13b shown in FIG. The electrode thin film 23a is electrically connected to the extraction electrodes 31a and 31b of the integrated circuit board 31 by the electrode connection portion 28, and functions as a ferroelectric capacitor, and the inductor 28a is extracted from the integrated circuit board 31. It is electrically connected to the electrodes 31c and 31d.

  Thereafter, as shown in FIG. 6B, a plating mold 27 made of a photoresist and a plating seed layer 26 made of Cu exposed on the surface are wet-etched from the upper surface of the bonding resin material 32, for example. Remove by etc.

  Finally, as shown in FIG. 6C, unnecessary portions of the bonding resin materials 24 and 32 are removed by ashing, for example, by patterning a photoresist, and the extraction electrodes 31a to 31d on the integrated circuit substrate 31 are exposed. Thus, the device 10 is completed.

Since the device 10 according to the present invention is constructed and manufactured as described above, the ferroelectric thin film 23a constituting the varactor 12 is integrated with the first electrode layer 22 and the second electrode 23b provided on both surfaces thereof. Bonded on the circuit board 31. Therefore, the bonding state between the ferroelectric thin film 23a and the electrode 23b is good.
Further, since the ferroelectric thin film 23a including the first electrode layer 22 and the second electrode 23b is transferred to the upper surface of the integrated circuit substrate 31 through the bonding resin materials 24 and 32, the yield in the transfer process is improved. .

  Further, since the ferroelectric thin film 23 a is covered with the first electrode layer 22 in the state of being transferred onto the integrated circuit substrate 31, the etching damage to the ferroelectric thin film 23 is removed in the etching process for removing the semiconductor substrate 21. Can be effectively prevented, and the performance of the device 10 is improved.

Here, an actual prototype of the device 10 of FIG. 1 is shown.
In the step shown in FIG. 2B, the BST layer 23 is sputter deposited at about 650 ° C. and patterned by RIE. The RIE conditions were Ar with a gas flow rate of 34 sccm and CHF ₃ with 6 sccm, a pressure of 5 Pa, a substrate temperature of 7 ° C., and an RF power of 100 W.
In the step shown in FIG. 2E, a 70 nm thick NiCr layer was formed as the base electrode 23b.
Further, in the process shown in FIGS. 2 (F) and 3 (B), photosensitive polyimide (UR-3100E manufactured by Toray Industries Inc.) is spin-coated with a thickness of 1.2 μm as the bonding resin materials 24 and 32, and N ₂ Full cure was performed at 350 ° C. in gas.

  Next, in the process shown in FIG. 3A, the extraction electrodes 31a to 31d are wired by lift-off, and in the process shown in FIG. 3C, the bonding atmosphere is vacuum, the bonding temperature is 350 ° C., and the bonding is performed. The surface pressure was set to 900 kPa, and such bonding conditions were maintained for 1 hour.

Further, used in the step shown in FIG. 4 (B), while using SF ₆ as an etching gas for RIE, in the step shown in FIG. 5 (A), as a RIE conditions, the Ar of SF ₆ and 3sccm gas flow rate 30sccm The pressure was 5 Pa, the substrate temperature was 7 ° C., and the RF power was 100 W.
In the step shown in FIG. 5B, as RIE conditions, 0 ₂ and 8 sccm of CF ₄ with a gas flow rate of 32 sccm, a pressure of 5 Pa, a substrate temperature of 7 ° C., an RF power of 100 W, and OFPR as a photoresist were used. .

Further, in the step shown in FIG. 6A, Au plating solution (EJA, MICROFAB Au310) and OFPR as a photoresist were used, and after plating, the seed layer 26 made of Cu was removed by wet etching.
Further, O ₂ ashing was used in the step shown in FIG.

When the device 10 was prototyped under such conditions, the following results were obtained.
7A and 7B are cross-sectional views and FIG. 7B is an enlarged perspective view of an electron micrograph in the prototype device 10 of FIG.
FIG. 8 shows the dielectric constant and tan δ with respect to the electric field before and after the transfer of the ferroelectric thin film 23a by the BST layer 23 for the prototype of the device 10 shown in FIG.

  According to FIG. 8, the dielectric constant and tan δ (%) after transfer indicated by B are hardly deteriorated compared to the dielectric constant and tan δ before transfer indicated by A. This is presumably because the ferroelectric thin film 23a is covered with the first electrode layer 22 and is not affected by etching damage.

  The present invention can be implemented in various forms without departing from the spirit of the present invention. For example, in the embodiment described above, the device 10 includes the inductor 13 adjacent to the varactor 12, but the present invention is not limited thereto, and the inductor 13 may be omitted.

  2 to 6, the bonding resin materials 24 and 32 are applied to the surfaces of both the semiconductor substrate 21 and the integrated circuit substrate 31, respectively. As shown, the bonding resin material 32 or 24 may be applied only to the integrated circuit substrate 31 or only to the semiconductor substrate 21 shown in FIG.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the invention described in the claims, and it goes without saying that these are also included in the scope of the present invention.

10: Integrated circuit board (device) having a ferroelectric capacitor
DESCRIPTION OF SYMBOLS 11, 61: Integrated circuit board 11a-11d: Metal pad 12: Varactor 12a, 12b: Electrode connection part 12c: First electrode 12d: Second electrode 13: Inductor 13a, 13b: Electrode connection parts 14, 24, 32, 62 : Bonding resin material 21: Semiconductor substrate 21a, 21b: Oxide film 21c, 21d: Alignment mark 22: First electrode layer 22a: First electrode 23: BST layer 23a: Ferroelectric thin film 23b: Second electrodes 25a-25d : Via hole 26: Seed layer 27: Plating mold 28: Plating layer 28a: Inductor 31: Integrated circuit boards 31 to 31d: Extraction electrode

Claims (4)

A first step of sequentially forming a first electrode layer, a ferroelectric thin film and a second electrode on a semiconductor substrate;
A second step of forming an extraction electrode on the upper surface of the integrated circuit substrate in which the integrated circuit is configured;
A bonding resin material is applied on the integrated circuit substrate from above the extraction electrode, or a bonding resin material is applied on the semiconductor substrate from above the first electrode layer, the ferroelectric thin film, and the second electrode. Or the third step of either applying the bonding resin material on both of the above substrates;
A fourth stage in which the semiconductor substrate is turned upside down and superimposed on the integrated circuit substrate; and
A fifth step of removing only the semiconductor substrate, leaving the first electrode layer, the ferroelectric thin film and the second electrode on the integrated circuit substrate;
A sixth step of patterning the first electrode layer on the ferroelectric thin film to form a first electrode;
A seventh step of forming an electrode connection for connecting the electrode on the ferroelectric thin film to the extraction electrode on the integrated circuit substrate;
A method for manufacturing an integrated circuit substrate having a ferroelectric capacitor, comprising:   2. The method of manufacturing an integrated circuit substrate having a ferroelectric capacitor according to claim 1, wherein an inductor is formed on the integrated circuit substrate together with the electrode connection portion in the seventh stage. 3. .   3. The method of manufacturing an integrated circuit substrate having a ferroelectric capacitor according to claim 1, wherein the ferroelectric thin film is a BST thin film in the first stage.   4. The method of manufacturing an integrated circuit substrate having a ferroelectric capacitor according to claim 1, wherein the bonding resin material is removed after the seventh step.