JP2013197548A - Wiring board and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inhibit the movements of voids formed in a through-hole conductor.SOLUTION: A planar conductor 11c is formed on a first surface F1 of a substrate 10, and a planar conductor 12c is formed on a second surface F2 of the substrate 10. Further, the substrate 10 has a through hole 10h, and a through-hole conductor 10c connecting the planar conductor 11c with the planar conductor 12c is provided in the through hole 10h. The interior of the through-hole conductor 10c includes a void V1. An insulation layer 20 is formed on the first surface F1 of the substrate 10 and the planar conductor 11c. A conductor pattern 21c is formed on the insulation layer 20. Multiple openings 20h exposing parts of the planar conductor 11c are provided at the insulation layer 20, and a via conductor 20c connecting the planar conductor 11c with the conductor pattern 21c is formed in each opening 20h.

Description

  The present invention relates to a wiring board and a manufacturing method thereof.

  In the technique described in Patent Document 1, a small-diameter through hole is provided by irradiating laser on both surfaces of the core substrate. And the through-hole conductor which can connect both surfaces of a core board | substrate is formed by filling the inside of this through-hole with plating.

JP 2006-041463 A

  When the technique described in Patent Literature 1 is used to fill the inside of a small-diameter through hole with plating, a void may be formed inside the through-hole conductor. In addition, when a test was conducted to pass a large current through the through-hole conductor in which the void was formed, the movement of the void was recognized. The moving void may enter a conductor pattern or via conductor formed immediately above the through-hole conductor. As a result, the conductor resistance of the conductor pattern and via conductor increases, and connection reliability may be reduced.

  The present invention has been made under the circumstances described above, and an object thereof is to suppress the movement of voids formed inside through-hole conductors.

In order to achieve the above object, a wiring board according to the first aspect of the present invention comprises:
A core substrate having a first surface and a second surface opposite to the first surface, and having a through hole;
A first planar conductor formed on the first surface of the core substrate;
A second planar conductor formed on the second surface of the core substrate;
A through-hole conductor provided inside the through hole and connecting the first planar conductor and the second planar conductor;
An insulating layer formed on the first surface and the first planar conductor of the core substrate;
A conductor pattern formed on the insulating layer;
A wiring board having
The insulating layer is provided with a plurality of openings exposing a part of the first planar conductor,
Via conductors connecting the conductor pattern and the first planar conductor are formed inside each of the openings,
A void is included in the through-hole conductor.

  The width of the first planar conductor is preferably larger than the width of the through-hole conductor.

  It is preferable that the entire surface of one end of each of the plurality of via conductors is in contact with the first planar conductor.

The through hole has a first opening that opens in the first surface of the core substrate, and a second opening that opens in the second surface;
It is preferable that the center of gravity of the first opening and the center of gravity of the second opening are separated from each other on a plane parallel to the first surface.

The through-hole conductor has an end that comes into contact with the first planar conductor and becomes thicker as it is closer to the first surface.
The void is preferably included in the end portion.

  The thickness of the core substrate is preferably 400 μm or less.

  The distance between the center of gravity of the first opening and the center of gravity of the second opening in a plane parallel to the first surface is preferably 20 μm or less.

  The maximum width of the through hole is preferably 100 μm or less.

  Each of the plurality of via conductors preferably has substantially the same thickness.

  It is preferable that the total area of the surfaces in contact with each of the plurality of via conductors and the first planar conductor is equal to the area of the surface in contact with the through-hole conductor and the first planar conductor.

A method for manufacturing a wiring board according to a second aspect of the present invention includes:
Providing a core substrate having a first surface and a second surface opposite to the first surface;
Forming a through hole in the core substrate;
Forming a first planar conductor on the first surface of the core substrate;
Forming a second planar conductor on the second surface of the core substrate;
Forming a through-hole conductor connecting the first planar conductor and the second planar conductor in the through hole; and
Forming an insulating layer on the first surface of the core substrate and on the first planar conductor;
Forming a conductor pattern on the insulating layer;
A method of manufacturing a wiring board having
Inside the through-hole conductor, a void is included,
The insulating layer is provided with a plurality of openings exposing a part of the first planar conductor,
A via conductor connecting the conductor pattern and the first planar conductor is formed inside each of the openings.

  The width of the first planar conductor is preferably larger than the width of the through-hole conductor.

  It is preferable that the entire surface of one end of each of the plurality of via conductors is in contact with the first planar conductor.

The through hole has a first opening that opens in the first surface of the core substrate, and a second opening that opens in the second surface;
It is preferable that the center of gravity of the first opening and the center of gravity of the second opening are separated from each other on a plane parallel to the first surface.

The through-hole conductor has an end that comes into contact with the first planar conductor and becomes thicker as it is closer to the first surface.
The void is preferably included in the end portion.

  The thickness of the core substrate is preferably 400 μm or less.

  The distance between the center of gravity of the first opening and the center of gravity of the second opening in a plane parallel to the first surface is preferably 20 μm or less.

  The maximum width of the through hole is preferably 100 μm or less.

  According to the present invention, the movement of voids formed inside the through-hole conductor can be suppressed.

It is sectional drawing of the wiring board which concerns on embodiment of this invention. It is a perspective view which shows the shape of a through-hole and a through-hole conductor. It is a figure which shows the plating film formed in a through-hole. It is a figure which shows the positional relationship of a through-hole conductor, a planar conductor, and a some via conductor. It is a figure for demonstrating the process of preparing a double-sided copper clad laminated board. It is a figure for demonstrating the process of forming a through-hole. It is a figure for demonstrating the process of forming an electroless plating film. It is a figure for demonstrating the process of forming an electrolytic plating film. It is a figure for demonstrating the process of forming an etching resist. It is a figure for demonstrating the process of etching a conductor film. It is a figure for demonstrating the process of forming an insulating layer on both surfaces of a board | substrate. It is a figure for demonstrating the process of forming an opening part. It is a figure for demonstrating the process of forming an electroless plating film. It is a figure for demonstrating the process of forming a plating resist. It is a figure for demonstrating the process of forming an electrolytic plating film. It is a figure for demonstrating the process of etching an electroless plating film. It is sectional drawing of the wiring board which concerns on other embodiment. It is a figure which shows the positional relationship of the through-hole conductor which concerns on other embodiment, a planar conductor, and a some via conductor. It is a perspective view which shows the shape of the through-hole and through-hole conductor which concern on other embodiment. It is sectional drawing of the wiring board which concerns on other embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the figure, arrows Z1 and Z2 indicate the normal direction of the main surface (front and back surfaces) of the wiring board. This normal direction corresponds to the stacking direction of the wiring boards or the thickness direction of the wiring boards. On the other hand, each of arrows X1, X2, Y1, and Y2 indicates a direction orthogonal to the stacking direction. The main surface of the wiring board is an XY plane. The side surface of the wiring board is an XZ plane or a YZ plane. In the Z direction, the side closer to the core of the wiring board is called the inner layer side, and the side far from the core is called the outer layer side. Directly above means the outer layer side in the Z direction.

  The conductor layer is composed of one or more conductor patterns. The conductor pattern may include a wiring (including a ground), a pad, a land, or the like that constitutes an electric circuit, or may include a planar conductor pattern that does not constitute an electric circuit.

  The opening includes a hole and a groove. The hole is not limited to a through hole, and includes a non-through hole. The holes include via holes and through holes. A conductor formed inside the via hole is called a via conductor, and a conductor formed inside the through hole is called a through hole conductor.

  In addition to wet plating such as electrolytic plating, plating includes dry plating such as PVD (Physical Vapor Deposition) and CVD (Chemical Vapor Deposition).

  Unless otherwise specified, the “width” of the hole or column means a diameter in the case of a circle, and 2√ (cross-sectional area / π) otherwise. When the dimensions are not uniform (when there are irregularities or when they are tapered, etc.), in principle, the average value of the dimensions (average of only effective values excluding abnormal values) is used. However, this does not apply when it is clearly stated that a value other than the average value is used, such as the maximum value.

  As shown in FIG. 1, the wiring board 100 according to the present embodiment includes a substrate 10, insulating layers 20, 30, 40, 50 and conductor layers 11, 12, 21, 31, 41, 51. doing. The wiring board 100 is, for example, a rectangular wiring board. However, the present invention is not limited to this, and the wiring board 100 may have a shape other than the rectangular plate shape. Further, the wiring board 100 may be a flexible wiring board.

  The substrate 10 has an insulating property and corresponds to the core substrate of the wiring board 100. The substrate 10 is formed, for example, by laminating a base material 10b impregnated with an epoxy resin. This base material 10b is, for example, a glass cloth, and is made of an inorganic material such as glass fiber or aramid fiber. However, it is not limited to this, The material of the board | substrate 10 is arbitrary. Hereinafter, the main surface in the Z1 direction of the substrate 10 is referred to as a first surface F1, and the main surface in the Z2 direction is referred to as a second surface F2.

  The substrate 10 has an hourglass-shaped through hole 10h. The through-hole 10h has an opening 101h that narrows from the first surface F1 toward the second surface F2, and an opening 102h that narrows from the second surface toward the first surface.

  The opening 101h and the opening 102h are in contact with each other at the surface F3. As shown in FIG. 2, the surface F3 is defined by a constricted portion 103 where the wall surface of the opening 101h and the wall surface of the opening 102h intersect. Note that the reference for defining the surface F3 is not limited to the constricted portion 103. For example, the surface F3 can be defined as a minimal curved surface when the wall surface of the through hole 10h is used as a boundary condition.

  As shown in FIG. 2, the opening 101h has an opening 105 formed in the first surface F1, and the opening 102h has an opening 106 formed in the second surface F2. Both the widths of the openings 105 and 106 are equal to the maximum width of the through hole 10h. The maximum width of the through hole 10h is preferably 100 μm or less. The openings 105 and 106 according to the present embodiment have a circular shape in the XY plane, but are not limited thereto, and may have an arbitrary shape.

  The points G1 and G2 shown in FIG. 2 indicate the centers of gravity of the openings 105 and 106, respectively. A point G3 indicates an intersection between the first surface F1 and a straight line L1 passing through the point G2 and perpendicular to the first surface F1.

  It is preferable that the openings 105 and 106 face each other exactly. When the openings 105 and 106 are accurately opposed to each other, the distance D108 between the point G1 and the point G3 is zero. However, the distance D108 may be greater than zero due to various factors. This distance D108 is preferably 20 μm or less. The distance D108 is not limited to the first surface F1, but can be defined on an arbitrary plane parallel to the first surface F1. When the distance D108 is 20 μm or less, as shown in FIG. 3, the distance near the center of the through hole 10h (the length of the small diameter portion) is suppressed from becoming excessively large, and the vicinity of the center of the through hole 10h is electrolytically plated. It becomes easy to block | close with 107, and the plating filling to subsequent through-hole 10h becomes easy.

  A through-hole conductor 10c having the same shape as the through-hole 10h is provided inside the through-hole 10h. The through-hole conductor 10c is formed, for example, by performing copper plating on the wall surface of the through hole 10h.

  As shown in FIG. 2, the through-hole conductor 10 c has an end 101 c having a shape similar to that of the opening 101 h, and the end 101 c has a surface F 5 having a shape similar to that of the opening 105. The through-hole conductor 10c has an end 102c having the same shape as the opening 102h, and the end 102c has a surface F6 having the same shape as the opening 106.

  In addition, voids V1 and V2 are formed in the through-hole conductor 10c as shown in FIG. The voids V1 and V2 are, for example, bubbles formed when the through hole conductor 10c is provided in the through hole 10h. In the present embodiment, the void V1 is included in the end portion 101c (opening portion 101h), and the void V2 is included in the end portion 102c (opening portion 102h).

  On the first surface F <b> 1 of the substrate 10, the conductor layers 11, 21, 31 and the insulating layers 20, 30 are alternately stacked. On the second surface F2 of the substrate 10, the conductor layers 12, 41, 51 and the insulating layers 40, 50 are alternately stacked.

  Each of the insulating layers 20, 30, 40, and 50 has an insulating property and corresponds to an interlayer insulating layer. The insulating layers 20, 30, 40, and 50 all include an epoxy resin and an inorganic filler. However, it is not limited to this, The material of each insulating layer is arbitrary, For example, it may consist of resin other than an epoxy resin, and may contain the core material.

  The insulating layer 20 has a plurality of openings 20h. Each opening 20h is a via hole. Each of the openings 20h according to the present embodiment has a circular shape on the XY plane, but is not limited thereto, and the opening 20h may have an arbitrary shape. Similarly to the insulating layer 20, each of the insulating layers 30, 40, 50 has a plurality of openings.

  A via conductor 20c is provided inside each of the plurality of openings 20h. The via conductor 20c is, for example, a filled conductor that fills the opening 20h by performing copper plating on the wall surface and bottom surface of the opening 20h. Each of the via conductors 20c has substantially the same thickness. The via conductors 20c electrically connect the conductor layer 11 and the conductor layer 21 to each other.

  Similar to the via conductor 20c, the via conductor 30c is provided in each of the plurality of openings of the insulating layer 30. Each of the via conductors 30c has substantially the same thickness. The via conductors 30 c electrically connect the conductor layer 21 and the conductor layer 31. Each via conductor 30c is stacked immediately above each via conductor 20c.

  In addition, a via conductor 40 c that electrically connects the conductor layer 12 and the conductor layer 41 is provided in each of the plurality of openings 40 h of the insulating layer 40. In addition, a via conductor 50 c that electrically connects the conductor layer 41 and the conductor layer 51 is provided in each of the plurality of openings of the insulating layer 50. Each via conductor 50c is stacked immediately above each via conductor 40c.

  The conductor layer 11 is formed on the first surface F1 by, for example, copper plating. The conductor layer 12 is formed on the second surface F2 by, for example, copper plating. The conductor layer 11 has a planar conductor 11c, and the conductor layer 12 has a planar conductor 12c.

  The planar conductors 11c and 12c are, for example, lands of the through-hole conductor 10c and are formed at positions facing each other. Each of the planar conductors 11c and 12c has a circular shape in the XY plane, but is not limited thereto, and may have an arbitrary shape. The planar conductors 11c and 12c are electrically connected to each other through the through-hole conductor 10c.

  The conductor layer 21 is formed on the insulating layer 20. The conductor layer 21 has a conductor pattern 21c. The conductor pattern 21c is electrically connected to all of the plurality of via conductors 20c. The conductor pattern 21c is electrically connected to all of the plurality of via conductors 30c.

  Here, the positional relationship among the through-hole conductor 10c, the planar conductor 11c, the via conductor 20c, and the conductor pattern 21c in the XY plane will be described with reference to FIG.

  A surface F5 illustrated in FIG. 4 indicates a surface where the through-hole conductor 10c and the planar conductor 11c are in contact with each other. The width D10 of the surface F5 is equal to the maximum width of the through-hole conductor 10c.

  Also, as shown in FIG. 4, the width D11 of the planar conductor 11c is larger than the width D10 of the surface F5. The width D11 is, for example, 200 to 300 μm. Further, the width D10 is, for example, 100 μm. The width D10 is preferably 100 μm or less.

  A surface F201 illustrated in FIG. 4 indicates one end (bottom surface) of the via conductor 20c on the inner layer side. The entire surface of each surface F201 is in contact with the planar conductor 11c. A width D201 of the surface F201 is, for example, 50 μm.

  A surface F202 shown in FIG. 4 indicates one end on the outer layer side of the via conductor 20c. The width D202 of each surface F202 is larger than the width D201. Further, the entire surface of each surface F202 is in contact with the conductor pattern 21c.

  Note that the plurality of surfaces F201 shown in FIG. 4 all have substantially the same width D201, and the plurality of surfaces F202 all have substantially the same width 202.

  Returning to FIG. 1, the conductor layer 31 is formed on the insulating layer 30 and has a pad 31c. The pad 31c is, for example, a footprint for surface mounting electronic components. The pad 31c is in contact with the entire surface of one end on the outer layer side of each of the plurality of via conductors 30c.

  The conductor layer 41 is formed on the insulating layer 40. The conductor layer 41 has a conductor pattern 41c. The conductor layer 51 is formed on the insulating layer 50. The conductor layer 51 has a pad 51c. The pad 51c is in contact with the entire surface of one end on the outer layer side of each of the plurality of via conductors 50c.

  The planar conductor 12c, the via conductor 40c, the conductor pattern 41c, and the via conductor 50c, and the planar conductor 11c, the via conductor 20c, the conductor pattern 21c, and the via conductor 30c are arranged symmetrically with respect to the substrate 10. .

  The pads 31c and 51c are electrically connected to each other through the through-hole conductor 10c, the planar conductors 11c and 12c, the via conductors 20c, 30c, 40c, and 50c, and the conductor patterns 21c and 41c. The wiring from the pad 31c to the pad 51c is used for, for example, a power supply or a ground. When this wiring is used as a power source or the like, the power loss is reduced because the current path is short. However, the wiring from the pad 31c to the pad 51c can also be used as a signal wiring.

  As described above, in the wiring board 100 according to the present embodiment, the plurality of via conductors 20c are formed immediately above the through-hole conductor 10c including the void V1.

  When the current density of the current flowing through the conductor becomes non-uniform, tensile stress is generated in the conductor. And the copper atom which comprises a conductor moves to the one where tensile stress is higher. This phenomenon is known as so-called migration. As a result of this migration, the void V1 is considered to move in the Z1 direction.

  In the wiring board 100 according to the present embodiment, the current density of the current flowing through the through-hole conductor 10c, the planar conductor 11c, and the via conductor 20c is compared with the case where the single via conductor 20c is stacked on the through-hole conductor 10c. Is more uniform. Thereby, it is thought that the movement of the void V1 can be suppressed.

  Further, the width D11 of the planar conductor 11c according to the present embodiment is larger than the width D10 of the surface F5. Thereby, the planar conductor 11c and the through-hole conductor 10c can be reliably electrically connected.

  Further, each of the plurality of via conductors 20c according to the present embodiment has substantially the same thickness. Thereby, since the current flows uniformly to each of the plurality of via conductors 20c, it is possible to prevent the current density from becoming non-uniform. As a result, the movement of the void can be suppressed.

  Further, when the through-hole conductor 10c is formed in the hourglass-shaped through hole 10h as in the present embodiment, it is considered that voids are likely to occur. Moreover, when the board | substrate 10 has the base material 10b laminated | stacked like this embodiment, and when the distance D108 shown by FIG. 2 becomes larger than zero, it is thought that a void is easy to generate | occur | produce. Even in these cases, the wiring board 100 according to the present embodiment can suppress the movement of the void V1.

Further, as shown in FIG. 4, the area of the surface F5 where the through-hole conductor 10c and the planar conductor 11c are in contact is approximately 7850 μm ² (= 50 × 50 × 3.14). The total area of the surface F201 where the plurality of via conductors 20c and the planar conductor 11c contact is approximately 7850 μm ² (= 25 × 25 × 3.14 × 4), which is equal to the area of the surface F5. Thereby, the current density at the boundary between the through-hole conductor 10c and the planar conductor 11c is equal to the current density at the boundary between the planar conductor 11c and the plurality of via conductors 20c. As a result, the current density is made uniform and the movement of voids can be suppressed.

  The wiring board 100 according to the present embodiment can be electrically connected to, for example, an electronic component or another wiring board. For example, an electronic component (for example, an IC chip) can be mounted on the pad 31c or 51c by solder. Further, the wiring board 100 can be mounted on another wiring board (for example, a mother board) by the pads 31c and 51c.

  Then, the manufacturing method of the wiring board 100 is demonstrated, referring FIGS.

  First, as shown in FIG. 5, a double-sided copper-clad laminate 10p is prepared. The double-sided copper-clad laminate 10p includes a substrate 10, a copper foil 13 formed on the first surface F1 of the substrate 10, and a copper foil 14 formed on the second surface F2.

  Next, for example, both surfaces of the double-sided copper-clad laminate 10p are irradiated with CO2 laser or UV laser. Thereby, as shown in FIG. 6, a through hole 10 h having openings 101 h and 102 h is formed. Thereafter, desmear is applied to the through hole 10h. Note that laser irradiation may be performed on each side or on both sides simultaneously. Prior to laser irradiation, the surfaces of the copper foils 13 and 14 may be blackened.

  Next, for example, a catalyst such as Pd is applied to the wall surface of the through hole 10h. Thereafter, as shown in FIG. 7, an electroless plating film 15 made of, for example, copper is formed on the substrate surface including the wall surface of the through hole 10h by electroless plating. Note that the material of the electroless plating film 15 may be nickel, titanium, chromium, or the like. In addition to the electroless plating film 15, a sputtered film or a CVD film can also be used. In the case of a sputtered film or a CVD film, no catalyst is required.

  Next, as shown in FIG. 8, an electroplating film 16 is formed by electroplating using the electroless plating film 15 as a seed layer. Thereby, the electroless plating film 15 and the electrolytic plating 16 are filled in the through hole 10h, and the through-hole conductor 10c including the voids V1 and V2 is formed.

  Next, as shown in FIG. 9, an etching resist 17 is formed by, for example, a photolithography technique. The shape of the etching resist 17 corresponds to the conductor pattern (see FIG. 10) of the conductor layers 11 and 12.

  Next, portions of the conductor film formed on the first surface F1 and the second surface F2 of the substrate 10 that are not covered with the etching resist 17 are removed by etching. Thereby, as shown in FIG. 10, the conductor layer 11 having the planar conductor 11c and the conductor layer 12 having the planar conductor 12c are formed. Thereafter, if necessary, the surfaces of the conductor layers 11 and 12 are roughened to ensure adhesion with the insulating layers 20 and 40 provided on the outer layer side.

  Next, as shown in FIG. 11, the insulating layer 20 is pressure-bonded on the first surface F <b> 1 of the substrate 10 so as to cover the conductor layer 11. A copper foil 22 is formed on one surface of the insulating layer 20. Further, the insulating layer 40 is pressure-bonded on the second surface F2 of the substrate 10 so as to cover the conductor layer 12. A copper foil 42 is formed on one surface of the insulating layer 40.

  Next, the openings 20h and 40h are formed by laser irradiation. Specifically, as shown in FIG. 12, a plurality of openings 20 h are formed in the insulating layer 20, and a plurality of openings 40 h are formed in the insulating layer 40. Then, desmear is performed as needed.

  Next, a catalyst such as Pd is applied to the wall surfaces of the openings 20h and 40h. Then, as shown in FIG. 13, for example, by chemical plating, electroless plating films 23 and 43 made of copper are formed on the copper foils 22 and 42 and in the openings 20 h and 40 h. In addition, the material of the electroless plating films 23 and 43 is not limited to copper, and may be any, for example, nickel, titanium, or chromium.

  Next, a dry film is formed and patterned by a lithography technique. Thereby, as shown in FIG. 14, plating resists 24 and 44 having openings 24 h and 44 h are formed on the electroless plating films 23 and 43. The openings 24h and 44h of the plating resists 24 and 44 have patterns corresponding to the conductor patterns (see FIG. 16) of the conductor layers 21 and 41, respectively.

  Next, electrolytic plating films 25 and 45 are formed in the openings 24h and 44h by, for example, pattern plating. As a result, as shown in FIG. 15, electrolytic plating films 25 and 45 are filled in the openings 20h and 40h, respectively, and via conductors 20c and 40c made of copper are formed. The seed layer for electrolytic plating is not limited to the electroless plating film, and a sputtered film, a CVD film, or the like may be used as the seed layer.

  Thereafter, the plating resists 24 and 44 are removed using a predetermined stripping solution. Further, unnecessary electroless plating films 23 and 43 and copper foils 22 and 42 are removed (quick etching). Thereby, the conductor layers 21 and 41 are formed as shown in FIG.

  Next, the insulating layers 30 and 50 and the conductor layers 31 and 51 are formed in the same manner as the formation of the insulating layers 20 and 40 and the conductor layers 21 and 41.

  Through the above steps, the wiring board 100 according to the present embodiment is completed. Then perform electrical tests if necessary. A solder resist layer may be formed on the insulating layers 30 and 50 and the conductor layers 31 and 51. Further, external connection terminals (solder bumps) may be formed on the pads 31c and 51c.

  The manufacturing method according to the present embodiment is suitable for manufacturing the wiring board 100. It is considered that this manufacturing method can provide a good wiring board 100 at low cost.

  In this embodiment, the through-hole conductor 10c is formed by filling the through hole 10h with a conductor by plating. For this reason, resin filling and polishing processes are not required. As a result, the process can be simplified and the cost can be reduced.

  In addition, although the wiring board 100 is a double-sided printed wiring board which has a conductor layer on both surfaces of the board | substrate 10, the wiring board which can be manufactured is not limited to this. For example, the manufacturing method according to the present invention can also be applied to manufacturing a single-sided printed wiring board having a wiring layer only on one side of the substrate 10.

  As mentioned above, although embodiment of this invention was described, this invention is not limited by the said embodiment. For example, the following modifications can be made.

  The planar conductor 11c according to the above embodiment has a width larger than the width of the surface F5, but is not limited thereto. For example, as shown in FIG. 17, the width of the surface F5 and the width of the planar conductor 11c May be equal.

  In the insulating layer 20 according to the above embodiment, four via conductors 20c are formed as shown in FIG. 4, but the present invention is not limited to this. For example, as shown in FIG. 20c may be formed. Further, the number of via conductors 20c formed in the insulating layer 20 may be two or less, or five or more.

  The through-hole 10h and the through-hole conductor 10c according to the above embodiment were hourglass types. The through hole 10h and the through hole conductor 10c are not limited to this, and may have a substantially cylindrical shape as shown in FIG. 19, for example. In this case, it is difficult to define the surface F3 according to the above embodiment, but the surface is parallel to the first surface F1 and the distance from the first surface F1 is equal to the distance from the second surface F2. What is necessary is just to prescribe | regulate as the surface F3.

  Although the wiring board 100 according to the above embodiment is composed of six conductor layers, as shown in FIG. 20, it is also possible to constitute a wiring board having a multilayer conductor layer. In addition, a wiring board having fewer than six conductor layers can be configured.

  In the above embodiment, the end 101c of the through-hole conductor 10c includes the void V1, and the end 102c includes the void V2. However, the number and shape of the voids are not limited to this and are arbitrary. For example, like the through-hole conductor 10e shown in FIG. 20, a void V3 that intersects the plane F3 may be included.

  The via conductors 20c, 30c, 40c, and 50c according to the above embodiment have a structure (full stack structure) that is stacked up to the outermost layer, but is not limited thereto. For example, as shown in FIG. 20, the wiring board 100 may have a structure (partial stack structure) S1, S2, and S3 in which via conductors are partially stacked.

  Only the through-hole conductor 10c including the voids V1 and V2 was formed on the substrate 10 according to the above embodiment. For example, as illustrated in FIG. 20, a plurality of through-hole conductors 10 d and 10 e including voids may be formed on the substrate 10. In addition, a through-hole conductor 10f that does not include a void and does not have a plurality of via conductors directly above and through-hole conductors 10d and 10e that include a void may be mixed.

  In addition, the through-hole conductor 10c and the via conductor 20c according to the above embodiment are formed by filling the through hole 10h and the opening 20h with the conductor. The through hole conductor 10c and the via conductor 20c may be formed on the inner walls of the through hole 10h and the opening 20h. When the through-hole conductor 10c and the via conductor 20c are formed on the inner wall, the through-hole conductor 10c and the via conductor 20c are filled with resin or the like. In this case, a void (bubble) may be formed between the conductor and the resin. Even in such a case, the movement of the void can be suppressed by forming the via conductor 20c as in the above embodiment.

  In addition, the configuration of the wiring board 100, in particular, the type, performance, dimensions, material, shape, number of layers, or arrangement of the components can be arbitrarily changed without departing from the spirit of the present invention.

  Moreover, the manufacturing method of a wiring board is not limited to the order and content demonstrated in the said embodiment, In the range which does not deviate from the meaning of this invention, an order and content can be changed arbitrarily. Moreover, you may omit the process which is not required according to a use etc.

  For example, the formation method of each conductor layer is arbitrary. For example, any one of a panel plating method, a pattern plating method, a full additive method, a semi-additive (SAP) method, a subtractive method, a transfer method, and a tenting method, or a combination of any two or more thereof. A conductor layer may be formed.

  Further, instead of the laser, processing may be performed by wet or dry etching. In the case of processing by etching, it is considered preferable to protect a portion that is not desired to be removed in advance with a resist or the like.

  The said embodiment and modification can be combined arbitrarily. It is considered preferable to select an appropriate combination according to the application.

  The embodiment of the present invention has been described above. However, various modifications and combinations required for design reasons and other factors are not limited to the invention described in the “claims” or the “mode for carrying out the invention”. It should be understood that it is included in the scope of the invention corresponding to the specific examples described in the above.

DESCRIPTION OF SYMBOLS 10 Board | substrate 10b Base material 10c, 10d, 10e, 10f Through-hole conductor 10h Through-hole 100 Wiring board 101h, 102h Opening part 101c, 102c End part 103 Constriction part 105, 106 Opening 107 Electrolytic plating 10p Double-sided copper clad laminated board 11, 12 , 21, 31, 41, 51 Conductor layer 11c, 12c Planar conductor 13, 14, 22, 42 Copper foil 15, 23, 43 Electroless plating film 16, 25, 45 Electrolytic plating film 17 Etching resist 20, 30, 40 50 Insulating layer 20c, 30c, 40c, 50c Via conductor 20h, 24h, 40h, 44h, 101, 102 Opening 21c, 41c Conductive pattern 24, 44 Plating resist 31c, 51c Pad F1 First surface F2 Second surface F3, F5, F6, F201, F202 plane G1, G2, G3 S1, S2 structure V1, V2, V3 void

Claims (18)

A core substrate having a first surface and a second surface opposite to the first surface, and having a through hole;
A first planar conductor formed on the first surface of the core substrate;
A second planar conductor formed on the second surface of the core substrate;
A through-hole conductor provided inside the through hole and connecting the first planar conductor and the second planar conductor;
An insulating layer formed on the first surface and the first planar conductor of the core substrate;
A conductor pattern formed on the insulating layer;
A wiring board having
The insulating layer is provided with a plurality of openings exposing a part of the first planar conductor,
Via conductors connecting the conductor pattern and the first planar conductor are formed inside each of the openings,
The inside of the through-hole conductor contains a void,
Wiring board. A width of the first planar conductor is greater than a width of the through-hole conductor;
The wiring board according to claim 1. The entire surface of one end of each of the plurality of via conductors is in contact with the first planar conductor;
The wiring board according to claim 1 or 2. The through hole has a first opening that opens in the first surface of the core substrate, and a second opening that opens in the second surface;
The center of gravity of the first opening and the center of gravity of the second opening are separated from each other in a plane parallel to the first surface;
The wiring board according to any one of claims 1 to 3. The through-hole conductor has an end that comes into contact with the first planar conductor and becomes thicker as it is closer to the first surface.
The void is included in the end,
The wiring board according to any one of claims 1 to 4. The core substrate has a thickness of 400 μm or less.
The wiring board according to any one of claims 1 to 5. The distance between the center of gravity of the first opening and the center of gravity of the second opening in a plane parallel to the first surface is 20 μm or less.
The wiring board according to claim 4. The maximum width of the through hole is 100 μm or less.
The wiring board according to any one of claims 1 to 7. Each of the plurality of via conductors has substantially the same thickness.
The wiring board according to any one of claims 1 to 8. The total area of the surfaces where each of the plurality of via conductors and the first planar conductor are in contact is equal to the area of the surface where the through-hole conductor and the first planar conductor are in contact,
The wiring board according to any one of claims 1 to 9. Providing a core substrate having a first surface and a second surface opposite to the first surface;
Forming a through hole in the core substrate;
Forming a first planar conductor on the first surface of the core substrate;
Forming a second planar conductor on the second surface of the core substrate;
Forming a through-hole conductor connecting the first planar conductor and the second planar conductor in the through hole; and
Forming an insulating layer on the first surface of the core substrate and on the first planar conductor;
Forming a conductor pattern on the insulating layer;
A method of manufacturing a wiring board having
Inside the through-hole conductor, a void is included,
The insulating layer is provided with a plurality of openings exposing a part of the first planar conductor,
Forming a via conductor connecting the conductor pattern and the first planar conductor in each of the openings;
A method for manufacturing a wiring board. A width of the first planar conductor is greater than a width of the through-hole conductor;
The manufacturing method of the wiring board of Claim 11. The entire surface of one end of each of the plurality of via conductors is in contact with the first planar conductor;
The manufacturing method of the wiring board of Claim 11 or 12. The through hole has a first opening that opens in the first surface of the core substrate, and a second opening that opens in the second surface;
The center of gravity of the first opening and the center of gravity of the second opening are separated from each other in a plane parallel to the first surface;
The method for manufacturing a wiring board according to claim 11. The through-hole conductor has an end that comes into contact with the first planar conductor and becomes thicker as it is closer to the first surface.
The void is included in the end,
The manufacturing method of the wiring board of any one of Claims 11 thru | or 14. The core substrate has a thickness of 400 μm or less.
The manufacturing method of the wiring board of any one of Claims 11 thru | or 15. The distance between the center of gravity of the first opening and the center of gravity of the second opening in a plane parallel to the first surface is 20 μm or less.
The manufacturing method of the wiring board of Claim 14. The maximum width of the through hole is 100 μm or less.
The manufacturing method of the wiring board of any one of Claims 11 thru | or 17.

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