JP2013197172A - Resistance change memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a resistance change memory that is capable of suppressing power consumption at the time of switching of resistance of a resistance change layer.SOLUTION: A storage element 10 of a resistance change memory includes: a plate electrode 13; a fine wire electrode 16; and a resistance change layer 14 that is arranged between the plate electrode 13 and the fine wire electrode 16 and is made of a metallic oxide whose resistance changes due to application of a voltage between the plate electrode 13 and the fine wire electrode 16. Also, the storage element 10 includes a current barrier part 15 formed between the fine wire electrode 16 and the resistance change layer 14. Current is hard to flow through the current barrier part 15 in one current flow direction between the plate electrode 13 and the fine wire electrode 16 in comparison with the resistance change layer 14.

Description

  The technology of the present disclosure relates to a memory having a resistance change layer that is a layer in which a plurality of resistance values different from each other are held as information.

  A resistance change memory, which is a memory having a resistance change layer, is expected as a next-generation memory because it can operate at high speed and store multiple values. Among such resistance change layers, in the resistance change layer made of a binary metal oxide described in Patent Document 1, it is considered that the resistance value is switched by the mechanism described below.

  First, a conductive voltage is formed between two electrodes by applying a set voltage for writing information to the initial resistance change layer. When a reset voltage for erasing information written in the resistance change layer is applied, an electric field is formed in the resistance change layer, or a magnetic field is formed in the resistance change layer. The part disappears. Thereby, the resistance change layer is in a high resistance state in which the resistance value is relatively high.

  Next, when a set voltage is applied to the resistance change layer in the high resistance state, an electric field is formed in the resistance change layer, or a magnetic field is formed in the resistance change layer, and the lost conductive filament is again formed. It is formed. As a result, the resistance change layer is in a low resistance state in which the resistance value is relatively low.

JP 2004-363604 A

  By the way, in the resistance change memory, a set operation that is switching from the low resistance state to the high resistance state, a reset operation that is switching from the high resistance state to the low resistance state, and a read that is detection of the resistance value in the resistance change layer. In operation, power is consumed. In particular, since a relatively large current flows when switching the resistance value of the resistance change layer, the resistance change memory consumes relatively large power each time information is written to and erased from the storage element. Will end up. Therefore, the above-described resistance change memory is required to suppress the power consumed by switching the resistance in the resistance change layer.

  Note that in a resistance change memory using a multi-component metal oxide such as a perovskite-type metal oxide, it is considered that the mechanism of resistance change is different from that of a binary metal oxide. However, even in such a resistance change memory, the resistance value is switched by applying a voltage, and the power is consumed by applying the voltage. Therefore, the problem generally common to the above occurs.

  An object of the technology of the present disclosure is to provide a resistance change memory capable of suppressing power consumption when switching the resistance value of a resistance change layer.

Hereinafter, means for solving the above-described problems and the effects thereof will be described.
One aspect of the resistance change memory according to the present disclosure includes a resistance change layer and a write electrode that applies a write voltage to the resistance change layer, and the write electrode suppresses a current from flowing due to the application of the write voltage. A portion connected to the variable resistance layer through an energy barrier and connected to the variable resistance layer is formed as a fine dot that changes the resistance value of the variable resistance layer by the write voltage.

  According to the above-described aspect, the write electrode that changes the resistance value of the variable resistance layer is connected to the variable resistance layer via the energy barrier. Therefore, when a write voltage is applied to the variable resistance layer, Current flow is suppressed. And since the portion of the write electrode connected to the resistance change layer is formed in a minute dot shape so that the resistance value of the resistance change layer is changed even if no current flows due to the energy barrier, a plurality of different resistance values are information. In the resistance change memory treated as, the power consumption is suppressed.

Another aspect of the resistance change memory according to the present disclosure is a Schottky barrier in which the energy barrier is formed by a junction between the resistance change layer and the write electrode.
According to the above aspect, since the resistance change layer and the write electrode form a Schottky junction, the configuration of the resistance change memory is compared with the configuration in which the energy barrier is formed by a member different from the resistance change layer and the write electrode. Can be simplified.

  Another aspect of the resistance change memory according to the present disclosure further includes an energy barrier layer sandwiched between the resistance change layer and the write electrode, and the energy barrier layer is one of the resistance change layer and the write electrode. The Schottky barrier which is the energy barrier is formed by the junction with.

  According to the above aspect, since the energy barrier layer is sandwiched between the resistance change layer and the write electrode, the resistance change layer is formed as compared with the configuration in which the energy barrier is formed by joining the resistance change layer and the write electrode. It is also possible to expand the range of materials and the range of materials for forming the writing electrode.

  Another aspect of the resistance change memory according to the present disclosure further includes a read electrode that reads a resistance value of the resistance change layer, and the write electrode also serves as the read electrode and serves as a read voltage with respect to the Schottky barrier in a forward direction. Apply voltage.

  In the above-described aspect, since the write electrode also serves as the read electrode, the configuration of the resistance change memory can be simplified as compared with a configuration in which the write electrode and the read electrode are different from each other.

Another aspect of the resistance change memory according to the present disclosure further includes a read electrode that reads a resistance value of the resistance change layer, and the write electrode and the read electrode are different from each other.
In the above-described aspect, since the write electrode and the read electrode are different from each other, the write electrode does not receive restrictions necessary for reading the resistance value of the resistance change layer with respect to the electrode structure and the electrode material. Therefore, it is also possible to apply to the write electrode and the read electrode those specialized in the change in the resistance value of the resistance change layer with respect to the electrode structure and the electrode material.

  Another aspect of the resistance change memory according to the present disclosure further includes an insulating layer sandwiched between the resistance change layer and the write electrode, wherein the energy barrier includes a junction between the write electrode and the insulating layer, and the resistance change. It is formed by joining the layer and the insulating layer.

  In the above-described aspect, an energy barrier is formed by the junction between the write electrode and the insulating layer and the junction between the variable resistance layer and the insulating layer, so that the current flowing from the variable resistance layer to the write electrode and the resistance change from the write electrode Current can be reliably suppressed in the layer.

In another aspect of the resistance change memory according to the present disclosure, the resistance change layer is made of titanium oxide, and a portion of the write electrode that is in contact with the resistance change layer is made of rhodium or iridium. The area of the surface in contact with the variable resistance layer is 0.01 μm ² or less.

In the above aspect, the portion of the writing electrode that contacts the resistance change layer is made of either rhodium or iridium, and the contact area between the writing electrode and the resistance change layer is 0.01 μm ² or less, and the resistance change Since the layer is made of titanium oxide, a Schottky barrier is formed at the contact surface between the write electrode and the resistance change layer. According to such an aspect, since the energy barrier is formed by the write electrode and the resistance change layer, the number of steps necessary for forming the resistance change memory can be reduced.

In another aspect of the resistance change memory according to the present disclosure, the resistance change layer is made of titanium oxide, and the write electrode is made of a carbon nanotube.
In the above-described aspect, since the write electrode is made of carbon nanotubes and the variable resistance layer is made of titanium oxide, a Schottky barrier is formed at the contact surface between the write electrode and the variable resistance layer. According to such an aspect, the energy barrier is formed by the write electrode and the resistance change layer, so that the steps necessary for forming the resistance change memory can be reduced. In addition, according to the carbon nanotube, since it is easy to form a minute electrode having a diameter of about several tens of nanometers, it is possible to form a resistance change memory more than in the case of forming a minute electrode by processing another metal material. It will be easy.

FIG. 3 is a cross-sectional view showing a cross-sectional structure of a memory element constituting the first embodiment of the resistance change memory according to the present disclosure. FIG. 6 is an operation diagram illustrating a setting operation in the memory element according to the first embodiment. FIG. 6 is an operation diagram illustrating a reset operation in the memory element according to the first embodiment. FIG. 6 is an operation diagram showing a read operation in the memory element of the first embodiment. Sectional drawing which shows the cross-section of the memory element which comprises 2nd Embodiment of the resistance change memory in this indication. FIG. 9 is an operation diagram illustrating a setting operation in the memory element according to the second embodiment. FIG. 9 is an operation diagram illustrating a reset operation in the memory element according to the second embodiment. FIG. 9 is an operation diagram illustrating a read operation in the memory element according to the second embodiment. Sectional drawing which shows the cross-section of the memory element which comprises 3rd Embodiment of the resistance change memory in this indication. 3 is a current-voltage characteristic graph showing a relationship between a voltage applied to a memory element constituting the resistance change memory of Example 1 and a flowing current. 9 is a current-voltage characteristic graph showing a relationship between a voltage applied to a storage element constituting the resistance change memory of Example 2 and a flowing current. FIG. 9 is a cross-sectional view illustrating a cross-sectional structure of a memory element that constitutes a modification of the resistance change memory according to the present disclosure. FIG. 9 is a cross-sectional view illustrating a cross-sectional structure of a memory element that constitutes a modification of the resistance change memory according to the present disclosure. FIG. 9 is a cross-sectional view illustrating a cross-sectional structure of a memory element that constitutes a modification of the resistance change memory according to the present disclosure.

[First Embodiment]
Hereinafter, a first embodiment of a resistance change memory according to the present disclosure will be described with reference to FIGS. First, a schematic configuration of a memory element constituting the resistance change memory will be described with reference to FIG.

  As shown in FIG. 1, a plate-like electrode 13 is laminated on the base layer 12 formed on the substrate 11, and a resistance change layer 14 is laminated on a part of the upper surface of the plate-like electrode 13. Yes. A fine linear electrode 16 as a writing electrode is laminated on a part of the upper surface of the resistance change layer 14. In the present embodiment, the interface between the resistance change layer 14 and the fine linear electrode 16 is a current barrier portion 15 as an energy barrier, and the current barrier portion 15 is viewed from the direction facing the upper surface of the resistance change layer 14. It is in the form of fine dots. The resistance change layer 14, the plate-like electrode 13, and the fine linear electrode 16 constitute the memory element 10.

As the substrate 11, a semiconductor substrate such as a silicon substrate or a compound semiconductor substrate, or an insulator substrate such as a glass substrate, a quartz substrate, or a resin substrate is used.
For the underlayer 12, for example, various silicon compounds such as a silicon oxide layer and a silicon nitride layer are used. The underlayer 12 has an insulating property to electrically insulate the memory element 10 from elements other than the connection destination of the memory element 10 among the active elements and wirings formed on the upper surface of the substrate.

  The plate electrode 13 is made of a metal element included in Group 4 to Group 14. Further, the plate-like electrode 13 has a single layer structure made of the above-mentioned forming material or a laminated structure of two or more layers made of different forming materials among the above-mentioned forming materials.

The resistance change layer 14 includes a non-polar variable resistance material that can be switched between a high resistance state and a low resistance state according to an absolute value of a voltage applied to the resistance change layer 14, or a voltage applied to the resistance change layer 14. A bipolar variable resistance material that can be switched between a high-resistance state and a low-resistance state depending on the orientation is used. The nonpolar resistance change material includes one selected from the group consisting of titanium oxide, tungsten oxide, cobalt oxide, and tantalum oxide, or at least two of these oxides. A mixture is used. Note that one of the binary metal oxides or a mixture containing at least two of these oxides is not only used as a non-polar variable resistance material, but, for example, the writing electrode is a fine line as in this embodiment. Or a specific resistance change material and an electrode material, it also functions as a bipolar resistance change material. In addition to the above-described binary metal oxides, non-polar variable resistance materials include SrZrO ₃ , ZrTiO ₃ , Pb (Zr, Ti) O ₃ , Zn _0.4 Cd _0.6 S, Pr Perovskite oxides such as _0.7 Ca _0.3 MnO ₃ are used. As the bipolar variable resistance material, a chalcogenide material such as germanium-tin-tellurium or indium-tin-tellurium is used. Note that the variable resistance layer 14 has a single-layer structure made of the above-described forming material or a laminated structure of two or more layers made of different forming materials among the above-described forming materials. In the resistance change layer 14, the resistance value changes as follows according to the voltage applied between the plate-like electrode 13 and the fine linear electrode 16.

  That is, the set voltage Vset, which is a voltage at which the fine linear electrode 16 is negative with respect to the potential of the plate electrode 13 and has a relatively large absolute value or more than a predetermined threshold value, When applied to, the resistance change layer 14 transitions from the high resistance state to the low resistance state. In addition, when the reset voltage Vreset, which is a voltage at which the fine linear electrode 16 is positive with respect to the potential of the plate electrode 13 and has a relatively small absolute value, is applied, the resistance change layer 14 becomes low. Transition from the resistance state to the high resistance state.

  The fine linear electrode 16 has a circular column shape in which the diameter of the surface in contact with the resistance change layer 14 is 5 nm or more and 100 nm or less, or a rectangular column shape in which one side of the surface in contact with the resistance change layer 14 is 5 nm or more and 100 nm or less. It is a fine electrode made of a metal element included in Group 14 to Group 14 or a carbon nanotube. The fine linear electrode 16 has a single-layer structure made of the above-described forming material, or a laminated structure of two or more layers made of different forming materials among the above-mentioned forming materials, like the plate-like electrode 13. Is used.

  The current barrier portion 15 which is an interface between the variable resistance electrode 14 and the fine linear electrode 16 is such that the fine linear electrode 16 is made of the above-described forming material, and the fine linear electrode 16 and the variable resistance layer 14 are in contact with each other. The following first Schottky junction or the following second Schottky junction is formed because the part is a minute dot. That is, the forming material of the variable resistance layer 14 and the forming material of the fine linear electrode 16 and the area of the surface where the variable resistance layer 14 and the fine linear electrode 16 are in contact with each other are the first Schottky junction or , Selected from the combination in which the second Schottky junction is formed. Note that the number of such fine linear electrodes 16 is preferably 100 or less with respect to a rectangular plane having a side of 10 μm on the upper surface of the resistance change layer 14.

  In the first Schottky junction, when the power supply voltage Vss is applied to the plate electrode 13 and the set voltage Vset is applied to the fine linear electrode 16, the current barrier portion 15 that is a Schottky barrier is used. This is a junction through which a forward current flows from the plate electrode 13 to the fine linear electrode 16. The first Schottky junction is a current barrier portion 15 that is a Schottky barrier when the power supply voltage Vss is applied to the plate electrode 13 and the reset voltage Vreset is applied to the fine linear electrode 16. In this connection, the reverse current flowing from the fine linear electrode 16 to the plate electrode 13 is suppressed compared to the forward current.

  In the second Schottky junction, when the power supply voltage Vss is applied to the plate-like electrode 13 and the above-described reset voltage Vreset is applied to the fine linear electrode 16, the current Schottky junction is the current barrier portion 15 that is a Schottky barrier. This is a junction in which a current in the reverse direction flows from the fine linear electrode 16 to the plate electrode 13. The second Schottky junction is a current barrier portion 15 that is a Schottky barrier when the power supply voltage Vss is applied to the plate electrode 13 and the set voltage Vset is applied to the fine linear electrode 16. In this connection, forward current flowing from the plate electrode 13 to the fine linear electrode 16 is suppressed as compared with current in the reverse direction.

  When the above-described first Schottky junction is formed by the current barrier portion 15, the reverse current is less likely to flow in the memory element 10, and the forward current is relatively easier to flow. On the other hand, when the second Schottky junction described above is formed by the current barrier 15, in the memory element 10, the reverse current is relatively easy to flow and the forward current is relatively difficult to flow. .

  Next, the set operation, the reset operation, and the read operation in the memory element 10 will be described with reference to FIGS. First, the case where the current barrier unit 15 is the first Schottky junction will be described.

  As shown in FIG. 2, when a power supply voltage Vss of, for example, 0V is applied to the plate-like electrode 13 and a set voltage Vset of, for example, −5.0V is applied to the fine linear electrode 16, the plate-like electrode 13. An electric field directed from 1 to the fine linear electrode 16 is locally formed in the resistance change layer 14. Then, when the set current Iset that is a forward current flows through the resistance change layer 14, the resistance change layer 14 transitions from the high resistance state to the low resistance state.

  As shown in FIG. 3, when the power supply voltage Vss is applied to the plate-like electrode 13 and the reset voltage Vreset of 2.0 V, for example, is applied to the fine linear electrode 16 as a writing voltage, the fine linear electrode 16 An electric field from the first electrode to the plate electrode 13 is locally formed in the resistance change layer 14. Alternatively, a magnetic field accompanying such a change in voltage is locally formed in the resistance change layer 14. At this time, the electric field or the magnetic field described above acts locally while the reverse current flowing from the fine linear electrode 16 to the plate electrode 13 is suppressed by the current barrier unit 15 which is a Schottky barrier. Thus, the resistance change layer 14 transitions from the low resistance state to the high resistance state. That is, the memory element 10 writes that the resistance change layer 14 is in a high resistance state.

  As shown in FIG. 4, a power supply voltage Vss is applied to the plate electrode 13 and a negative voltage having a smaller absolute value than the set voltage Vset, for example, a read voltage Vsens of −1.0 V is fine as a read voltage. When applied to the linear electrode 16, a forward read current Isens corresponding to the resistance state of the resistance change layer 14 is detected outside the memory element 10. That is, it is read out whether the resistance change layer 14 is in a low resistance state or a high resistance state.

  Therefore, in the memory element 10 having the first Schottky junction, the resistance state in the resistance change layer 14 is switched by changing the direction of the voltage applied to the resistance change layer 14 or the absolute value. Then, when the resistance change layer 14 transitions from the low resistance state to the high resistance state, the current barrier portion 15 that is a Schottky barrier suppresses a current in the reverse direction from flowing. Thereby, compared with the case where such a current barrier part 15 is not formed, the electric power consumed when switching the resistance value of the resistance change layer 14 can be suppressed.

  When the second Schottky junction is formed in the current barrier portion 15, the power supply voltage Vss is applied to the plate electrode 13 and the set voltage Vset is applied as the write voltage to the fine linear electrode 16. As a result, the set operation is performed. At this time, the forward current flowing from the plate-like electrode 13 toward the fine linear electrode 16 is suppressed by the current barrier portion 15 which is a Schottky barrier. Further, the reset operation is performed by applying the power supply voltage Vss to the plate electrode 13 and applying the reset voltage Vreset to the fine linear electrode 16. At this time, a current in the reverse direction from the fine linear electrode 16 toward the plate electrode 13 flows through the current barrier portion 15 which is a Schottky barrier. Then, the power supply voltage Vss is applied to the fine linear electrode 16 and the read voltage Vsens is applied to the plate electrode 13 as a read voltage, so that a reverse read current corresponding to the resistance state of the resistance change layer 14 is obtained. Isens is detected outside the storage element 10.

  The resistance change memory including the memory element 10 described above is, for example, a 1T1R type having one transistor and one memory element 10 as a unit structure of the resistance change memory, or a rectifier element and the memory element 10 as a unit structure of the resistance change memory. And 1D1R type having one each. For example, in the 1T1R type, the drain of the transistor is connected to the fine linear electrode 16, and the plate electrode 13 is connected to the GND line. Then, the set voltage Vset, the reset voltage Vreset, and the read voltage Vsens are applied to the fine linear electrode 16 separately by the potential difference between the gate and the source of the transistor. Accordingly, the memory element 10 connected to the selected transistor by selecting the word line to which the gates of two or more transistors are connected and selecting the bit line to which the sources of the two or more transistors are connected. Any of the set operation, the reset operation, and the read operation described above is performed.

As described above, according to the first embodiment of the resistance change memory of the present disclosure, the effects listed below can be obtained.
(1) Since the fine linear electrode 16 that changes the resistance value of the resistance change layer 14 is connected to the resistance change layer 14 via a Schottky barrier, when the set voltage Vset is applied to the resistance change layer 14, Alternatively, when the reset voltage Vreset is applied to the resistance change layer 14, it is possible to suppress a current from flowing through the resistance change layer 14. The portions of the fine linear electrodes 16 connected to the resistance change layer 14 are made minute dots so that the resistance value of the resistance change layer 14 is changed even if no current flows due to the Schottky barrier, and therefore different from each other. In a resistance change memory in which a plurality of resistance values are handled as information, power consumption can be suppressed.

  (2) Moreover, since the variable resistance layer 14 and the fine linear electrode 16 form a Schottky junction, the energy barrier is formed by a member different from the variable resistance layer 14 and the fine linear electrode 16. It is possible to simplify the configuration of the resistance change memory.

  (3) The fine linear electrode 16 functions as an electrode that writes a resistance value, which is information, to the resistance change layer 14, and also functions as an electrode that reads the resistance value in the resistance change layer 14. Therefore, the configuration of the resistance change memory can be simplified as compared with a configuration in which the write electrode and the read electrode are different from each other.

(4) The difference in switching of the resistance state depending on the size of the contact area between the resistance change layer 14 and the fine linear electrode 16 is that the diameter of the contact area or one side of the contact area is about 50 nm or less. Electric field concentration is likely to occur in the change layer 14. Therefore, even when a current that flows in the forward direction of the Schottky barrier flows, the resistance state is easily changed by the assistance of such an electric field, so the power required for switching the resistance state at that time should be reduced. Is also possible.
[Second Embodiment]
Hereinafter, a second embodiment of the resistance change memory according to the present disclosure will be described with reference to FIGS. The memory element of the resistance change memory in the second embodiment is provided with three electrodes for applying a voltage to the resistance change layer, as compared with the memory element of the resistance change memory in the first embodiment described above. Is different. Therefore, in the following, such differences will be described in detail.

  As shown in FIG. 5, a resistance change layer 33 including a current barrier portion 34 and a fine linear electrode 35 are stacked on a part of the upper surface of the base layer 32 on the substrate 31. Further, assuming that the direction in which the resistance change layer 33 and the fine linear electrode 35 are laminated on the base layer 32 is a lamination direction and the direction perpendicular to the lamination direction is a plane direction, both end portions in the surface direction of the resistance change layer 33 The first plate electrode 36 and the second plate electrode 37 are formed so as to sandwich the resistance change layer 33 in the surface direction. In the present embodiment, the memory element 30 is configured by the fine linear electrode 35 including the current barrier portion 34, the resistance change layer 33, the first plate electrode 36, and the second plate electrode 37.

  The substrate 31, the base layer 32, the resistance change layer 33, and the fine linear electrode 35 include the substrate 11, the base layer 12, the resistance change layer 14, and the fine linear electrode 16 in the first embodiment, respectively. The same material is used. Further, the same material as that of the plate electrode 13 in the first embodiment is used for the first plate electrode 36 and the second plate electrode 37. The current barrier portion 34 as an energy barrier, which is an interface with the variable resistance layer 33 in the fine linear electrode 35, includes the fine linear electrode 35 made of the above-described forming material, and the resistance change with the fine linear electrode 35. Since the portion in contact with the layer 33 is minute, the first Schottky junction described above or the second Schottky junction described above is formed as in the first embodiment.

  Next, the set operation, the reset operation, and the read operation in the memory element 30 described above will be described with reference to FIGS. First, the case where the current barrier part 34 is the first Schottky junction will be described.

  As shown in FIG. 6, a power supply voltage Vss of, for example, 0V is applied to the first plate electrode 36 and the second plate electrode 37, and a set voltage Vset of, for example, -5.0V is applied to the fine linear electrode 35. Is applied, the electric field from the first plate electrode 36 and the second plate electrode 37 toward the fine linear electrode 35 is locally formed in the resistance change layer 33. When the set current Iset flows from the first plate electrode 36 and the second plate electrode 37 toward the fine linear electrode 35, the resistance change layer 33 transitions from the high resistance state to the low resistance state.

  As shown in FIG. 7, for example, a power supply voltage Vss of 0 V is applied to the first plate electrode 36 and the second plate electrode 37, and a reset voltage Vreset of 2.0 V, for example, is applied to the fine linear electrode 35. When applied as a write voltage, an electric field directed from the first plate electrode 36 and the second plate electrode 37 toward the fine linear electrode 35 is locally formed. Alternatively, a magnetic field accompanying such a change in voltage is locally formed in the resistance change layer 33. At this time, in the current barrier portion 34 which is a Schottky barrier, while the reverse current flowing from the fine linear electrode 35 to the first plate electrode 36 and the second plate electrode 37 is suppressed, the above-described electric field, Alternatively, when the magnetic field acts locally, the resistance change layer 33 transitions from the low resistance state to the high resistance state. That is, the memory element 30 writes that the resistance change layer 33 is in the high resistance state.

  As shown in FIG. 8, for example, a power supply voltage Vss of 0 V is applied to the first plate electrode 36, a read voltage Vsens of −1.0 V, for example, is applied to the second plate electrode 37 as a read voltage, and For example, a power supply voltage Vss of 0 V is applied to the fine linear electrode 35. As a result, the read current Isens corresponding to the resistance state of the resistance change layer 33 is detected outside the storage element 30. That is, it is read out whether the resistance change layer 33 is in a low resistance state or a high resistance state.

  Therefore, in the memory element 30 having the first Schottky junction, as in the first embodiment, when the variable resistance layer 33 transitions from the low resistance state to the high resistance state, the current barrier portion 34 that is a Schottky barrier is Suppresses reverse current flow. Thereby, compared with the case where such a current barrier part 34 is not formed, the electric power consumed when switching the resistance value of the resistance change layer 33 can be suppressed. In addition, since no Schottky barrier is formed between the first plate electrode 36 and the resistance change layer 33 and between the second plate electrode 37 and the resistance change layer 33, the read voltage Vsens is If the voltage is different from the power supply voltage Vss, the read current Isens flows. Therefore, the memory element 30 can detect the resistance state of the resistance change layer 33 without being restricted by the absolute value of the read voltage Vsens being smaller than the set voltage Vset.

  When the second Schottky junction is formed in the current barrier portion 34, the set voltage Vset is applied as the write voltage to the first plate electrode 36 and the second plate electrode 37, and fine The set operation is performed by applying the power supply voltage Vss to the linear electrode 35. At this time, the forward current flowing from the first plate electrode 36 and the second plate electrode 37 toward the fine linear electrode 35 is suppressed by the current barrier portion 34 that is a Schottky barrier. Further, the reset operation is performed by applying the reset voltage Vreset to the first plate electrode 36 and the second plate electrode 37 and applying the power supply voltage Vss to the fine linear electrode 35. At this time, a current in a reverse direction from the fine linear electrode 35 toward the first plate electrode 36 and the second plate electrode 37 flows through the current barrier portion 34 that is a Schottky barrier. The power supply voltage Vss is applied to the first plate electrode 36 and the fine linear electrode 35, and the lead voltage Vsens is applied to the second plate electrode 37, whereby the resistance change layer 33 is brought into the resistance state. The corresponding read current Isens is detected outside the storage element 30.

  The resistance change memory including the memory element 30 described above is, for example, a 2T1R type having two transistors and the memory element 30 as a unit structure of the resistance change memory, or two rectifying elements as a unit structure of the resistance change memory, for example. The 2D1R type having the memory element 30 is embodied. For example, the drain of the first transistor is connected to the fine linear electrode 35, and the first plate electrode 36 is connected to the GND line. The drain of the second transistor is connected to the second plate electrode 37. Then, the set voltage Vset, the reset voltage Vreset, and the power supply voltage Vss are applied to the fine linear electrode 35 separately by the potential difference between the gate and the source of the first transistor. Further, the power supply voltage Vss and the read voltage Vsens are applied to the second plate electrode 37 separately by the potential difference between the gate and the source of the second transistor. As a result, any one of the above-described set operation, reset operation, and read operation is performed in the memory element 30 connected to the selected transistor.

As described above, according to the second embodiment of the resistance change memory of the present disclosure, the following effects can be obtained in addition to the effects obtained in the first embodiment.
(5) Since the fine linear electrode 35 that writes the resistance value as information to the resistance change layer 33 and the second plate electrode 37 that reads the resistance value in the resistance change layer 33 are different from each other, the electrode structure and the electrode material On the other hand, the fine linear electrode 35 does not receive the restriction required for reading the resistance value of the resistance change layer 33. Therefore, what is specialized for changing the resistance value in the resistance change layer 33 with respect to the electrode structure and the electrode material is applied to the fine linear electrode 35, and the resistance value is read out in the resistance change layer 33. Therefore, it is possible to apply a specialized one to the second plate electrode 37. For example, a voltage different from the voltage applied to the first plate electrode 36 is applied to the second plate electrode 37 without being restricted by the absolute value of the read voltage Vsens being smaller than the set voltage Vset. The resistance state of the resistance change layer 33 can be detected.
[Third Embodiment]
Hereinafter, a third embodiment of the resistance change memory according to the present disclosure will be described with reference to FIG. 9. Note that the memory element of the resistance change memory according to the third embodiment has a different current barrier configuration from the memory element of the resistance change memory according to the second embodiment described above. Therefore, in the following, such differences will be described in detail.

  As illustrated in FIG. 9, a resistance change layer 33 and a current barrier layer 38 are sequentially stacked on a part of the upper surface of the base layer 32 on the substrate 31. A fine linear electrode 35 is laminated on a part of the upper surface of the current barrier layer 38. Further, similarly to the second embodiment, the first plate electrode 36 and the second plate electrode 37 sandwich the resistance change layer 33 in the surface direction at both ends in the surface direction of the resistance change layer 33. It is connected. In the present embodiment, the resistance change layer 33, the fine linear electrode 35, the first plate electrode 36, the second plate electrode 37, and the current barrier layer 38 constitute the memory element 40.

  The current barrier layer 38 is an insulating film made of a silicon compound such as silicon oxide or silicon nitride, or a metal compound such as a metal oxide or metal nitride having a band gap comparable to these, and changes in resistance. The layer 33 is formed on the entire top surface. The current barrier layer 38 has a single-layer structure made of the above-described forming material or a stacked structure of two or more layers made of different forming materials among the above-described forming materials. That is, an insulating barrier composed of the current barrier layer 38 is formed at the interface between the current barrier layer 38 and the fine linear electrode 35 and the interface between the current barrier layer 38 and the resistance change layer 33. Regardless of the voltage value applied to, current flowing between the resistance change layer 33 and the fine linear electrode 35 is suppressed. Such a current barrier layer 38 constitutes an energy barrier layer and an insulating layer.

  Next, the set operation, the reset operation, and the read operation in the memory element 40 will be described. In the various operations in the memory element 40 described above, the voltages applied to the fine linear electrode 35, the first plate electrode 36, and the second plate electrode 37 are the same as those in the second embodiment, and the set The value of the current flowing through the resistance change layer 33 differs between the operation and the reset operation. Therefore, these differences will be described in detail below.

  First, in the set operation, a power supply voltage Vss of, for example, 0 V is applied to the first plate electrode 36 and the second plate electrode 37, and a set voltage Vset of, for example, −5.0 V is written to the fine linear electrode 35. Applied as a voltage. At this time, an electric field from the first plate electrode 36 and the second plate electrode 37 toward the fine linear electrode 35 is locally formed in the resistance change layer 33. The current or magnetic field described above is locally generated while the current flowing from the fine linear electrode 35 to the first plate electrode 36 and the second plate electrode 37 is suppressed by the current barrier layer 38 which is an insulating barrier. Thus, the resistance change layer 33 transitions from the low resistance state to the high resistance state. That is, the fact that the resistance change layer 33 is in the high resistance state is written in the memory element 40.

  Next, in the reset operation, a power supply voltage Vss of, for example, 0V is applied to the first plate electrode 36 and the second plate electrode 37, and a reset voltage Vreset of, for example, 2.0V is applied to the fine linear electrode 35 as a write voltage. As applied. At this time, an electric field directed from the first plate electrode 36 and the second plate electrode 37 toward the fine linear electrode 35 is locally formed. Alternatively, a magnetic field accompanying such a change in voltage is locally formed in the resistance change layer 33. Then, in the current barrier layer 38 which is an insulating barrier, while the reverse current flowing from the fine linear electrode 35 to the first plate electrode 36 and the second plate electrode 37 is suppressed, the above electric field, or When the magnetic field acts locally, the resistance change layer 33 transitions from the high resistance state to the low resistance state. That is, it is written in the memory element 40 that the resistance change layer 33 is in the low resistance state.

  At this time, in the memory element 40 having an insulating barrier, both when the resistance change layer 33 transits from the low resistance state to the high resistance state and when the resistance change layer 33 transits from the high resistance state to the low resistance state. The current barrier layer 38 which is an insulating barrier suppresses the flow of current. Thereby, compared with the case where such a current barrier layer 38 is not formed, the electric power consumed when switching the resistance value of the resistance change layer 33 can be suppressed.

  As described above, according to the third embodiment of the resistance change memory of the present disclosure, in addition to the effects obtained in the first embodiment and the effects obtained in the second embodiment, the following effects can be obtained. Can be obtained.

  (6) Since the energy barrier is formed by the junction of the fine linear electrode 35 and the current barrier layer 38 and the junction of the resistance change layer 33 and the current barrier layer 38, the resistance change layer 33 to the fine linear electrode 35. And the current flowing from the fine linear electrode 35 to the resistance change layer 33 can be reliably suppressed.

[Example 1]
A titanium layer as a plate electrode 13 was formed by sputtering on a silicon substrate having a thermal oxide film, and a titanium oxide layer was formed by sputtering as a resistance change layer 14 on the titanium layer. The titanium oxide layer was formed by sputtering a titanium dioxide target with an argon gas flow rate of 9.5 sccm, an oxygen gas flow rate of 0.5 sccm, a deposition pressure of 0.5 Pa, and a target power of 200 W. The thickness of the titanium oxide layer was 30 nm. And the fine linear electrode 16 whose diameter of a contact surface with the resistance change layer 14 is 30 nm was formed with rhodium, and the memory element of Example 1 was obtained. The measurement result of the current-voltage characteristic obtained from this memory element is shown in FIG. 10 indicates the potential of the fine linear electrode 16 relative to the potential of the plate electrode 13, minus indicates that the fine linear electrode 16 is lower than the potential of the plate electrode 13, and plus indicates This indicates that the fine linear electrode 16 is higher than the potential of the plate electrode 13. Also, the solid line in FIG. 10 shows the current-voltage characteristics when the resistance change layer 14 is in the high resistance state, and the alternate long and short dash line in FIG. 10 shows the current-voltage characteristics when the resistance change layer 14 is in the low resistance state. Indicates.

  As shown in FIG. 10, a state in which no current flows between the plate-like electrode 13 and the fine linear electrode 16 at a bias voltage of −0.5V is defined as an initial state, and a bias voltage of −3.0V from the initial state. It was confirmed that a current of −0.5 nA flows between the plate electrode 13 and the fine linear electrode 16 with a bias voltage of −0.5V. Accordingly, it was recognized that the resistance change layer 14 was switched from the high resistance state to the low resistance state by the set voltage Vset of −3.0V.

  Next, when a bias voltage of 1.0 V is applied to the resistance change layer 14 in the low resistance state, a current flows between the plate electrode 13 and the fine linear electrode 16 with a bias voltage of −0.5 V. It was recognized that there was no. Accordingly, it was recognized that the resistance change layer 14 is switched from the low resistance state to the high resistance state by the reset voltage Vreset of 1.0 V.

  Through the measurement of the current-voltage characteristics, it was confirmed that no current flows between the plate electrode 13 and the fine linear electrode 16 at a positive bias voltage. Accordingly, it was recognized that a Schottky barrier that suppresses a current flowing from the resistance change layer 14 to the fine linear electrode 16 is formed at the interface between the resistance change layer 14 and the fine linear electrode 16.

[Example 2]
An electrode in which rhodium is adhered to the surface of acicular silicon is used as a fine linear electrode 16, and the diameter of the contact surface between rhodium and the resistance change layer in the fine linear electrode 16 is 50 nm. A memory element of Example 2 was obtained using the same configuration as in Example 1. FIG. 11 shows the result of measuring the current-voltage characteristics of this memory element under the same conditions as in Example 1. In FIG. 11, similarly to FIG. 10 described above, minus indicates that the fine linear electrode 16 is lower than the potential of the plate electrode 13, and plus indicates finer than the potential of the plate electrode 13. It shows that the linear electrode 16 is high.

  As shown in FIG. 11, it was confirmed that the current-voltage characteristic equivalent to the current-voltage characteristic shown in FIG. 10 which is the result obtained in Example 1 was obtained. That is, it is recognized that the resistance change layer 14 is switched from the high resistance state to the low resistance state by the set voltage Vset of −3.0 V, and the resistance change layer 14 is in the low resistance state by the reset voltage Vreset of 1.0 V. It was observed that the switch to the high resistance state. It was recognized that a Schottky barrier that suppresses the current flowing from the resistance change layer 14 to the fine linear electrode 16 is formed at the interface between the resistance change layer 14 and the fine linear electrode 16.

[Example 3]
A carbon nanotube having a diameter of about 5 nm was used as the fine linear electrode 16, and the same configuration as in Example 1 was used for the other configuration, so that a memory element of Example 3 was obtained. When the current-voltage characteristics of this memory element were measured under the same conditions as in Example 1, results equivalent to those in Example 1 and Example 2 were obtained. That is, it is recognized that a Schottky barrier that suppresses the current flowing from the resistance change layer 14 to the fine linear electrode 16 is also formed at the interface between the fine linear electrode 16 made of carbon nanotubes and the resistance change layer 14. It was.

[Example 4]
A titanium oxide layer was formed by sputtering as the resistance change layer 33 on the silicon substrate having the thermal oxide film. Further, by forming a titanium layer as the first plate electrode 36 and the second plate electrode 37 on the resistance change layer 33 by sputtering and further forming carbon nanotubes as the fine linear electrode 35, FIG. A memory element of Example 4 having the structure shown in FIG. The diameter of the carbon nanotube is about 5 nm.

  In this memory element, a power supply voltage Vss of 0 V is applied to the first plate electrode 36 and the second plate electrode 37, and a voltage of −1.0 V is applied to the fine linear electrode 35, thereby forming a fine linear shape. A state where no current flows through the electrode 35 is defined as an initial state. From the initial state, it was recognized that when a voltage of −5.0 V was applied to the fine linear electrode 35, a current of −5.0 nA was flowing in the fine linear electrode 35. Accordingly, it was recognized that the resistance change layer 33 was switched from the high resistance state to the low resistance state by the set voltage Vset of −5.0V. At this time, when a power supply voltage Vss of 0 V is applied to the first plate electrode 36 and the fine linear electrode 35 and a voltage of −1.0 V is applied to the second plate electrode 37 as the lead voltage Vsens. It was confirmed that a current of -0.5 nA flows as the read current Isens.

  Next, when the power supply voltage Vss of 0 V is applied to the first plate electrode 36 and the second plate electrode 37 and the voltage of 2.0 V is applied to the fine linear electrode 35, the above-described reading operation is performed. Thus, it was confirmed that the read current Isens was 0.1 pA or less, and it was almost in an insulating state. Accordingly, it was recognized that the resistance change layer 14 was switched from the low resistance state to the high resistance state by the reset voltage Vreset of 2.0V.

  Further, through the measurement of the current-voltage characteristics, the current flowing from the fine linear electrode 35 to the first plate electrode 36 and the current flowing from the fine linear electrode 35 to the second plate electrode 37 were not recognized. Accordingly, even in such a memory element, a Schottky barrier that suppresses a current flowing from the resistance change layer 33 to the fine linear electrode 35 is formed at the interface between the resistance change layer 33 and the fine linear electrode 35. Admitted.

[Example 5]
A memory element of Example 5 having the structure of FIG. 9 was obtained by using a silicon oxide film having a thickness of 1 nm as the current barrier layer 38 and using the same configuration as that of Example 4 for other configurations.

  In this memory element as well, as in Example 4, when the set voltage Vset of −5.0 V is applied to the fine linear electrode 35, it is recognized that the resistance change layer 33 is switched from the high resistance state to the low resistance state. It was. Further, it was recognized that when the reset voltage Vreset of 2.0 V is applied to the fine linear electrode 35, the resistance change layer 33 is switched from the low resistance state to the high resistance state. During this time, the current flowing from the fine linear electrode 35 to the first plate electrode 36 through the current barrier layer 38 and the current flowing from the fine linear electrode 35 to the second plate electrode 37 through the current barrier layer 38 are not recognized. It was.

[Example 6]
A rhodium magnetized by an external magnetic field was used as the fine linear electrode 35, and the same configuration as that of Example 4 was used for the other configuration, thereby obtaining a memory element of Example 5. In addition, the diameter of the contact surface with the resistance change layer 33 in the fine linear electrode 35 was 30 nm.

  In this memory element, a power supply voltage Vss of 0 V is applied to the first plate electrode 36 and the second plate electrode 37, and an external magnetic field from the resistance change layer 33 toward the fine linear electrode 35 is applied. A state in which no current flows through the linear electrode 35 is defined as an initial state. From the initial state, it was recognized that when the external magnetic field was reversed, a current of −5.0 nA was flowing in the fine linear electrode 35. Accordingly, it was recognized that the resistance change layer 33 was switched from the high resistance state to the low resistance state by the external magnetic field from the fine linear electrode 35 toward the resistance change layer 33. At this time, when a power supply voltage Vss of 0V is applied to the first plate electrode 36 and a voltage of −1.0V is applied to the second plate electrode 37 as a read voltage Vsens, −0 as a read current Isens. A current of .5 nA was observed to flow.

  Next, when a power supply voltage Vss of 0 V is applied to the first plate electrode 36 and the second plate electrode 37 and an external magnetic field from the resistance change layer 33 toward the fine linear electrode 35 is applied, In the reading operation, it was confirmed that the read current Isens was 0.1 pA or less and was almost in an insulating state. Thus, it was recognized that the resistance change layer 14 was switched from the low resistance state to the high resistance state by an external magnetic field directed from the resistance change layer 33 to the fine linear electrode 35.

  This switching of the resistance state by an electric field or a magnetic field suggests that charges are accumulated in the current barrier part that is a Schottky barrier or the current barrier layer that is an insulating barrier, thereby maintaining the resistance state. Yes.

[Comparative Example 1]
A fine linear electrode 16 having a contact surface with the resistance change layer 14 having a diameter of 30 nm was formed of gold, and the memory element of Comparative Example 1 was obtained by using the same configuration as that of Example 1 for other configurations. When the current-voltage characteristics of the memory element of Comparative Example 1 were measured under the same conditions as in Example 1, it was recognized that current flowed even when switching from the low resistance state to the high resistance state. In other words, it was recognized that a Schottky barrier serving as a barrier against a current from the resistance change layer to the upper electrode was not formed on the contact surface between the resistance change layer and the upper electrode.

In addition, each above-mentioned embodiment can also be suitably changed and implemented as follows.
The current barrier 15 in the first embodiment may be a layer different from the resistance change layer 14. Further, the current barrier section 34 in the second embodiment may be a layer different from the resistance change layer 33. For example, as shown in FIG. 12, a plate electrode 13 and a resistance change layer 14 are sequentially stacked on the base layer 12 formed on the substrate 11, and the entire upper surface of the resistance change layer 14 is A current barrier layer 15a as an energy barrier layer is stacked, and a fine linear electrode 16 is stacked on a part of the upper surface of the current barrier layer 15a. Even in such a configuration, if the current barrier layer 15a is a material that forms the first Schottky junction or the second Schottky junction, the same effect as in the first embodiment can be obtained. Is possible.

  The fine linear electrode 35 in the second embodiment may be connected not to the upper surface of the resistance change layer 33 but to the lower surface that is the surface of the resistance change layer 33 on the base layer 32 side. That is, as shown in FIG. 13, the wiring 35 a to be connected to the fine linear electrode 35 and the base layer 32 are laminated on the upper surface of the substrate 31 of the memory element 30, and the fine layer is formed inside the base layer 32. A linear electrode 35 is embedded. A resistance change layer 33 is laminated on a portion of the upper surface of the base layer 32 including the upper surface of the fine linear electrode 35, and the first plate electrode 36 and the both ends of the resistance change layer 33 in the surface direction are stacked. A second plate electrode 37 is connected. Even with such a memory element structure, it is possible to obtain the same effect as in the second embodiment.

  The current barrier layer 38 and the fine linear electrode 35 in the third embodiment may be formed not on the upper surface of the resistance change layer 33 but on the lower surface side that is the surface on the base layer 32 side of the resistance change layer 33. That is, as shown in FIG. 14, the wiring 35 a to which the fine linear electrode 35 is connected and the base layer 32 are laminated on the upper surface of the substrate 31 of the memory element 40, and the base layer 32 has a fine structure. A linear electrode 35 is embedded. A current barrier layer 38 and a resistance change layer 33 are sequentially stacked on a portion of the upper surface of the base layer 32 including the upper surface of the fine linear electrode 35, and at both ends in the surface direction of the resistance change layer 33, The first plate electrode 36 and the second plate electrode 37 are connected. Even with such a memory element structure, it is possible to obtain the same effects as those of the third embodiment.

  The size in the surface direction of the current barrier layers 15a and 38 may be smaller than the size in the surface direction of the resistance change layer as long as the size is interposed between the fine linear electrode and the resistance change layer, or The size in the surface direction of the resistance change layer may be larger.

  In the second embodiment, the resistance state of the resistance change layer 33 may be detected using the fine linear electrode 35 and one of the first plate electrode 36 and the second plate electrode 37.

  DESCRIPTION OF SYMBOLS 10, 30, 40 ... Memory element 11, 31 ... Substrate, 12, 32 ... Underlayer, 13 ... Plate electrode, 14, 33 ... Resistance change layer, 15, 34 ... Current barrier part, 15a, 38 ... Current barrier Layers 16, 35 ... fine linear electrodes, 35a ... wiring, 36 ... first plate electrode, 37 ... second plate electrode.

Claims (8)

A resistance change layer;
A write electrode for applying a write voltage to the variable resistance layer;
The write electrode is
The resistance change layer is connected to the variable resistance layer through an energy barrier that suppresses the flow of current by applying the write voltage, and the resistance value of the variable resistance layer is changed by the write voltage at a portion connected to the variable resistance layer. Resistance change memory with minute dots. The energy barrier is
The resistance change memory according to claim 1, wherein the resistance change memory is a Schottky barrier formed by a junction between the resistance change layer and the write electrode. An energy barrier layer sandwiched between the variable resistance layer and the write electrode;
The resistance change memory according to claim 1, wherein the energy barrier layer forms a Schottky barrier, which is the energy barrier, by a junction between the resistance change layer and the write electrode. It further comprises a read electrode for reading the resistance value of the variable resistance layer,
The resistance change memory according to claim 2, wherein the write electrode also serves as the read electrode and applies a forward voltage as a read voltage to the Schottky barrier. It further comprises a read electrode for reading the resistance value of the variable resistance layer,
The resistance change memory according to claim 2, wherein the write electrode and the read electrode are different from each other. An insulating layer sandwiched between the variable resistance layer and the write electrode;
The resistance change memory according to claim 5, wherein the energy barrier is formed by a junction between the write electrode and the insulating layer and a junction between the resistance change layer and the insulating layer. The variable resistance layer is made of titanium oxide,
The portion in contact with the resistance change layer in the writing electrode is composed of either rhodium or iridium,
The resistance change memory according to claim ² , wherein an area of a surface of the write electrode that contacts the resistance change layer is 0.01 μm ² or less. The variable resistance layer is made of titanium oxide,
The resistance change memory according to claim 2, wherein the write electrode is made of a carbon nanotube.

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