JP2013192375A - Three-level power converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a three-level power converter that has a stack structure capable of reducing a surge voltage more.SOLUTION: In an inverter bridge of one phase comprising switching elements Q1, Q2, Q3, Q4, freewheeling diodes DF1, DF2, DF3, DF4 and clamp diodes DP, DN, the switching element Q1, the clamp diode DP, the clamp diode DN and the switching element Q4 are pressure-connected in order from a positive potential side to form a first stack, the freewheeling diode DF1, the freewheeling diode DF2 and the switching element Q3 are pressure-connected in order from the positive potential side to form a second stack, and the freewheeling diode DF4, the freewheeling diode DF3 and the switching element Q2 are pressure-connected in order from a negative potential side to form a third stack.

Description

  The present invention relates to a three-level power converter using an improved stack configuration.

  In a normal power converter, a surge voltage is generated when the switching element is cut off, and the surge voltage increases in accordance with the cut-off current. In particular, in a large-capacity power converter to which a pressure contact type switching element is applied, the current that can be cut off or the element applied voltage is limited in order to keep the surge voltage within the element rated range. A representative of a large-capacity power converter to which the pressure-contact type switching element is applied is a three-level power converter. In this case, the stack configuration for one phase of the switching leg of the converter is usually a main switching element, a clamp diode, 1 stack and one flywheel diode stack, and a total of two stacks (see, for example, Patent Document 1).

Japanese Patent No. 4582629 (page 4-6, FIG. 1)

  In order to suppress the surge voltage, it is necessary to reduce the wiring inductance. However, in the stack configuration of a general three-level power converter disclosed in Patent Document 1, the surge voltage is cut off when the switching element is cut off. There was a limit to reducing this. This is because, in a normal stack configuration, the wiring inductance that can be reduced has a structural and layout limitation.

  The present invention has been made in view of the above problems, and an object thereof is to provide a three-level power converter having a stack configuration capable of further reducing a surge voltage.

  In order to achieve the above object, the three-level power converter of the present invention comprises three sets of three-level inverter bridges for one phase having three DC potential terminals of positive potential, negative potential and intermediate potential, and an AC output terminal. The one-phase portion of the three-level inverter bridge includes a first switching element whose collector is connected to the positive potential terminal, and a collector which is the first switching element. A second switching element connected to the emitter; a third switching element having a collector connected to the emitter of the third switching element; a collector connected to the emitter of the third switching element; A fourth switching element connected to the negative potential terminal, and a current to flow from the intermediate potential terminal to the emitter of the first switching element. A first clamp diode connected in a direction, a second clamp diode connected in a direction in which a current flows from the emitter of the third switching element to the intermediate potential, and the first to fourth switching elements. First, second, third, and fourth flywheel diodes connected in anti-parallel to each other, the first switching element, the first clamp diode, the second clamp diode, and the The fourth switching element is sequentially pressed from the positive potential side to form a first stack, and the first flywheel diode, the second flywheel diode, and the third switching element are sequentially connected to the positive potential. Pressure-welded from the side to form a second stack, the fourth flywheel diode, the third flywheel diode and Said second switching element, is characterized in that the formation of the third stack sequentially pressed from the negative potential side.

  According to the present invention, it is possible to provide a three-level power converter having a stack configuration that can further reduce a surge voltage.

The circuit block diagram for 1 phase of the 3 level power converter which concerns on this invention. FIG. 3 is a stack configuration diagram for one phase of the three-level power converter according to the present invention. The comparison figure (A) equivalent to FIG. The comparison figure (B) equivalent to FIG. The arrangement schematic diagram of the stack for one phase of the three level power converter concerning the present invention.

  Hereinafter, a three-level power converter according to the present invention will be described with reference to FIGS.

  FIG. 1 is a circuit configuration diagram for one phase of a three-level power converter according to an embodiment of the present invention. FIG. 1A is a circuit configuration diagram according to a conventional description method, and FIG. 1B is a circuit configuration diagram according to a description method in consideration of the stack configuration for one phase of the three-level power converter of the present invention.

  In FIG. 1A, a three-level DC voltage is applied from a positive potential terminal P, a negative potential terminal N, and an intermediate potential terminal C. Between the positive potential terminal P and the negative potential terminal N, a series circuit of switching elements (self-extinguishing semiconductor elements) Q1, Q2, Q3, and Q4 is connected. Further, flywheel diodes DF1, DF2, DF3, and DF4 are connected in antiparallel to the switching elements Q1, Q2, Q3, and Q4, respectively. The clamp diode DP is connected in a direction in which a current flows from the intermediate potential terminal C toward the connection point of the switching elements Q1 and Q2 connected in series, and the clamp diode DN is connected to the switching elements Q3 and Q4 connected in series. They are connected in a direction in which current flows from the point toward the intermediate potential terminal C. The terminal AC is an output terminal connected to a load (not shown). The circuit thus connected operates as one phase of the inverter bridge of the power converter.

  Next, FIG. 2B will be described. In FIG. 2B, a series circuit including a switching element Q1, a clamp diode DP, a clamp diode DN, and a switching element Q4 provided between the positive potential terminal P and the negative potential terminal N in the center is illustrated. Show. On the left side of the figure, a series circuit composed of flywheel diodes DF1 and DF2 and switching element Q3 provided between the positive potential terminal P and the connection point of the clamp diode DN and switching element Q4. Further, on the right side of the drawing, a series circuit including a switching element Q2 and flywheel diodes DF3 and DF4 provided between the connection point of the switching element Q1 and the clamp diode DP and the negative potential terminal N. Is shown.

  Then, the connection point between the switching element Q3 and the flywheel diode DF1 and the terminal AC are connected. As a result, the circuit configuration shown in FIG. 1B is equivalent to the circuit configuration shown in FIG.

  FIG. 2 is a schematic structural diagram of the circuit configuration shown in FIG. In FIG. 2, a series circuit including a switching element Q1, a clamp diode DP, a clamp diode DN, and a switching element Q4 is referred to as a stack (series press contact body) 2A, and is configured to be integrally pressed in a skewer shape. Similarly, a series circuit composed of flywheel diodes DF1, DF2 and switching element Q3 is referred to as stack 2B, and a series circuit composed of switching element Q2, flywheel diodes DF3, DF4 is referred to as stack 2C. Fins attached to the semiconductor elements of each stack are shown by white rectangles, and the wiring conductors between these fins and input / output are shown by shading. In FIG. 2, these fins and wiring conductors simultaneously display their inductances. Hereinafter, the inductance of the interruption loop that governs the surge voltage at the time of interruption of the current applied to each switching element in FIG. 2 will be analyzed.

  In the analysis, an actual measurement value is approximated, and the wiring inductance is set to 20 nH and the fin inductance is set to 5 nH.

  First, consider the current interruption of the switching element Q1. The cutoff loop at this time is P → Q1 → DP → C, and the loop inductance LQ1 is LQ1 = 20 nH + 5 nH + 5 nH + 5 nH + 20 nH = 55 nH.

  Next, the cut-off loop of the switching element Q2 is DP → Q2 → DF3 → DF4 → N. Therefore, the loop inductance LQ2 is LQ2 = 20nH + 5nH + 5nH + 20nH + 5nH + 5nH + 5nH + 5nH + 20nH + 5nH + 20nH = 115 nH.

  Next, the cut-off loop of the switching element Q3 is P → DF1 → DF2 → Q3 → DN → C. Therefore, the loop inductance LQ3 is LQ3 = 20nH + 5nH + 20nH + 5nH + 5nH + 5nH + 5nH + 20nH + 5nH + 5nH +20 nH = 115 nH.

  The cutoff loop of the switching element Q4 is N → Q4 → DN → C. Therefore, the loop inductance LQ4 is LQ4 = 20 nH + 5 nH + 5 nH + 5 nH + 20 nH = 55 nH.

  Here, when the current in the interruption loop flows toward another stack, the current flows in the lateral direction with respect to the fin, and thus the wiring inductance of the cooling fin increases. When the wiring inductance in that case is corrected to a double value of 10 nH, each loop inductance is as follows.

LQ1 = 20nH + 5nH + 5nH + 10nH + 20nH = 65nH (1)
LQ2 = 20nH + 10nH + 10nH + 20nH + 10nH + 5nH + 5nH + 10nH + 20nH + 10nH + 20nH = 140nH (2)
LQ3 = 20nH + 10nH + 20nH + 10nH + 5nH + 5nH + 10nH + 20nH + 10nH + 10nH + 20nH = 140nH (3)
LQ4 = 20nH + 5nH + 5nH + 10nH + 20nH = 60nH (4)
FIG. 3 is a comparative diagram (A) for evaluating the loop inductance in the case of FIG. 2, and shows a schematic structural diagram of the circuit configuration shown in FIG. 1 (a). Therefore, the central portion is a stack of switching elements, the right side is a stack of flywheel diodes, and the left side is a stack of clamp diodes. In the stack configuration of FIG. 3, the loop inductances LQ1A, LQ2A, LQ3A, and LQ4A obtained by correcting the fin inductance as described above are obtained as follows.

LQ1A = 20nH + 5nH + 10nH + 20nH + 10nH + 10nH + 20nH = 95nH (5)
LQ2A = 20nH + 10nH + 10nH + 20nH + 10nH + 10nH + 20nH + 10nH + 5nH + 10nH + 20nH + 10nH + 20nH = 175nH (6)
LQ3A = 20nH + 10nH + 20nH + 10nH + 5nH + 10nH + 20nH + 10nH + 10nH + 20nH + 10nH + 10nH + 20nH = 175nH (7)
LQ4A = 20nH + 5nH + 10nH + 20nH + 10nH + 10nH + 20nH = 95nH (8)
From the above formulas (1) to (8), LQ1 <LQ1A, LQ2 <LQ2A, LQ3 <LQ3A, and LQ4 <LQ4A are established. Therefore, the stack configuration shown in FIG. It can be seen that is reduced.

  Next, FIG. 4 is also a comparative diagram (B) for evaluating the loop inductance. In FIG. 3, the stack of clamp diodes is taken into the stack of switching elements to form a two-stack configuration. The hatched portion in FIG. 4 indicates an insulator.

  In the stack configuration of FIG. 4, the loop inductances LQ1B, LQ2B, LQ3B, and LQ4B corrected for the fin inductance are as follows. However, the connection inductance of the stack is 40 nH according to the actual structure.

LQ1B = 20nH + 10nH + 40nH + 10nH + 10nH + 40nH + 10nH + 10nH + 20nH = 170nH (9)
LQ2B = 20nH + 10nH + 10nH + 40nH + 10nH + 10nH + 40nH + 10nH + 5nH + 10nH + 20nH = 185nH (10)
LQ3B = 20nH + 10nH + 10nH + 40nH + 10nH + 10nH + 40nH + 10nH + 5nH + 10nH + 20nH = 185nH (11)
LQ4B = 20nH + 10nH + 40nH + 10nH + 10nH + 40nH + 10nH + 10nH + 20n = 170nH (12)
From the above formulas (1) to (4) and (9) to (12), LQ1 <LQ1B, LQ2 <LQ2A, LQ3 <LQ3B, and LQ4 <LQ4B are established, so the stack configuration shown in FIG. It can be seen from the stack configuration of 4 that all loop inductances are reduced.

  FIG. 5 is a schematic diagram showing the arrangement of the stack configuration of the present invention shown in FIG. 2, showing a plan view when the stacks 2A, 2B, and 2C are arranged in the panel so that the center line is in the vertical direction. Yes.

In FIG. 2, the connection line 1 connects the stack 2B and the stack 2C, but depending on the arrangement, the stack 2A becomes an obstacle and the connection line 1 bypasses the stack 2A. In contrast, as shown in FIG. 5, the stacks 2A, 2B, and 2C are shifted so that the center lines of the stacks 2A, 2B, and 2C are spatially parallel and so that the connection line 1 does not bypass the stack 2A. If it arrange | positions so that it may become a shape, it will become possible to prevent the increase in loop inductance.

1 Connection line 2A, 2B, 2C Stack (series pressure contact)
Q1, Q2, Q3, Q4 Switching element (self-extinguishing semiconductor element)
DF1, DF2, DF3, DF4 Flywheel diode DP, DN Clamp diode

Claims (2)

A three-level power converter composed of three sets of three-level inverter bridges for one phase having three DC potential terminals of positive potential, negative potential and intermediate potential, and an AC output terminal,
One phase of the three-level inverter bridge is
A first switching element having a collector connected to the positive potential terminal;
A second switching element having a collector connected to the emitter of the first switching element;
A third switching element having a collector connected to the emitter of the third switching element;
A fourth switching element having a collector connected to the emitter of the third switching element and an emitter connected to the negative potential terminal;
A first clamp diode connected in a direction in which a current flows from the intermediate potential terminal to the emitter of the first switching element;
A second clamp diode connected in a direction in which a current flows from the emitter of the third switching element to the intermediate potential;
First, second, third and fourth flywheel diodes connected in anti-parallel to each of the first to fourth switching elements;
The first switching element, the first clamp diode, the second clamp diode, and the fourth switching element are sequentially pressed from the positive potential side to form a first stack;
The first flywheel diode, the second flywheel diode, and the third switching element are sequentially pressed from the positive potential side to form a second stack,
A three-level power converter, wherein the fourth flywheel diode, the third flywheel diode, and the second switching element are sequentially pressed from the negative potential side to form a third stack.   Connection lines connecting the second stack and the third stack do not bypass the first stack so that the center lines of the first stack, the second stack, and the third stack are spatially parallel to each other. The three-level power converter according to claim 1, wherein the three-level power converter is arranged so as to be shifted.

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