JP2013191752A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device for forming a semiconductor device of good characteristics, including the reduced effect of distortion component (noise).SOLUTION: On a first surface of a first substrate S1, impurity ion is implanted in a region 1B on the outer periphery of a high frequency MISFET formation region 1A, to form a diffusion layer s1c, and then by oxidizing the first surface side of the first substrate S1, a silicon oxide film s1d is formed on the diffusion layer s1c. After that, a first surface side of a second substrate S2 containing a BOX film 3 on the first surface side is laminated to the first surface side of the first substrate S1. By providing the diffusion layer s1c as described above, the effect of noise on the high frequency MISFET formation region 1A can be reduced. Further, by employing a lamination method as a method of forming an SOI substrate to form the diffusion layer s1c before the lamination step, the diffusion layer s1c can be formed precisely.

Description

  The present invention relates to a method for manufacturing a semiconductor device using an SOI (Silicon On Insulator) substrate, and more particularly to a technique effective when applied to a method for manufacturing a semiconductor device in which a high-frequency signal flows.

  Currently, semiconductor devices using an SOI substrate are used as semiconductor devices capable of suppressing the generation of parasitic capacitance. In the SOI substrate, a BOX (Buried Oxide) film (buried oxide film) is formed on a support substrate made of Si (silicon) or the like, and a thin layer (silicon layer) mainly containing Si (silicon) is formed on the BOX film. Substrate. When the MISFET is formed on such an SOI substrate, the parasitic capacitance generated in the diffusion region formed in the silicon layer can be reduced. For this reason, manufacturing a semiconductor device using an SOI substrate can be expected to improve the integration density and operation speed of the semiconductor device, and to make the latch-up free. Here, MISFET is an abbreviation for Metal Insulator Semiconductor Field Effect Transistor (Field Effect Transistor), and is sometimes called MOS (Metal Oxide Semiconductor) or MOSFET.

  Japanese Patent Application Laid-Open No. 2004-111521 discloses a method for manufacturing an SOI substrate. Specifically, a plurality of grooves (3) are formed on the first main surface (K) of the first substrate (7) made of silicon single crystal so as to reach the outer edge, and made of silicon single crystal. A silicon oxide film (2) is formed as an insulating film on the first main surface (J) of the second substrate (1). Thereafter, the first substrate (7) and the second substrate (1) are bonded together such that the respective first main surfaces (J, K) are interposed via the silicon oxide film (2). Thereafter, the thickness of the second substrate (1) is reduced so as to leave a residual layer region (5) including a silicon layer region to be the SOI layer (10). And the formed groove | channel (3) is embedded by the particle | grain flow from an own circumference part by performing heat processing.

  In Patent Document 2 (Japanese Patent Laid-Open No. 2002-33250), an active silicon in which a silicon oxide film (22) is formed on a bulk silicon layer (23) and a circuit pattern is to be formed on the silicon oxide film (22). An SOI substrate (W2) configured by forming a layer (21) is disclosed. In this SOI substrate (W2), an identification code pattern (30) is formed at the interface between the bulk silicon layer (23) and the silicon oxide film (22). In addition, the symbol in the said parenthesis is a code | symbol described in the said patent document.

JP 2004-111521 A JP 2002-33250 A

  The MISFET, which is a high-frequency field effect transistor used in an antenna switch for a cellular phone, does not output the input signal as it is without being affected by noise, and a signal mixed with distortion components (noise) is likely to be output. Characteristics (distortion characteristics). This distortion component is likely to be generated as a harmonic having a wavelength twice or three times the wavelength of the input signal. The distortion component is a frequency component unrelated to the original input signal, and there is a problem that it becomes impossible to output the signal accurately by mixing such an extra frequency component with the input signal.

  In order to solve such a problem, use of an SOS substrate in which a silicon layer is formed on a sapphire layer which is an insulating layer has been studied. Although this SOS substrate can suppress the generation of “a distortion component having a frequency twice that of the input signal” due to the parasitic capacitance between the well and the substrate, the “SOS substrate” is caused by the parasitic capacitance between the well and the source / drain. It is difficult to suppress the generation of a “distortion component having a frequency three times that of the input signal”.

  On the other hand, a method of using an SOI substrate as a low-cost semiconductor substrate capable of suppressing the generation of parasitic capacitance between the gate electrode and the semiconductor substrate can be considered, but even an SOI substrate is caused by parasitic capacitance. Distortion characteristics that generate noise (distortion component). For example, when a high-frequency signal generated externally is transmitted to a MISFET that performs switching or the like, there is a problem that a distortion component (noise) is generated in the MISFET and the characteristics of the semiconductor device deteriorate.

  Therefore, an object of the embodiment described below is to provide a method for manufacturing a semiconductor device that forms a semiconductor device with good characteristics. In particular, an object of the present invention is to provide a method for manufacturing a semiconductor device that can reduce the influence of distortion components (noise).

  The above and other objects and novel features will become apparent from the description of the specification and the accompanying drawings.

  Of the embodiments disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A manufacturing method of a semiconductor device shown in a typical embodiment disclosed in the present application prepares a first semiconductor substrate having a first semiconductor region on the first surface side, and has an insulating layer on the first surface side. Then, a second semiconductor substrate having a semiconductor layer on the second surface side is prepared, and the first surface side of the first semiconductor substrate and the first surface side of the second semiconductor substrate are bonded together.

  In the method of manufacturing a semiconductor device shown in the representative embodiment disclosed in the present application, the first semiconductor region is formed by implanting impurity ions into the outer periphery of the first region on the first surface of the first semiconductor substrate. A second semiconductor substrate having an insulating layer on the first surface side and a semiconductor layer on the second surface side is prepared, and the first surface side of the first semiconductor substrate and the second surface of the second semiconductor substrate are prepared. Affix the first side. As a result, a substrate having the first semiconductor substrate, the insulating layer disposed on the first semiconductor substrate, and the semiconductor layer disposed on the insulating layer is formed, and the semiconductor layer corresponding to the first region is formed on the semiconductor layer. 1 MISFET is formed.

  In the method of manufacturing a semiconductor device shown in the representative embodiment disclosed in the present application, the first semiconductor region is formed by implanting impurity ions into the outer periphery of the first region on the first surface of the first semiconductor substrate. Then, an oxide film is formed on the first semiconductor region by oxidizing the first surface side of the first semiconductor substrate. Thereafter, a second semiconductor substrate having an insulating layer on the first surface side and a semiconductor layer on the second surface side is prepared, and the first surface side of the first semiconductor substrate and the second semiconductor substrate described above are prepared. The first surface side is bonded together. As a result, a substrate having the first semiconductor substrate, the insulating layer disposed on the first semiconductor substrate and the semiconductor layer disposed on the insulating layer is formed, and the semiconductor layer corresponding to the first region is formed on the semiconductor layer. A first MISFET is formed. Further, in the substrate, a step due to the oxide film occurs at the end of the first semiconductor region.

  According to the method for manufacturing a semiconductor device disclosed in the following representative embodiment disclosed in the present application, a semiconductor device having good characteristics can be formed.

It is sectional drawing which shows the manufacturing process of the semiconductor device of this Embodiment. FIG. 2 is a cross-sectional view showing the manufacturing process of the semiconductor device of the present embodiment, which is a cross-sectional view showing the manufacturing process following FIG. 1. FIG. 3 is a cross-sectional view showing a manufacturing step of the semiconductor device of the present embodiment, which is a cross-sectional view showing a manufacturing step following FIG. 2; FIG. 4 is a cross-sectional view showing a manufacturing process of the semiconductor device of the present embodiment, which is a cross-sectional view showing a manufacturing process following FIG. 3. FIG. 5 is a cross-sectional view showing a manufacturing step of the semiconductor device of the present embodiment, which is a cross-sectional view showing a manufacturing step following FIG. 4; FIG. 6 is a cross-sectional view showing a manufacturing step of the semiconductor device of the present embodiment, which is a cross-sectional view showing a manufacturing step following FIG. 5; FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device of the present embodiment, which is a cross-sectional view showing a manufacturing step following FIG. 6; FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device of the present embodiment, which is a cross-sectional view showing a manufacturing step following FIG. 7. FIG. 9 is a cross-sectional view showing a manufacturing step of the semiconductor device of the present embodiment, which is a cross-sectional view showing a manufacturing step following FIG. 8; FIG. 10 is a cross-sectional view showing a manufacturing step of the semiconductor device of the present embodiment, which is a cross-sectional view showing a manufacturing step following FIG. 9; FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device of the present embodiment, which is a cross-sectional view showing a manufacturing step following FIG. 10; FIG. 12 is a cross-sectional view showing a manufacturing step of the semiconductor device of the embodiment, and is a cross-sectional view showing a manufacturing step following FIG. 11. FIG. 13 is a cross-sectional view showing a manufacturing step of the semiconductor device of the embodiment, and is a cross-sectional view showing a manufacturing step following FIG. 12; FIG. 14 is a cross-sectional view showing a manufacturing step of the semiconductor device of the present embodiment, which is a cross-sectional view showing a manufacturing step following FIG. 13; FIG. 15 is a cross-sectional view showing a manufacturing step of the semiconductor device of the embodiment, and is a cross-sectional view showing a manufacturing step following FIG. 14. FIG. 16 is a cross-sectional view showing a manufacturing step of the semiconductor device of the embodiment, and is a cross-sectional view showing a manufacturing step following FIG. 15; FIG. 17 is a cross-sectional view showing a manufacturing step of the semiconductor device of the embodiment, and is a cross-sectional view showing a manufacturing step following FIG. 16; FIG. 18 is a cross-sectional view showing a manufacturing step of the semiconductor device of the embodiment, and is a cross-sectional view showing a manufacturing step following FIG. 17. FIG. 19 is a cross-sectional view showing a manufacturing step of the semiconductor device of the embodiment, and is a cross-sectional view showing a manufacturing step following FIG. 18. FIG. 20 is a cross-sectional view showing a manufacturing step of the semiconductor device of the embodiment, and is a cross-sectional view showing a manufacturing step following FIG. 19. FIG. 21 is a cross-sectional view showing a manufacturing step of the semiconductor device of the embodiment, and is a cross-sectional view showing a manufacturing step following FIG. 20. It is a top view which shows an example of the layout of the MISFET formation area for high frequencies. It is sectional drawing which shows typically the semiconductor device of the comparative example of this Embodiment. It is a graph which shows the operating characteristic of MISFET for high frequencies. It is a circuit diagram which shows the example of application of the semiconductor device of this Embodiment. It is a top view of a board | substrate (wafer). It is sectional drawing which shows the other manufacturing process of the semiconductor device of this Embodiment. It is a top view which shows the other manufacturing process of the semiconductor device of this Embodiment. It is sectional drawing which shows the other manufacturing process of the semiconductor device of this Embodiment.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Are partly or entirely modified, application examples, detailed explanations, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Furthermore, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numbers and the like (including the number, numerical value, quantity, range, etc.).

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same or related reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted. In addition, when there are a plurality of similar members (parts), a symbol may be added to the generic symbol to indicate an individual or specific part. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

  In the cross-sectional view and the plan view, the size of each part does not correspond to the actual device, and a specific part may be displayed relatively large for easy understanding of the drawing. Even when the plan view and the cross-sectional view correspond to each other, the size of each part may be changed and displayed.

(Embodiment)
Hereinafter, the structure and manufacturing method of the semiconductor device of the present embodiment will be described in detail with reference to the drawings. 1 to 21 are cross-sectional views showing the manufacturing process of the semiconductor device of the present embodiment. FIG. 22 is a plan view showing an example of the layout of the high-frequency MISFET formation region. FIG. 23 is a cross-sectional view schematically showing a semiconductor device of a comparative example of the present embodiment. FIG. 24 is a graph showing the operating characteristics of a high-frequency MISFET. FIG. 25 is a circuit diagram showing an application example of the semiconductor device of this embodiment.

[Description of structure]
First, a characteristic configuration of the semiconductor device of the present embodiment will be described with reference to FIG. 21 which is a cross-sectional view showing a manufacturing process of the semiconductor device of the present embodiment.

  The semiconductor device of the present embodiment includes a high-frequency MISFET (switching MISFET) T1 and a control circuit MISFET (T2n, T2p) arranged on an SOI substrate.

  The SOI substrate includes a first substrate (support substrate, semiconductor substrate) S1, a BOX film 3 disposed on the first substrate S1, and a silicon layer 4 disposed on the BOX film 3. The first substrate S1 is a semiconductor substrate made of, for example, Si (silicon), and is a high-resistance semiconductor substrate having a resistance of, for example, 750 Ωcm or more. The BOX film 3 is made of an insulating film such as a silicon oxide film. The silicon layer 4 is made of, for example, single crystal Si having a resistance of about 1 to 10 Ωcm.

  The SOI substrate has a high-frequency MISFET formation region 1A and a control circuit MISFET formation region 2A.

  A high-frequency MISFET (T1) is disposed in the high-frequency MISFET formation region 1A. This high frequency MISFET (T1) is a MISFET to which a high frequency signal is applied.

The high-frequency MISFET (T1) is, for example, an n-channel type MISFET, and as shown in FIG. 21, a gate electrode disposed on the silicon layer 4 (p-type well 6p) with a gate insulating film 7 interposed therebetween. 8 and source and drain regions arranged in the silicon layer 4 (p-type well 6 p) on both sides of the gate electrode 8. The source and drain regions have an LDD (Lightly Doped Drain) structure and are composed of an extension region 9 which is an n ⁻ type semiconductor region and an n type high concentration semiconductor region 11. A silicide layer 12 is disposed on the gate electrode 8 and the high-concentration semiconductor region 11. A side wall 10 is disposed on the side of the gate electrode 8.

  In the MISFET formation region 2A for the control circuit, an MISFET (T2n) for an n-channel control circuit and a MISFET (T2p) for a p-channel control circuit are arranged. The MISFET for the control circuit is, for example, a MISFET constituting the control circuit unit 110 described later (see FIG. 25).

As shown in FIG. 21, the MISFET (T2n) for the n-channel control circuit includes a gate electrode 8 disposed on the silicon layer 4 (p-type well 6p) via a gate insulating film 7, and a gate electrode 8 Source and drain regions arranged in the silicon layer 4 (p-type well 6p) on both sides. The source and drain regions have an LDD structure and are composed of an extension region 9 which is an n ⁻ type semiconductor region and an n type high concentration semiconductor region 11. A silicide layer 12 is disposed on the gate electrode 8 and the high-concentration semiconductor region 11. A side wall 10 is disposed on the side of the gate electrode 8.

As shown in FIG. 21, the MISFET (T2p) for the p-channel control circuit includes a gate electrode 8 disposed on the silicon layer 4 (n-type well 6n) via a gate insulating film 7, and a gate electrode 8 Source and drain regions arranged in the silicon layer 4 (n-type well 6n) on both sides of the substrate. The source and drain regions have an LDD structure and are composed of an extension region 9 which is a p ⁻ type semiconductor region and a p type high concentration semiconductor region 11. A silicide layer 12 is disposed on the gate electrode 8 and the high-concentration semiconductor region 11. A side wall 10 is disposed on the side of the gate electrode 8.

  An insulating film 14 and an interlayer insulating film 15 are disposed above the high-frequency MISFET (T1) and the control circuit MISFETs (T2n, T2p). A first plug P1 is disposed on the source and drain regions (high-concentration semiconductor region 11) of these MISFETs (T1, T2n, T2p). The first plug P1 is disposed inside the contact hole C1b. Further, a first layer wiring M1 is disposed on the first plug P1. Note that an insulating film, a plug, and a wiring may be arranged on the first layer wiring to form a multilayer wiring structure.

  An element isolation insulating film 5 is disposed between the high frequency MISFET formation region 1A and the control circuit MISFET formation region 2A. In the MISFET formation region 2A for the control circuit, an element isolation insulating film 5 is disposed between the MISFET (T2n) for the n-channel type control circuit and the MISFET (T2p) for the p-channel type control circuit. ing.

  Here, in the semiconductor device of the present embodiment, as shown in FIG. 21, in the outer periphery (region 1B) of the high frequency MISFET formation region 1A (two high frequency MISFETs (T1)), the first substrate S1. A diffusion layer (semiconductor region, implantation layer) s1c is disposed at the boundary between the BOX film 3 and the BOX film 3. Further, a first plug P1 disposed in the contact hole C1a is disposed above the diffusion layer s1c. A first layer wiring M1 is disposed on the first plug P1. The layout of the first plug P1 and the diffusion layer s1c is not limited. For example, as shown in FIG. 22, the first plug P1 and the diffusion layer s1c may be disposed along the outer periphery of the high-frequency MISFET formation region 1A. .

  As shown in FIG. 22, the high frequency MISFET formation region 1A is arranged in a substantially rectangular shape. Inside, a plurality of high-frequency MISFETs (T1) are arranged. In the high-frequency MISFET formation region 1A, a plurality of substantially rectangular gate electrodes 8 having long sides in the Y direction are arranged at predetermined intervals in the X direction. A space between the gate electrodes 8 is a source / drain region (high concentration semiconductor region 11). Each gate electrode 8 is connected to a gate line 8a having a long side in the X direction, and a first plug P1 is disposed on the gate line 8a. The first plug P1 is also disposed in the source and drain regions (high concentration semiconductor region 11).

  Here, four contact holes C1a are disposed along each side of the substantially rectangular high-frequency MISFET formation region 1A, and the first plug P1 is disposed therein. Further, four diffusion layers s1c are arranged along the sides of the substantially rectangular high-frequency MISFET formation region 1A at the bottom of the contact hole C1a. Note that the four diffusion layers s1c or the four first plugs P1 may be connected so as to surround the high-frequency MISFET (T1). Alternatively, only two diffusion layers s1c extending in the X direction or two first plugs P1 extending in the X direction may be used. Alternatively, only two diffusion layers s1c extending in the Y direction or two first plugs P1 extending in the Y direction may be used.

  Thus, in the present embodiment, since the diffusion layer s1c located on the outer periphery of the high-frequency MISFET formation region 1A is provided, noise is generated in the high-frequency MISFET (T1) due to the influence of the high-frequency signal from the outside. Can be prevented. Furthermore, the effect of the guard ring can be further enhanced by forming the first plug P1 above the diffusion layer s1c. The guard ring referred to here is a low ring formed around the element, for example, for the purpose of preventing an external current from flowing to the element formed on the substrate and fixing the potential of the substrate. It means a resistance region.

  FIG. 23 is a cross-sectional view schematically showing a semiconductor device of a comparative example of the present embodiment. In the drawing, 16 indicates an insulating film including the interlayer insulating film 15 and the like, P2 indicates a second plug, and M2 indicates a second layer wiring. In FIG. 23, the silicon layer 4 in the MISFET formation region 1A for high frequency and the silicon layer 4 in the MISFET formation region 2A for control circuit are arranged on the BOX film 3 constituting the SOI substrate. In such a case, even if an insulating film such as the element isolation insulating film 5 is disposed between the silicon layers 4, the lower part of the BOX film 3 is connected to each other via the conductive first substrate S1. Therefore, these silicon layers 4 can interfere with each other. Specifically, the depletion layer 2 that spreads from the interface between the BOX film 3 and the first substrate S1 changes based on the voltage change applied to the silicon layer 4, so that the silicon layer 4 and the first substrate S1 The capacitance between them (substrate capacitance) changes. Such a change in the substrate capacitance depending on the voltage change may cause an imbalance in the amplitude on the + or − side of the input signal of the high-frequency MISFET (T1) as noise, which may prevent an accurate signal from being output. There is.

  In contrast, in the present embodiment, the diffusion layer s1c is provided below the BOX film 3 on the outer periphery of the high-frequency MISFET formation region 1A, thereby reducing the change in the substrate capacitance depending on the voltage change. Can do. As a result, the influence of noise on the high-frequency MISFET formation region 1A can be reduced, and the operating characteristics of the high-frequency MISFET (T1) can be improved.

  FIG. 24 is a graph showing the operating characteristics of a high-frequency MISFET. The horizontal axis represents input power [dBm], and the vertical axis represents the characteristic improvement rate [%]. A square mark indicates the case of a high-frequency MISFET in which the diffusion layer s1c is not provided, and a circle indicates a case of a high-frequency MISFET in which the diffusion layer s1c is provided. The characteristic improvement rate was calculated from the second harmonic distortion (2HD [dBc]). That is, with reference to 2HDa in the case of a high-frequency MISFET not provided with the diffusion layer s1c, the improvement rate of 2HDb in the case of the high-frequency MISFET provided with the diffusion layer s1c (((2HDb-2HDa) / 2HDa) × 100 ) Was defined as a characteristic improvement rate [%].

  As shown in the graph of FIG. 24, for any input power, the second harmonic distortion of the high-frequency MISFET provided with the diffusion layer s1c is improved, and the improvement rate increases to a specific input power. There was a trend. Also from this graph, it can be seen that by providing the diffusion layer s1c below the BOX film 3, the operating characteristics of the high-frequency MISFET (T1) are improved.

  FIG. 25 is a circuit diagram showing an application example of the semiconductor device of this embodiment. A high-frequency MISFET (T1a) is connected between the antenna and the terminal TX, and a high-frequency MISFET (T1b) is connected between the antenna and the terminal RX. Further, a high-frequency MISFET (T1c) is connected between the terminal TX and the ground, and a high-frequency MISFET (T1d) is connected between the terminal RX and the ground. The switch circuit unit 100 includes these four high-frequency MISFETs (T1a to T1d). The terminal TX is a transmission terminal, and the terminal RX is a reception terminal.

  The gate electrodes of these high-frequency MISFETs (T1a to T1d) are connected to the control circuit unit 110. The control circuit unit 110 includes a negative bias circuit 111, an oscillation circuit 113, a decoder circuit 115 that performs DA conversion and AD conversion, and the like. The negative bias circuit 111 operates the MISFET stably by bias-controlling the potential applied to the high-frequency MISFET (T1a to T1d).

  As the high frequency MISFET (T1a) of the switch circuit unit 100 shown in FIG. 25, for example, a MISFET having a layout shown in FIG. 22 can be applied. Similarly, the MISFETs having the layout shown in FIG. 22 can be applied to the high-frequency MISFETs (T1b to T1d) of the switch circuit unit 100 shown in FIG.

  Further, as the MISFET constituting the negative bias circuit 111 of the control circuit unit 110 shown in FIG. 25, the MISFET (T2n, T2p) for the control circuit shown in FIG. 21 can be applied.

  In this way, by applying the MISFET (high frequency MISFET (T1) and control circuit MISFET (T2n, T2p)) of the present embodiment to the circuit shown in FIG. 25, the high frequency MISFET (T1) is applied. The influence of noise can be reduced and the operating characteristics of the circuit can be improved.

  Furthermore, in this embodiment, the bonding layer is used as a method for forming the SOI substrate, and the diffusion layer s1c can be formed with high accuracy by forming the diffusion layer s1c before the bonding step. In addition, by using a step of the silicon oxide film at the end of the diffusion layer s1c described later as an alignment mark, accurate position recognition can be performed and high-precision pattern formation can be performed. These will be described in detail in the “Production Method” section below.

[Product description]
Next, the method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 1 to 21 and the configuration of the semiconductor device will be clarified.

<SOI substrate formation process>
A semiconductor substrate made of Si is prepared as the first substrate (support substrate) S1. The first substrate S1 is a high-resistance semiconductor substrate, and the resistance is, for example, 750 Ωcm or more. Next, as shown in FIG. 1, a silicon oxide film s1a is formed on the first substrate S1 as a base oxide film by using a thermal oxidation method or the like. Next, a silicon nitride film s1b is formed as a mask film on the silicon oxide film s1a by a CVD (Chemical Vapor Deposition) method or the like.

  Next, as shown in FIG. 2, the silicon nitride film s1b and the silicon oxide film s1a are patterned to form openings in the region 1B. Specifically, a photoresist film (not shown) is formed on the silicon nitride film s1b, and the photoresist film in the region 1B is removed by exposure and development. Next, the opening is formed by etching the silicon nitride film s1b and the silicon oxide film s1a using the photoresist film as a mask. Next, the photoresist film is removed by ashing or the like. Such a process from formation to removal of the photoresist film is called patterning.

  Next, as shown in FIG. 3, n-type or p-type impurity ions are ion-implanted using the silicon nitride film s1b as a mask. Thereby, the diffusion layer s1c is formed in the region 1B (see FIG. 4). Here, B (boron) ions which are p-type impurity ions are implanted.

  Next, as shown in FIG. 4, the first substrate (diffusion layer s1c) S1 exposed from the region 1B is oxidized. Specifically, the silicon oxide film s1d is formed in the region 1B by wet oxidation using the silicon nitride film s1b as a mask. As wet oxidation, for example, heat treatment at 700 to 1200 ° C. is performed in a hydrogen and oxygen atmosphere. Here, the film thickness of the silicon oxide film s1d is larger than the film thickness of the silicon oxide film s1a, and its bottom is positioned deeper than the bottom of the silicon oxide film s1a. Therefore, a difference in thickness St between the silicon oxide film s1d and the silicon oxide film s1a causes a step St of the silicon oxide film (s1a, s1d) at the end of the region 1B. In other words, a step St caused by the silicon oxide film s1d occurs at the end of the diffusion layer s1c.

  Next, as shown in FIG. 5, the silicon nitride film s1b is polished by a CMP (Chemical Mechanical Polishing) method until the silicon oxide film s1a is exposed. As a result, the surface of the first substrate (silicon oxide film s1d and silicon oxide film s1a) S1 is planarized. At this time, the upper portion of the silicon oxide film s1a may be removed by CMP, but polishing is performed so that the first substrate S1 is not exposed and the surface of the first substrate S1 is covered with the silicon oxide film s1d or the silicon oxide film s1a. Adjust the amount.

  Next, as shown in FIG. 6, the first surface (surface, BOX film 3 formation) of the second substrate (semiconductor substrate) S2 is formed on the first surface (surface, the surface on the silicon oxide film s1d formation side) of the first substrate S1. Adhere the side surface. The second substrate S2 is a semiconductor substrate made of Si (silicon) having a resistance of about 1 to 10 Ωcm, and has a BOX film 3 made of an insulating film on the first surface (front surface). The BOX film 3 is, for example, a silicon oxide film, and is formed on the first surface of the second substrate S2 using a CVD method or the like. The film thickness of the BOX film 3 is, for example, about 400 nm. The first surface side of the second substrate S2 is mounted on the first surface of the first substrate S1, and bonded (bonded) by applying pressure at a high temperature, for example. A part of the second substrate S2 becomes a silicon layer (4) described later. Specifically, a region having a predetermined thickness (for example, 60 nm) from the BOX film 3 of the second substrate S2 becomes the silicon layer (4).

  Next, as shown in FIG. 7, the second surface (the back surface, the surface opposite to the first surface) of the second substrate S2 is polished by CMP to form a thin film. As a result, a silicon layer (SOI layer) 4 is formed on the BOX film 3. The thickness of the silicon layer 4 is, for example, about 60 nm. In FIG. 7 and subsequent figures, the silicon oxide films (s1a, s1d) and the BOX film 3 are integrated and denoted by reference numeral 3.

  Through the above steps, an SOI substrate in which the BOX film 3 and the silicon layer 4 are disposed on the first substrate S1 is formed. Here, a diffusion layer s1c is formed at the boundary between the first substrate S1 and the BOX film 3 in the region 1B of the SOI substrate. Further, a step St of the silicon oxide film (s1a, s1d) occurs at the end of the diffusion layer s1c. The height of the step St, that is, the difference between the position of the bottom of the silicon oxide film s1a and the position of the bottom of the silicon oxide film s1d (see FIG. 4) is, for example, about 50 nm to 200 nm.

  As described above, in this embodiment, the bonding layer is used as a method for forming the SOI substrate, and the diffusion layer s1c can be formed with high accuracy by forming the diffusion layer s1c before the bonding step. . For example, in the SOI substrate in which the BOX film 3 and the silicon layer 4 are disposed on the first substrate S1, the boundary between the first substrate S1 and the BOX film 3 is obtained by ion implantation through the silicon layer 4 and the BOX film 3. It is also possible to form the diffusion layer s1c in the part.

  However, ion implantation to such a relatively deep position requires implantation of impurity ions with high energy, and crystal defects are likely to occur in the silicon layer 4. Since the silicon layer 4 is a MISFET formation region, it can be a factor of MISFET characteristic deterioration.

  Moreover, it is difficult to control the ion implantation to a relatively deep position, and it is difficult to implant impurity ions with a desired profile at a desired position even if implantation is performed with high energy.

  On the other hand, according to the present embodiment, since the diffusion layer s1c is formed before the bonding step, it is not necessary to perform ion implantation through the silicon layer 4, and crystal defects in the silicon layer 4 are reduced. Can do.

  Further, since the impurity ions are implanted near the surface of the first substrate S1 (see FIG. 3), the control becomes easy, and the impurity ions can be implanted at a desired position with a desired profile with low energy. Specifically, high-concentration impurity ions can be implanted at a relatively shallow depth. Further, even when an element having an atomic weight larger than that of B (boron) is used, it can be implanted with good controllability.

  Furthermore, accurate position recognition can be performed by using the step St of the silicon oxide film (s1a, s1d) at the end of the diffusion layer s1c as an alignment mark. This will be described in detail in the following “MISFET etc. forming step” column.

<MISFET formation process>
Next, a high-frequency MISFET (T1) and a control circuit MISFET (T2n, T2p) are formed on the main surface of the silicon layer 4 of the SOI substrate. The process will be described in detail below.

  As shown in FIG. 8, a laminated film of an insulating film 5a and an insulating film 5b is formed on the surface of the silicon layer 4. These laminated films serve as a mask film when a groove (element isolation groove) 5c described later is formed.

  For example, the insulating film 5a is formed by thermal oxidation or the like on the surface of the silicon layer 4, and the insulating film 5b is formed on the insulating film 5a by using a CVD method or the like. The insulating film 5a is made of silicon oxide or the like, and the insulating film 5b is made of a silicon nitride film or the like.

  Next, a photoresist film R1 is formed on the insulating film 5b, and exposed and developed to remove the photoresist film R1 in the region where the element isolation insulating film 5 is to be formed. At this time, the reticle (mask original) on which the region to be removed from the photoresist film R1 or the region (pattern) to be left (pattern) is aligned with the SOI substrate, and the reticle pattern is exposed and transferred to a predetermined region. Here, in the present embodiment, since the step St of the silicon oxide film is formed at the end of the diffusion layer s1c, this step St can be used as an alignment mark (alignment mark).

  Thus, in the present embodiment, accurate position recognition can be performed by using the step St of the silicon oxide film at the end of the diffusion layer s1c as an alignment mark. In this embodiment, the step St is used as an alignment mark when the element isolation insulating film 5 is formed. However, it can also be used as an alignment mark in other processes such as the gate electrode 8. However, when the first pattern is formed (here, when the groove (element isolation groove) 5c is formed), no pattern is formed in the lower layer. Therefore, when the groove 5c is formed, alignment can be performed with reference to the step St, so that accurate position recognition is possible.

  Next, as shown in FIG. 9, the laminated film (insulating films 5a and 5b) is patterned using the photoresist film R1 as a mask to remove the laminated film in the region where the element isolation insulating film is to be formed. Next, after removing the photoresist film R1 by ashing or the like, the silicon layer 4 is etched using the laminated film as a mask to form a groove (element isolation groove) 5c. In the present embodiment, since the element isolation insulating film 5 is formed also in the region 1B, the groove 5c is formed also in the region 1B. As described above, according to the present embodiment, the groove 5c is formed using the step St of the silicon oxide film at the end of the diffusion layer s1c as an alignment mark. Therefore, the groove 5c is accurately formed in a desired region. Can be formed.

Next, as shown in FIG. 10, an element isolation insulating film 5 is formed by embedding an insulating film in the trench 5c. For example, after the insulating film 5b is removed by wet etching using hot phosphoric acid or the like, a thin insulating film (not shown) is formed by oxidizing the inside (side wall and bottom) of the groove 5c. Next, a silicon oxide film having a thickness sufficient to fill the trench 5c is formed on the SOI substrate by a CVD method or the like. A silicon oxynitride film may be used instead of the silicon oxide film. The thin insulating film located on the inner wall of the groove 5c has a function of relieving stress due to volume expansion of the element isolation insulating film 5 disposed in the groove 5c. As the silicon oxide film embedded in the groove 5c, a silicon oxide film formed by HDP-CVD (High Density Plasma CVD) method can be used. Further, an O ₃ -TEOS oxide film may be used. The O ₃ -TEOS oxide film is a silicon oxide film formed by a thermal CVD method using O ₃ (ozone) and TEOS (Tetraethoxysilane: Tetra Ethyl Ortho Silicate) as a source gas (source gas). is there.

  Next, the element isolation insulating film 5 is polished by CMP to remove the element isolation insulating film 5 outside the trench 5c, thereby leaving the element isolation insulating film 5 only in the trench 5c. Next, by heat-treating the SOI substrate at, for example, about 1150 ° C., the element isolation insulating film 5 embedded in the trench 5c is baked. Thus, according to the present embodiment, element isolation is achieved by embedding the silicon oxide film in the trench 5c formed using the step St of the silicon oxide film at the end of the diffusion layer s1c as an alignment mark. Since the insulating film 5 is formed, the element isolation insulating film 5 can be accurately formed in a desired region. In the subsequent patterning, the step St of the silicon oxide film at the end of the diffusion layer s1c may be used as an alignment mark, but after this, the layer patterned immediately before (for example, in the next step) For example, the alignment may be performed using an element isolation insulating film 5 or the like.

  As described above, a method of isolating elements by embedding an insulating film in the trench 5c is called an STI (Shallow Trench Isolation) method. Element isolation may be performed using a LOCOS (Local Oxidization of Silicon) method instead of the STI method. For example, the element isolation insulating film 5 may be formed by performing thermal oxidation using the insulating film 5b shown in FIG. 9 as a mask. Also in this case, since the insulating film 5b is patterned using the step St of the silicon oxide film at the end of the diffusion layer s1c as an alignment mark, the element isolation insulating film 5 can be accurately formed in a desired region. .

  The element isolation insulating film 5 is provided on the outer periphery of the high frequency MISFET formation region 1A (including the boundary with the MISFET formation region 2A for the control circuit). The element isolation insulating film 5 is provided between the p-channel MISFET (T2p) and the n-channel MISFET (T2n) in the MISFET formation region 2A for the control circuit.

  Next, as shown in FIG. 11, a p-type well 6 p and an n-type well 6 n are formed in the silicon layer 4. For example, in the silicon layer 4, a photoresist film (not shown) in which the n-channel MISFET (T2n) formation region of the high-frequency MISFET formation region 1A and the MISFET formation region 2A for the control circuit is opened is used as a mask. A type impurity ion (for example, B (boron)) is ion-implanted. Next, after removing the photoresist film (not shown), the photoresist film (not shown) in which the p channel MISFET (T2p) formation region of the MISFET formation region 2A for the control circuit is opened is used as a mask. N-type impurity ions (for example, P (phosphorus) or As (arsenic)) are ion-implanted into the layer 4. Next, the photoresist film (not shown) is removed.

  Next, as shown in FIG. 12, a gate insulating film 7 is formed on the SOI substrate (the surfaces of the p-type well 6p and the n-type well 6n). The gate insulating film 7 is made of, for example, a thin silicon oxide film and is formed by a thermal oxidation method or the like. A silicon nitride film or the like may be used instead of the silicon oxide film.

  Next, a silicon film is formed on the SOI substrate (gate insulating film 7) as a conductive film for forming a gate electrode. For example, a polycrystalline silicon film is formed on the gate insulating film 7 using a CVD method or the like. Further, instead of the polycrystalline silicon film, an amorphous silicon film may be formed and polycrystallized by a subsequent heat treatment. Next, n-type or p-type impurity ions are implanted into the polycrystalline silicon film to form a low-resistance doped polysilicon film. At this time, n-type impurity ions are ion-implanted into the polycrystalline silicon film in the n-channel MISFET (T2n) forming region of the high-frequency MISFET forming region 1A and the MISFET forming region 2A for the control circuit. The doped polysilicon film. A p-type impurity ion is ion-implanted into the polycrystalline silicon film in the formation region of the p-channel type MISFET (T2p) in the MISFET formation region 2A for the control circuit to form a p-type doped polysilicon film. Next, the gate electrode 8 is formed by patterning the doped polysilicon film. The ion implantation is performed using a photoresist film (not shown) having an opening in a predetermined region as a mask. Either ion implantation of n-type or p-type impurity ions may be performed first, and the photoresist film (not shown) used for the ion implantation is removed by ashing or the like after the ion implantation.

Next, as shown in FIG. 13, extension regions 9 are formed in the silicon layer 4 (p-type well 6 p or n-type well 6 n) on both sides of the gate electrode 8. For example, an n-type MISFET (T2n) forming region in the MISFET forming region 1A for high frequency and the MISFET forming region 2A for the control circuit is used as a mask, and an n-type is formed using the gate electrode 8 as a mask. The impurity ions are implanted. Thereby, extension regions 9 which are n ⁻ type semiconductor regions are formed in the p type well 6 p on both sides of the gate electrode 8. Further, p-type impurity ions are ion-implanted using a photoresist film (not shown) having an opening in the formation region of the p-channel MISFET (T2p) in the MISFET formation region 2A for the control circuit and the gate electrode 8 as a mask. Thus, extension regions 9 which are p ⁻ type semiconductor regions are formed in the n type well 6 n on both sides of the gate electrode 8. Note that either ion implantation of n-type or p-type impurity ions may be performed first, and the photoresist film (not shown) used for the ion implantation is removed by ashing or the like after the ion implantation. . In addition, ion implantation may be performed in different steps (different conditions) for the formation region of the n-channel MISFET (T2n) in the high-frequency MISFET formation region 1A and the control circuit MISFET formation region 2A.

  Next, as shown in FIG. 14, a sidewall (sidewall insulating film, sidewall spacer) 10 made of an insulating film is formed on the sidewall of the gate electrode 8. For example, a silicon oxide film or a silicon nitride film or a laminated film thereof is deposited as an insulating film on an SOI substrate using a CVD method, and this insulating film is anisotropically etched using a RIE (Reactive Ion Etching) method or the like. To do. Thereby, the sidewall 10 made of the insulating film can remain on the sidewall of the gate electrode 8.

  Next, as shown in FIG. 15, the high concentration semiconductor region 11 is formed in the silicon layer 4 (p-type well 6 p or n-type well 6 n) on both sides of the composite of the gate electrode 8 and the sidewall 10. For example, a photoresist film (not shown) in which an n-channel MISFET (T2n) formation region in the high-frequency MISFET formation region 1A and the MISFET formation region 2A for the control circuit is opened, the gate electrode 8 and the sidewall 10 are masked. N-type impurity ions are implanted. As a result, the n-type high concentration semiconductor region 11 is formed in the p-type well 6p on both sides of the composite of the gate electrode 8 and the sidewall 10. Next, a p-type impurity ion is formed using a photoresist film (not shown) having an opening in the formation region of the p-channel type MISFET (T2p) in the MISFET formation region 2A for the control circuit, the gate electrode 8 and the sidewall 10 as a mask. Ion implantation. Thus, the p-type high concentration semiconductor region 11 is formed in the n-type well 6n on both sides of the composite of the gate electrode 8 and the sidewall 10. Note that either ion implantation of n-type or p-type impurity ions may be performed first, and the photoresist film (not shown) used for the ion implantation is removed by ashing or the like after the ion implantation. . In addition, ion implantation may be performed in different steps (different conditions) for the formation region of the n-channel MISFET (T2n) in the high-frequency MISFET formation region 1A and the control circuit MISFET formation region 2A.

  The extension region 9 is formed in a self-aligned manner with respect to the gate electrode 8, and the high-concentration semiconductor region 11 is formed in a self-aligned manner with respect to the sidewall 10 on the side wall of the gate electrode 8. The high concentration semiconductor region 11 and the extension region 9 in contact therewith constitute an LDD structure source / drain region. The high concentration semiconductor region 11 has a higher concentration of impurity ions than the extension region 9 in contact therewith.

  Next, heat treatment is performed to activate the impurity ions introduced in the ion implantation step. For example, a spike annealing process at about 1050 ° C. is performed.

  Through the above steps, an n-channel high-frequency MISFET (T1) is formed in the high-frequency MISFET formation region 1A. Also, an n-channel MISFET (T2n) and a p-channel MISFET (T2p) are formed in the MISFET formation region 2A for the control circuit.

Next, as shown in FIG. 16, a silicide layer 12 is formed on the gate electrode 8 and the high concentration semiconductor region 11. The silicide layer 12 is formed using a so-called salicide (Salicide: Self Aligned Silicide) technique. For example, a metal film containing, for example, Co (cobalt) is formed as a metal film on the surface of the SOI substrate including the gate electrode 8 and the high-concentration semiconductor region 11 by a sputtering method. Next, heat treatment is performed to cause a silicidation reaction at a contact portion between the metal film and Si (silicon) constituting the gate electrode 8 or the high-concentration semiconductor region 11. It is preferable to perform the heat treatment twice. As the first heat treatment (1st annealing treatment), after heat treatment at about 250 ° C. to 500 ° C., the unreacted metal film is removed, and as the second heat treatment, heat treatment at about 500 ° C. to 700 ° C. is performed. The unreacted metal film is removed by wet cleaning using sulfuric acid or wet cleaning using SPM (Sulfuric acid Hydrogen Peroxide Mixture). Thereby, a silicide layer 12 made of CoSi ₂ (cobalt silicide) is formed on the gate electrode 8 and the high-concentration semiconductor region 11. Note that a metal film containing titanium, nickel, platinum, or the like may be used as the metal film, and titanium silicide, nickel silicide, platinum silicide, or the like may be formed.

  Next, as shown in FIG. 17, an insulating film 14 is formed on the n-channel high-frequency MISFET (T1), the n-channel MISFET (T2n), and the p-channel MISFET (T2p). The insulating film 14 is made of, for example, a silicon nitride film, and is formed by a plasma CVD method or the like at a deposition temperature (substrate temperature) of about 450 ° C. The insulating film 14 functions as an etching stopper film when forming the contact hole C1b.

  Next, the insulating film 14 is patterned to remove the insulating film 14 in the region 1B and form an opening OA. The opening OA is located in the region 1B and includes at least the contact hole C1a formation region and is larger than the contact hole C1a formation region.

  Next, as shown in FIG. 18, an interlayer insulating film 15 thicker than the insulating film 14 is formed on the insulating film 14 including the inside of the opening OA. The interlayer insulating film 15 is made of, for example, a silicon oxide film or the like, and is formed by a plasma CVD method or the like at a film forming temperature of about 450 ° C. using TEOS as a source gas. Next, the upper surface of the interlayer insulating film 15 is planarized by polishing the surface of the interlayer insulating film 15 by a CMP method or the like.

  Next, as shown in FIG. 19, the interlayer insulating film 15, the element isolation insulating film 5, and the BOX film 3 are etched (patterned) to form a contact hole C1a on the diffusion layer s1c. The contact hole C1a is formed so as to pass through the opening OA. Here, since the insulating film 14 is removed in the opening OA, the silicon oxide film constituting the interlayer insulating film 15, the element isolation insulating film 5, and the BOX film 3 may be etched. That is, it is not necessary to switch the etching conditions in the middle to etch the insulating film 14 which is a silicon nitride film, and further to switch the etching conditions to etch the element isolation insulating film 5 and the BOX film 3. That is, the contact hole C1a can be formed with high accuracy by one etching using the etching selectivity between the silicon oxide film and the silicon constituting the diffusion layer s1c.

  Next, as shown in FIG. 20, the interlayer insulating film 15 and the insulating film 14 are etched (patterned) to form a contact hole C1b on the high-concentration semiconductor region 11. In this etching, the contact hole C1b can be formed with high accuracy by using the insulating film 14 as an etching stopper film. When forming the contact hole C1b, a contact hole may be formed above the gate electrode 8 or a wiring in the same layer connected to the gate electrode 8 (for example, the gate line 8a shown in FIG. 22). .

  There is no limitation on the order of forming the contact hole C1a and the contact hole C1b, and either may be formed first.

  Next, as shown in FIG. 21, a first plug (connection portion, contact plug) P1 is formed by embedding a conductive film inside the contact hole C1a and the contact hole C1b. For example, on the interlayer insulating film 15 including the insides of the contact hole C1a and the contact hole C1b, for example, a titanium film, a titanium nitride film, or a laminated film thereof is formed as a thin barrier conductor film. These films are formed by, for example, a plasma CVD method at a film formation temperature (substrate temperature) of about 450 ° C. Next, a tungsten film, for example, is deposited as a main conductor film with a film thickness enough to fill the contact holes (C1a, C1b) by CVD or the like. Thereafter, unnecessary main conductor films and barrier conductor films on the interlayer insulating film 15 are removed by a CMP method, an etch back method, or the like, thereby forming a first plug P1 made of the main conductor film and the barrier conductor film.

  Next, the first layer wiring M1 is formed on the first plug P1. For example, an Al (aluminum) film is formed as a conductive film on the first plug P1 and the interlayer insulating film 15 using a sputtering method or the like. Next, the first layer wiring M1 is formed on the first plug P1 by patterning the Al film.

  Thereafter, the multilayer wiring may be formed by repeating the steps of forming the interlayer insulating film, the plug and the wiring.

  Through the above steps, each component of the semiconductor device illustrated in FIG. 21 can be formed. According to the semiconductor device of the present embodiment formed as described above, the diffusion layer s1c is provided under the BOX film 3 on the outer periphery of the high-frequency MISFET formation region 1A. The influence of noise on the high frequency MISFET formation region 1A can be reduced. As a result, it is possible to prevent malfunction due to noise of the high-frequency MISFET (T1), and to improve its operating characteristics. Furthermore, the reliability of the semiconductor device can be improved.

  In the above embodiment, the step St of the silicon oxide film provided in the high-frequency MISFET formation region 1A is used as an alignment mark (alignment mark). However, an alignment mark (alignment mark) is previously formed on the scribe line. Mark) may be provided.

  First, the scribe line will be described. FIG. 26 is a plan view of a substrate (wafer). The first substrate S1, the second substrate S2, and the SOI substrate described in the above embodiment are, for example, substantially circular thin plates as shown in FIG. Such a substrate is provided with a plurality of substantially rectangular chip regions CH, and scribe lines SC are provided between the chip regions CH. After a desired semiconductor device is completed in the chip region CH, the substrate (wafer) is cut along the scribe line SC, and a plurality of chips (chip regions CH) are cut out.

  27 to 29 are cross-sectional views or plan views showing other manufacturing steps of the semiconductor device of the present embodiment.

  As shown in FIG. 27, a diffusion layer (semiconductor region, implantation layer) Ms1c is formed on the scribe line SC of the first substrate S1 in the same manner as the diffusion layer s1c. There is no limitation on the planar shape of the diffusion layer Ms1c, but the shape is easy to recognize the position (cross shape, rectangular shape, etc.).

  Next, the diffusion layer Ms1c is wet-oxidized in the same manner as the diffusion layer s1c. As a result, a step St is generated at the end of the diffusion layer Ms1c.

  Next, after polishing the first surface (surface, the surface on the silicon oxide film s1d formation side) of the first substrate S1, the first surface (surface, the surface on the BOX film 3 formation side) of the second substrate S2 is formed thereon. Bonding is performed, and the second surface of the second substrate S2 is polished by CMP to form a thin film. Thereby, an SOI substrate is formed. FIG. 28 is a plan view when the diffusion layer Ms1c is rectangular. A step St is formed along the end of the diffusion layer Ms1c and can be used as an alignment mark (alignment mark).

  That is, when the photoresist film R1 on the insulating film 5b described with reference to FIG. 8 is exposed and developed, the step St at the end of the diffusion layer Ms1c provided in the scribe line SC shown in FIG. 29 is aligned. Used as a mark (alignment mark).

  Thus, by providing a mark for alignment (alignment mark) on the scribe line in advance, accurate position recognition becomes possible. In the present embodiment, the step St is used as an alignment mark when the element isolation insulating film 5 is formed. However, it can also be used as an alignment mark in other processes such as the gate electrode 8. However, when the first pattern is formed as in the case of forming the element isolation insulating film 5, no pattern is formed in the lower layer. Therefore, when the element isolation insulating film 5 is formed, accurate position recognition can be performed by using the step St as an alignment mark. Further, by forming the scribe line SC, it is possible to obtain a shape (cross shape, rectangular shape, etc.) that allows easy position recognition, and position recognition with higher accuracy is possible.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, an n-channel type MISFET is exemplified as a high-frequency MISFET, but this may be a p-channel type MISFET. Further, an n-channel MISFET and a p-channel MISFET may be mixed and used in the high-frequency MISFET formation region 1A.

1A High-frequency MISFET formation region 1B Region 2 Depletion layer 2A MISFET formation region 3 for control circuit BOX film 4 Silicon layer 5 Element isolation insulating film 5a Insulating film 5b Insulating film 5c Groove 6n N-type well 6p P-type well 7 Gate insulating Film 8 Gate electrode 8a Gate line 9 Extension region 10 Side wall 11 High concentration semiconductor region 12 Silicide layer 14 Insulating film 15 Interlayer insulating film 16 Insulating film 100 Switch circuit unit 110 Control circuit unit 111 Negative bias circuit 113 Oscillation circuit 115 Decoder circuit C1a Contact hole C1b Contact hole CH Chip region M1 First layer wiring M2 Second layer wiring Ms1c Diffusion layer OA Opening P1 First plug P2 Second plug R1 Photoresist film RX Terminal S1 First substrate S2 Second substrate SC Scribe line St Step T1 high MISFET for frequency
MISFET for T2 control circuit
MISFET for T2n n-channel control circuit
MISFET for T2p p-channel control circuit
TX terminal s1a silicon oxide film s1b silicon nitride film s1c diffusion layer s1d silicon oxide film

Claims (12)

(A) preparing a first semiconductor substrate having a first surface and a second surface opposite to the first surface, and having a first semiconductor region on the first surface side;
(B) A second semiconductor substrate having a first surface and a second surface opposite to the first surface, an insulating layer on the first surface side, and a semiconductor layer on the second surface side. A preparation process;
(C) bonding the first surface side of the first semiconductor substrate and the first surface side of the second semiconductor substrate;
A method for manufacturing a semiconductor device, comprising: (A) Impurity ions are implanted into the outer periphery of the first region in the first surface of the first semiconductor substrate having the first surface and the second surface opposite to the first surface. Forming, and
(B) A second semiconductor substrate having a first surface and a second surface opposite to the first surface, an insulating layer on the first surface side, and a semiconductor layer on the second surface side. A preparation process;
(C) By bonding the first surface side of the first semiconductor substrate and the first surface side of the second semiconductor substrate,
Forming a substrate having the first semiconductor substrate, an insulating layer disposed on the first semiconductor substrate, and a semiconductor layer disposed on the insulating layer;
(D) forming a first MISFET in the semiconductor layer corresponding to the first region;
A method for manufacturing a semiconductor device, comprising: A second region is disposed outside the first region via the first semiconductor region,
3. The method of manufacturing a semiconductor device according to claim 2, wherein, in the step (d), a second MISFET is formed in the semiconductor layer corresponding to the second region. (A) Impurity ions are implanted into the outer periphery of the first region in the first surface of the first semiconductor substrate having the first surface and the second surface opposite to the first surface. Forming, and
(B) After the step (a), forming an oxide film on the first semiconductor region by oxidizing the first surface side of the first semiconductor substrate;
(C) A second semiconductor substrate having a first surface and a second surface opposite to the first surface, an insulating layer on the first surface side, and a semiconductor layer on the second surface side. A preparation process;
(D) By bonding the first surface side of the first semiconductor substrate and the first surface side of the second semiconductor substrate,
Forming a substrate having the first semiconductor substrate, an insulating layer disposed on the first semiconductor substrate, and a semiconductor layer disposed on the insulating layer;
(E) forming a first MISFET in the semiconductor layer corresponding to the first region,
In the substrate, a step due to the oxide film is generated at an end portion of the first semiconductor region. The step (b)
5. The semiconductor device according to claim 4, wherein the oxide film is formed on the first semiconductor region by wet oxidation using a first insulating film having an opening on the first semiconductor region as a mask. Production method. After the step (b) and before the step (d),
6. The method of manufacturing a semiconductor device according to claim 5, further comprising a step of polishing upper portions of the first insulating film and the oxide film. The method of manufacturing a semiconductor device according to claim 6, wherein the step is caused by a difference in film thickness between the first insulating film and the oxide film after the step (f). After the step (d),
(G) having a step of forming a pattern of a predetermined shape in or on the semiconductor layer;
5. The method of manufacturing a semiconductor device according to claim 4, wherein the step (g) includes a step of performing alignment based on the step. The step (g)
A step of exposing and transferring the pattern of the predetermined shape to the photoresist film on the semiconductor layer;
9. The method of manufacturing a semiconductor device according to claim 8, wherein the alignment is performed based on the step during the exposure transfer. The step (g)
(G1) forming a groove in the semiconductor film based on the pattern of the predetermined shape;
(G2) burying a second insulating film inside the groove;
The method of manufacturing a semiconductor device according to claim 8, wherein: In the step (a), a second semiconductor region is formed by implanting the impurity ions into the scribe region of the first semiconductor substrate,
In the step (b), the oxide film is formed on the first semiconductor region and the second semiconductor region by oxidizing the first surface side of the first semiconductor substrate,
5. The method of manufacturing a semiconductor device according to claim 4, wherein a step due to the oxide film is generated at an end of the second semiconductor region in the substrate. After the step (d),
(G) having a step of forming a pattern of a predetermined shape in the semiconductor layer or on the semiconductor film;
The method of manufacturing a semiconductor device according to claim 11, wherein the step (g) includes a step of performing alignment based on the step in the scribe region.

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