JP2013187993A - Estimated voltage data calculation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an estimated voltage data calculation device in which voltage variation of an AC power supply can be reflected on the estimated voltage data.SOLUTION: Estimated voltage data Vp(n+1) is calculated by the sum of voltage data Vi(n) and a differential value ΔVt(n). Consequently, in the estimated voltage data calculation processing, the voltage data can be estimated by simple and easy calculation processing, without using the calculation processing of a complex curve such as a sine wave. Furthermore, since the component of each term on the right side is a value calculated already, as shown by formula 2, the future voltage data of tn+1 in the sample timing tn can be predicted.

Description

  The present invention relates to an estimated voltage data calculation device that performs an estimation calculation of a voltage value of AC power.

  In power converters such as an AC / DC converter, a power supply voltage is detected using a voltage detection circuit such as a voltage dividing resistor. When the voltage value is detected by the voltage detection circuit, the detection signal is output to the control device, and the control device causes the AC / DC converter to generate and output a drive signal (output signal in claims). ing.

  Japanese Patent Laying-Open No. 2005-229792 (Patent Document 1) shows an example of such a power converter. The power supply apparatus includes an AC / DC converter, two voltage dividing resistors provided in the AC / DC converter, and a control unit including a microcomputer as main components. Of these, one of the voltage dividing resistors is provided on the input side of the converter, and outputs a detection signal of a full-wave rectified wave output from the rectifier circuit. The other voltage dividing resistor is provided on the output side of the converter, and outputs the voltage value of the smoothing capacitor as a detection signal.

Japanese Patent Application Laid-Open No. 2005-229792

  When controlling a power conversion circuit such as a step-up chopper circuit, a technique for estimating an input voltage, setting a control signal (PWM signal) before and after the current time, and controlling the power conversion circuit based on the control signal There is. For example, in the calculation process of the input value of the AC power supply, the input voltage value (estimated voltage data at the time to be estimated) is determined by specifying the phase of the AC power supply using sine waveform data representing the input voltage. ) Is calculated based on sine waveform data.

  However, according to the estimation calculation process as described above, when the load connected to the power network changes, the voltage waveform of the AC power supply also changes accordingly, so that an accurate input voltage value is estimated. I can't. In addition, it is conceivable to reflect the amplitude fluctuation of the AC voltage in the sine waveform data, but even if such estimation calculation processing is adopted, the frequency error of the AC power supply (within 0.2 Hz with respect to 50 Hz or 60 Hz). It is impossible to correct it.

  In view of the above problems, an object of the present invention is to provide an estimated voltage data arithmetic device capable of reflecting voltage fluctuations of an AC power supply in estimated voltage data.

  In order to solve the above problems, the present invention has the following configuration of the estimated voltage data calculation device. That is, the estimated voltage data calculation process includes: a voltage data acquisition process that samples the voltage data of the AC input based on a voltage detection signal that indicates a voltage value of the AC input; Increase / decrease value calculation processing for calculating a difference value with the second voltage data sampled after the sample timing of the first voltage data, and an estimated voltage corresponding to the sample timing after the sample timing of the second voltage data An estimated voltage data calculation process for calculating data based on the difference value is caused to function.

  Preferably, the estimated voltage data is calculated by adding the second voltage data and the difference value.

  Preferably, the sample timing corresponding to the second voltage data is a sample timing that comes immediately after the sample timing corresponding to the first voltage data, and the estimated voltage data is the second voltage data The estimated voltage at the sample timing that comes immediately after the sample timing corresponding to is shown.

  Preferably, the estimated voltage data is calculated by a sum of the second voltage data, the difference value, and the phase compensation value.

  More preferably, the phase compensation value is ΔVk, the time interval between the first sample timing and the second sample timing is Δtd, the difference value calculated for the time interval is ΔVd, and the phase compensation value is The phase compensation value ΔVk is determined by ΔVk = m · ΔVd, where Δtk is the corresponding offset period and m is an integer value determined based on the solution of Δtk / Δtd.

  According to the estimated voltage data calculation device according to the present invention, the fluctuation amount of the input voltage is calculated using the already acquired voltage data, and the estimated voltage data is calculated based on the fluctuation amount. Accordingly, in the estimated voltage data calculated as the predicted value, the fluctuation state of the AC power supply voltage is included in the fluctuation amount of the voltage data, and the fluctuation state of the AC power supply voltage is reflected.

The figure which shows the circuit structure of an AC / DC converter. The figure which shows notionally the calculation process of the estimated voltage data which concerns on Example 1. FIG. The figure explaining the phase delay with respect to AC voltage. The figure which shows notionally the calculation process of the estimated voltage data which concerns on Example 2. FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows an AC / DC power converter according to this embodiment. The AC / DC power conversion apparatus 100 includes a rectification unit 110, an input voltage detection unit 120, a converter unit 130, and a control device 140 connected to an AC power source AC (that is, an AC input). Yes. In the present embodiment, it is assumed that the AC power supply AC is a commercial power supply of 50 Hz or 60 Hz.

  In the rectifying unit 110, each diode is connected in a bridge shape. In the rectifier 110, the power supply voltage Vac is full-wave rectified and output to the subsequent circuit. Hereinafter, the voltage output from the rectifying unit 110 may be referred to as a rectified voltage. Further, bus lines BH and BL are connected to the output point of the rectifying unit 110, respectively.

  According to the figure, the input voltage detection unit 120 uses voltage dividing resistors r1 to r2. Both ends of the voltage dividing resistors r1 and r2 are connected to a bus line. Further, the signal line is connected to the contact point between the resistor r1 and the resistor r2, and the voltage detection signal SGv proportional to the value of the rectified voltage is output. That is, the voltage detection signal SGv is a signal indicating the voltage value of the AC input, and is hereinafter referred to as a detection signal for convenience.

  The converter unit 130 is a so-called PFC converter, and is connected to a reactor L and a diode D inserted in the bus line BH, a power transistor Tr, a drive circuit Drv for supplying a gate signal thereto, and a cathode side of the diode D. The smoothing capacitor Cp is provided. The drive circuit Drv is provided with a PWM-IC and an amplification circuit. When the output signal SGt is received from the control device, the drive circuit Drv generates a PWM signal proportional to the output signal SGt and adjusts the voltage value of the PWM signal to the power transistor Tr. Output. When the power transistor Tr is driven, the PFC converter controls the duty factor to be appropriately adjusted while continuously forming a similar triangular current wave to the rectified voltage and controlling the power factor close to 1. The output voltage is controlled to a constant value.

  The control device 140 is provided with element circuits including a central processing circuit 141, a nonvolatile memory circuit 143, an A / D conversion circuit 144, a volatile memory circuit 145, and a D / A conversion circuit 146. Work with the program to build appropriate functions.

  The central processing circuit 141 constructs an output signal calculation unit in accordance with a command defined by the program. The output signal calculation unit refers to the input value information recorded in the storage area of the memory circuit, and sets the output signal SGt to be supplied to the drive circuit Drv.

  In addition, in the central processing circuit 141, an appropriate program is started, and processing functions related to input voltage estimation calculation such as voltage data increase / decrease calculation processing and estimated voltage data calculation processing are constructed. These processing functions will be described in detail later.

  As shown in the figure, the central processing circuit 141 is appropriately connected to element circuits such as an A / D conversion circuit and a memory circuit via a CPU bus 142. The CPU bus 142 transmits and receives information via a data bus, specifies an address of a storage area of the memory circuit via an address bus, and transmits control signals such as timing via a control bus.

  The nonvolatile memory circuit 143 is a memory circuit called “Read only Memory”, and maintains information in the storage area regardless of the power supply state. In the present embodiment, various programs are recorded in the storage area of the nonvolatile memory circuit 143.

  The A / D conversion circuit 144 samples AC input voltage data based on the detection signal SGv. The A / D conversion circuit 144 includes a plurality of channels of AD registers. When the sampling timing arrives, the AD register creates read data based on the detection signal SGv and performs an operation of sequentially holding this as voltage data. In this embodiment, the timer is set so that the sampling timing in the A / D conversion circuit 144 arrives every 45.5 μsec. Then, the voltage data of the AD register is sequentially stored (electrically held) in the volatile memory circuit 145 in accordance with a command from the central processing circuit 141 synchronized with the sample timing.

  The volatile memory circuit 145 is a memory circuit called “Random Access Memory”, and includes SRAM, DRAM, and the like. The volatile memory circuit 145 electrically holds the voltage data sampled by the A / D conversion circuit 144 in a predetermined storage area. The voltage data is appropriately read into the data register of the central processing circuit 141 in accordance with a predetermined command.

  The D / A conversion circuit 146 outputs an appropriate output signal SGt according to the processing result of the output signal calculation unit. The output signal SGt is a signal including duty information, and may be a PWM signal depending on the configuration of the drive circuit Drv.

  The AC / DC power converter 100 having such a configuration generates and outputs the output signal SGt by the function of the output signal calculation unit, and controls the power transistor Tr on / off via the drive circuit Drv. The power transistor Tr operates in accordance with the duty ratio of the applied PWM signal, and controls the voltage value of the smoothing capacitor Cp. In order to perform such control, the control device 140 converts the AC input detection signal SGv into digital information and stores it as voltage data in the volatile memory circuit 145.

  Further, the control device 140 according to the present embodiment uses the voltage data to estimate voltage data such as an increase / decrease value calculation process for calculating a difference value of the voltage data, an estimated voltage data calculation process for calculating estimated voltage data, and the like. Various processes related to the calculation of are performed. The functional unit of the control device constructed by these processes will be called the estimated voltage data calculation device 140. Hereinafter, these processes will be described in detail with reference to examples.

  FIG. 2 shows sampling timing tn, voltage data Vi (n) and estimated voltage data Vpn corresponding thereto. According to the present embodiment, the sample timing interval is set to 45.5 μsec, which is called the sample interval Δtc. In the figure, the sample timing of the current time is tn. Therefore, the sample timing tn + 1 indicates 45.5 μsec after counting from tn, and the sample timing tn + 2 indicates 91.0 μsec after counting from tn. That is, the right side of the sample timing tn indicates the future, and the left side of the sample timing tn indicates the past.

  When the detection data generation and storage in the volatile memory circuit (hereinafter referred to as data acquisition) of the voltage data Vi (n) at the sample timing tn are completed, the storage of the volatile memory circuit (hereinafter referred to as the memory circuit). The area stores voltage data Vi (n-2), voltage data Vi (n-1) that arrives immediately after this, and voltage data Vi (n) that comes immediately after Vi (n-1). That's right. Here, in the processing corresponding to the current sample timing tn, Vi (n−1) corresponding to the sample timing tn−1 is referred to as first voltage data, and Vi (n) corresponding to the sample timing tn is second. This is called voltage data.

When the second voltage data Vi (n) is acquired, an increase / decrease value calculation process is started. In this process, the second voltage data Vi (n) and the first voltage data Vin (n The difference value ΔVt (n) from −1) is calculated.
ΔVt (n) = Vi (n) −Vi (n−1) Equation 1

  The difference value ΔVt (n) indicates an increase / decrease state between the voltage data at the sample timing tn. In particular, the difference value ΔVt (n) is a parameter that reflects the fluctuation of the AC power supply, and reflects the amplitude fluctuation of the voltage waveform and the frequency fluctuation of the voltage waveform. That is, if the amplitude of the voltage waveform increases, the difference value tends to increase, and if the frequency fluctuation of the voltage waveform occurs, the difference value is finely adjusted as needed.

When this calculation process is completed, an estimated voltage data calculation process is started. In this process, estimated voltage data Vp (n + 1) that arrives after the second voltage data Vi (n) is calculated. In this embodiment, estimated voltage data Vp (n + 1) corresponding to the sample timing tn + 1 is calculated.
Vp (n + 1) = Vi (n) + ΔVt (n) Equation 2

  In this embodiment, as shown in Expression 2, the estimated voltage data Vp (n + 1) is calculated by the sum of the voltage data Vi (n) and the difference value ΔVt (n). Therefore, in the estimated voltage data calculation process, the voltage data can be estimated by a simple and easy calculation process without using a complicated calculation process such as a sine wave calculation. Further, as shown in Expression 2, since the component of each term on the right side is a value that has already been calculated, it is possible to predict the voltage data of tn + 1 which will be in the future at the sample timing tn.

  Further, the estimated voltage data Vp (n + 1) calculated according to the present embodiment uses the difference value ΔVt (n) as a component, and reflects fluctuations in the voltage waveform of the AC power supply, and responds to amplitude fluctuations and frequency fluctuations thereof. Thus, an estimated value with a small error is calculated. In this respect, signal processing with high responsiveness can be realized as compared with the prior art that does not consider fluctuations in the AC power supply.

  Note that the estimated voltage data calculation process is performed when the sample timing is started corresponding to tn + 1, based on the voltage data Vi (n + 1) and the difference value ΔV (n + 1), the estimated voltage data Vp (n + 2) corresponding to the time tn + 2. ) Is calculated. Thus, in this process, as the sample timing advances, the voltage data is estimated at the immediately subsequent sample timing.

  As described above, according to the estimated voltage data calculation device 140 according to the present embodiment, the fluctuation amount of the input voltage is calculated using the already acquired voltage data, and the estimated voltage data is calculated based on the fluctuation amount. . Accordingly, in the estimated voltage data calculated as the predicted value, the fluctuation state of the AC power supply voltage is included in the fluctuation amount of the voltage data, and the fluctuation state of the AC power supply voltage is reflected. By adopting a process that suppresses such an error to some extent, highly responsive control is realized.

  In the present embodiment, the difference value and the estimated voltage data are calculated at each sample timing, but the invention described in the claims is not limited to this. For example, the timing for calculating the difference value and the estimated voltage data may be tn, tn + 2, tn + 4,. As described above, the time interval for calculating the difference value and the estimated voltage data may be appropriately set by the designer according to the sample interval Δtc set by the AD conversion circuit or the CPU.

  Generally, in an electronic device such as a microcomputer, a low-pass filter is provided at an input port, so that a phase delay of a detection signal occurs with a CR filter component. FIG. 3 shows a phase delay state of the detection signal SGv. On the left side of the figure, the moment when the voltage value of the AC voltage is zero is indicated by a solid line vector, and the vector indicated by the dotted line indicates the state of the detection signal SGv. On the other hand, on the right side of the figure, the temporal change of the voltage value is shown, the voltage value Vac of the AC power supply is shown by a solid line, and the voltage value Vi of the detection signal SGv is shown by a dotted line.

  As shown in the figure, the phase of the voltage waveform of the detection signal SGv has a delay angle φ compared to the phase of the actual AC voltage waveform. In the case where a phase delay has occurred, referring to time tx in the figure, the voltage value acquired by the detection signal SGv is recognized as 0 even though the actual AC voltage value is Vx. In this way, a voltage value detection error occurs in accordance with the phase delay. In this embodiment, phase compensation is performed so that such detection errors can be eliminated.

  FIG. 4 shows an example of the phase compensation method. Here, tn-1 to tn + 5 indicate sample timings, Δtc indicates a time interval between preceding and following sample timings, Vac (solid line curve) indicates a voltage waveform of an AC voltage, and Vi (dashed line curve) indicates a voltage based on a detection signal. Waveform is shown. In the following description, it is assumed that tn corresponds to the current process.

  In the present embodiment, similar to the processing according to the first embodiment, the voltage data Vi (n) corresponding to the current sample timing is acquired, and thereafter, the difference value calculation processing and the estimated voltage data calculation processing are executed. That is, when the data acquisition of the voltage data Vi (n) is completed, the estimated voltage data calculation device 140 reads necessary voltage data from the memory circuit and calculates the difference value ΔVt (n). When this process is completed, the estimated voltage data calculation process is started, and the estimated voltage data Vq (n + 1) corresponding to tn + 1 is calculated. Thus, the estimated voltage data before phase compensation is expressed as Vq (n + 1).

Thereafter, in this embodiment, phase compensation processing is performed. In such processing, the phase compensation value ΔVk (n + 1) is further added to the estimated voltage data Vq (n + 1). That is, the phase-compensated estimated voltage data Vp (n + 1) is calculated by the following formula.
Vp (n + 1) = Vi (n) + ΔVt (n) + ΔVk (n + 1) Equation 3

  In this embodiment, the phase compensation value ΔVk (n + 1) is calculated by a process corresponding to tn, so that the phase compensation of the estimated voltage data Vp (n + 1) is completed at the time tn. For this reason, even in the present embodiment, signal processing using estimated voltage data is possible.

  Here, the phase compensation value ΔVk (n + 1) corresponds to a difference value between the estimated voltage data Vq (n + 1) and the AC power supply voltage value. Assuming that a vector connecting the acquired Vi (n) and the estimated voltage data Vq (n + 1) is Vct (n), the horizontal line including the extension line of the vector Vct (n) and the AC voltage value at tn + 1 is shown in FIG. The axis intersects in the vicinity of the timing tn + 5. That is, the vertical component of the vector of the start point Vq (n + 1) and the end point Vq (n + 5) is the phase compensation value ΔVk (n + 1), and this value ΔVk (n + 1) is the difference value as follows: Calculated based on ΔVt (n).

In the phase compensation processing according to the present embodiment, the difference value ΔVt (n) and the integer value m set according to the delay angle are read from the memory circuit, and the phase compensation value ΔVk (n + 1) is calculated by the following equation. .
ΔVk (n + 1) = m · ΔVt (n) Equation 4

The integer value m is a result value implemented in advance, and is not specifically calculated again by the CPU. This integer value m is
N = ΔVt (n) / Δtc Equation 5
Assuming that the value calculated by is a quotient N, an integer value m is determined based on the quotient N. The integer value m may be determined by rounding off the value after the decimal point, or may be determined by rounding up or down the decimal point. Then, based on such prior examination, an integer value m corresponding to the phase delay angle is set. The timing interval Δtc is an example of the time interval Δtd in the claims. Further, the difference value ΔVt corresponding to Δtc is an example of the difference value ΔVd in the claims.

  In this embodiment, the integer value is set as m = 4. As a result, the value of the phase compensation value ΔVk (n + 1) substantially matches the difference between the voltage value of the AC power supply at tn + 1 and the estimated voltage value Vq (n + 1). Therefore, although the estimated voltage data Vp (n + 1) calculated by Expression 3 is a predicted value, the phase compensation is accurately performed.

  In this embodiment, the phase delay related to the CR filter is mentioned, but the processing delay component related to the processing delay of the AD conversion circuit or the calculation of the CPU may be included in the phase compensation value.

  Note that the estimated voltage data calculation device described in the claims is not limited to the converter described in the embodiment, and various circuit configurations for detecting an AC voltage such as a power conditioner isolated operation detection device. It is possible to use.

  100 AC / DC converter, AC AC power supply, 110 rectification unit, 120 input voltage detection unit, 130 converter unit, 140 control device (estimated voltage data calculation device), 141 central processing circuit, 143 nonvolatile memory circuit, 144 input voltage Detection circuit, 145 volatile memory circuit.

Claims (5)

  A voltage data acquisition process for sampling the voltage data of the AC input based on a voltage detection signal indicating a voltage value of the AC input, and after the first voltage data of the voltage data and the sampling timing of the first voltage data. An increase / decrease value calculation process for calculating a difference value from the sampled second voltage data, and estimated voltage data corresponding to a sample timing after a sample timing of the second voltage data are calculated based on the difference value. An estimated voltage data calculation device characterized by causing an estimated voltage data calculation process to function.   The estimated voltage data calculation device according to claim 1, wherein the estimated voltage data is calculated by adding the second voltage data and the difference value. The sample timing corresponding to the second voltage data is a sample timing that comes immediately after the sample timing corresponding to the first voltage data,
3. The estimated voltage according to claim 1, wherein the estimated voltage data indicates an estimated voltage at a sample timing that comes immediately after a sample timing corresponding to the second voltage data. Data arithmetic unit.   The estimated voltage data calculation device according to claim 1, wherein the estimated voltage data is calculated by a sum of the second voltage data, the difference value, and a phase compensation value. The phase compensation value is ΔVk, the time interval between the first sample timing and the second sample timing is Δtd, the difference value calculated for the time interval is ΔVd, and the offset period corresponding to the phase compensation value Is Δtk, and an integer value determined based on the solution of Δtk / Δtd is m.
5. The estimated voltage data arithmetic device according to claim 4, wherein the phase compensation value ΔVk is determined by ΔVk = m · ΔVd.

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