JP2013180538A - Liquid ejecting apparatus and head control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid ejecting apparatus that has a head with a power-on-reset circuit of a compact configuration.SOLUTION: A liquid ejecting apparatus includes a head part that has a first MOS transistor; a second MOS transistor; a first inverter; and a second inverter, and ejects the liquid. A gate and a source of the first MOS transistor are connected to a first power supply, a drain is connected with an input side of the first inverter, the gate of the second MOS transistor is connected with a second power supply that is smaller than the first power supply in terms of output voltage, the source is connected with the ground, the drain is connected with the input side of the first inverter, the output side of the first invertor is connected to the input side of the second invertor, and the second inverter outputs a power-on reset signal that is made from the voltage of the first power supply or the voltage of the ground.

Description

  The present invention relates to a liquid ejection apparatus and a head control circuit.

  2. Description of the Related Art There is known a liquid ejecting apparatus that performs recording by ejecting liquid from a nozzle provided in a head unit and landing droplets (ink dots) on a medium. When liquid is ejected from the liquid ejection device, a drive signal for driving the head and a logic signal are generated by a head control circuit mounted on the head unit, and the operation of the head is performed by applying these signals. Be controlled.

  Normally, these signals are generated using the voltage of the power supply, but after the power supply voltage is turned ON, after the power supply voltage is turned ON, due to the influence of the intermediate potential while the voltage rises from the ground potential, The circuit may malfunction. As a means to prevent malfunction of the control circuit, the control circuit is kept in the reset state until the voltage rises and stabilizes, and the control circuit is operated after the voltage reaches a predetermined level. There is a method of providing a circuit. For example, in Patent Document 1, such a power-on reset circuit is mounted, and a power-on reset signal is generated to suppress malfunction of the control circuit when the power supply voltage rises.

JP-A-5-183416

  In the power-on reset circuit of Patent Document 1, a resistance element is used as an element for generating a power-on reset signal. However, since the size of the resistance element is increased in order to obtain a sufficient resistance value, there is a problem that the control circuit itself is increased in size. In particular, in a liquid ejection apparatus such as an ink jet printer, there is a great demand for miniaturization of the head, and for this purpose, a power-on reset circuit needs to be configured compactly.

  An object of the present invention is to provide a liquid ejection apparatus having a head including a power-on reset circuit having a compact configuration.

  A main invention for achieving the above object is a liquid that includes a first MOS transistor, a second MOS transistor, a first inverter, and a second inverter, and includes a head unit that discharges liquid. In the ejection device, the gate and source of the first MOS transistor are connected to a first power source, the drain is connected to the input side of the first inverter, and the gate of the second MOS transistor is connected to the first power source. Connected to a second power supply whose output voltage is lower than that of the first power supply, a source connected to the ground, a drain connected to the input side of the first inverter, and an output side of the first inverter connected to the second power supply. The second inverter is connected to the input side of the inverter, and the second inverter is a power-on reset composed of the voltage of the first power supply or the voltage of the ground And it outputs the items, a liquid ejecting apparatus according to claim.

  Other features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

1 is a block diagram illustrating an overall configuration of a printer. FIG. 2A is a diagram illustrating the configuration of the printer according to the present embodiment. FIG. 2B is a side view illustrating the configuration of the printer according to the present embodiment. It is sectional drawing for demonstrating the structure of a head. FIG. 4A is a diagram for explaining how the voltage fluctuates when the first power supply is turned on / off. FIG. 4B is a diagram for explaining how the voltage fluctuates when the second power supply is turned ON / OFF. It is a figure showing the structure of the POR circuit of embodiment. It is a schematic explanatory drawing of N channel type MOS FET. It is a figure explaining the 1st inverter 423. FIG. It is a figure explaining the mode of the fluctuation | variation of the voltage in the input side (IN1) of the 1st inverter 423 when a power supply is turned ON / OFF. It is a figure explaining the mode of the fluctuation | variation of the voltage in the output side (IN2) of the 1st inverter 423 when a power supply is turned ON / OFF. It is a figure explaining the mode of the fluctuation | variation of the voltage in the output side (OUT3) of the 2nd inverter 424 when a power supply is turned ON / OFF.

  At least the following matters will become clear from the description of the present specification and the accompanying drawings.

A liquid discharge apparatus having a first MOS transistor, a second MOS transistor, a first inverter, and a second inverter, and having a head portion for discharging a liquid, wherein the first MOS The gate and source of the transistor are connected to a first power supply, the drain is connected to the input side of the first inverter, and the gate of the second MOS transistor has a second output voltage lower than that of the first power supply. The power source of the first inverter is connected to the ground, the drain is connected to the input side of the first inverter, the output side of the first inverter is connected to the input side of the second inverter, The inverter 2 outputs a power-on reset signal composed of the voltage of the first power source or the voltage of the ground. Apparatus.
According to such a liquid ejecting apparatus, a head for ejecting liquid can be reduced in size by including a power-on reset circuit having a compact configuration.

In such a liquid ejecting apparatus, it is preferable that the first power supply is turned on before the second power supply when the liquid ejecting apparatus is operated.
According to such a liquid ejecting apparatus, by turning on the power supply with the larger voltage first, the overall start-up time (time until the voltage rises) can be shortened compared to the reverse case. Can do. In addition, by starting the first power supply first, it becomes easier to generate the POR signal using the voltage of the first power supply.

In such a liquid discharge apparatus, it is desirable that the ON resistance of the first MOS transistor is smaller than the ON resistance of the second MOS transistor.
According to such a liquid ejecting apparatus, the voltage output by the first MOS transistor is affected by the voltage output by the second MOS transistor, and a voltage lower than the voltage of the first power supply is output. The Thereby, the H / L switching timing of the signal input to the inverter can be adjusted.

In this liquid discharge apparatus, it is preferable that the first MOS transistor and the second MOS transistor are both N-channel field effect transistors.
According to such a liquid ejecting apparatus, it is possible to generate a power-on reset signal using only the voltage supplied from the power source (first power source) and to realize a stable liquid ejecting operation.

  A head control circuit that includes a first MOS transistor, a second MOS transistor, a first inverter, and a second inverter, and controls an operation of a head unit that ejects liquid; The gate and source of the first MOS transistor are connected to a first power supply, the drain is connected to the input side of the first inverter, and the gate of the second MOS transistor is output from the first power supply. Connected to a second power supply having a low voltage, connected to the ground at the source, connected to the input side of the first inverter, and output side of the first inverter to the input side of the second inverter. The second inverter outputs a power-on reset signal composed of the voltage of the first power supply or the voltage of the ground. Head control circuit for the butterflies.

=== Basic Configuration of Liquid Discharge Device ===
An ink jet printer (printer 1) will be described as an example of a liquid ejection apparatus for carrying out the invention.

<Printer configuration>
FIG. 1 is a block diagram illustrating the overall configuration of the printer 1. The printer 1 is a liquid ejection device that records (prints) characters and images on a medium such as paper, cloth, and film, and is connected to a computer 110 that is an external device so as to be communicable.

  A printer driver is installed in the computer 110. The printer driver is a program for displaying a user interface on a display device (not shown) and converting image data output from an application program into print data. This printer driver is recorded on a recording medium (computer-readable recording medium) such as a flexible disk FD or a CD-ROM. Also, the printer driver can be downloaded to the computer 110 via the Internet. In addition, this program is comprised from the code | cord | chord for implement | achieving various functions.

  The computer 110 outputs print data corresponding to the image to be printed to the printer 1 in order to cause the printer 1 to print an image. The print data is data in a format that can be interpreted by the printer 1 and includes various command data and pixel data. The command data is data for instructing the printer 1 to execute a specific operation. The command data includes, for example, command data for instructing paper feed, command data for indicating the carry amount, and command data for instructing paper discharge. The pixel data is data related to pixels of an image to be printed. Here, a pixel is a unit element constituting an image, and an image is formed by arranging these pixels two-dimensionally. The pixel data SI in the print data is data (for example, gradation values) related to dots formed on a medium (for example, paper S). The pixel data is composed of, for example, 2-bit data for each pixel.

  The printer 1 includes a transport unit 20, a carriage unit 30, a head unit 40, a detector group 50, and a controller 60. The controller 60 controls each unit such as the head unit 40 based on print data received from the computer 110 which is an external device, and prints an image on a medium. The situation in the printer 1 is monitored by the detector group 50, and the detector group 50 outputs the detection result to the controller 60. The controller 60 controls each unit based on the detection result output from the detector group 50.

<Transport unit 20>
FIG. 2A is a bird's-eye view showing the configuration of the printer 1 of this embodiment, and FIG. 2B is a side view showing the configuration of the printer 1.

  The transport unit 20 is for transporting a medium (for example, paper S) in a predetermined direction (hereinafter referred to as a transport direction). Here, the transport direction is a direction that intersects the moving direction of the carriage. The transport unit 20 includes a paper feed roller 21, a transport motor 22, a transport roller 23, a platen 24, and a paper discharge roller 25 (FIGS. 2A and 2B).

  The paper feed roller 21 is a roller for feeding the paper inserted into the paper insertion slot into the printer. The transport roller 23 is a roller that transports the paper S fed by the paper feed roller 21 to a printable region, and is driven by the transport motor 22. The operation of the transport motor 22 is controlled by a controller 60 on the printer side. The platen 24 is a member that supports the paper S being printed from the back side of the paper S. The paper discharge roller 25 is a roller for discharging the paper S to the outside of the printer, and is provided on the downstream side in the transport direction with respect to the printable area.

<Carriage unit 30>
The carriage unit 30 is for moving (also referred to as “scanning”) the carriage 31 to which the head unit 40 is attached in a predetermined direction (hereinafter referred to as a moving direction). The carriage unit 30 includes a carriage 31 and a carriage motor 32 (also referred to as a CR motor) (FIGS. 2A and 2B).

  The carriage 31 can reciprocate in the moving direction and is driven by a carriage motor 32. The operation of the carriage motor 32 is controlled by a controller 60 on the printer side. Further, the carriage 31 detachably holds an ink cartridge that stores ink.

<Head unit 40>
The head unit 40 is for ejecting ink onto the paper S. The head unit 40 includes a head 41 having a plurality of nozzles and a head controller 42.

  The head 41 is mounted on the carriage 31, and when the carriage 31 moves in the movement direction, the head 41 also moves in the movement direction. Then, when the head 41 is intermittently ejected while moving in the moving direction, dot lines (raster lines) along the moving direction are formed on the medium.

  FIG. 3 is a cross-sectional view showing the structure of the head 41. The head 41 includes a case 411, a flow path unit 412, and a piezo element PZT. The case 411 houses the piezo element PZT, and the flow path unit 412 is joined to the lower surface of the case 411. The flow path unit 412 includes a flow path forming plate 412a, an elastic plate 412b, and a nozzle plate 412c. The flow path forming plate 412a is formed with a groove portion serving as a pressure chamber 412d, a through hole serving as a nozzle communication port 412e, a through port serving as a common ink chamber 412f, and a groove portion serving as an ink supply path 412g. The elastic plate 412b has an island portion 412h to which the tip of the piezo element PZT is joined. An elastic region is formed by an elastic film 412i around the island portion 412h. The ink stored in the ink cartridge is supplied to the pressure chamber 412d corresponding to each nozzle Nz via the common ink chamber 412f. The nozzle plate 412c is a plate on which the nozzles Nz are formed. On the nozzle surface, a yellow nozzle row Y for discharging yellow ink, a magenta nozzle row M for discharging magenta ink, a cyan nozzle row C for discharging cyan ink, and a black nozzle row K for discharging black ink are formed. Has been. Each nozzle row is configured by arranging a plurality of nozzles Nz at predetermined intervals in the transport direction.

  When a drive signal that is a voltage waveform signal is applied to the piezo element PZT, the piezo element PZT expands and contracts (drives) in the vertical direction in accordance with the potential difference between the drive signal and the ground (GND). When the piezo element PZT expands and contracts, the island portion 412h is pushed toward the pressure chamber 412d or pulled in the opposite direction. At this time, the elastic film 412i around the island portion 412h is deformed, and the pressure in the pressure chamber 412d rises and falls, whereby ink droplets are ejected from the nozzles NZ.

The head control unit 42 is a control IC for controlling the operation of the head 41, and is provided in the vicinity of the head 41. For example, it is attached to a cable (flexible flat cable FFC) for transmitting data and the like from the controller 60 to the head 41. Then, a drive signal for driving the piezo element PZT is generated according to a signal transmitted from the controller 60, or a control signal (for example, SW signal) for controlling the drive signal to be applied to the piezo element PZT is generated. Or the operation of the head 41 is controlled by these signals.
The head controller 42 is provided with a power-on reset circuit described later.

<Detector group 50>
The detector group 50 is for monitoring the status of the printer 1. The detector group 50 includes a linear encoder 51, a rotary encoder 52, a paper detection sensor 53, an optical sensor 54, and the like (FIGS. 2A and 2B).

  The linear encoder 51 detects the position of the carriage 31 in the moving direction. The rotary encoder 52 detects the rotation amount of the transport roller 23. The paper detection sensor 53 detects the position of the leading edge of the medium (paper S) being fed. The optical sensor 54 detects the presence / absence of the medium at the opposing position by the light emitting unit and the light receiving unit attached to the carriage 31, for example, detects the position of the edge of the paper while moving, and detects the width of the paper can do. The optical sensor 54 also detects the front end (the end on the downstream side in the transport direction, also referred to as the upper end) and the rear end (the end on the upstream side in the transport direction, also referred to as the lower end) depending on the situation. it can.

<Controller 60>
The controller 60 is a control unit (control unit) for controlling the printer 1. The controller 60 includes an interface unit 61, a CPU 62, a memory 63, and a unit control circuit 64.

  The interface unit 61 transmits and receives data between the computer 110 that is an external device and the printer 1. The CPU 62 is an arithmetic processing device for performing overall control of the printer 1. The memory 63 is for securing an area for storing a program of the CPU 62, a work area, and the like, and is configured by a storage element such as a RAM or an EEPROM. The CPU 62 controls each unit such as the transport unit 20 and the carriage unit 30 via the unit control circuit 64 in accordance with a program stored in the memory 63.

<Printer operation>
The printing operation of the printer 1 will be briefly described. The controller 60 receives a print command from the computer 110 via the interface unit 61 and controls each unit to perform a paper feed process, a dot formation process, a transport process, and the like.

  The paper feed process is a process of supplying paper to be printed into the printer and positioning the paper at a print start position (also referred to as a cue position). The dot formation process is a process of forming dots on paper by intermittently ejecting ink from a head that moves in the movement direction (scanning direction). The carrying process is a process of moving the paper relative to the head in the carrying direction.

The controller 60 alternately repeats the dot formation process and the conveyance process until there is no more data to be printed, and gradually prints an image composed of dot lines on paper. When there is no more data to be printed, the paper discharge roller 25 is rotated to discharge the paper.
The same processing is repeated when printing on the next paper, and the printing operation is terminated when not printing.

=== About the power-on reset circuit ===
A power-on reset circuit provided in the control circuit (head control unit 42 in the present embodiment) will be briefly described. In general, in a power-on reset circuit (hereinafter also referred to as a POR circuit), a control circuit is kept in a reset state from when the power is turned on until the voltage rises and stabilizes, and the voltage has a predetermined magnitude. This circuit generates a power-on reset signal (hereinafter also referred to as a POR signal) that causes the control circuit to operate after becoming.

  FIG. 4A is a diagram for explaining how the voltage fluctuates when the first power supply is turned on / off. FIG. 4B is a diagram for explaining how the voltage fluctuates when the second power supply is turned ON / OFF. The horizontal axis of the figure represents time, and the vertical axis represents the magnitude of the power supply voltage. In the printer 1, the drive signal described above is generated using a voltage of about 42 V supplied from a first power source (hereinafter also referred to as a main power source). Further, the control signal is generated using a voltage of about 3.3 V supplied from a second power source (hereinafter also referred to as a logic power source).

  At time a in FIG. 4A, the first power supply (main power supply) is first turned on, and the voltage gradually rises (rises) from 0.0 V (ground (GND) potential) with time, and at time b. Becomes 42V. When the voltage rises to 42, the main power supply is brought up normally and keeps a stable voltage as it is. When the main power supply is turned off at time i, the voltage gradually decreases as time elapses from 42 V, and becomes GND potential (0.0 V) at time j.

  Further, the second power supply (logic power supply) is turned on at time c in FIG. 4B, the voltage gradually increases (rises) from 0.0V (ground (GND) potential) with time, and the voltage at time e. Becomes 3.3V. When the voltage rises to 3.3, the logic power supply starts up normally and keeps a stable voltage as it is. When the logic power supply is turned off at time f, the voltage gradually decreases as time elapses from 3.3 V, and becomes GND potential (0.0 V) at time h.

  It should be noted that the time required for the high voltage main power supply (42V) to start up is longer than the time required for the low voltage logic power supply (3.3V) to start up. Therefore, in this embodiment, by turning on the logic power supply after turning on the main power supply, the time until both power supplies are completely started up is shortened as much as possible, thereby saving the overall startup time. In addition, by starting the first power supply (main power supply) first, it is possible to generate the POR signal using the voltage (42V) of the main power supply.

  Here, in order to operate the control circuit stably, it is necessary to normally supply both voltages of the main power supply (42V) and the logic power supply (3.3V) to the control circuit. However, during the period when only the main power supply is starting up (the section represented by the hatched portions b to c in FIG. 4A), the logic power supply is not supplied, and the control circuit may malfunction.

  Further, even after the logic power supply is turned on at time c, the voltage gradually rises from 0.0 V and reaches a certain level (hereinafter also referred to as a specified voltage) at which the control circuit operates normally. Takes time. If the time to reach the specified voltage is d, a low voltage less than the specified voltage is supplied to the control circuit in the section indicated by the hatched portion of cd in FIG. 4B. There is a risk.

  In order to suppress such malfunction of the control circuit, at least until both the first power supply (main power supply) and the second power supply (logic power supply) are equal to or higher than the specified voltage (section ax). The control circuit needs to be in a reset state. Then, in a state where both of the two power supply voltages have reached the specified voltage (more precisely, after reaching the specified voltage, the peripheral circuits are stabilized), the reset state is released. The same applies to the operation when the power is turned off, and the control circuit is reset when the two power supply voltages become lower than the specified voltage (gi section in the figure). A signal for forcibly resetting the control circuit at this time is a POR signal.

  In a conventional POR circuit, a POR signal is often generated using a resistance element. However, a certain amount of area is required to make the resistance element have sufficient resistance, and the POR circuit itself is enlarged. There was a problem.

  In the printer 1 of the present embodiment, the head control unit 42 is provided in the vicinity of the head unit 40, and the head control unit 42 is configured to move together with the carriage unit 30 or the like in some cases. Therefore, it is desirable that the size of the head control unit 42 be as small as possible. For this purpose, it is necessary to reduce the size of the POR circuit.

=== Embodiment ===
<Configuration of POR circuit>
FIG. 5 is a diagram showing the configuration of the POR circuit of this embodiment. In the present embodiment, the POR circuit shown in FIG. 5 is incorporated on the wiring board on which the head controller 42 is mounted. The POR circuit generates a POR signal using a voltage of 42 V supplied from the first power source (main power source) and outputs the POR signal to the head control unit 42, thereby allowing the first power source (main power source) and the second power source to be output. The head control unit 42 is prevented from malfunctioning when the power supply (logic power supply) is turned on / off.

  The POR circuit includes a first MOS transistor 421, a second MOS transistor 422, a first inverter 423, and a second inverter 424. The “MOS transistor” means a MOS FET (field effect transistor).

  The first MOS transistor 421 is an N-channel MOS FET (Metal Oxide Semiconductor Field Effect Transistor). FIG. 6 is a schematic explanatory diagram of an N-channel type MOS FET. In the N channel type MOS FET, the source (s) and drain (d) electrodes are provided in the N portion of the NPN type semiconductor, and the gate (g) electrode is formed on the oxide insulating film attached to the NPN type semiconductor. As a metal. When a voltage (positive voltage) is applied to the gate, electrons (carriers) in the N part move to the P part, and a current flows between the source and the drain.

  The length in the direction in which current flows between the source and the drain in the channel of the MOS FET (the length in the lateral direction of the channel in FIG. 6) is referred to as the channel length (L). As the channel length is longer, carriers (electrons) are less likely to flow, and the resistance (ON resistance) of the MOS FET is increased. Further, the length in the direction intersecting the direction in which current flows between the source and drain of the MOS FET (the length in the vertical direction of the channel in FIG. 6) is called the channel width (W). The wider the channel width, the easier the carriers (electrons) flow, so the resistance (ON resistance) of the MOS FET becomes smaller.

  In the present embodiment, the source and gate of the first MOS transistor 421 are connected to the first power supply, and the drain is connected to the input side of the first inverter 423 (see FIG. 5).

  The second MOS transistor 422 is an N-channel type MOS FET. The basic structure is the same as that of the first MOS transistor 421.

  In the present embodiment, the source of the second MOS transistor 422 is connected to the ground (GND), the gate is connected to the second power supply, and the drain is connected to the input side of the first inverter 423 (see FIG. 5).

  The first inverter 423 is a NOT gate, and outputs an H level signal when an L level signal is input. Conversely, when an H level signal is input, an L level signal is output. The output side of the first inverter 423 is connected to the input side of the second inverter 424. As shown in FIG. 5, the point on the input side of the first inverter 423 is IN1, and the point on the output side of the first inverter 423 (that is, the point on the input side of the second inverter 424) is IN2.

  FIG. 7 is a diagram illustrating the first inverter 423. In the first inverter 423, two MOS transistors are complementarily connected, Q1 in the figure is a P-type channel MOS transistor, and Q2 is an N-channel type MOS transistor. When an H level signal is input from the input side (IN1) of the first inverter 423, Q2 is turned on and Q1 is turned off. As a result, the potential on the output side (IN2) of the first inverter 423 is substantially equal to the ground potential (GND) 0.0V. That is, an L level signal is output. Conversely, when an L level signal is input from the input side (IN1) of the first inverter 423, Q2 is turned off and Q1 is turned on. As a result, the potential of IN2 is substantially equal to the voltage 42V of the first power supply, and an H level signal is output.

  The second inverter 424 is a NOT gate similar to the first inverter 423, and outputs an H level signal when an L level signal is input, and outputs an L level signal when an H level signal is input. To do. As shown in FIG. 5, the point on the input side of the second inverter 424 is IN2, and the point on the output side of the second inverter 424 is OUT3.

<POR signal generation operation>
When the first power supply (main power supply) is turned on in the POR circuit of FIG. 5, a voltage is supplied to the gate terminal of the first MOS transistor 421, and the MOS transistor is turned on. That is, a current flows (conducts) between the drain and source of the first MOS transistor 421. Subsequently, when the second power supply (logic power supply) is turned on, a voltage is supplied to the gate terminal of the second MOS transistor 422, and a current flows (conducts) between the drain and source of the second MOS transistor 422.

  FIG. 8 is a diagram for explaining how the voltage fluctuates on the input side (IN1) of the first inverter 423 when the power is turned ON / OFF. The vertical and horizontal axes shown in the figure are the same as those described in FIG. 4A. A voltage value at IN1 is represented by a thick solid line, and a voltage (corresponding to FIG. 4A) supplied from the first power supply (main power supply) is represented by a thick broken line.

  When the first power supply is turned on at time a, the first MOS transistor 421 is turned on, the voltage at the drain terminal of the first MOS transistor 421 begins to rise from 0.0 V, and at time b, the voltage is first The voltage of the power supply (42V). At time c, the second MOS transistor 422 is turned on, and the drain terminal of the second MOS transistor 422 becomes the ground (GND) voltage (0.0 V). In the present embodiment, the ON resistance of the first MOS transistor 421 is lower than the ON resistance of the second MOS transistor 422. Therefore, the first MOS transistor 421 is more likely to pass current, and the influence of the voltage from the first power supply becomes larger than the GND voltage at the point IN1 in FIG. For this reason, the voltage from the first power supply is pulled to the GND side, and the input side (IN1) of the first inverter 423 is lower than the voltage from the first power supply (bold broken line in FIG. 8) after time c. A voltage value (thick solid line in FIG. 8) is output. Then, while the power supply voltage supplied via the first MOS transistor 421 is affected by the GND voltage by the second MOS transistor 422, the output voltage value gradually decreases with time as shown in the section ce in FIG. To do.

  Here, when the threshold value for switching between the H level and the L level of the first inverter 423 is Vth, the time from when the first power supply rises to 42 V at time b until the second power supply rises to the specified voltage at time d. In the meantime, the input side voltage (voltage at IN1) of the first inverter 423 is at the H level. Therefore, the output of the first inverter 423 is at L level at least in the hatched section (bd section) in the figure. On the other hand, when the input-side voltage of the first inverter 423 falls below Vth at time d, the input becomes L level, so the output of the first inverter 423 becomes H level.

  The operation when the voltage drops when the first and second power supplies are turned off is the opposite. That is, in (f-g section), the input voltage of the first inverter 423 is smaller than Vth and becomes L level, so the output of the first inverter 423 is H level. In the hatched section (gi section), the input voltage of the first inverter 423 becomes H level when it is equal to or higher than Vth, so that the output of the first inverter 423 becomes L level.

  FIG. 9 is a diagram for explaining the state of voltage fluctuation on the output side (IN2) of the first inverter 423 when the power is turned ON / OFF. The vertical and horizontal axes in FIG. 9 are the same as those described with reference to FIGS. 4 and 8, and the voltage value at IN2 is represented by a bold solid line. As described above, since the input of the first inverter 423 is at the H level in the (b-d section), the voltage on the output side is the ground (GND) voltage. In the (d-g section), the input of the first inverter 423 is at the L level, so that the voltage on the output side is the voltage (42V) of the first power supply. In (g-i period), the input of the first inverter 423 becomes H level again, so that the ground (GND) voltage is output.

  FIG. 10 is a diagram for explaining the state of voltage fluctuation on the output side (OUT3) of the second inverter 424 when the power is turned ON / OFF. Since the second inverter 424 inverts the signal output from the first inverter 423, the second inverter 424 outputs an L level signal in the (dg section) and an H level signal in the other sections. Therefore, as shown in FIG. 10, the voltage of the first power supply is output in (ad section), the ground (GND) voltage is output in (d section), and (gi section). Then, the voltage of the first power supply is output again. In this embodiment, this voltage signal output from OUT3 is used as the POR signal.

  Thus, after the main power supply is turned on and subsequently the logic power supply is turned on, the voltage of the logic power supply reaches a voltage value (specified voltage value) at which the head control unit 42 operates normally (ad section). ), The POR signal is turned ON, and the head controller 42 is reset. When the voltage of the logic power supply reaches the specified voltage and completely rises (dg section), the POR signal is turned OFF, the head controller 42 operates normally, and the operation of the head 41 is controlled. Then, when the logic power supply and the main power supply are turned off and the voltage of the logic power supply falls below the specified voltage (gi period), the POR signal is turned on again, and the head controller 42 is reset.

<Effect of this embodiment>
In the present embodiment, the POR circuit is configured by using two MOS transistors, and the POR signal is generated, so that the head controller 42 is prevented from malfunctioning when the main power supply and the logic power supply are turned on / off, The head 41 can be operated stably. Thereby, an accurate liquid discharge operation can be performed. Further, since the POR circuit can be made compact by using the MOS transistor, the head controller itself can be downsized. Further, a power-on reset signal can be generated using a voltage supplied from the main power supply. This makes it easier to realize a more stable liquid discharge operation without hindering the operation of the head 41.

=== Other Embodiments ===
Although a printer or the like as one embodiment has been described, the above embodiment is for facilitating the understanding of the present invention, and is not intended to limit the present invention. The present invention can be changed and improved without departing from the gist thereof, and it is needless to say that the present invention includes equivalents thereof. In particular, the embodiments described below are also included in the present invention.

<About liquid ejection device>
In each of the above-described embodiments, the printer has been described as an example of the liquid ejection apparatus, but the present invention is not limited to this. For example, color filter manufacturing apparatus, dyeing apparatus, fine processing apparatus, semiconductor manufacturing apparatus, surface processing apparatus, three-dimensional molding machine, liquid vaporizer, organic EL manufacturing apparatus (especially polymer EL manufacturing apparatus), display manufacturing apparatus, film formation The same technology as that of the present embodiment may be applied to various liquid ejection devices to which inkjet technology such as a device and a DNA chip manufacturing device is applied.

<About piezo elements>
In each of the above-described embodiments, the piezo element PZT is exemplified as an element that performs an operation for discharging a liquid. However, other elements may be used. For example, a heating element or an electrostatic actuator may be used.

<About other liquid ejection devices>
In each of the above-described embodiments, an ink jet printer (serial printer) of a type that moves the head 41 together with the carriage has been described as an example. However, the printer may be a so-called line printer having a fixed head.

<About the printer driver>
In each of the embodiments described above, the printer driver processing is performed by the computer 110 (PC). However, the printer driver may be installed in the controller 60 and the printer driver processing may be performed by the printer itself.

1 printer,
20 transport units, 21 paper feed rollers, 22 transport motors,
23 transport roller, 24 platen, 25 discharge roller,
30 Carriage unit, 31 Carriage, 32 Carriage motor,
40 head units, 41 heads, 411 case, 412 flow path unit,
412a flow path forming plate, 412b elastic plate, 412c nozzle plate,
412d pressure chamber, 412e nozzle communication port, 412f common ink chamber,
412g Ink supply path, 412h island part, 412i elastic film,
42 head controller,
421 first MOS transistor, 422 second MOS transistor,
423 1st inverter, 424 2nd inverter,
50 detector groups, 51 linear encoder, 52 rotary encoder,
53 Paper detection sensor, 54 Optical sensor,
60 controller, 61 interface part,
62 CPU, 63 memory, 64 unit control circuit,
110 computers,
PZT Piezo element

Claims (5)

A liquid ejecting apparatus having a first MOS transistor, a second MOS transistor, a first inverter, and a second inverter, and including a head unit that ejects liquid,
A gate and a source of the first MOS transistor are connected to a first power supply; a drain is connected to an input side of the first inverter;
A gate of the second MOS transistor is connected to a second power supply having an output voltage lower than that of the first power supply, a source is connected to the ground, and a drain is connected to an input side of the first inverter;
The output side of the first inverter is connected to the input side of the second inverter;
The second inverter outputs a power-on reset signal composed of the voltage of the first power supply or the voltage of the ground;
A liquid discharge apparatus characterized by that. The liquid ejection device according to claim 1,
When operating the liquid ejecting apparatus, the first power source is turned on before the second power source. The liquid ejection device according to claim 1 or 2,
The liquid discharge apparatus according to claim 1, wherein an ON resistance of the first MOS transistor is smaller than an ON resistance of the second MOS transistor. The liquid ejection device according to any one of claims 1 to 3,
The liquid ejection apparatus, wherein both the first MOS transistor and the second MOS transistor are N-channel field effect transistors. A head control circuit that has a first MOS transistor, a second MOS transistor, a first inverter, and a second inverter, and controls the operation of a head unit that ejects liquid;
A gate and a source of the first MOS transistor are connected to a first power supply; a drain is connected to an input side of the first inverter;
A gate of the second MOS transistor is connected to a second power supply having an output voltage lower than that of the first power supply, a source is connected to the ground, and a drain is connected to an input side of the first inverter;
The output side of the first inverter is connected to the input side of the second inverter;
The second inverter outputs a power-on reset signal composed of the voltage of the first power supply or the voltage of the ground;
A head control circuit.

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