JP2013180537A - Liquid ejecting apparatus and head control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid ejecting apparatus that has a head with a power-on-reset circuit of a compact configuration.SOLUTION: A liquid ejecting apparatus includes a head part that has a first MOS transistor; a second MOS transistor different from the first MOS transistor; and an inverter and ejects the liquid. A gate and a source of the first MOS transistor are connected to a power supply, a drain is connected with an input side of the inverter, the gate of the second MOS transistor is connected with the power supply, the source is connected with the ground, the drain is connected with the input side of the inverter, and the inverter outputs a power-on reset signal that is made from the voltage of the power supply or the voltage of the ground.

Description

  The present invention relates to a liquid ejection apparatus and a head control circuit.

  2. Description of the Related Art There is known a liquid ejecting apparatus that performs recording by ejecting liquid from a nozzle provided in a head unit and landing droplets (ink dots) on a medium. When liquid is ejected from the liquid ejection device, a drive signal for driving the head and a logic signal are generated by a head control circuit mounted on the head unit, and the operation of the head is performed by applying these signals. Be controlled.

  Normally, these signals are generated using the voltage of the power supply, but after the power supply voltage is turned ON, after the power supply voltage is turned ON, due to the influence of the intermediate potential while the voltage rises from the ground potential, The circuit may malfunction. As a means to prevent malfunction of the control circuit, the control circuit is kept in the reset state until the voltage rises and stabilizes, and the control circuit is operated after the voltage reaches a predetermined level. There is a method of providing a circuit. For example, in Patent Document 1, such a power-on reset circuit is mounted, and a power-on reset signal is generated to suppress malfunction of the control circuit when the power supply voltage rises.

JP-A-5-183416

  In the power-on reset circuit of Patent Document 1, a resistance element is used as an element for generating a power-on reset signal. However, since the size of the resistance element is increased in order to obtain a sufficient resistance value, there is a problem that the control circuit itself is increased in size. In particular, in a liquid ejection apparatus such as an ink jet printer, there is a great demand for miniaturization of the head, and for this purpose, a power-on reset circuit needs to be configured compactly.

  An object of the present invention is to provide a liquid ejection apparatus having a head including a power-on reset circuit having a compact configuration.

  A main invention for achieving the above object is a liquid having a first MOS transistor, a second MOS transistor different from the first MOS transistor, and an inverter, and having a head portion for discharging liquid. In the discharge device, a gate and a source of the first MOS transistor are connected to a power source, a drain is connected to an input side of the inverter, a gate of the second MOS transistor is connected to the power source, and a source is The liquid ejecting apparatus is characterized in that the drain is connected to the ground, the drain is connected to the input side of the inverter, and the inverter outputs a power-on reset signal composed of the voltage of the power source or the voltage of the ground.

  Other features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

1 is a block diagram illustrating an overall configuration of a printer. FIG. 2A is a diagram illustrating the configuration of the printer according to the present embodiment. FIG. 2B is a side view illustrating the configuration of the printer according to the present embodiment. It is sectional drawing for demonstrating the structure of a head. It is a figure explaining the mode of the fluctuation | variation of the voltage when a power supply is turned ON / OFF. It is a figure showing the structure of the POR circuit of embodiment. It is a schematic explanatory drawing of N channel type MOS FET. It is a figure explaining the inverter 423. FIG. It is a figure explaining the mode of the fluctuation | variation of the voltage in the input side (IN1) of the inverter 423 when a power supply is turned ON / OFF. It is a figure explaining the mode of the fluctuation | variation of the voltage in the output side (OUT2) of the inverter 423 when a power supply is turned ON / OFF. It is a figure explaining the mode of the voltage fluctuation of IN1 when ON resistance of the 2nd MOS transistor 422 is made small. It is a figure explaining the mode of the voltage fluctuation of OUT2 when ON resistance of the 2nd MOS transistor 422 is made small.

  At least the following matters will become clear from the description of the present specification and the accompanying drawings.

A liquid discharge apparatus having a first MOS transistor, a second MOS transistor different from the first MOS transistor, and an inverter, and having a head portion for discharging liquid, wherein the first MOS The gate and source of the transistor are connected to the power supply, the drain is connected to the input side of the inverter, the gate of the second MOS transistor is connected to the power supply, the source is connected to the ground, and the drain is input to the inverter. The liquid ejecting apparatus according to claim 1, wherein the inverter outputs a power-on reset signal composed of a voltage of the power source or a voltage of the ground.
According to such a liquid ejecting apparatus, a head for ejecting liquid can be reduced in size by including a power-on reset circuit having a compact configuration.

In such a liquid discharge apparatus, it is desirable that the ON resistance of the first MOS transistor is smaller than the ON resistance of the second MOS transistor.
According to such a liquid ejecting apparatus, the voltage output by the first MOS transistor is affected by the voltage output by the second MOS transistor, and a voltage lower than the power supply voltage is output. Thereby, the H / L switching timing of the signal input to the inverter can be adjusted.

In such a liquid ejection apparatus, when a current starts to flow between the source and the drain of the first MOS transistor, a threshold value when a current starts to flow between the source and the drain of the second MOS transistor It is desirable to be smaller than the threshold value.
According to such a liquid ejecting apparatus, the second MOS transistor becomes easier to operate before the first MOS transistor.

In such a liquid ejecting apparatus, when the liquid is ejected from the liquid ejecting apparatus, the first MOS transistor and the second MOS transistor operate simultaneously, or only the second MOS transistor operates. It is desirable to do.
According to such a liquid ejecting apparatus, since the second MOS transistor is always operating when the first MOS transistor is operating, the voltage on the output side of the two transistors is always higher than the voltage of the power supply. Also lower.

In this liquid discharge apparatus, it is preferable that the first MOS transistor and the second MOS transistor are both N-channel field effect transistors.
According to such a liquid ejecting apparatus, it is possible to generate a power-on reset signal using only the voltage supplied from the power source, thereby realizing a stable liquid ejecting operation.

In this liquid discharge apparatus, the length of the direction in which the current flows between the source and the drain in the channel of the first MOS transistor is the length in the direction in which the current flows in the channel of the second MOS transistor. Longer than the length is desirable.
According to such a liquid ejecting apparatus, the ON resistance of the second MOS transistor becomes smaller than the ON resistance of the first MOS transistor, and the signal input to the inverter is switched between H / L when the voltage rises. Timing can be delayed.

In such a liquid ejection device, the length in the direction intersecting the direction in which the current flows between the source and the drain in the channel of the first MOS transistor has a length in the channel of the second MOS transistor. It is desirable that the length is shorter than the length in the direction intersecting the direction in which the gas flows.
According to such a liquid ejecting apparatus, the ON resistance of the second MOS transistor becomes smaller than the ON resistance of the first MOS transistor, and the signal input to the inverter is switched between H / L when the voltage rises. Timing can be delayed.

  A head control circuit that has a first MOS transistor, a second MOS transistor different from the first MOS transistor, and an inverter, and controls the operation of a head unit that ejects liquid; The gate and source of the first MOS transistor are connected to a power source, the drain is connected to the input side of the inverter, the gate of the second MOS transistor is connected to the power source, the source is connected to ground, and the drain Is connected to the input side of the inverter, and the inverter outputs a power-on reset signal composed of the voltage of the power supply or the voltage of the ground.

=== Basic Configuration of Liquid Discharge Device ===
An ink jet printer (printer 1) will be described as an example of a liquid ejection apparatus for carrying out the invention.

<Printer configuration>
FIG. 1 is a block diagram illustrating the overall configuration of the printer 1. The printer 1 is a liquid ejection device that records (prints) characters and images on a medium such as paper, cloth, and film, and is connected to a computer 110 that is an external device so as to be communicable.

  A printer driver is installed in the computer 110. The printer driver is a program for displaying a user interface on a display device (not shown) and converting image data output from an application program into print data. This printer driver is recorded on a recording medium (computer-readable recording medium) such as a flexible disk FD or a CD-ROM. Also, the printer driver can be downloaded to the computer 110 via the Internet. In addition, this program is comprised from the code | cord | chord for implement | achieving various functions.

  The computer 110 outputs print data corresponding to the image to be printed to the printer 1 in order to cause the printer 1 to print an image. The print data is data in a format that can be interpreted by the printer 1 and includes various command data and pixel data. The command data is data for instructing the printer 1 to execute a specific operation. The command data includes, for example, command data for instructing paper feed, command data for indicating the carry amount, and command data for instructing paper discharge. The pixel data is data related to pixels of an image to be printed. Here, a pixel is a unit element constituting an image, and an image is formed by arranging these pixels two-dimensionally. The pixel data SI in the print data is data (for example, gradation values) related to dots formed on a medium (for example, paper S). The pixel data is composed of, for example, 2-bit data for each pixel.

  The printer 1 includes a transport unit 20, a carriage unit 30, a head unit 40, a detector group 50, and a controller 60. The controller 60 controls each unit such as the head unit 40 based on print data received from the computer 110 which is an external device, and prints an image on a medium. The situation in the printer 1 is monitored by the detector group 50, and the detector group 50 outputs the detection result to the controller 60. The controller 60 controls each unit based on the detection result output from the detector group 50.

<Transport unit 20>
FIG. 2A is a bird's-eye view showing the configuration of the printer 1 of this embodiment, and FIG. 2B is a side view showing the configuration of the printer 1.

  The transport unit 20 is for transporting a medium (for example, paper S) in a predetermined direction (hereinafter referred to as a transport direction). Here, the transport direction is a direction that intersects the moving direction of the carriage. The transport unit 20 includes a paper feed roller 21, a transport motor 22, a transport roller 23, a platen 24, and a paper discharge roller 25 (FIGS. 2A and 2B).

  The paper feed roller 21 is a roller for feeding the paper inserted into the paper insertion slot into the printer. The transport roller 23 is a roller that transports the paper S fed by the paper feed roller 21 to a printable region, and is driven by the transport motor 22. The operation of the transport motor 22 is controlled by a controller 60 on the printer side. The platen 24 is a member that supports the paper S being printed from the back side of the paper S. The paper discharge roller 25 is a roller for discharging the paper S to the outside of the printer, and is provided on the downstream side in the transport direction with respect to the printable area.

<Carriage unit 30>
The carriage unit 30 is for moving (also referred to as “scanning”) the carriage 31 to which the head unit 40 is attached in a predetermined direction (hereinafter referred to as a moving direction). The carriage unit 30 includes a carriage 31 and a carriage motor 32 (also referred to as a CR motor) (FIGS. 2A and 2B).

  The carriage 31 can reciprocate in the moving direction and is driven by a carriage motor 32. The operation of the carriage motor 32 is controlled by a controller 60 on the printer side. Further, the carriage 31 detachably holds an ink cartridge that stores ink.

<Head unit 40>
The head unit 40 is for ejecting ink onto the paper S. The head unit 40 includes a head 41 having a plurality of nozzles and a head controller 42.

  The head 41 is mounted on the carriage 31, and when the carriage 31 moves in the movement direction, the head 41 also moves in the movement direction. Then, when the head 41 is intermittently ejected while moving in the moving direction, dot lines (raster lines) along the moving direction are formed on the medium.

  FIG. 3 is a cross-sectional view showing the structure of the head 41. The head 41 includes a case 411, a flow path unit 412, and a piezo element PZT. The case 411 houses the piezo element PZT, and the flow path unit 412 is joined to the lower surface of the case 411. The flow path unit 412 includes a flow path forming plate 412a, an elastic plate 412b, and a nozzle plate 412c. The flow path forming plate 412a is formed with a groove portion serving as a pressure chamber 412d, a through hole serving as a nozzle communication port 412e, a through port serving as a common ink chamber 412f, and a groove portion serving as an ink supply path 412g. The elastic plate 412b has an island portion 412h to which the tip of the piezo element PZT is joined. An elastic region is formed by an elastic film 412i around the island portion 412h. The ink stored in the ink cartridge is supplied to the pressure chamber 412d corresponding to each nozzle Nz via the common ink chamber 412f. The nozzle plate 412c is a plate on which the nozzles Nz are formed. On the nozzle surface, a yellow nozzle row Y for discharging yellow ink, a magenta nozzle row M for discharging magenta ink, a cyan nozzle row C for discharging cyan ink, and a black nozzle row K for discharging black ink are formed. Has been. Each nozzle row is configured by arranging a plurality of nozzles Nz at predetermined intervals in the transport direction.

  When a drive signal that is a voltage waveform signal is applied to the piezo element PZT, the piezo element PZT expands and contracts (drives) in the vertical direction in accordance with the potential difference between the drive signal and the ground (GND). When the piezo element PZT expands and contracts, the island portion 412h is pushed toward the pressure chamber 412d or pulled in the opposite direction. At this time, the elastic film 412i around the island portion 412h is deformed, and the pressure in the pressure chamber 412d rises and falls, whereby ink droplets are ejected from the nozzles NZ.

The head control unit 42 is a control IC for controlling the operation of the head 41, and is provided in the vicinity of the head 41. For example, it is attached to a cable (flexible flat cable FFC) for transmitting data and the like from the controller 60 to the head 41. Then, a drive signal for driving the piezo element PZT is generated according to a signal transmitted from the controller 60, or a control signal (for example, SW signal) for controlling the drive signal to be applied to the piezo element PZT is generated. Or the operation of the head 41 is controlled by these signals.
The head controller 42 is provided with a power-on reset circuit described later.

<Detector group 50>
The detector group 50 is for monitoring the status of the printer 1. The detector group 50 includes a linear encoder 51, a rotary encoder 52, a paper detection sensor 53, an optical sensor 54, and the like (FIGS. 2A and 2B).

  The linear encoder 51 detects the position of the carriage 31 in the moving direction. The rotary encoder 52 detects the rotation amount of the transport roller 23. The paper detection sensor 53 detects the position of the leading edge of the medium (paper S) being fed. The optical sensor 54 detects the presence / absence of the medium at the opposing position by the light emitting unit and the light receiving unit attached to the carriage 31, for example, detects the position of the edge of the paper while moving, and detects the width of the paper can do. The optical sensor 54 also detects the front end (the end on the downstream side in the transport direction, also referred to as the upper end) and the rear end (the end on the upstream side in the transport direction, also referred to as the lower end) depending on the situation. it can.

<Controller 60>
The controller 60 is a control unit (control unit) for controlling the printer 1. The controller 60 includes an interface unit 61, a CPU 62, a memory 63, and a unit control circuit 64.

  The interface unit 61 transmits and receives data between the computer 110 that is an external device and the printer 1. The CPU 62 is an arithmetic processing device for performing overall control of the printer 1. The memory 63 is for securing an area for storing a program of the CPU 62, a work area, and the like, and is configured by a storage element such as a RAM or an EEPROM. The CPU 62 controls each unit such as the transport unit 20 and the carriage unit 30 via the unit control circuit 64 in accordance with a program stored in the memory 63.

<Printer operation>
The printing operation of the printer 1 will be briefly described. The controller 60 receives a print command from the computer 110 via the interface unit 61 and controls each unit to perform a paper feed process, a dot formation process, a transport process, and the like.

  The paper feed process is a process of supplying paper to be printed into the printer and positioning the paper at a print start position (also referred to as a cue position). The dot formation process is a process of forming dots on paper by intermittently ejecting ink from a head that moves in the movement direction (scanning direction). The carrying process is a process of moving the paper relative to the head in the carrying direction.

The controller 60 alternately repeats the dot formation process and the conveyance process until there is no more data to be printed, and gradually prints an image composed of dot lines on paper. When there is no more data to be printed, the paper discharge roller 25 is rotated to discharge the paper.
The same processing is repeated when printing on the next paper, and the printing operation is terminated when not printing.

=== About the power-on reset circuit ===
A power-on reset circuit provided in the control circuit (head control unit 42 in the present embodiment) will be briefly described. In general, in a power-on reset circuit (hereinafter also referred to as a POR circuit), a control circuit is kept in a reset state from when the power is turned on until the voltage rises and stabilizes, and the voltage has a predetermined magnitude. This circuit generates a power-on reset signal (hereinafter also referred to as a POR signal) that causes the control circuit to operate after becoming.

  FIG. 4 is a diagram for explaining how the voltage fluctuates when the power is turned on / off. The horizontal axis of the figure represents time, and the vertical axis represents the magnitude of the power supply voltage. When the power supply is turned on at time a, the voltage gradually increases (rises) from 0.0 V (ground (GND) potential) with time, and becomes Vdd at time c. When the voltage rises to Vdd, the power supply starts up normally and keeps a stable voltage as it is. When the power is turned off at time d, the voltage gradually decreases with time from Vdd, and becomes GND potential (0.0 V) at time f.

  Here, if the time from when the voltage rises from 0.0 V to the voltage for normal operation of the control circuit (hereinafter also referred to as a specified voltage) is b, it is represented by the hatched portions in FIGS. If a low voltage lower than the specified voltage is supplied to the control circuit during the interval, the control circuit may malfunction. In order to suppress malfunction of the control circuit, it is necessary to keep the control circuit in a reset state at least until the voltage reaches the specified voltage (a-b interval). Then, after the voltage reaches the specified voltage (more precisely, after the specified voltage is reached, the peripheral circuits are stabilized), the reset state is released. The same applies to the operation when turning off the power, and the control circuit is reset when the voltage becomes lower than the specified voltage (section ef in the figure). A signal for forcibly resetting the control circuit at this time is a POR signal.

  In a conventional POR circuit, a POR signal is often generated using a resistance element. However, a certain amount of area is required to make the resistance element have sufficient resistance, and the POR circuit itself is enlarged. There was a problem.

  In the printer 1 of the present embodiment, the head control unit 42 is provided in the vicinity of the head unit 40, and the head control unit 42 is configured to move together with the carriage unit 30 or the like in some cases. Therefore, it is desirable that the size of the head control unit 42 be as small as possible. For this purpose, it is necessary to reduce the size of the POR circuit.

=== Embodiment ===
<Configuration of POR circuit>
FIG. 5 is a diagram showing the configuration of the POR circuit of this embodiment. In the present embodiment, the POR circuit shown in FIG. 5 is incorporated on the wiring board on which the head controller 42 is mounted. The POR circuit generates a POR signal using the voltage supplied from the power supply and outputs the POR signal to the head control unit 42, thereby suppressing the head control unit 42 from malfunctioning when the power is turned on / off. Note that the power supply shown in the figure is a power supply (also referred to as a logic power supply) that supplies a voltage of about 3.3 V used to generate a control signal.

  The POR circuit includes a first MOS transistor 421, a second MOS transistor 422, and an inverter 423. The “MOS transistor” means a MOS FET (field effect transistor).

  The first MOS transistor 421 is an N-channel MOS FET (Metal Oxide Semiconductor Field Effect Transistor). FIG. 6 is a schematic explanatory diagram of an N-channel type MOS FET. In the N channel type MOS FET, the source (s) and drain (d) electrodes are provided in the N portion of the NPN type semiconductor, and the gate (g) electrode is formed on the oxide insulating film attached to the NPN type semiconductor. As a metal. When a voltage (positive voltage) is applied to the gate, electrons (carriers) in the N part move to the P part, and a current flows between the source and the drain.

  The length in the direction in which current flows between the source and the drain in the channel of the MOS FET (the length in the lateral direction of the channel in FIG. 6) is referred to as the channel length (L). As the channel length is longer, carriers (electrons) are less likely to flow, and the resistance (ON resistance) of the MOS FET is increased. Further, the length in the direction intersecting the direction in which current flows between the source and drain of the MOS FET (the length in the vertical direction of the channel in FIG. 6) is called the channel width (W). The wider the channel width, the easier the carriers (electrons) flow, so the resistance (ON resistance) of the MOS FET becomes smaller.

  In the present embodiment, the source and gate of the first MOS transistor 421 are connected to the power supply, and the drain is connected to the input side of the inverter 423 (see FIG. 5).

  The second MOS transistor 422 is an N-channel type MOS FET. The basic structure is the same as that of the first MOS transistor 421, but the channel length L and the channel width W are different, and the ON resistance value and the conduction threshold value are thereby different. That is, in the present embodiment, a transistor different from the first MOS transistor 421 is used as the second MOS transistor 422. The conduction threshold is a value representing the ease of flow when current begins to flow between the drain and the source. The smaller the conduction threshold, the easier the current flows.

  In the present embodiment, the source of the second MOS transistor 422 is connected to the ground (GND), the gate is connected to the power supply, and the drain is connected to the input side of the inverter 423 (see FIG. 5).

  The inverter 423 is a NOT gate, and outputs an H level signal when an L level signal is input. Conversely, when an H level signal is input, an L level signal is output. As shown in FIG. 5, the point on the input side of the inverter 423 is IN1, and the point on the output side of the inverter 423 is OUT2.

  FIG. 7 is a diagram illustrating the inverter 423. The inverter 423 has two MOS transistors connected in a complementary manner, Q1 in the figure is a P-type channel MOS transistor, and Q2 is an N-channel type MOS transistor. When an H level signal is input from the input side (IN1) of the inverter 423, Q2 is turned on and Q1 is turned off. As a result, the potential on the output side (OUT2) of the inverter 423 becomes substantially equal to the potential 0.0V of the ground (GND). That is, an L level signal is output. Conversely, when an L level signal is input from the input side (IN1) of the inverter 423, Q2 is turned off and Q1 is turned on. As a result, the potential of OUT2 becomes substantially equal to the power supply voltage vdd, and an H level signal is output.

<POR signal generation operation>
When the power is turned on in the POR circuit of FIG. 5, the power supply voltage is supplied to the gate terminals of the first MOS transistor 421 and the second MOS transistor 422, and each MOS transistor is turned on. That is, a current flows (conducts) between the drain and source of the MOS transistor. In the present embodiment, the conduction threshold of the second MOS transistor 422 is set lower than that of the first MOS transistor 421. Therefore, the second MOS transistor 422 is more likely to be conducted first. That is, when the POR circuit of this embodiment operates, only the second MOS transistor 422 operates (is in an ON state), and the first MOS transistor 421 and the second MOS transistor 422 operate simultaneously ( May be ON at the same time).

  FIG. 8 is a diagram for explaining how the voltage fluctuates on the input side (IN1) of the inverter 423 when the power is turned ON / OFF. The vertical and horizontal axes shown in the figure are the same as those described in FIG. A voltage value at IN1 is represented by a thick solid line, and a voltage (corresponding to FIG. 4) supplied from a power source is represented by a thick broken line.

  When the power supply is turned on at time a, the second MOS transistor 422 is turned on, and the drain terminal of the second MOS transistor 422 becomes the ground (GND) voltage (0.0 V). The first MOS transistor 421 is turned on slightly later than the second MOS transistor 422, and the drain terminal of the first MOS transistor 421 becomes the voltage of the power supply. In the present embodiment, the ON resistance of the first MOS transistor 421 is lower than the ON resistance of the second MOS transistor 422. Therefore, the first MOS transistor 421 is more likely to pass current, and the influence of the power supply voltage is larger than the GND voltage at the point IN1 in FIG. For this reason, the power supply voltage is pulled toward the GND side, and a voltage value (thick solid line in FIG. 8) lower than the power supply voltage (thick broken line in FIG. 8) is output on the input side (IN1) of the inverter 423. The voltage value at IN1 is always affected by the GND voltage because the second MOS transistor 422 is always ON when the first MOS transistor 421 is ON due to the magnitude of the conduction threshold as described above. A value lower than the power supply voltage is output. Then, while the power supply voltage supplied via the first MOS transistor 421 is affected by the GND voltage by the second MOS transistor 422, the output voltage value gradually increases with the passage of time as in the section a-c in FIG. To do.

  Here, assuming that the threshold for switching between the H level and the L level of the inverter 423 is Vth, the input-side voltage of the inverter 423 (voltage at IN1) is L until the time b is reached after the power is turned on at time a. Is a level. For this reason, the output of the inverter 423 is at the H level in the hatched section (ab section). On the other hand, when the input side voltage of inverter 423 exceeds Vth at time b, the input becomes H level, so the output of inverter 423 becomes L level.

  The operation when the power is turned off and the voltage drops is the opposite. That is, in the (be-e period), the input voltage of the inverter 423 becomes H level when it is equal to or higher than Vth. In the hatched section (e-f section), the input voltage of the inverter 423 is smaller than Vth and becomes L level, so that the output of the inverter 423 becomes H level.

  FIG. 9 is a diagram for explaining the state of voltage fluctuation on the output side (OUT2) of the inverter 423 when the power is turned ON / OFF. The vertical and horizontal axes in FIG. 9 are the same as those described with reference to FIGS. 4 and 8, and the voltage value at OUT2 is represented by a bold solid line. As described above, since the input of the inverter 423 is at the L level in the (a−b section), the voltage on the output side is the power supply voltage. In (be section), since the input of the inverter 423 is at the H level, the voltage on the output side is 0.0V. In (ef section), since the input of the inverter 423 becomes L level again, the power supply voltage is output. In this embodiment, this voltage signal output from OUT2 is used as the POR signal.

  Thereby, after the power is turned on, the POR signal is turned on until the power supply voltage reaches the voltage value (specified voltage value) at which the head control unit 42 operates normally (a-b section), and the head The controller 42 is reset. When the power supply voltage reaches the specified voltage and completely rises (be-e section), the POR signal is turned OFF, the head control unit 42 operates normally, and the operation of the head 41 is controlled. When the power supply is turned off and the power supply voltage falls below the specified voltage (e-f section), the POR signal is turned on again, and the head controller 42 is reset.

<POR signal reset switching timing>
In FIG. 9, the example in which the ON / OFF switching of the POR signal is performed at the timing of time b and time e has been described, but this switching timing can be changed by adjusting the magnitude of the ON resistance of the MOS transistor. Can do.

  For example, by reducing the ON resistance of the second MOS transistor 422, the ON / OFF switching timing of the POR signal when the voltage rises can be delayed. FIG. 10 is a diagram for explaining the voltage fluctuation state of IN1 when the ON resistance of the second MOS transistor 422 is reduced. FIG. 11 is a diagram for explaining the state of voltage fluctuation at OUT2 when the ON resistance of the second MOS transistor 422 is reduced.

  By reducing the ON resistance, a current easily flows through the second MOS transistor 422. Accordingly, the influence of the GND voltage on the power supply voltage in IN1 increases, and the output voltage of IN1 decreases. Since the output voltage is reduced, the time required for the voltage to rise to the threshold value Vth of the inverter 423 after the power supply is turned on becomes longer. In FIG. 10, the voltage reaches Vth at time b2 later than time b. This causes a delay in the timing at which the output of the inverter 423 switches from the H level to the L level. Therefore, in the generated POR signal, the switching timing when the control circuit is reset is delayed (in FIG. 11, it is delayed from time b to time b2). In this way, by changing the reset switching timing, it is possible to generate and input the POR signal that is the optimal switching timing for the control circuit to the control circuit.

  As a method of reducing the ON resistance of the second MOS transistor 422, there is a method of widening the channel width or shortening the channel length. Further, in such timing adjustment, there is a problem in the ease of current flow when compared with the first MOS transistor 421. Therefore, the relationship between the first MOS transistor 421 and the second MOS transistor 422 may be adjusted by reducing the channel length or increasing the channel width so that the second MOS transistor 422 has a smaller ON resistance. Conversely, there is a method in which the ON resistance of the first MOS transistor 421 is larger than that of the second MOS transistor 422.

  Further, when the ON / OFF switching timing of the POR signal is desired to be advanced, the ON resistance of the first MOS transistor 421 is decreased or the ON resistance of the second MOS transistor 422 is increased.

<Effect of this embodiment>
In the present embodiment, the POR circuit is configured using two different MOS transistors and the POR signal is generated, so that the head controller 42 is prevented from malfunctioning when the power is turned on / off, and the head 41 is It can be operated stably. Thereby, an accurate liquid discharge operation can be performed. Further, since the POR circuit can be made compact by using the MOS transistor, the head controller itself can be downsized. Further, the power-on reset signal can be generated using only the voltage supplied from the power source. Accordingly, it is easy to realize a more stable liquid discharge operation without hindering the operation of the head 41.

=== Other Embodiments ===
Although a printer or the like as one embodiment has been described, the above embodiment is for facilitating the understanding of the present invention, and is not intended to limit the present invention. The present invention can be changed and improved without departing from the gist thereof, and it is needless to say that the present invention includes equivalents thereof. In particular, the embodiments described below are also included in the present invention.

<About liquid ejection device>
In each of the above-described embodiments, the printer has been described as an example of the liquid ejection apparatus, but the present invention is not limited to this. For example, color filter manufacturing apparatus, dyeing apparatus, fine processing apparatus, semiconductor manufacturing apparatus, surface processing apparatus, three-dimensional molding machine, liquid vaporizer, organic EL manufacturing apparatus (especially polymer EL manufacturing apparatus), display manufacturing apparatus, film formation The same technology as that of the present embodiment may be applied to various liquid ejection devices to which inkjet technology such as a device and a DNA chip manufacturing device is applied.

<About piezo elements>
In each of the above-described embodiments, the piezo element PZT is exemplified as an element that performs an operation for discharging a liquid. However, other elements may be used. For example, a heating element or an electrostatic actuator may be used.

<About other liquid ejection devices>
In each of the above-described embodiments, an ink jet printer (serial printer) of a type that moves the head 41 together with the carriage has been described as an example. However, the printer may be a so-called line printer having a fixed head.

<About the printer driver>
In each of the embodiments described above, the printer driver processing is performed by the computer 110 (PC). However, the printer driver may be installed in the controller 60 and the printer driver processing may be performed by the printer itself.

1 printer,
20 transport units, 21 paper feed rollers, 22 transport motors,
23 transport roller, 24 platen, 25 discharge roller,
30 Carriage unit, 31 Carriage, 32 Carriage motor,
40 head units, 41 heads, 411 case, 412 flow path unit,
412a flow path forming plate, 412b elastic plate, 412c nozzle plate,
412d pressure chamber, 412e nozzle communication port, 412f common ink chamber,
412g Ink supply path, 412h island part, 412i elastic film,
42 head controller,
421 first MOS transistor, 422 second MOS transistor,
423 inverter,
50 detector groups, 51 linear encoder, 52 rotary encoder,
53 Paper detection sensor, 54 Optical sensor,
60 controller, 61 interface part,
62 CPU, 63 memory, 64 unit control circuit,
110 computers,
PZT Piezo element

Claims (8)

A liquid ejecting apparatus including a first MOS transistor, a second MOS transistor different from the first MOS transistor, and an inverter, and including a head unit that ejects liquid,
The gate and source of the first MOS transistor are connected to a power source, the drain is connected to the input side of the inverter,
The gate of the second MOS transistor is connected to the power supply, the source is connected to the ground, the drain is connected to the input side of the inverter,
The inverter outputs a power-on reset signal composed of the voltage of the power supply or the voltage of the ground;
A liquid discharge apparatus characterized by that. The liquid ejection device according to claim 1,
The liquid discharge apparatus according to claim 1, wherein an ON resistance of the first MOS transistor is smaller than an ON resistance of the second MOS transistor. The liquid ejection device according to claim 1 or 2,
A threshold value when starting a current flow between the source and drain of the first MOS transistor is smaller than a threshold value when starting a current flow between the source and drain of the second MOS transistor; A liquid ejecting apparatus. The liquid ejection device according to any one of claims 1 to 3,
When discharging liquid from the liquid discharge device,
The liquid ejection apparatus, wherein the first MOS transistor and the second MOS transistor operate simultaneously, or only the second MOS transistor operates. A liquid ejection apparatus according to any one of claims 1 to 4,
The liquid ejection apparatus, wherein both the first MOS transistor and the second MOS transistor are N-channel field effect transistors. A liquid ejection device according to any one of claims 1 to 5,
A length in a direction in which a current flows between a source and a drain in a channel of the first MOS transistor is longer than a length in a direction in which the current flows in a channel of the second MOS transistor. A liquid ejection device. The liquid ejection device according to claim 1,
The length in the direction intersecting the direction in which the current flows between the source and the drain in the channel of the first MOS transistor is in the direction intersecting the direction in which the current flows in the channel of the second MOS transistor. A liquid discharge apparatus characterized by being shorter than a length. A head control circuit that has a first MOS transistor, a second MOS transistor different from the first MOS transistor, and an inverter, and controls the operation of a head unit that ejects liquid,
The gate and source of the first MOS transistor are connected to a power source, the drain is connected to the input side of the inverter,
The gate of the second MOS transistor is connected to the power supply, the source is connected to the ground, the drain is connected to the input side of the inverter,
The inverter outputs a power-on reset signal composed of the voltage of the power supply or the voltage of the ground;
A head control circuit.

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