JP2013162437A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To further enhance responsiveness by reducing aliasing in a correlative double sampling circuit.SOLUTION: First and second variable capacitors C5 and C6 and first and second input control sections CG1 and CG2 are connected in series to differential input of a differential amplifier CDS of a correlative double sampling circuit 11, and differential input of an A/D converter 13 is connected through a variable gain amplifier 12 to differential output of CDS. A digital conversion output signal DOUT of the A/D converter 13 and a black level instruction signal CLP_LV are supplied to a digital comparator 14 and capacitance values of C5, C6 are controlled by output of the comparator 14. The input control sections CG1, CG2 include parallel connections of input resistors R2, R3 and input control switches SW14, SW15. The SW14, SW15 are controlled into conducted state in a first half of a feed-through period and a first half of a signal period and controlled into non-conducted state in a latter half of the feed-through period and a latter half of the signal period.

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a technique effective in reducing aliasing noise of a correlated double sampling circuit and further improving its responsiveness.

  Conventionally, an analog image processing circuit called an analog front end (AFE) such as a camera mounted on a mobile phone or a digital still camera does not use a single-ended amplifier circuit to remove common-mode noise such as disturbance. A dynamic amplifier circuit is used. An image sensor output signal of a solid-state imaging device such as a CCD (Charge Coupled Device) or a CMOS image sensor is sampled by a correlated double sampling circuit (Correlated Double Sampling), and then a variable gain amplifier (PGA: Programmable Gain Amplifier) To the input terminal.

  In recent years, with the increase in readout frequency accompanying the increase in the number of pixels in an image sensor, high-frequency noise is superimposed on the sensor output signal, the S / N ratio is degraded, and a high-quality image signal cannot be obtained. was there. Further, in the CCD, random noise such as dark current shot noise, reset noise in floating diffusion (FD), FD amplifier noise, optical shot noise, etc. is generated. The floating diffusion (FD) is constituted by an N-type region formed on the silicon substrate adjacent to the last stage of the horizontal CCD, and functions as an input terminal of the floating diffusion amplifier (FDA).

  In Patent Document 1 below, an input terminal of a correlated double sampling circuit (CDS) is connected to an output terminal of a CCD that is a solid-state imaging device in order to reduce the above-described reset noise of the CCD as a solid-state imaging device. Is described. Further, in Patent Document 1 below, a correlated double sampling circuit (CDS) is composed of first, second, and third sample-and-hold circuits and a subtracting circuit. It is described that the output signal of the CCD is supplied to the input terminal of the second sample hold circuit, and the output terminal of the second sample hold circuit is connected to the input terminal of the third sample hold circuit. The first input terminal and the second input terminal of the subtraction circuit are connected to the output terminal of the first sample hold circuit and the output terminal of the third sample hold circuit, respectively, and the first sample hold circuit and the third sample hold circuit are connected. A second pulse signal is supplied to the circuit, and a first pulse signal is supplied to the second sample and hold circuit. The first pulse signal is set to a high level during a feed-through period after the reset period, and the second pulse signal is set to a high level during a signal period after the feed-through period. Accordingly, the pixel signal of the signal period is supplied to the first input terminal of the subtraction circuit via the first sample hold circuit, and the second sample hold circuit and the third sample hold are supplied to the second input terminal of the subtraction circuit. The voltage of the feed-through period is supplied via the circuit, and the difference voltage output between the voltage of the feed-through period and the voltage of the pixel signal in the signal period is generated from the output terminal of the subtraction circuit. It is said that noise components are removed at the time.

  Further, in Patent Document 1 below, in order to reduce aliasing noise generated by sampling by a correlated double sampling circuit (CDS), an output terminal of a CCD that is a solid-state imaging device and an input terminal of a correlated double sampling circuit (CDS) It is described that a low-pass filter is connected in between, and the influence of aliasing due to sampling of high-frequency noise is reduced.

  In Patent Document 2 below, in order to reduce aliasing noise due to high-frequency noise sampling by a correlated double sampling circuit (CDS) for reducing noise in the output of a CCD, first and second low-pass filters and first The use of 1 and a second gate circuit is described. The output signal of the CCD is supplied to the input terminals of both the first and second gate circuits, and the first pulse signal that is set to the high level during the feed-through period is supplied to the first gate circuit. The second pulse signal which is set to the high level at the timing of the pixel signal in the signal period is supplied to the gate circuit. The first gate circuit extracts the voltage of the feed-through period during the high level period of the first pulse signal, and the second gate circuit extracts the voltage of the pixel signal during the signal period during the high level period of the second pulse signal. To do. The extracted voltage in the feed-through period of the output of the first gate circuit is subtracted through the second low-pass filter, the second sample hold circuit and the third sample hold circuit of the correlated double sampling circuit (CDS). It is supplied to the second input terminal of the differential amplifier as a circuit. The extracted voltage of the pixel signal in the signal period of the output of the second gate circuit is obtained by the differential amplifier as a subtracting circuit through the first low-pass filter and the first sample hold circuit of the correlated double sampling circuit (CDS). Supplyed to the first input terminal. A third pulse signal that is set to a high level during the feed-through period is supplied to the second sample-and-hold circuit, and the first sample-and-hold circuit and the third sample-and-hold circuit are supplied with the timing of the pixel signal in the signal period. A fourth pulse signal that is set to a high level is supplied. In the differential amplifier as the subtracting circuit, the reset signal of the CCD and the 1 / f noise are canceled by subtracting the output signal of the first sample hold circuit and the output signal of the third sample hold circuit. It is supposed to output image signals.

JP-A-5-68210 JP-A-8-9262

  Prior to the present invention, the present inventors engaged in the development of a semiconductor integrated circuit incorporating an analog front end (AFE) such as a camera mounted on a mobile phone or a digital still camera.

  FIG. 6 is a diagram showing a configuration of a semiconductor integrated circuit incorporating an analog front end (AFE) studied by the present inventors prior to the present invention.

  The analog front end (AFE) built in the semiconductor integrated circuit IC shown in FIG. 6 includes a sample hold circuit (SH) 10, a correlated double sampling circuit (CDS) 11, a variable gain amplifier (PGA) 12, and an analog / digital circuit. A converter (ADC) 13, a digital comparator (CMP) 14, and a clamp controller 15 are included. In FIG. 6, the circuits and elements inside the broken line IC are integrated on the semiconductor chip of the semiconductor integrated circuit IC.

In FIG. 6, the image sensor output signal CDSIN from the CCD as the solid-state imaging device is supplied to the terminal T1. Image sensor output signal CDSIN terminal T1 is supplied through an input coupling capacitor _{C IN} to the terminal T2, the image sensor output signal CDSIN terminal T2 is the sample and hold circuit (SH) 10 and a correlated double sampling circuit (CDS) 11 and.

  The switch SW1 and the capacitor C1 are connected to the non-inverting input terminal + of the differential amplifier of the sample hold circuit (SH) 10, and the switch SW2 and the capacitor C2 are connected to the inverting input terminal − of the differential amplifier. One end of the switch SW1 is connected to the terminal T2, the other end of the switch SW1 is connected to one end of the capacitor C1 and the non-inverting input terminal + of the differential amplifier, and the other end of the capacitor C1 is connected to the ground voltage. One end of the switch SW2 is connected to a terminal T5 functioning as a feedback terminal FBC, the other end of the switch SW2 is connected to one end of the capacitor C2 and the inverting input terminal − of the differential amplifier, and the other end of the capacitor C2 is connected to the ground voltage. Connected. The output terminal of the differential amplifier of the sample hold circuit (SH) 10 is connected to a terminal T6 functioning as the sample hold terminal SHC and one end of the resistor R1, and the other end of the resistor R1 is one end of the external capacitor C4 via the terminal T7. The other end of the external capacitor C4 is connected to the ground voltage. An external capacitor C3 is connected between a terminal T5 functioning as a feedback terminal FBC and a terminal T6 functioning as a sample hold terminal SHC. Since the switches SW1 and SW2 are driven by the first pulse signal φ1 that is set to the high level in the feed-through period after the reset period, the black level in the feed-through period after the reset period is set in the sample hold circuit (SH) 10. The signal is sampled by the capacitor C1 of the non-inverting input terminal + of the differential amplifier and buffered at the output terminal of the differential amplifier of the sample hold circuit (SH) 10.

  Connected to the correlated double sampling circuit (CDS) 11 are switches SW3, SW4, SW5, SW6, SW7, SW8, SW9, SW10, SW9 and capacitors C5, C6, C7, C8. The image sensor output signal CDSIN of the terminal T2 is supplied to one end of the switch SW3, one end of the switch SW4 is connected to the output terminal of the differential amplifier of the sample hold circuit (SH) 10, and the other end of the switch SW3 is connected to the switch SW5. One end is connected to one end of the capacitor C5, and the other end of the switch SW4 is connected to the other end of the switch SW5 and one end of the capacitor C6. The switches SW3 and SW4 are driven by the second pulse signal φ2 that is set to the high level at the timing of the pixel signal in the signal period after the feed-through period, and the switch SW5 is an inverted second pulse that is an inverted signal of the second pulse signal φ2. Driven by the signal / φ2.

  The other end of the capacitor C5 is connected to the non-inverting input terminal + of the differential amplifier of the correlated double sampling circuit (CDS) 11, one end of the capacitor C7 and one end of the switch SW6, and the other end of the capacitor C6 is the correlated double sampling circuit. The inverting input terminal of the differential amplifier (CDS) 11 is connected to one end of the capacitor C8 and one end of the switch SW7, and the other end of the switch SW6 and the other end of the switch SW7 are connected to the ground voltage. The other end of the capacitor C7 is connected to one end of the switch SW8 and one end of the switch SW10. The other end of the switch SW8 is an inverting output terminal of the differential amplifier of the correlated double sampling circuit (CDS) 11 and a variable gain amplifier (PGA). The other end of the switch SW10 is connected to the ground voltage. The other end of the capacitor C8 is connected to one end of the switch SW9 and one end of the switch SW11, and the other end of the switch SW9 is a non-inverting output terminal + of the differential amplifier of the correlated double sampling circuit (CDS) 11 and a variable gain amplifier ( PGA) 12 is connected to the inverting input terminal −, and the other end of the switch SW11 is connected to the ground voltage. The switches SW6, SW7, SW10 and SW11 are driven by the second pulse signal φ2, and the switches SW8 and SW9 are driven by the inverted second pulse signal / φ2 which is an inverted signal of the second pulse signal φ2.

  The differential analog input terminal of the analog-to-digital converter (ADC) 13 is connected to the inverting output terminal − and the non-inverting output terminal + of the differential amplifier of the correlated double sampling circuit (CDS) 11 via the variable gain amplifier (PGA) 12. The digital conversion output signal DOUT is generated at the terminal T3. The first input terminal and the second input terminal of the digital comparator (CMP) 14 have a digital conversion output signal DOUT generated at the terminal T3 during the feed-through period and a digital indicating a clamp level corresponding to the black level of the pixel signal. A signal CLP_LV is supplied. The comparison output signal of the digital comparator (CMP) 14 is supplied to the input terminal of the clamp control unit 15, and the output signal of the clamp control unit 15 is supplied to the terminal T5 functioning as the feedback terminal FBC and one end of the switch SW2. As a result, the sample-and-hold circuit (SH) 10 and the correlation so that the digital conversion output signal DOUT generated at the terminal T3 during the feed-through period matches the black level digital signal CLP_LV (clamp level corresponding to the black level). The offset of the differential amplifier of the double sampling circuit (CDS) 11 can be compensated.

  The offset-compensated black level signal generated at the output terminal of the differential amplifier of the sample hold circuit (SH) 10 is a correlated double sampling circuit during the high level period of the second pulse signal φ2 via the switch SW4 and the capacitor C6. It is supplied to the inverting input terminal − of the differential amplifier of the circuit (CDS) 11. That is, this black level signal is sampled between both terminals of the capacitor C6 during the high level period of the second pulse signal φ2.

  The pixel signal in the signal period after the feed-through period of the image sensor output signal CDSIN at the terminal T2 is correlated with a double sampling circuit (CDS) in the high level period of the second pulse signal φ2 via the switch SW3 and the capacitor C5. 11 is supplied to the non-inverting input terminal + of the differential amplifier. That is, the pixel signal in the signal period is sampled between both terminals of the capacitor C5 during the high level period of the second pulse signal φ2.

  During the high level period of the inverted second pulse signal / φ2, the switches SW5, SW8, and SW9 are turned on. As a result, during this period, the pixel signal of the signal period sampled in the capacitor C5 is amplified by the first negative feedback amplification path including the capacitors C5 and C7 and the differential amplifier of the correlated double sampling circuit (CDS) 11. The black level signal sampled in the capacitor C6 is amplified by a second negative feedback amplification path including the capacitors C6 and C8 and the differential amplifier of the correlated double sampling circuit (CDS) 11. Therefore, the differential voltage output between the black level signal in the feed-through period and the voltage of the pixel signal in the signal period is output from the inverting output terminal − and the non-inverting output terminal + of the differential amplifier of the correlated double sampling circuit (CDS) 11. In this case, the noise component can be removed.

  FIG. 7 is a diagram showing waveforms for explaining the operation of the semiconductor integrated circuit incorporating the analog front end (AFE) studied by the present inventors prior to the present invention shown in FIG.

  In FIG. 7, the image sensor output signal CDSIN at the terminal T 2, the first pulse signal φ 1, the second pulse signal φ 2, the waveform of the inverted second pulse signal / φ 2, and the analog / digital converter (ADC) 13 are generated. A digital conversion output signal DOUT is shown.

  Periods T1, T5, and T9 in FIG. 7 are reset periods, and an N-type region called a floating diffusion (FD) of a CCD as a solid-state imaging device is reset to a reset voltage. Periods T2, T6, and T10 in FIG. 7 are feed-through periods after the reset period, and in this feed-through period, the image sensor output signal CDSIN corresponds to the black level of the pixel signal. Periods T3, T4, T7, T8, T11, and T12 in FIG. 7 are signal periods after the feed-through period. In this signal period, the image sensor output signal CDSIN corresponds to the pixel signal of the subject. Periods T1, T2, T5, T6, T9, and T10 in FIG. 7 are amplification periods by the correlated double sampling circuit (CDS) 11 and the variable gain amplifier (PGA) 12 after the signal period.

  The black level clamping operation is executed by the high-level first pulse signal φ1 in the feed-through periods T2, T6, and T10, and the high-level second pulse signal φ2 in the signal periods T3, T4, T7, T8, T11, and T12. Thus, the black level sampling operation and the pixel signal sampling operation in the signal period are executed. Generation operation of a differential voltage output between the black level signal in the feed-through period and the voltage of the pixel signal in the signal period by the high-level inverted second pulse signal / φ2 in the amplification periods T1, T2, T5, T6, T9, and T10 An amplification operation is performed. In response to the differential amplification signals generated in the amplification periods T1, T2, T5, T6, T9, and T10, output data DATA (n−2), DATA (n−1), which are digital conversion output signals DOUT, DATA (n) is generated.

  However, in the semiconductor integrated circuit incorporating the analog front end (AFE) studied by the inventors prior to the present invention shown in FIG. 6, external capacitors C3 and C4 having large capacitance values need to be connected. In addition, a large loop delay occurs in the clamping operation by the external capacitors C3 and C4 having larger capacitance values. Therefore, in order to prevent undesired oscillation in the clamp operation, it is necessary to set the loop gain to a relatively small value, and it is difficult to shorten the pull-in time of the clamp operation.

  FIG. 8 is a diagram showing a configuration of a semiconductor integrated circuit incorporating an analog front end (AFE), which was studied by the present inventors prior to the present invention in order to solve the problem of the semiconductor integrated circuit shown in FIG. is there.

  In the semiconductor integrated circuit IC shown in FIG. 8, compared to the semiconductor integrated circuit IC shown in FIG. 6, the sample hold circuit (SH) 10 and external capacitors C3 and C4 having large capacitance values and switches SW1, SW2, SW3, SW4 , SW5 and capacitors C1 and C2 are omitted. Instead, compared with the semiconductor integrated circuit IC shown in FIG. 6, switches SW12 and SW13 are added to the semiconductor integrated circuit IC shown in FIG. 6, and the capacitors C5 and C6 are capacitive digital-analog converters (capacitor DAC). ) As a variable capacitor. That is, the capacitance values of the variable capacitors C5 and C6 are set by the digital output signal of the clamp control unit 15.

  One end of the variable capacitor C5 is supplied with the image sensor output signal CDSIN of the terminal T2, and one end of the variable capacitor C6 is connected to the ground voltage via the terminal T8. The other end of the variable capacitor C5 is connected to the first terminal of the switch SW12. The second terminal and the third terminal of the switch SW12 are connected to the non-inverting input terminal + of the differential amplifier of the correlated double sampling circuit (CDS) 11 and the ground. Connected to the voltage respectively. The other end of the variable capacitor C6 is connected to the first terminal of the switch SW13. The second terminal and the third terminal of the switch SW13 are connected to the inverting input terminal − of the differential amplifier of the correlated double sampling circuit (CDS) 11 and the ground voltage. And connected respectively.

  In response to the high-level inverted second pulse signal / φ2, the path between the first terminal and the second terminal of the switch SW12 is connected, and the path between the first terminal and the third terminal of the switch SW12 is In a non-connected state, the path between the first terminal and the second terminal of the switch SW13 is set in a connected state, and the path between the first terminal and the third terminal of the switch SW13 is set in a non-connected state. Further, in response to the high-level first pulse signal φ1, the path between the first terminal and the second terminal of the switch SW12 is disconnected, and the path between the first terminal and the third terminal of the switch SW12 is disconnected. The connected state is set, the path between the first terminal and the second terminal of the switch SW13 is disconnected, and the path between the first terminal and the third terminal of the switch SW13 is connected.

  The second terminal of the switch SW12 is connected to the non-inverting input terminal + of the differential amplifier of the correlated double sampling circuit (CDS) 11, one end of the capacitor C7 and one end of the switch SW6, and the second terminal of the switch SW13 is correlated double. The inverting input terminal of the differential amplifier of the sampling circuit (CDS) 11 is connected to one end of the capacitor C8 and one end of the switch SW7, and the other end of the switch SW6 and the other end of the switch SW7 are connected to the ground voltage. The other end of the capacitor C7 is connected to one end of the switch SW8 and one end of the switch SW10. The other end of the switch SW8 is an inverting output terminal of the differential amplifier of the correlated double sampling circuit (CDS) 11 and a variable gain amplifier (PGA). The other end of the switch SW10 is connected to the ground voltage. The other end of the capacitor C8 is connected to one end of the switch SW9 and one end of the switch SW11, and the other end of the switch SW9 is a non-inverting output terminal + of the differential amplifier of the correlated double sampling circuit (CDS) 11 and a variable gain amplifier ( The other end of the switch SW11 is connected to the ground voltage. The switches SW6, SW7, SW10 and SW11 are driven by the second pulse signal φ2, and the switches SW8 and SW9 are driven by the inverted second pulse signal / φ2 which is an inverted signal of the second pulse signal φ2.

  Also in the semiconductor integrated circuit IC shown in FIG. 8, the differential analog input terminal of the analog-to-digital converter (ADC) 13 is connected to the differential amplifier of the correlated double sampling circuit (CDS) 11 via the variable gain amplifier (PGA) 12. Connected to the inverting output terminal − and the non-inverting output terminal +, the digital conversion output signal DOUT is generated at the terminal T3. The first input terminal and the second input terminal of the digital comparator (CMP) 14 have a digital conversion output signal DOUT generated at the terminal T3 during the feed-through period and a digital indicating a clamp level corresponding to the black level of the pixel signal. A signal CLP_LV is supplied. Since the comparison output signal of the digital comparator (CMP) 14 is supplied to the capacitance value control terminals of the variable capacitors C5 and C6 via the clamp controller 15, the capacitance values of the variable capacitors C5 and C6 are It is set by the digital output signal. As a result, the digital conversion output signal DOUT generated at the terminal T3 in the feed-through period in accordance with the capacitance values of the variable capacitors C5 and C6 matches the black level digital signal CLP_LV (clamp level corresponding to the black level). In addition, the offset of the differential amplifier of the sample hold circuit (SH) 10 or the correlated double sampling circuit (CDS) 11 can be compensated.

  That is, in this offset compensation operation, the path between the first terminal and the third terminal of the switch SW12 is connected by the first pulse signal φ1 that is set to the high level in the first half of the feed-through period after the reset period. Therefore, the black level during the feed-through period is sampled between both terminals of the variable capacitor C5. At this time, the path between the first terminal and the third terminal of the switch SW13 is brought into a connected state by the first pulse signal φ1 which is set to the high level, so that the ground voltage of the terminal T8 is between the two terminals of the variable capacitor C6. Is sampled.

  Furthermore, in the offset compensation operation, the path between the first terminal and the second terminal of the switch SW12 is connected by the inverted second pulse signal / φ2 that is set to the high level in the second half of the feed-through period. A black level voltage sampled between both terminals of the variable capacitor C5 is amplified by a first negative feedback amplification path including capacitors C5 and C7 and a differential amplifier of the correlated double sampling circuit (CDS) 11. At this time, since the path between the first terminal and the second terminal of the switch SW13 is connected by the inverted second pulse signal / φ2 which is set to the high level, sampling is performed between both terminals of the variable capacitor C6. The ground voltage is amplified by the second negative feedback amplification path including the capacitors C6 and C8 and the differential amplifier of the correlated double sampling circuit (CDS) 11.

  The black level amplified signal at the differential output terminal of the differential amplifier of the correlated double sampling circuit (CDS) 11 during this offset compensation operation period is passed through the variable gain amplifier (PGA) 12 to the analog / digital converter (ADC). ) 13 differential analog input terminals. As a result, a digital conversion output signal DOUT corresponding to the black level amplification signal is generated at the output terminal T3 of the analog / digital converter (ADC) 13.

  A digital signal indicating the digital conversion output signal DOUT generated at the terminal T3 during the feed-through period and the clamp level corresponding to the black level of the pixel signal at the first input terminal and the second input terminal of the digital comparator (CMP) 14 CLP_LV is supplied. Since the comparison output signal of the digital comparator (CMP) 14 is supplied to the capacitance value control terminals of the variable capacitors C5 and C6 via the clamp controller 15, the capacitance values of the variable capacitors C5 and C6 are Set by digital output signal. As a result, the digital conversion output signal DOUT generated at the terminal T3 in the feed-through period in accordance with the capacitance values of the variable capacitors C5 and C6 matches the black level digital signal CLP_LV (clamp level corresponding to the black level). In addition, the offset of the differential amplifier of the sample hold circuit (SH) 10 or the correlated double sampling circuit (CDS) 11 can be compensated.

  The normal operation after the above-described offset compensation operation is completed as follows.

  That is, the path between the first terminal and the third terminal of the switch SW12 is connected by the first pulse signal φ1 that is set to the high level in the feed-through period after the reset period. The level is sampled between both terminals of the variable capacitor C5. At this time, since the path between the first terminal and the third terminal of the switch SW13 is brought into a connected state by the first pulse signal φ1 being set to the high level, the ground voltage of the terminal T8 is between the two terminals of the variable capacitor C6. Is sampled.

  Since the path between the first terminal and the second terminal of the switch SW12 is connected by the inverted second pulse signal / φ2 that is set to the high level in the signal period after the feed-through period, the pixel signal of the signal period The difference voltage of the black level sampled between both terminals of the voltage and the variable capacitor C5 is amplified by a first negative feedback amplification path including the capacitors C5 and C7 and the differential amplifier of the correlated double sampling circuit (CDS) 11. . Further, since the path between the first terminal and the second terminal of the switch SW13 is connected by the inverted second pulse signal / φ2 which is set to the high level in the signal period after the feed through period, the grounding of the terminal T8 is performed. A second negative feedback amplification path in which the difference voltage of approximately zero volts between the voltage and the ground voltage sampled between both terminals of the variable capacitor C6 is formed by the capacitors C6 and C8 and the differential amplifier of the correlated double sampling circuit (CDS) 11. It is amplified by. Therefore, the differential voltage output between the black level signal in the feed-through period and the voltage of the pixel signal in the signal period is output from the inverting output terminal − and the non-inverting output terminal + of the differential amplifier of the correlated double sampling circuit (CDS) 11. In this case, the noise component can be removed.

  FIG. 9 is a diagram showing waveforms for explaining the operation of the semiconductor integrated circuit including the analog front end (AFE) studied by the present inventors prior to the present invention shown in FIG.

  In FIG. 9, the waveform of the image sensor output signal CDSIN, the first pulse signal φ1, the second pulse signal φ2, the inverted second pulse signal / φ2 at the terminal T2, and the analog / digital converter (ADC) 13 are generated. A digital conversion output signal DOUT is shown.

  Periods T1, T5, and T9 in FIG. 9 are reset periods, and an N-type region called floating diffusion (FD) of a CCD as a solid-state imaging device is reset to a reset voltage. Periods T2, T6, and T10 in FIG. 9 are feed-through periods after the reset period. In this feed-through period, the image sensor output signal CDSIN corresponds to the black level of the pixel signal. The periods T3, T4, T7, T8, T11, and T12 in FIG. 9 are signal periods after the feed-through period. In this signal period, the image sensor output signal CDSIN corresponds to the pixel signal of the subject. The periods T3, T4, T7, T8, T11, and T12 in FIG. 9 are amplification periods by the correlated double sampling circuit (CDS) 11 and the variable gain amplifier (PGA) 12 in the signal period.

  Sampling to the variable capacitor C5 of the black level during the feed-through period, sampling to the ground voltage of the terminal T8 and the variable capacitor C6 by the first pulse signal φ1 which is set to the high level in the feed-through periods T2, T6, T10 Is executed. Next, in the amplification periods T3, T4, T7, T8, T11, and T12, a high-level inverted second pulse signal / φ2 is used to amplify the difference between the voltage of the pixel signal in the signal period and the sampling black level of the variable capacitor C5. And an operation of amplifying a difference voltage of approximately zero volts between the ground voltage of the terminal T8 and the sampling ground voltage of the variable capacitor C6. Therefore, in response to the differential amplification signals generated in the amplification periods T3, T4, T7, T8, T11, and T12, the output data DATA (n−1), DATA (n), which are the digital conversion output signals DOUT, DATA (n + 1) is generated.

  However, in the semiconductor integrated circuit incorporating the analog front end (AFE) studied by the present inventors prior to the present invention shown in FIG. 6 and FIG. As described, it has been clarified by the examination by the inventors prior to the present invention that there is a problem that aliasing noise is generated due to sampling of high frequency noise by the correlated double sampling circuit (CDS) 11.

  10 prior to the present invention to solve the above-described problem of aliasing noise in a semiconductor integrated circuit incorporating an analog front end (AFE), which was studied by the present inventors prior to the present invention shown in FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit incorporating an analog front end (AFE) studied by the present inventors.

  Compared with the semiconductor integrated circuit IC shown in FIG. 6, the semiconductor integrated circuit IC shown in FIG. 10 has a first low-pass filter LPF1 including a resistor R2 and a capacitor C9, a second low-pass filter including a resistor R3 and a capacitor C10. LPF2 is added. Note that the first low-pass filter LPF1 and the second low-pass filter LPF2 are similar to the low-pass filter for reducing aliasing noise described in Patent Document 1 and Patent Document 2.

  That is, the first low-pass filter LPF1 is connected in series with the switch SW3 between the terminal T2 and the non-inverting input terminal + of the differential amplifier of the correlated double sampling circuit (CDS) 11, and the second low-pass filter LPF2 The switch SW1 is connected in series between the terminal T2 and the non-inverting input terminal + of the differential amplifier of the sample hold circuit (SH) 10.

  However, the semiconductor integrated circuit incorporating the analog front end (AFE) studied by the present inventors prior to the present invention shown in FIG. 10 can reduce the aliasing noise, but is supplied to the terminal T1. It has been clarified by examination by the present inventors that there is a problem that the response of the correlated double sampling circuit (CDS) 11 to the change in the signal level of the image sensor output signal CDSIN from the CCD is not good. Further, the semiconductor integrated circuit examined by the inventors prior to the present invention shown in FIG. 10 is large, similar to the semiconductor integrated circuit examined by the inventors prior to the present invention shown in FIG. There is a problem that it is necessary to connect the external capacitors C3 and C4 of the capacitance value, and further, it is difficult to shorten the pull-in time of the clamp operation.

  FIG. 11 shows an embodiment of the present invention prior to the present invention in order to solve the above-described problem in a semiconductor integrated circuit incorporating an analog front end (AFE) studied by the present inventors prior to the present invention shown in FIG. 1 is a diagram illustrating a configuration of a semiconductor integrated circuit incorporating an analog front end (AFE) that has been studied by a person or the like. FIG.

  Compared with the semiconductor integrated circuit IC shown in FIG. 8, the semiconductor integrated circuit IC shown in FIG. 11 includes a first low-pass filter LPF1 including a resistor R2 and a capacitor C9, a second low-pass filter including a resistor R3 and a capacitor C10. LPF2 is added. Note that the first low-pass filter LPF1 and the second low-pass filter LPF2 are similar to the low-pass filter for reducing aliasing noise described in Patent Document 1 and Patent Document 2.

  That is, the first low-pass filter LPF1 is connected in series with the variable capacitor C5 between the terminal T2 and the non-inverting input terminal + of the differential amplifier of the correlated double sampling circuit (CDS) 11, and the second low-pass filter The LPF 2 is connected in series with the variable capacitor C6 between the terminal T8 and the inverting input terminal − of the differential amplifier of the correlated double sampling circuit (CDS) 11.

  Therefore, the semiconductor integrated circuit incorporating the analog front end (AFE) studied by the present inventors prior to the present invention shown in FIG. 11 can reduce aliasing noise and shorten the clamping operation pull-in time. Also, it is unnecessary to connect the external capacitors C3 and C4 having a large capacitance value. However, the semiconductor integrated circuit incorporating the analog front end (AFE) studied by the present inventors prior to the present invention shown in FIG. 11 is supplied to the terminal T1 in the same manner as the semiconductor integrated circuit IC shown in FIG. It has been clarified by examinations by the present inventors that there is a problem that the response of the correlated double sampling circuit (CDS) 11 to the change in the signal level of the image sensor output signal CDSIN from the CCD is not good. .

  The present invention has been made as a result of the examination by the present inventors prior to the present invention as described above.

  Therefore, an object of the present invention is to reduce the aliasing noise of the correlated double sampling circuit and further improve the response.

  Another object of the present invention is to reduce the number of connected external capacitors having a large capacitance value.

  It is still another object of the present invention to shorten the pull-in time for the black level clamping operation.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  A typical one of the inventions disclosed in the present application will be briefly described as follows.

  That is, a semiconductor integrated circuit (IC) according to a representative embodiment of the present invention includes a first variable capacitor (C5), a second variable capacitor (C6), a correlated double sampling circuit (11), an analog A digital converter (13) and a digital comparator (14) are provided.

  An image sensor output signal (CDSIN) of a solid-state imaging device is supplied to one end of the first variable capacitor (C5), and a ground voltage is supplied to one end of the second variable capacitor (C6).

  The correlated double sampling circuit (11) includes a differential amplifier (CDS), a first input switch (SW12), a second input switch (SW13), a first feedback capacitor (C7), and a second feedback capacitor (C8). A first feedback switch (SW8) and a second feedback switch (SW9) are included.

  The other end of the first variable capacitor (C5) is connected to a first terminal of the first input switch (SW12), and a second terminal of the first input switch (SW12) is not connected to the differential amplifier (CDS). An inverting input terminal (+) is connected, and a third terminal of the first input switch (SW12) is connected to the ground voltage.

  The other end of the second variable capacitor (C6) is connected to a first terminal of the second input switch (SW13), and a second terminal of the second input switch (SW13) is an inversion of the differential amplifier (CDS). The third terminal of the second input switch (SW13) is connected to the ground voltage.

  The first feedback capacitor (C7) and the first feedback switch (SW8) are connected in series between the non-inverting input terminal (+) and the inverting output terminal (−) of the differential amplifier (CDS), The second feedback capacitor (C8) and the second feedback switch (SW9) are connected in series between the inverting input terminal (−) and the non-inverting output terminal (+) of the differential amplifier (CDS). .

  The path between the first terminal and the third terminal of the first input switch (SW12) and the path between the first terminal and the third terminal of the second input switch (SW13) are: In response to the first level of the pulse signal (φ1), the conduction state is controlled in the feed-through period after the reset period of the solid-state imaging device.

  The path between the first terminal and the third terminal of the first input switch (SW12) and the path between the first terminal and the third terminal of the second input switch (SW13) are: In response to a second level different from the first level of the first pulse signal (φ1), the non-conductive state is controlled.

  The first feedback switch (SW8) and the second feedback switch (SW9) are responsive to the first level of the inverted second pulse signal (/ φ2) that is an inverted signal of the second pulse signal (φ2). The solid-state imaging device is controlled to be in a conductive state in a signal period after the feed-through period.

  The first feedback switch (SW8) and the second feedback switch (SW9) are controlled to be non-conductive in response to a second level different from the first level of the inverted second pulse signal (/ φ2). The

  The path between the first terminal and the second terminal of the first input switch (SW12) and the path between the first terminal and the second terminal of the second input switch (SW13) are the inversions. The conduction state is controlled in response to the first level of the second pulse signal (/ φ2).

  The path between the first terminal and the second terminal of the first input switch (SW12) and the path between the first terminal and the second terminal of the second input switch (SW13) are: The non-conductive state is controlled in response to the second level different from the first level of the inverted second pulse signal (/ φ2).

  The differential input terminals of the analog / digital converter (13) are the inverting output terminal (−) and the non-inverting output terminal (+) of the differential amplifier (CDS) of the correlated double sampling circuit (11). In response to the differential amplification output signal between the two, a digital conversion output signal (DOUT) is generated from the output terminal (T3) of the analog-to-digital converter (13).

  The first input terminal and the second input terminal of the digital comparator (14) indicate clamp levels corresponding to the black levels of the digital conversion output signal (DOUT) and the image sensor output signal (CDSIN), respectively. A digital instruction signal (CLP_LV) can be supplied.

  In the digital comparator (14), the digital conversion output signal (DOUT) generated from the output terminal (T3) of the analog-digital converter (13) in the feed-through period of the solid-state imaging device is the digital comparator (14). The capacitance values of the first variable capacitor (C5) and the second variable capacitor (C6) are controlled so as to coincide with the digital instruction signal (CLP_LV).

  The semiconductor integrated circuit (IC) includes a first input control unit (GC1) including a first input resistor (R2) and a first input control switch (SW14) connected in parallel, and a second input resistor connected in parallel. (R3) and a second input control unit (GC2) including a second input control switch (SW15).

  The image sensor output signal (CDSIN) of the solid-state imaging device can be supplied to one end of the first variable capacitor (C5) via the first input controller (GC1), and the second variable capacitor (CSIN) can be supplied. The ground voltage can be supplied to the one end of C6) via the second input controller (GC2).

  The first input control switch (SW14) of the first input control unit (GC1) and the second input control switch (SW15) of the second input control unit (GC2) are the switches of the switch control signal (φSW_EN). It is controlled to a conductive state by the first level.

  The first input control switch (SW14) of the first input control unit (GC1) and the second input control switch (SW15) of the second input control unit (GC2) are connected to the switch control signal (φSW_EN). The non-conductive state is controlled in response to the second level different from the first level.

  In the first half of the feed-through period in which the first pulse signal (φ1) is at the first level and in the first half of the signal period in which the inverted second pulse signal (/ φ2) is at the first level, the switch The control signal (φSW_EN) is set to the first level, so that the first input control switch (SW14) and the second input control switch (SW15) are controlled to the conductive state.

  In the second half of the feed-through period in which the first pulse signal (φ1) is the first level and in the second half of the signal period in which the inverted second pulse signal (/ φ2) is the first level, the switch When the control signal (φSW_EN) is set to the second level, the first input control switch (SW14) and the second input control switch (SW15) are controlled to the non-conduction state. (See FIGS. 1 and 4).

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to the present invention, the aliasing noise of the correlated double sampling circuit can be reduced, and the response can be further improved.

FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit incorporating an analog front end (AFE) according to Embodiment 1 of the present invention. FIG. 2 is a diagram showing a configuration of variable capacitors C5 and C6 functioning as a capacitive digital-to-analog converter (capacitor DAC) included in the semiconductor integrated circuit IC according to the first embodiment of the present invention shown in FIG. is there. FIG. 3 is a diagram showing the configuration of each of the switches SW6 to SW11, SW14, and SW14 included in the semiconductor integrated circuit IC according to the first embodiment of the present invention shown in FIG. FIG. 4 is a diagram showing waveforms for explaining the operation of the semiconductor integrated circuit IC incorporating the analog front end (AFE) according to the first embodiment of the present invention shown in FIG. FIG. 5 shows a pipelined A / D converter suitable as an analog / digital converter (ADC) 13 of a semiconductor integrated circuit IC incorporating an analog front end (AFE) according to the first embodiment of the present invention shown in FIG. FIG. FIG. 6 is a diagram showing a configuration of a semiconductor integrated circuit incorporating an analog front end (AFE) studied by the present inventors prior to the present invention. FIG. 7 is a diagram showing waveforms for explaining the operation of the semiconductor integrated circuit incorporating the analog front end (AFE) studied by the present inventors prior to the present invention shown in FIG. FIG. 8 is a diagram showing a configuration of a semiconductor integrated circuit incorporating an analog front end (AFE), which was studied by the present inventors prior to the present invention in order to solve the problem of the semiconductor integrated circuit shown in FIG. is there. FIG. 9 is a diagram showing waveforms for explaining the operation of the semiconductor integrated circuit including the analog front end (AFE) studied by the present inventors prior to the present invention shown in FIG. 10 prior to the present invention to solve the above-described problem of aliasing noise in a semiconductor integrated circuit incorporating an analog front end (AFE), which was studied by the present inventors prior to the present invention shown in FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit incorporating an analog front end (AFE) studied by the present inventors. FIG. 11 shows an embodiment of the present invention prior to the present invention in order to solve the above-described problem in a semiconductor integrated circuit incorporating an analog front end (AFE) studied by the present inventors prior to the present invention shown in FIG. 1 is a diagram illustrating a configuration of a semiconductor integrated circuit incorporating an analog front end (AFE) that has been studied by a person or the like. FIG.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to with parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A semiconductor integrated circuit (IC) according to a typical embodiment of the present invention includes a first variable capacitor (C5), a second variable capacitor (C6), a correlated double sampling circuit (11), an analog A digital converter (13) and a digital comparator (14) are provided.

  An image sensor output signal (CDSIN) of a solid-state imaging device can be supplied to one end of the first variable capacitor (C5), and a ground voltage can be supplied to one end of the second variable capacitor (C6). .

  The correlated double sampling circuit (11) includes a differential amplifier (CDS), a first input switch (SW12), a second input switch (SW13), a first feedback capacitor (C7), and a second feedback capacitor (C8). A first feedback switch (SW8) and a second feedback switch (SW9) are included.

  The other end of the first variable capacitor (C5) is connected to a first terminal of the first input switch (SW12), and a second terminal of the first input switch (SW12) is not connected to the differential amplifier (CDS). An inverting input terminal (+) is connected, and a third terminal of the first input switch (SW12) is connected to the ground voltage.

  The other end of the second variable capacitor (C6) is connected to a first terminal of the second input switch (SW13), and a second terminal of the second input switch (SW13) is an inversion of the differential amplifier (CDS). The third terminal of the second input switch (SW13) is connected to the ground voltage.

  The first feedback capacitor (C7) and the first feedback switch (SW8) are connected in series between the non-inverting input terminal (+) and the inverting output terminal (−) of the differential amplifier (CDS), The second feedback capacitor (C8) and the second feedback switch (SW9) are connected in series between the inverting input terminal (−) and the non-inverting output terminal (+) of the differential amplifier (CDS). .

  The path between the first terminal and the third terminal of the first input switch (SW12) and the path between the first terminal and the third terminal of the second input switch (SW13) are: In response to the first level of the pulse signal (φ1), the conduction state is controlled in the feed-through period after the reset period of the solid-state imaging device.

  The path between the first terminal and the third terminal of the first input switch (SW12) and the path between the first terminal and the third terminal of the second input switch (SW13) are: In response to a second level different from the first level of the first pulse signal (φ1), the non-conductive state is controlled.

  The first feedback switch (SW8) and the second feedback switch (SW9) are responsive to the first level of the inverted second pulse signal (/ φ2) that is an inverted signal of the second pulse signal (φ2). The solid-state imaging device is controlled to be in a conductive state in a signal period after the feed-through period.

  The first feedback switch (SW8) and the second feedback switch (SW9) are controlled to be non-conductive in response to the second level different from the first level of the inverted second pulse signal (/ φ2). Is done.

  The path between the first terminal and the second terminal of the first input switch (SW12) and the path between the first terminal and the second terminal of the second input switch (SW13) are the inversions. The conduction state is controlled in response to the first level of the second pulse signal (/ φ2).

  The path between the first terminal and the second terminal of the first input switch (SW12) and the path between the first terminal and the second terminal of the second input switch (SW13) are: The non-conductive state is controlled in response to the second level different from the first level of the inverted second pulse signal (/ φ2).

  The differential input terminals of the analog / digital converter (13) are the inverting output terminal (−) and the non-inverting output terminal (+) of the differential amplifier (CDS) of the correlated double sampling circuit (11). In response to the differential amplification output signal between the two, a digital conversion output signal (DOUT) is generated from the output terminal (T3) of the analog-to-digital converter (13).

  The first input terminal and the second input terminal of the digital comparator (14) indicate clamp levels corresponding to the black levels of the digital conversion output signal (DOUT) and the image sensor output signal (CDSIN), respectively. A digital instruction signal (CLP_LV) can be supplied.

  In the digital comparator (14), the digital conversion output signal (DOUT) generated from the output terminal (T3) of the analog-digital converter (13) in the feed-through period of the solid-state imaging device is the digital comparator (14). The capacitance values of the first variable capacitor (C5) and the second variable capacitor (C6) are controlled so as to coincide with the digital instruction signal (CLP_LV).

  The semiconductor integrated circuit (IC) includes a first input control unit (GC1) including a first input resistor (R2) and a first input control switch (SW14) connected in parallel, and a second input resistor connected in parallel. (R3) and a second input control unit (GC2) including a second input control switch (SW15).

  The image sensor output signal (CDSIN) of the solid-state imaging device can be supplied to the one end of the first variable capacitor (C5) via the first input controller (GC1), and the second variable capacitor The ground voltage can be supplied to the one end of (C6) via the second input control unit (GC2).

  The first input control switch (SW14) of the first input control unit (GC1) and the second input control switch (SW15) of the second input control unit (GC2) are the switches of the switch control signal (φSW_EN). It is controlled to a conductive state by the first level.

  The first input control switch (SW14) of the first input control unit (GC1) and the second input control switch (SW15) of the second input control unit (GC2) are connected to the switch control signal (φSW_EN). The non-conductive state is controlled in response to the second level different from the first level.

  In the first half of the feed-through period in which the first pulse signal (φ1) is at the first level and in the first half of the signal period in which the inverted second pulse signal (/ φ2) is at the first level, the switch The control signal (φSW_EN) is set to the first level, so that the first input control switch (SW14) and the second input control switch (SW15) are controlled to the conductive state.

  In the second half of the feed-through period in which the first pulse signal (φ1) is the first level and in the second half of the signal period in which the inverted second pulse signal (/ φ2) is the first level, the switch When the control signal (φSW_EN) is set to the second level, the first input control switch (SW14) and the second input control switch (SW15) are controlled to the non-conduction state. (See FIGS. 1 and 4).

  According to the embodiment, the aliasing noise of the correlated double sampling circuit can be reduced, and the response can be further improved.

  In a preferred embodiment, an ON resistance of the first input control switch (SW14) controlled by the first level of the switch control signal (φSW_EN) and the second input control switch (SW15). The on-resistance is characterized by being set to a resistance value lower than the resistance value of the first input resistance (R2) and the resistance value of the second input resistance (R3) (see FIG. 1). ).

  In another preferred embodiment, the semiconductor integrated circuit (IC) further includes a variable gain amplifier (12).

  The differential input terminal of the analog / digital converter (13) is connected to the inverting output terminal (CDS) of the differential amplifier (CDS) of the correlated double sampling circuit (11) via the variable gain amplifier (12). −) And the non-inverting output terminal (+) (see FIG. 1).

  In still another preferred embodiment, the semiconductor integrated circuit (IC) further includes a clamp control unit (15).

  The comparison output signal of the digital comparator (14) is supplied to the capacitance value control terminals of the first variable capacitor (C5) and the second variable capacitor (C6) via the clamp controller (15). (See FIG. 1).

  In a more preferred embodiment, the first variable capacitor (C5) and the second variable capacitor (C6) are a plurality of weighted capacitors (1 * C0, 2 * C0, 4 * C0... 32 * C0). ) In parallel (see FIG. 2).

  In another more preferred embodiment, the first variable capacitor (C5) and the second variable capacitor (C6) each include a plurality of control switches (SW50, SW51, SW52... SW55). .

  In the first variable capacitor (C5) and the second variable capacitor (C6), each of the plurality of capacitors (1 * C0, 2 * C0, 4 * C0... 32 * C0) and the plurality of control switches ( SW50, SW51, SW52... SW55) are connected in series (see FIG. 2).

  In still another more preferred embodiment, the plurality of control switches (SW50, SW51, SW52... SW55) are a plurality of switch control signals (D50, D51, D52...) Generated from the clamp control unit (15). D55) (see FIG. 2).

  In a specific embodiment, the first feedback switch (SW8), the second feedback switch (SW9), the first input control switch (SW14), and the second input control switch (SW15) are respectively CMOS. It is characterized by comprising an analog switch circuit (see FIG. 3).

  In another specific embodiment, the analog-digital converter (13) is a pipeline type A / D converter (see FIG. 5).

  In the most specific embodiment, the solid-state imaging device is a CCD (see FIG. 1).

2. Details of Embodiment Next, the embodiment will be described in more detail. In all the drawings for explaining the best mode for carrying out the invention, components having the same functions as those in the above-mentioned drawings are denoted by the same reference numerals, and repeated description thereof is omitted.

[Embodiment 1]
<< Configuration of Semiconductor Integrated Circuit with Built-in AFE >>
FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit incorporating an analog front end (AFE) according to Embodiment 1 of the present invention.

  The semiconductor integrated circuit IC according to the first embodiment of the present invention shown in FIG. 1 is different from the semiconductor integrated circuit IC examined by the inventors prior to the present invention shown in FIG. 11 in the following points. is there.

  That is, in the semiconductor integrated circuit IC according to the first embodiment of the present invention shown in FIG. 1, instead of the first low-pass filter LPF1 and the second low-pass filter LPF2 used in the semiconductor integrated circuit IC shown in FIG. A first gain control unit GC1 and a second gain control unit GC2 are used.

  Therefore, in the semiconductor integrated circuit IC according to the first embodiment of the present invention shown in FIG. 1, the first gain control unit GC1 is configured by a parallel connection of the resistor R2 and the switch SW14, and the second gain control unit GC2 is a resistor. It is configured by parallel connection of R3 and switch SW15. The switch SW14 of the first gain control unit GC1 and the switch SW15 of the second gain control unit GC2 are driven by the gain switch control signal φSW_EN, and the switches SW14 and SW15 are turned on by the high level gain switch control signal φSW_EN. Then, the switches SW14 and SW15 are turned off by the low level gain switch control signal φSW_EN.

  The on-resistances of the switches SW14 and SW15 that are turned on by the high-level gain switch control signal φSW_EN are set to resistance values sufficiently lower than the resistance values of the resistors R2 and R3.

  Other configurations of the semiconductor integrated circuit IC according to the first embodiment of the present invention shown in FIG. 1 are the same as those of the semiconductor integrated circuit IC studied by the inventors prior to the present invention shown in FIG.

Therefore, in the semiconductor integrated circuit IC incorporating the analog front end (AFE) according to the first embodiment of the present invention shown in FIG. 1, the image sensor output signal CDSIN from the CCD as the solid-state imaging device is supplied to the terminal T1. , image sensor output signal CDSIN terminal T1 is supplied to the second terminal T2 via the input coupling capacitor _{C iN.}

  The image sensor output signal CDSIN at the terminal T2 is supplied to the correlated double sampling circuit (CDS) via the first gain controller GC1, the variable capacitor C5 functioning as a capacitive digital-analog converter (capacitor DAC), and the switch SW12. ) 11 is supplied to the non-inverting input terminal + of the differential amplifier. The ground voltage at the terminal T8 is the difference between the correlated double sampling circuit (CDS) 11 through the second gain control unit GC2, the variable capacitor C2 functioning as a capacitive digital-analog converter (capacitor DAC), and the switch SW13. It is supplied to the non-inverting input terminal − of the dynamic amplifier.

  Accordingly, one end of the variable capacitor C5 is connected to the terminal T2 through the first gain control unit GC1, and one end of the variable capacitor C6 is connected to the terminal T8 through the second gain control unit GC2.

  The other end of the variable capacitor C5 is connected to the first terminal of the switch SW12. The second terminal and the third terminal of the switch SW12 are connected to the non-inverting input terminal + of the differential amplifier of the correlated double sampling circuit (CDS) 11 and the ground. Connected to the voltage respectively. The other end of the variable capacitor C6 is connected to the first terminal of the switch SW13. The second terminal and the third terminal of the switch SW13 are connected to the inverting input terminal − of the differential amplifier of the correlated double sampling circuit (CDS) 11 and the ground voltage. And connected respectively.

  In response to the high-level inverted second pulse signal / φ2, the path between the first terminal and the second terminal of the switch SW12 is connected, and the path between the first terminal and the third terminal of the switch SW12 is In a non-connected state, the path between the first terminal and the second terminal of the switch SW13 is set in a connected state, and the path between the first terminal and the third terminal of the switch SW13 is set in a non-connected state. Further, in response to the high-level first pulse signal φ1, the path between the first terminal and the second terminal of the switch SW12 is disconnected, and the path between the first terminal and the third terminal of the switch SW12. Is connected, the path between the first terminal and the second terminal of the switch SW13 is disconnected, and the path between the first terminal and the third terminal of the switch SW13 is connected.

  The second terminal of the switch SW12 is connected to the non-inverting input terminal + of the differential amplifier of the correlated double sampling circuit (CDS) 11, one end of the capacitor C7 and one end of the switch SW6, and the second terminal of the switch SW13 is correlated double. The inverting input terminal of the differential amplifier of the sampling circuit (CDS) 11 is connected to one end of the capacitor C8 and one end of the switch SW7, and the other end of the switch SW6 and the other end of the switch SW7 are connected to the ground voltage. The other end of the capacitor C7 is connected to one end of the switch SW8 and one end of the switch SW10. The other end of the switch SW8 is an inverting output terminal of the differential amplifier of the correlated double sampling circuit (CDS) 11 and a variable gain amplifier (PGA). The other end of the switch SW10 is connected to the ground voltage. The other end of the capacitor C8 is connected to one end of the switch SW9 and one end of the switch SW11, and the other end of the switch SW9 is a non-inverting output terminal + of the differential amplifier of the correlated double sampling circuit (CDS) 11 and a variable gain amplifier ( The other end of the switch SW11 is connected to the ground voltage. The switches SW6, SW7, SW10 and SW11 are driven by the second pulse signal φ2, and the switches SW8 and SW9 are driven by the inverted second pulse signal / φ2 which is an inverted signal of the second pulse signal φ2. Although not shown in FIG. 1, the variable gain amplifier (PGA) 12 can be variably set in amplification gain by a multi-bit digital control signal.

<Offset compensation operation>
Also in the semiconductor integrated circuit IC according to the first embodiment of the present invention shown in FIG. 1, the differential analog input terminal of the analog-to-digital converter (ADC) 13 is a correlated double sampling circuit (via a variable gain amplifier (PGA) 12). The CDS) 11 is connected to the inverting output terminal − and the non-inverting output terminal + of the differential amplifier, and the digital conversion output signal DOUT is generated at the terminal T3. The first input terminal and the second input terminal of the digital comparator (CMP) 14 have a digital conversion output signal DOUT generated at the terminal T3 during the feed-through period and a digital indicating a clamp level corresponding to the black level of the pixel signal. A signal CLP_LV is supplied. Since the comparison output signal of the digital comparator (CMP) 14 is supplied to the capacitance value control terminals of the variable capacitors C5 and C6 via the clamp controller 15, the capacitance values of the variable capacitors C5 and C6 are It is set by the digital output signal. As a result, the digital conversion output signal DOUT generated at the terminal T3 in the feed-through period in accordance with the capacitance values of the variable capacitors C5 and C6 matches the black level digital signal CLP_LV (clamp level corresponding to the black level). In addition, the offset of the differential amplifier of the correlated double sampling circuit (CDS) 11 can be compensated.

  That is, in this offset compensation operation, the path between the first terminal and the third terminal of the switch SW12 is connected by the first pulse signal φ1 that is set to the high level in the first half of the feed-through period after the reset period. Therefore, the black level during the feed-through period is sampled between both terminals of the variable capacitor C5. At this time, the path between the first terminal and the third terminal of the switch SW13 is brought into a connected state by the first pulse signal φ1 which is set to the high level, so that the ground voltage of the terminal T8 is between the two terminals of the variable capacitor C6. Is sampled.

  Furthermore, in the offset compensation operation, the path between the first terminal and the second terminal of the switch SW12 is connected by the inverted second pulse signal / φ2 that is set to the high level in the second half of the feed-through period. A black level voltage sampled between both terminals of the variable capacitor C5 is amplified by a first negative feedback amplification path including capacitors C5 and C7 and a differential amplifier of the correlated double sampling circuit (CDS) 11. At this time, since the path between the first terminal and the second terminal of the switch SW13 is connected by the inverted second pulse signal / φ2 which is set to the high level, sampling is performed between both terminals of the variable capacitor C6. The ground voltage is amplified by the second negative feedback amplification path including the capacitors C6 and C8 and the differential amplifier of the correlated double sampling circuit (CDS) 11.

  The black level amplified signal at the differential output terminal of the differential amplifier of the correlated double sampling circuit (CDS) 11 during this offset compensation operation period is passed through the variable gain amplifier (PGA) 12 to the analog / digital converter (ADC). ) 13 differential analog input terminals. As a result, a digital conversion output signal DOUT corresponding to the black level amplification signal is generated at the output terminal T3 of the analog / digital converter (ADC) 13.

  A digital signal indicating the digital conversion output signal DOUT generated at the terminal T3 during the feed-through period and the clamp level corresponding to the black level of the pixel signal at the first input terminal and the second input terminal of the digital comparator (CMP) 14 CLP_LV is supplied. Since the comparison output signal of the digital comparator (CMP) 14 is supplied to the capacitance value control terminals of the variable capacitors C5 and C6 via the clamp controller 15, the capacitance values of the variable capacitors C5 and C6 are Set by digital output signal. As a result, the digital conversion output signal DOUT generated at the terminal T3 in the feed-through period in accordance with the capacitance values of the variable capacitors C5 and C6 matches the black level digital signal CLP_LV (clamp level corresponding to the black level). In addition, the offset of the differential amplifier of the correlated double sampling circuit (CDS) 11 can be compensated.

<< Capacitance DAC >>
FIG. 2 is a diagram showing a configuration of variable capacitors C5 and C6 functioning as a capacitive digital-to-analog converter (capacitor DAC) included in the semiconductor integrated circuit IC according to the first embodiment of the present invention shown in FIG. is there.

  As shown in FIG. 2, each of the variable capacitors C5 and C6 is weighted with binary weights of 1 * C0, 2 * C0, 4 * C0, 8 * C0, 16 * C0, 32 * C0. Includes parallel connection of multiple capacities. A switch SW50 driven by a switch control signal D50 is connected in series to the capacitor 1 * C0, and a switch SW51 driven by a switch control signal D51 is connected in series to the capacitor 2 * C0. A switch SW52 driven by a switch control signal D52 is connected in series to the capacitor 4 * C0, and a switch SW53 driven by a switch control signal D53 is connected in series to the capacitor 8 * C0. A switch SW54 driven by a switch control signal D54 is connected in series to the capacitor 16 * C0, and a switch SW55 driven by a switch control signal D55 is connected in series to the capacitor 32 * C0.

  The switch control signals D50, D51, D52, D53, D54, and D55 supplied to the variable capacitors C5 and C6 are digital output signals generated from the clamp control unit 15.

<Switch configuration>
FIG. 3 is a diagram showing the configuration of each of the switches SW6 to SW11, SW14, and SW14 included in the semiconductor integrated circuit IC according to the first embodiment of the present invention shown in FIG.

  In the symbol of each switch SW at the upper left in FIG. 3, the terminals T1 and T2 are controlled to be in a conductive state and a non-conductive state, respectively, according to the high level and low level of the control signal supplied to the control terminal CT.

  The circuit diagram at the lower left of FIG. 3 shows the configuration of the CMOS analog switch circuit SW that realizes the function of the symbol of each switch SW at the upper left of FIG. That is, the CMOS analog switch circuit SW is composed of a P channel MOS transistor Qp, an N channel MOS transistor Qn, and a CMOS inverter Inv. The terminal T1 is connected to the source S of the P channel MOS transistor Qp and the drain D of the N channel MOS transistor Qn, and the terminal T2 is connected to the drain D of the P channel MOS transistor Qp and the source S of the N channel MOS transistor Qn. . The control terminal CT is connected to the gate G of the P-channel MOS transistor Qp and the input terminal of the CMOS inverter Inv, and the output terminal of the CMOS inverter Inv is connected to the gate G of the N-channel MOS transistor Qn.

<Normal operation>
The normal operation of the semiconductor integrated circuit IC according to the first embodiment of the present invention shown in FIG. 1 after completion of the offset compensation operation described above is performed as follows.

  That is, the path between the first terminal and the third terminal of the switch SW12 is connected by the first pulse signal φ1 that is set to the high level in the feed-through period after the reset period. The level is sampled between both terminals of the variable capacitor C5. At this time, since the path between the first terminal and the third terminal of the switch SW13 is brought into a connected state by the first pulse signal φ1 being set to the high level, the ground voltage of the terminal T8 is between the two terminals of the variable capacitor C6. Is sampled. Further, in the first half of the pulse period of the high-level first pulse signal φ1, the gain switch control signal φSW_EN supplied to the switch SW14 of the first gain control unit GC1 and the switch SW15 of the second gain control unit GC2 is at the high level. The switches SW14 and SW15 are controlled to be on. As a result, the sampling of the black level variable capacitor C5 and the sampling of the ground voltage to the variable capacitor C6 are speeded up, and the response of the analog front end (AFE) can be improved. Further, in the second half of the pulse period of the first pulse signal φ1 at the high level, the gain switch control signal φSW_EN supplied to the switch SW14 of the first gain control unit GC1 and the switch SW15 of the second gain control unit GC2 is low. The switches SW14 and SW15 are controlled to be turned off. Therefore, in this state, the gain for the input high frequency noise of the correlated double sampling circuit (CDS) 11 is low due to the large resistance values of the resistor R2 of the first gain control unit GC1 and the resistor R3 of the second gain control unit GC2. It will be controlled by the value. As a result, according to the semiconductor integrated circuit IC according to the first embodiment of the present invention shown in FIG. 1, the aliasing noise of the correlated double sampling circuit (CDS) 11 can be reduced.

  Since the path between the first terminal and the second terminal of the switch SW12 is connected by the inverted second pulse signal / φ2 that is set to the high level in the signal period after the feed-through period, the pixel signal of the signal period The difference voltage of the black level sampled between both terminals of the voltage and the variable capacitor C5 is amplified by a first negative feedback amplification path including the capacitors C5 and C7 and the differential amplifier of the correlated double sampling circuit (CDS) 11. . Further, since the path between the first terminal and the second terminal of the switch SW13 is connected by the inverted second pulse signal / φ2 which is set to the high level in the signal period after the feed through period, the grounding of the terminal T8 is performed. A difference voltage of approximately zero volts between the voltage and the ground voltage sampled between both terminals of the variable capacitor C6 is a second negative feedback amplification path composed of the differential amplifiers of the capacitors C6 and C8 and the correlated double sampling circuit (CDS) 11. Amplified. Further, in the first half of the pulse period of the inverted second pulse signal / φ2, the gain switch control signal φSW_EN supplied to the switch SW14 of the first gain control unit GC1 and the switch SW15 of the second gain control unit GC2 is set to the high level. Thus, the switches SW14 and SW15 are controlled to be on. As a result, the first negative feedback amplification path amplifies the difference voltage between the pixel signal voltage and the black level during the signal period, and the second negative feedback amplification of the difference voltage between the ground voltage of the terminal T8 and the sampling ground voltage of the variable capacitor C6. The amplification by the path is accelerated, and the response of the analog front end (AFE) can be improved. Further, in the second half of the pulse period of the inverted second pulse signal / φ2, the gain switch control signal φSW_EN supplied to the switch SW14 of the first gain control unit GC1 and the switch SW15 of the second gain control unit GC2 is set to the low level. Thus, the switches SW14 and SW15 are controlled to the off state. Therefore, in this state, the gain for the input high frequency noise of the correlated double sampling circuit (CDS) 11 is low due to the large resistance values of the resistor R2 of the first gain control unit GC1 and the resistor R3 of the second gain control unit GC2. It will be controlled by the value. As a result, according to the semiconductor integrated circuit IC according to the first embodiment of the present invention shown in FIG. 1, the aliasing noise of the correlated double sampling circuit (CDS) 11 can be reduced.

<< Operation Waveform of Semiconductor Integrated Circuit >>
FIG. 4 is a diagram showing waveforms for explaining the operation of the semiconductor integrated circuit IC incorporating the analog front end (AFE) according to the first embodiment of the present invention shown in FIG.

  FIG. 4 shows the waveform of the image sensor output signal CDSIN, the first pulse signal φ1, the second pulse signal φ2, the inverted second pulse signal / φ2, and the gain switch control signal φSW_EN at the terminal T2, and an analog / digital converter (ADC). ) 13 and a digital conversion output signal DOUT generated from 13.

  Periods T1, T5, and T9 in FIG. 4 are reset periods, and an N-type region called a floating diffusion (FD) of a CCD as a solid-state imaging device is reset to a reset voltage. Periods T2, T6, and T10 in FIG. 4 are feed-through periods after the reset period. In this feed-through period, the image sensor output signal CDSIN corresponds to the black level of the pixel signal. Periods T3, T4, T7, T8, T11, and T12 in FIG. 4 are signal periods after the feed-through period, and in this signal period, the image sensor output signal CDSIN corresponds to the pixel signal of the subject. Periods T3, T4, T7, T8, T11, and T12 in FIG. 4 are amplification periods by the correlated double sampling circuit (CDS) 11 and the variable gain amplifier (PGA) 12 in the signal period.

《Feed-through period》
Sampling to the variable capacitor C5 of the black level during the feed-through period, sampling to the ground voltage of the terminal T8 and the variable capacitor C6 by the first pulse signal φ1 which is set to the high level in the feed-through periods T2, T6, T10 Is executed.

  Further, in the first half of the pulse period (feed-through period) of the high-level first pulse signal φ1, a gain switch is supplied to the switch SW14 of the first gain control unit GC1 and the switch SW15 of the second gain control unit GC2. The control signal φSW_EN is set to the high level, and the switches SW14 and SW15 are controlled to be on. As a result, the sampling of the black level variable capacitor C5 and the sampling of the ground voltage to the variable capacitor C6 are speeded up, and the response of the analog front end (AFE) can be improved. Further, in the second half of the pulse period (feed-through period) of the high-level first pulse signal φ1, the gain switch supplied to the switch SW14 of the first gain control unit GC1 and the switch SW15 of the second gain control unit GC2 The control signal φSW_EN is set to the low level, and the switches SW14 and SW15 are controlled to the off state. Therefore, in this state, the gain for the input high frequency noise of the correlated double sampling circuit (CDS) 11 is low due to the large resistance values of the resistor R2 of the first gain control unit GC1 and the resistor R3 of the second gain control unit GC2. It will be controlled by the value. As a result, according to the semiconductor integrated circuit IC according to the first embodiment of the present invention shown in FIG. 1, the aliasing noise of the correlated double sampling circuit (CDS) 11 can be reduced.

《Amplification period》
Next, in the amplification periods T3, T4, T7, T8, T11, and T12, the difference voltage between the voltage of the pixel signal of the signal period and the sampling black level of the variable capacitor C5 is amplified by the high-level inverted second pulse signal / φ2. The operation and the amplification operation of the difference voltage of approximately zero volts between the ground voltage of the terminal T8 and the sampling ground voltage of the variable capacitor C6 are executed.

  Further, in the first half of the pulse period (amplification period) of the inverted second pulse signal / φ2, the gain switch control signal φSW_EN supplied to the switch SW14 of the first gain control unit GC1 and the switch SW15 of the second gain control unit GC2. Is set to the high level, and the switches SW14 and SW15 are controlled to be on. As a result, the first negative feedback amplification path amplifies the difference voltage between the pixel signal voltage and the black level during the signal period, and the second negative feedback amplification of the difference voltage between the ground voltage of the terminal T8 and the sampling ground voltage of the variable capacitor C6. The amplification by the path is accelerated, and the response of the analog front end (AFE) can be improved.

  Further, in the second half of the pulse period (amplification period) of the inverted second pulse signal / φ2, gain switch control supplied to the switch SW14 of the first gain control unit GC1 and the switch SW15 of the second gain control unit GC2. The signal φSW_EN is set to a low level, and the switches SW14 and SW15 are controlled to be turned off. Therefore, in this state, the gain for the input high frequency noise of the correlated double sampling circuit (CDS) 11 is low due to the large resistance values of the resistor R2 of the first gain controller GC1 and the resistor R3 of the second gain controller GC2. It will be controlled by the value. As a result, according to the semiconductor integrated circuit IC according to the first embodiment of the present invention shown in FIG. 1, the aliasing noise of the correlated double sampling circuit (CDS) 11 can be reduced.

  In response to the differential amplification signals generated in the amplification periods T3, T4, T7, T8, T11, and T12, the output data DATA (n−1), DATA (n), DATA ( n + 1) is generated.

<< Pipeline type A / D converter >>
FIG. 5 shows a pipelined A / D converter suitable as an analog / digital converter (ADC) 13 of a semiconductor integrated circuit IC incorporating an analog front end (AFE) according to the first embodiment of the present invention shown in FIG. FIG.

  A pipeline type A / D converter suitable as the analog-to-digital converter (ADC) 13 shown in FIG. 5 can achieve high accuracy and low power consumption.

  The pipeline A / D converter shown in FIG. 5 includes a plurality of cascade-connected A / D conversion stages 1, 2,..., J, (j + 1), and an encoder ENC. The first A / D conversion stage 1 and the last A / D conversion stage (j + 1) have a resolution of 3 bits, and the other intermediate A / D conversion stages 2,..., J are 1.5 bits. Has resolution. The first A / D conversion stage 1 includes a sub A / D converter 10 to which an analog input signal Vi is supplied, and a sub D to which signals do, d1 and d2 from the sub A / D converter 10 are supplied. / A converter 11, switched capacitor circuit 12 (Scod, Scev), and differential amplifier 13 (AMP). As a result, a remainder signal Vres from the differential amplifier 13 (AMP) to the next A / D conversion stage 2 is formed.

  In the pipelined A / D converter capable of interleaving operation shown in FIG. 5, the first A / D conversion stage 1 monitors the signal level of the analog input signal Vi. When the analog input signal Vi reaches an excessive signal level that exceeds the maximum value on the positive side of the input dynamic range of A / D conversion, the first A / D conversion stage 1 forms an abnormality detection signal indicating an excessive level, and the encoder 100 (ENC). Then, a 16-bit output signal that is the maximum code is generated from the encoder 100 (ENC). When the analog input signal Vi becomes an under-signal level that exceeds the negative maximum value of the input dynamic range of A / D conversion, the first A / D conversion stage 1 forms an abnormality detection signal indicating an under-level and the encoder 100 (ENC). Then, the encoder 100 (ENC) generates a 16-bit output signal that is the minimum code.

  FIG. 5 also shows the configuration of the first A / D conversion stage 1 and the two A / D conversion stages 2.

  The first A / D conversion stage 1 includes a 3-bit sub A / D converter 10, a 1.5 bit sub D / A converter 11, a switched capacitor circuit 12 incorporating an adder, an amplifier 13 (AMP), Is included. The analog input signal Vi of the first stage 1 is roughly quantized by the sub A / D converter 10, and a quantized analog voltage is generated by the sub D / A converter D11 from the digital signal of the sub A / D converter 10. . The quantized analog error is generated by subtracting the quantized analog voltage from the original analog input signal Vi by the adder of the switched capacitor circuit 12. In order to generate the interstage remainder signal Vres of the analog signal, the quantized analog error is amplified by the amplifier 13 (AMP), and the quantized analog error is restored to the full scale range. In particular, the switched capacitor circuit 12 of the first A / D conversion stage 1 includes a first switched capacitor circuit Scod and a second switched capacitor circuit Scev. Therefore, the first switched capacitor circuit Scod performs the sampling operation in the odd-numbered pipeline period of the pipeline and the hold operation in the even-numbered pipeline period, and the second switched capacitor circuit Scev is the even-numbered pipeline period of the pipeline. A sample operation in the pipeline period and an odd-numbered hold operation in the pipeline period are performed. As a result, high accuracy and low power consumption of the first stage A / D conversion can be realized.

  The second A / D conversion stage 2 includes a 1.5-bit sub A / D converter 20, a 1.5-bit sub D / A converter 21, a switched capacitor circuit 22 incorporating an adder, and an amplifier 23. (AMP) is included. The 1.5-bit sub A / D converter 20 is supplied to the encoder 100 (ENC) and the next stage by being supplied with the analog inter-stage remainder signal Vres from the first stage A / D conversion stage 1. A 1.5-bit digital signal is generated. The 1.5-bit sub D / A converter 21 is supplied with a 1.5-bit digital signal from the first A / D conversion stage 1 to generate a quantized analog voltage. The quantized analog error is generated by subtracting the quantized analog voltage from the interstage remainder signal Vres of the analog signal from the first stage 1 by the adder of the switched capacitor circuit 22. The quantized analog error is amplified by the amplifier 23 (AMP) to generate the interstage remainder signal Vres of the analog signal, and the quantized analog error is restored to the full scale range. The 1.5-bit digital signal from the 1.5-bit sub A / D converter 20 of the second A / D conversion stage 2 and the interstage remainder signal Vres of the analog signal from the amplifier 23 (AMP) are This is supplied to the three A / D conversion stages 3. Similarly, up to the final A / D conversion stage (j + 1), the 1.5-bit digital signal and the interstage remainder signal Vres are transmitted from the preceding stage to the subsequent stage. The switched capacitor circuit 22 of the second A / D conversion stage 2 also includes a first switched capacitor circuit Scod and a second switched capacitor circuit Scev. Accordingly, the first switched capacitor circuit Scod performs the sampling operation in the odd-numbered pipeline period of the pipeline and the hold operation in the even-numbered pipeline period, and the second switched capacitor circuit Scev is the even-numbered pipe of the pipeline. A sample operation in the line period and an odd-number hold operation in the pipeline period are performed. As a result, high accuracy and low power consumption of the second stage A / D conversion can be realized.

  As mentioned above, the invention made by the present inventor has been specifically described based on various embodiments. However, the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention. Needless to say.

IC ... semiconductor integrated circuit CDSIN ... image sensor output signal C _{IN ...} input coupling capacitance R2, R3 ... resistor SW1, SW2 ... switch phi SW_EN ... gain switch control signal GC1 ... first gain controller GC2 ... second gain controller C5 , C6 ... variable capacitance 11 ... correlated double sampling circuit (CDS)
12 ... Variable gain amplifier (PGA)
13. Analog-to-digital converter (ADC)
14 ... Digital comparator (CMP)
DESCRIPTION OF SYMBOLS 15 ... Clamp control part SW6-SW12 ... Switch C7, C8 ... Capacity | capacitance φ1 ... 1st pulse signal φ2 ... 2nd pulse signal / φ2 ... Inversion 2nd pulse signal DOUT ... Digital conversion output signal CLP_LV ... Clamp level digital signal T1, T2 , T3, T4 ... terminals

Claims (10)

The semiconductor integrated circuit includes a first variable capacitor, a second variable capacitor, a correlated double sampling circuit, an analog / digital converter, and a digital comparator,
An image sensor output signal of a solid-state imaging device can be supplied to one end of the first variable capacitor, and a ground voltage can be supplied to one end of the second variable capacitor.
The correlated double sampling circuit includes a differential amplifier, a first input switch, a second input switch, a first feedback capacitor, a second feedback capacitor, a first feedback switch, and a second feedback switch,
The other end of the first variable capacitor is connected to a first terminal of the first input switch, a second terminal of the first input switch is connected to a non-inverting input terminal of the differential amplifier, and the first input switch A third terminal of the second terminal is connected to the ground voltage;
The other end of the second variable capacitor is connected to a first terminal of the second input switch. A second terminal of the second input switch is connected to an inverting input terminal of the differential amplifier. The third terminal is connected to the ground voltage,
The first feedback capacitor and the first feedback switch are connected in series between the non-inverting input terminal and the inverting output terminal of the differential amplifier, and the second feedback capacitor and the second feedback switch are connected to the differential amplifier. Connected in series between the inverting input terminal and the non-inverting output terminal of the amplifier;
The path between the first terminal and the third terminal of the first input switch and the path between the first terminal and the third terminal of the second input switch are the first level of the first pulse signal. In response to a conduction state in a feed-through period after a reset period of the solid-state imaging device,
The path between the first terminal and the third terminal of the first input switch and the path between the first terminal and the third terminal of the second input switch are the first pulse signal In response to a second level different from the first level, controlled to a non-conductive state;
The first feedback switch and the second feedback switch are in response to the first level of the inverted second pulse signal that is an inverted signal of the second pulse signal, after the feed-through period of the solid-state imaging device. Controlled to the conductive state during the signal period,
The first feedback switch and the second feedback switch are controlled to be non-conductive in response to the second level different from the first level of the inverted second pulse signal,
The path between the first terminal and the second terminal of the first input switch and the path between the first terminal and the second terminal of the second input switch are the same as those of the inverted second pulse signal. In response to the first level, controlled to a conductive state;
The path between the first terminal and the second terminal of the first input switch and the path between the first terminal and the second terminal of the second input switch are the inverted second pulse signal. In response to the second level different from the first level of
The differential input terminal of the analog-to-digital converter is responsive to a differential amplified output signal between the inverting output terminal and the non-inverting output terminal of the differential amplifier of the correlated double sampling circuit; A digital conversion output signal is generated from the output terminal of the analog / digital converter,
The digital input signal and the second input terminal of the digital comparator can be supplied with the digital conversion output signal and a digital instruction signal indicating a clamp level corresponding to the black level of the image sensor output signal, respectively. ,
The digital comparator may be configured such that the digital conversion output signal generated from the output terminal of the analog-digital converter coincides with the digital instruction signal during the feed-through period of the solid-state imaging device. Control the capacitance values of the variable capacitor and the second variable capacitor;
The semiconductor integrated circuit includes a first input control unit including a first input resistor and a first input control switch connected in parallel, and a second input including a second input resistor and a second input control switch connected in parallel. And further comprising a control unit,
The image sensor output signal of the solid-state imaging device can be supplied to the one end of the first variable capacitor via the first input control unit, and the second input control is supplied to the one end of the second variable capacitor. The ground voltage can be supplied through the unit,
The first input control switch of the first input control unit and the second input control switch of the second input control unit are controlled to be conductive by the first level of a switch control signal,
The first input control switch of the first input control unit and the second input control switch of the second input control unit are not responsive to the second level different from the first level of the switch control signal. Controlled to the conduction state,
In the first half of the feed-through period in which the first pulse signal is at the first level and in the first half of the signal period in which the inverted second pulse signal is at the first level, the switch control signal is at the first level. By being set to, the first input control switch and the second input control switch are controlled to the conductive state,
In the second half of the feed-through period in which the first pulse signal is at the first level and the second half of the signal period in which the inverted second pulse signal is at the first level, the switch control signal is at the second level. Accordingly, the first input control switch and the second input control switch are controlled to be in the non-conduction state. In claim 1,
The on-resistance of the first input control switch and the on-resistance of the second input control switch that are controlled to be in the conducting state by the first level of the switch control signal are the resistance value of the first input resistance and the first resistance. A semiconductor integrated circuit characterized by being set to a resistance value lower than a resistance value of two input resistors. In claim 2,
The semiconductor integrated circuit further comprises a variable gain amplifier,
The differential input terminal of the analog / digital converter is connected to the inverting output terminal and the non-inverting output terminal of the differential amplifier of the correlated double sampling circuit via the variable gain amplifier. A semiconductor integrated circuit. In claim 3,
The semiconductor integrated circuit further comprises a clamp control unit,
A semiconductor integrated circuit, wherein a comparison output signal of the digital comparator is supplied to capacitance value control terminals of the first variable capacitor and the second variable capacitor via the clamp controller. In claim 4,
The semiconductor integrated circuit according to claim 1, wherein the first variable capacitor and the second variable capacitor each include a parallel connection of a plurality of weighted capacitors. In claim 5,
The first variable capacitor and the second variable capacitor each include a plurality of control switches,
In the first variable capacitor and the second variable capacitor, each of the plurality of capacitors and each control switch of the plurality of control switches are connected in series. In claim 6,
The plurality of control switches are controlled by a plurality of switch control signals generated from the clamp control unit. In claim 7,
The semiconductor integrated circuit according to claim 1, wherein the first feedback switch, the second feedback switch, the first input control switch, and the second input control switch are each configured by a CMOS analog switch circuit. In claim 8,
2. The semiconductor integrated circuit according to claim 1, wherein the analog / digital converter is a pipeline type A / D converter. In claim 9,
A semiconductor integrated circuit, wherein the solid-state imaging device is a CCD.

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