JP2013162057A - Semiconductor light-emitting element and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inhibit Ag migration to improve reliability of a semiconductor light-emitting element.SOLUTION: A semiconductor light-emitting element comprises: a semiconductor laminate including a first semiconductor layer of a first conductivity type, an active layer formed on the first semiconductor layer, and a second semiconductor layer of a second conductivity type formed on the active layer; a first transparent conductive film formed on the second semiconductor layer; a second transparent conductive film having an inner peripheral part and an outer peripheral part which are formed on the first transparent conductive film at a predetermined interval; a light reflection layer which is formed on the second semiconductor layer in a region inside the inner peripheral part of the second transparent conductive film and has a film thickness not more than a film thickness of the second transparent conductive film; a junction layer for coating the second transparent conductive film and the light reflection layer; and a wiring electrode formed in contact with the first semiconductor layer.

Description

  The present invention relates to a semiconductor light emitting device and a method for manufacturing the same.

  A nitride semiconductor light emitting diode such as GaN can emit ultraviolet light or blue light, and can emit white light by using a phosphor. LEDs capable of generating high output white light are also used for illumination.

  Sapphire is generally used as a nitride semiconductor growth substrate. However, since the sapphire substrate is insulative, it is necessary to form the n-side and p-side electrodes on the same surface side (growth layer side). Light absorption by the pad and drive voltage increase due to increased series resistance are generated. Furthermore, the sapphire substrate has a low thermal conductivity and poor heat dissipation, and is not suitable for a device that inputs a large current.

  Therefore, in recent years, the n-side electrode and the p-side electrode are formed by removing the sapphire growth substrate by laser lift-off (LLO) or polishing and forming an n-side electrode on the exposed nitride semiconductor layer (n-type semiconductor layer). A device structure is being developed in which the two are arranged at opposite positions.

  Such a semiconductor light emitting device includes at least an n-type semiconductor layer, a semiconductor stack including an active layer for light emission, and a p-type semiconductor layer. A p-side electrode is formed over the entire light emitting region on the p-type semiconductor layer side, and an n-side electrode is formed on a part of the surface of the n-type semiconductor layer. Light is extracted from the n-type semiconductor layer side. A part of the light emitted from the active layer is directly emitted from the n-type semiconductor layer, but a part of the light is reflected from the p-side electrode provided in the p-type semiconductor layer and then extracted from the n-type semiconductor layer.

  In order to efficiently reflect light at the p-side electrode, a layer structure that improves the reflectivity of the p-side electrode is known, and in particular, a structure using a light reflecting electrode for the p-side electrode through a transparent electrode is known. Are known. The light reflecting electrode is made of a highly reflective metal material such as silver (Ag). However, Ag is easy to migrate, and when migration occurs, Ag precipitates in a colloidal form at the pn junction interface in the semiconductor light emitting device, which may deteriorate the electrical characteristics of the semiconductor light emitting device and reduce the reliability. .

  In order to suppress the migration of Ag, a migration barrier is provided so as to surround the periphery of the light reflecting electrode (see, for example, Patent Document 1 and Patent Document 2), and a metal film is installed using a plating method as an Ag protective film It is known (see, for example, Patent Document 3).

JP 2003-243705 A JP 2006-41403 A JP 2007-80899 A

  The conventional migration barrier described in Patent Document 1 and Patent Document 2 is provided on the side surface and a part of the upper surface of the light reflecting electrode so as to cover the edge portion of the light reflecting electrode containing Ag. In the conventional structure, since it is difficult to completely cover the edge portion of the light reflecting electrode, it is necessary to make the light reflecting electrode thin. However, when the light reflecting electrode is thinned, another problem that the high reflectance inherent in Ag cannot be obtained sufficiently occurs.

  Further, when a migration barrier is formed at the edge portion of the light reflecting electrode by vacuum film formation, slight cracks or porous defects are generated, and Ag migration occurs from that portion. In particular, cracks are prominently generated at the edge of the light reflecting electrode.

  Further, in the method shown in Patent Document 3, the Ag protective film is formed by a plating method. However, although the plating method is effective as a method for forming a dense film, the plating speed is used to eliminate porous defects. Therefore, it is necessary to increase the film thickness, and it takes time to form the film.

  An object of the present invention is to improve the reliability of a semiconductor light emitting device by suppressing Ag migration.

  According to one aspect of the present invention, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type, an active layer formed on the first semiconductor layer, and a first layer formed on the active layer. A semiconductor stack including a second-conductivity-type second semiconductor layer, a first transparent conductive film formed on the second semiconductor layer, and an inner portion formed on the first transparent conductive film with a predetermined interval. A second transparent conductive film having a peripheral portion and an outer peripheral portion, and formed on the second semiconductor layer in a region inside the inner peripheral portion of the second transparent conductive film, and having a thickness equal to or less than the thickness of the second transparent conductive film A light reflection layer having a thickness of 2 mm, a bonding layer covering the second transparent conductive film and the light reflection layer, and a wiring electrode formed in contact with the first semiconductor layer.

  According to another aspect of the present invention, a method for manufacturing a semiconductor light emitting device includes: (a) a step of preparing a growth substrate; and (b) a first semiconductor layer of a first conductivity type on the growth substrate. Growing a semiconductor stack including an active layer formed on the first semiconductor layer and a second semiconductor layer of a second conductivity type formed on the active layer; and (c) the first Forming a first transparent conductive film on the two semiconductor layers; and (d) forming a second transparent conductive film having an inner peripheral portion and an outer peripheral portion spaced apart from each other on the first transparent conductive film. And (e) forming a light reflecting layer having a film thickness equal to or smaller than the film thickness of the second transparent conductive film on the second semiconductor layer in the inner region of the inner periphery of the second transparent conductive film. (F) forming a bonding layer so as to cover the second transparent conductive film and the light reflecting layer; and (g) forming a eutectic layer on the surface. Providing a prepared support substrate; (h) a step of overlapping and bonding the eutectic layer and the bonding layer; (i) a step of peeling the growth substrate from the semiconductor stack; and (j) Forming a wiring electrode in contact with the first semiconductor stack.

  ADVANTAGE OF THE INVENTION According to this invention, the migration of Ag can be suppressed and the reliability of a semiconductor light-emitting device can be improved.

1 is a schematic cross-sectional view showing an element structure of a nitride semiconductor light emitting element (LED element) 101 according to an embodiment of the present invention and a diagram showing potential differences in respective regions. It is a schematic sectional drawing for demonstrating the manufacturing method of the nitride semiconductor light-emitting device (LED element) 101 by the Example of this invention. It is a schematic sectional drawing for demonstrating the manufacturing method of the nitride semiconductor light-emitting device (LED element) 101 by the Example of this invention. It is a schematic sectional drawing for demonstrating the manufacturing method of the nitride semiconductor light-emitting device (LED element) 101 by the Example of this invention. It is a schematic sectional drawing for demonstrating the manufacturing method of the nitride semiconductor light-emitting device (LED element) 101 by the Example of this invention. It is a schematic sectional drawing for demonstrating the manufacturing method of the nitride semiconductor light-emitting device (LED element) 101 by the Example of this invention. It is a schematic sectional drawing for demonstrating the manufacturing method of the nitride semiconductor light-emitting device (LED element) 101 by the Example of this invention.

  FIG. 1A is a schematic cross-sectional view showing an element structure of a nitride semiconductor light emitting element (LED element) 101 according to an embodiment of the present invention and a diagram showing a potential difference in each region. FIG. 1B is a schematic plan view showing a pattern of the second transparent electrode layer 32 of the nitride semiconductor light emitting device (LED device) 101 according to the embodiment of the present invention. In the figure, the size of each component is different from the actual ratio.

  The nitride semiconductor light emitting element (LED element) 101 is a vertical feed optical semiconductor device. For example, the first semiconductor layer (n-type semiconductor layer) 22, the active layer 23, and the second semiconductor layer (p-type semiconductor layer) 24. A GaN-based semiconductor layer (light emitting part) 2 composed of: a first transparent electrode layer 31, a second transparent electrode layer 32, a light reflecting layer (reflecting electrode layer) 33, and a eutectic layer containing a eutectic material 7 and a bonding layer 34, a silicon (Si) support substrate 10 bonded to the light reflection layer 33 and the second transparent electrode layer 32 through the eutectic alloy layer, and formed on the entire back surface of the support substrate 10. And the n-side electrode 8 formed on a part of the surface of the GaN-based semiconductor layer (light emitting portion) 2. Light is emitted from the n-type semiconductor layer 22 side.

Each layer of the GaN-based semiconductor layer 2 is made of a nitride semiconductor represented by Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), and an n-type dopant is used as necessary. Mg, etc. are added as Si and p-type dopants. The configuration of the semiconductor layer 2 is not limited to the above three types, and current diffusion, a cladding layer, a contact layer, and the like can be arbitrarily inserted in order to improve the light emission efficiency. (Quantum well structure).

The first transparent electrode layer 31 is formed on the entire surface of the p-type semiconductor layer 24 using indium tin oxide (ITO). The first transparent electrode layer 31 has ohmic characteristics with the p-type semiconductor layer 24. The sheet resistance of the first transparent electrode layer 31 is 50Ω / □ to 200Ω / □, and the contact resistance between the first transparent electrode layer 31 and the p-type semiconductor layer 24 is 2 × 10 ⁻⁴ Ωcm ^{2 to} 7 × 10 ^{−. 3} Ωcm ² . In addition, the film thickness of the 1st transparent electrode layer 31 is 5-20 nm.

  The second transparent electrode layer 32 is intermittently formed on the first transparent electrode layer 31 using indium tin oxide (ITO), and is viewed from the light emitting surface (upper surface) of the semiconductor light emitting element 101. It is formed in a double circumferential shape matching the outer shape of 101.

  The second transparent electrode layer 32 has ohmic characteristics with the first transparent electrode layer 31 and has a higher resistance than the first transparent electrode layer 31 by adjusting sputtering conditions. Thereby, a denser film can be formed. The film thickness of the second transparent electrode layer 32 is 100 to 200 nm.

  Hereinafter, in the present specification, the double second transparent electrode layer 32 formed on the outer edge portion of the semiconductor light emitting element 101 is referred to as the outer peripheral portion 32a of the second transparent electrode layer and is formed on the inner side thereof. This is called the inner peripheral portion 32b of the second transparent electrode layer. As shown in FIG. 1B, the outer peripheral portion 32a is formed on the outer side of the inner peripheral portion 32b so as to surround the inner peripheral portion 32b in a plan view at a constant interval.

  Further, a region (light emitting layer central region) inside the inner peripheral portion 32b of the second transparent electrode layer is referred to as a first region (light reflecting layer forming region) and is surrounded by the second transparent electrode layer 32 in the first region. This portion is referred to as a first trench portion TR1. A region outside the first region is called a second region (light emitting layer peripheral region), and a region in the second region between the outer peripheral portion 32a and the inner peripheral portion 32b is called a second trench portion TR2. .

  In this embodiment, since the outer shape of the semiconductor light emitting element 101 viewed from the upper surface is rectangular, the outer peripheral portion 32a and the inner peripheral portion 32b are also rectangular when viewed from the upper surface of the second transparent electrode layer 32. The width of the second transparent electrode layer 32 is set to 10 to 50 μm for both the outer peripheral portion 32a and the inner peripheral portion 32b, but both widths may be the same or different. Moreover, the width | variety of the area | region (2nd trench part TR2) between the outer peripheral part 32a and the inner peripheral part 32b of a 2nd transparent electrode layer is set to 10-20 micrometers.

  By forming the second transparent electrode layer 32 into a double structure of the outer peripheral portion 32a and the inner peripheral portion 32b, the bonding layer 34 formed on the second transparent electrode layer 32 increases the region where it can be bonded to the support substrate 10 (the eutectic layer 7). The adhesion strength is maintained. Therefore, it is possible to withstand the impact caused by laser irradiation during growth substrate peeling (LLO).

  The light reflecting layer 33 is formed in the first trench part TR1 using Ag or an alloy containing Ag. The light reflecting layer 33 is electrically joined to the first transparent electrode layer 31 and the second transparent electrode layer 32. The film thickness of the light reflecting layer 33 is 100 to 200 nm, and is the same film thickness as the second transparent electrode layer 32 or less. Note that the light reflecting layer 33 is not formed in the second region. When Ag formed by sputtering is used as the light reflecting layer 33, the reflectance is 94% or more.

  The bonding layer 34 is made of, for example, a stacked layer of TiW / Pt / Ti / Pt / Au, and the entire second region (including the inside of the second trench portion TR2) and the entire first region (inside and above the first trench portion TR1). The light reflection layer 33 is formed on the light reflection layer 33).

  In this way, Ag or a light reflecting layer 33 containing Ag is formed in the first trench part TR1 inside the inner peripheral part 32b of the second transparent electrode layer 32, and the film thickness of the light reflecting layer 33 is set to the second transparent thickness. Since the thickness is set equal to or less than the thickness of the electrode layer 32, the side surface of the light reflecting layer 33 is not exposed. Therefore, when the bonding layer 34 is formed, film defects such as cracks at the edge portions of the side surface and the upper surface of the light reflecting layer 33 are suppressed, and Ag migration can be suppressed.

  Hereinafter, a method for manufacturing a nitride semiconductor light emitting device (LED device) 101 according to an embodiment of the present invention will be described with reference to FIGS.

  First, a semiconductor film forming process is performed. Using MOCVD, a C-plane sapphire growth substrate 1, a buffer layer 20, an undoped GaN layer 21, a first semiconductor layer (n-type semiconductor layer) 22, an active layer 23, and a second semiconductor layer (p-type semiconductor layer) The semiconductor layer 2 composed of 24 is laminated to obtain an optical semiconductor epi-wafer shown in FIG.

Each layer is made of a nitride semiconductor represented by Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), and Si is used as an n-type dopant, and p-type dopant is used as necessary. Add Mg or the like.

  Next, the semiconductor epi-wafer obtained in the semiconductor film forming process is taken out from the MOCVD reactor and an element process is performed. First, the p-type semiconductor layer 24 is activated. In the p-type semiconductor layer 24, hydrogen is mixed in the film during the growth process to form Mg—H bonds. In such a state, the p-type semiconductor layer 24 cannot increase its resistance because it cannot function as a dopant. For this reason, an activation process for expelling hydrogen of the p-type semiconductor layer 24 from the film is required. Specifically, heat treatment is performed at 400 ° C. or higher in a vacuum or an inert gas atmosphere using a heat treatment furnace.

  Next, as shown in FIG. 2B, a first transparent electrode layer 31 made of indium tin oxide (ITO) is formed on the surface of the p-type semiconductor layer 24. First, ITO is laminated by RF sputtering so as to have a thickness of 20 nm. At this time, the substrate temperature is heated to 150 ° C. to 300 ° C. Since ITO accelerates crystallization from a substrate temperature of 150 ° C. or higher during film formation, the substrate temperature is preferably heated to 200 ° C. to 250 ° C. Thereafter, the laminated ITO film is wet-etched into a desired shape (for example, the shape of each semiconductor light emitting element 101) by a photolithography etching method, and the first transparent electrode layer 31 is formed. In this embodiment, the shape is 1000 μm □.

  Next, as shown in FIGS. 2C and 2D, a second transparent electrode layer 32 made of ITO is formed on the first transparent electrode layer 31 into a double circumferential shape in a lift-off process. In this example, the width of each circumferential second transparent electrode layer 32 was 50 μm, and the interelectrode width was 20 μm.

  First, as shown in FIG. 2C, a photoresist pattern PR1 is formed in a region other than the region where the second transparent electrode layer 32 is formed. Thereafter, ITO is laminated by RF sputtering so as to have a thickness of about 150 nm. At this time, the substrate temperature is controlled at room temperature. Note that the second transparent electrode layer 32 increases the flow rate of introduced oxygen as compared with the first transparent electrode layer 31 in order to increase the resistance compared to the first transparent electrode layer 31. For example, the first transparent electrode layer 31 is controlled at an oxygen flow rate of 0.1 to 0.5 sccm, and the second transparent electrode layer 32 is controlled at an oxygen flow rate of 0.6 sccm or more. In this embodiment, the oxygen flow rate is controlled by 0.3 sccm for the first transparent electrode layer 31 and 0.6 sccm for the second transparent electrode layer 32.

  Thereafter, as shown in FIG. 2D, the second transparent electrode layer 32 is formed by a lift-off process for removing the photoresist pattern PR1. After the removal of the photoresist pattern PR1, heating is performed at 400 ° C. to 800 ° C., preferably 400 ° C. to 700 ° C., in an atmosphere containing oxygen. In this embodiment, the heat treatment is performed at 500 ° C./1 min.

  In this embodiment, the first and second transparent electrode layers 31 and 32 are annealed after the second transparent electrode layer 32 is formed. The purpose of the heat treatment is to form the first transparent electrode layer 31 and the p-type. This is performed to form an ohmic contact with the semiconductor layer 24, and if the heat treatment of the first transparent electrode layer 31 is performed, the heat treatment of the second transparent electrode layer 32 is not necessarily required.

  Next, as shown in FIGS. 3A and 3B, a light reflecting layer 33 made of silver (Ag) is formed in the first region (in the first trench TR <b> 1) on the first transparent electrode layer 31. . First, as shown in FIG. 3A, a light reflecting layer 33 is laminated on the entire surface of the growth substrate 1 by RF sputtering so as to have a thickness of about 150 nm. At this time, the substrate temperature is room temperature. Thereafter, a photoresist pattern PR2 is formed so that Ag remains in the first region.

  Next, as shown in FIG. 3B, a light reflecting layer 33 made of Ag is formed in the first region by wet etching using a mixed solution made of phosphoric acid, acetic acid and nitric acid. When the wet etching method is used, it is possible to make contact with an adjacent layer without exposing the side surface of the light reflecting layer 33 at the boundary with the transparent electrode layer 32.

  Next, as shown in FIG. 3C, the bonding layer 34 is lifted off so as to cover the second region (including the inside of the second trench portion TR2) and the entire region of the light reflecting layer 33 formed in the first region. It is formed in a process. As the bonding layer 34, a multilayer metal layer made of TiW / Pt / Ti / Pt / Au is used. First, a photoresist pattern is formed so that the bonding layer 34 can be formed so as to cover the light reflecting layer 33 in the first region. Next, a multilayer metal layer made of TiW / Pt / Ti / Pt / Au is laminated by RF sputtering so that each film thickness becomes 500/100/100/100/200 nm. At this time, the substrate temperature is room temperature. Thereafter, by removing the photoresist pattern, the bonding layer 34 having a desired pattern is formed. The bonding layer is preferably formed with an RF power of 300 W or more in order to maintain adhesion with the light reflecting layer 33.

Next, as shown in FIG. 4A, the growth substrate 1 is partitioned into a desired semiconductor light emitting element size using the photoresist pattern PR3, and element isolation is performed. For element isolation, for example, reactive ion etching (RIE) is used. The RIE conditions are adjusted so that the process pressure is 1 Pa at an antenna output of 650 W, a bias output of 350 W, a Cl ₂ gas flow rate of 30 sccm, and the semiconductor layer 2 is etched as shown in FIG. Thereafter, as shown in FIG. 4C, the photoresist pattern PR3 is removed. Thereby, the epi wafer (growth substrate 1) is partitioned and separated for each semiconductor light emitting element.

  Since the semiconductor light emitting device 101 (FIG. 1) of this embodiment is a vertical feed optical semiconductor device, it is necessary to peel off the growth substrate 1. Therefore, there is a need for the conductive support substrate 10 in which the growth layer is self-supporting and the current can be injected in the vertical direction.

  As the conductive support substrate 10, for example, n-type Si or SiC can be used. A eutectic (bonding) layer 7 is formed on one surface of the support substrate 10. As the eutectic layer 7, an AuSn layer is formed, and the thickness of the AuSn layer is preferably 1 to 2 μm. The ratio of Au and Sn is Sn at 20 wt%. The eutectic layer 7 is not limited to AuSn.

  A support substrate 10 on which the eutectic layer 7 described above is formed is prepared, and as shown in FIG. 5A, the bonding layer 6 on the growth substrate 1 side and the eutectic layer 7 on the support substrate 10 side are overlapped to form a wafer. It heat-presses using a bonder apparatus, and a joining interface is AuSn eutectic and joined. In this embodiment, for example, bonding is performed for 5 minutes (thermocompression bonding) by pressurization of 350 kg and heating at 320 ° C.

  Thereafter, a growth substrate peeling step is performed. In this step, the growth substrate 1 is irradiated with a high-power pulsed laser beam having an energy capable of decomposing GaN such as excimer laser light from the back surface of the growth substrate 1 on the side where the semiconductor layer 2 is not grown. LLO (laser lift-off) method that separates from 2 is used. As the laser, a KrF excimer laser having a wavelength of 248 nm is used. The irradiation area is 1150 × 1150 μm, and the irradiation energy is 800 to 900 mJ / cm 2.

  As shown in FIG. 5B, the excimer laser is irradiated from the back surface of the growth substrate 1 to decompose a part of the buffer layer 20 and the GaN layer 21 to separate the growth substrate 1 and the GaN-based semiconductor layer 2. The state shown in FIG. Ga generated by laser lift-off is removed with hot water or the like, and then surface-treated with hydrochloric acid. As a result, the n-type semiconductor layer 22 (FIG. 1) is exposed. Any surface treatment can be used as long as it can etch a nitride semiconductor, and acids such as phosphoric acid, sulfuric acid, KOH, and NaOH, and chemicals such as alkali can also be used. The surface treatment may be performed by dry etching using Ar plasma or chlorine plasma, polishing, or the like.

  Further, the surface of the n-type semiconductor layer 22 is smoothed using a Cl or Ar treatment using a dry etching apparatus such as RIE or a CMP polishing apparatus to remove a laser mark or a laser damage layer. In order to improve the light extraction efficiency, the exposed n-type semiconductor layer 22 surface is preferably subjected to uneven processing (forms a light extraction structure).

  Next, the n-side electrode 8 is formed by a lift-off method. First, as shown in FIG. 6A, a photoresist pattern PR4 is formed in a region where the n-side electrode 8 is not formed by photolithography, and Ti having a thickness of about 1 nm is formed by electron beam vacuum deposition. A 1000 nm Al film is sequentially formed. Thereafter, as shown in FIG. 6B, the n-side electrode 8 is formed into a desired pattern by removing the photoresist pattern PR4.

  Next, as shown in FIG. 6C, the support substrate 10 is thinned by grinding and polishing treatment. For example, the supporting substrate 10 is thinned to about 250 μm by this process. Thereafter, the back electrode 9 is formed on the back surface of the support substrate 10 that has been made into a thin piece. The back electrode 9 is formed by sequentially depositing Ti / Pt / Au using, for example, an electron beam vacuum deposition method. In addition, each film thickness shall be about 50/150/200 nm, for example.

  Next, as shown in FIG. 7, the support substrate 10 is divided by laser scribing or dicing. Thus, the nitride semiconductor light emitting device 101 is completed. In order to whiten the blue GaN light emitting element, a yellow phosphor is put in a resin for sealing and filling the light emitting element.

  As described above, according to the embodiment of the present invention, the first transparent electrode layer 31 made of ITO is formed on the p-type semiconductor layer 24, and the second transparent electrode made of double circumferential ITO is further formed thereon. Layer 32 is formed. As a result, a plurality of trench structures (first trench part TR1 and second trench part TR2) dividing the first region and the second region can be formed.

  By embedding the light reflecting layer 33 made of Ag in the first trench part TR1 (first region), it is possible to eliminate the difference in film thickness between the second transparent electrode layer 32 made of ITO and the light reflecting layer 33 made of Ag. Thus, the bonding layer 34 can be laminated without exposing the side surface of the light reflecting layer 33 made of Ag at the ITO / Ag boundary. Furthermore, since the edge of the light reflecting layer 33 made of Ag is not projected and covered by the bonding layer 34 on the light reflecting layer 33, the edge layer of the reflecting layer is formed on the layer formed on the conventional Ag light reflecting layer. It is possible to prevent the microphone caused by the generated crack.

  Further, according to the embodiment of the present invention, the first region and the second region are electrically joined, and the first region and the second region are equal to the surface direction on the first transparent electrode layer 31. It is possible to supply current. Therefore, the active layer region can emit light uniformly throughout the first transparent electrode.

  According to the embodiment of the present invention, the potential applied to the first transparent electrode layer 31 differs between the first region and the second region. The relationship between potentials in each region is shown in the lower part of FIG. The second transparent electrode layer 32 adjacent to the light reflecting layer 33 in the second region has a high resistance because the carrier density in the ITO is reduced due to high oxygen introduction. For this reason, almost the same voltage as the applied voltage is applied, and the potential is the same at that portion. On the other hand, the region partitioned by the second transparent electrode layer 32 in the first region and the second region has no high resistance layer, so that current flows and becomes lower than the input voltage. Thereby, migration of Ag ions can be prevented by providing a portion having a different series resistance in the longitudinal direction of the semiconductor device and generating a potential difference.

  In addition, according to the embodiment of the present invention, it is possible to energize the entire first transparent electrode layer 31, and therefore, Ag migration can be suppressed without reducing the light emitting region. Moreover, since the film thickness of the 1st transparent electrode layer 31 is 5-20 micrometers, the reflectance of the light reflection layer 33 formed in the 1st area | region is not impaired.

  In the above-described embodiment, the second transparent conductive film 32 is separated from the inner peripheral portion 32b that defines the central region of the GaN-based semiconductor layer (light emitting portion) 2 with a predetermined interval from the inner peripheral portion 32b. The outer peripheral portion 32a is arranged so as to surround the inner peripheral portion in plan view, but two or more outer peripheral portions 32a may be arranged outside the inner peripheral portion 32b.

  As mentioned above, although this invention was demonstrated along the Example and the modification, this invention is not limited to these. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

DESCRIPTION OF SYMBOLS 1 ... Sapphire growth substrate, 2 ... GaN-type semiconductor layer (light emission part), 7 ... Eutectic layer, 10 ... Silicon (Si) support substrate, 8 ... N side electrode, 9 ... Back electrode, 20 ... Buffer layer, 21 ... , 22 ... first semiconductor layer (n-type semiconductor layer), 23 ... active layer, 24 ... second semiconductor layer (p-type semiconductor layer), 31 ... first transparent electrode layer, 32 ... second transparent electrode layer, 33 ... Light reflecting layer, 34... Bonding layer, 101... Nitride semiconductor light emitting element (LED element)

Claims (4)

A semiconductor stack including a first semiconductor layer of a first conductivity type, an active layer formed on the first semiconductor layer, and a second semiconductor layer of a second conductivity type formed on the active layer; ,
A first transparent conductive film formed on the second semiconductor layer;
A second transparent conductive film having an inner peripheral portion and an outer peripheral portion formed at a predetermined interval on the first transparent conductive film;
A light reflecting layer formed on the second semiconductor layer in an inner region of the inner periphery of the second transparent conductive film, and having a film thickness equal to or less than the film thickness of the second transparent conductive film;
A bonding layer covering the second transparent conductive film and the light reflecting layer;
A semiconductor light emitting device having a wiring electrode formed in contact with the first semiconductor layer.   The semiconductor light emitting element according to claim 1, wherein the second transparent conductive film has a higher resistance than the first transparent conductive film. (A) preparing a growth substrate;
(B) On the growth substrate, a first conductive type first semiconductor layer, an active layer formed on the first semiconductor layer, and a second conductive type second semiconductor layer formed on the active layer. Growing a semiconductor stack including two semiconductor layers;
(C) forming a first transparent conductive film on the second semiconductor layer;
(D) forming a second transparent conductive film having an inner peripheral part and an outer peripheral part spaced apart from each other on the first transparent conductive film;
(E) forming a light reflecting layer having a film thickness equal to or smaller than the film thickness of the second transparent conductive film on the second semiconductor layer in a region inside the inner peripheral portion of the second transparent conductive film;
(F) forming a bonding layer so as to cover the second transparent conductive film and the light reflection layer;
(G) preparing a support substrate having a eutectic layer formed on the surface;
(H) a step of overlapping and bonding the eutectic layer and the bonding layer;
(I) peeling the growth substrate from the semiconductor stack;
(J) forming a wiring electrode in contact with the first semiconductor stack;   The method of manufacturing a semiconductor light emitting element according to claim 3, wherein the second transparent conductive film is formed to have a higher resistance than the first transparent conductive film.

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