JP2013157638A - Method of manufacturing photoelectric conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve both: improvement of charge transfer characteristics when charge is output from a charge storage area; and suppression of occurrence of dark current during charge storage.SOLUTION: Depletion voltage in a charge storage area is formed in a range of 0 to supply voltage/2 (V), gate potential of a transfer MOS transistor during a period of charge transfer is formed in a range of the supply voltage/2 to supply voltage (V), and gate potential of the transfer MOS transistor during a period of charge storage is formed in a range of -(supply voltage/2) to 0 (V).

Description

  The present invention relates to a photoelectric conversion device, a manufacturing method thereof, and an imaging system, and more particularly to a CMOS area sensor, a manufacturing method thereof, and a photoelectric conversion device that can be suitably used in the manufacturing method, a manufacturing method thereof, and an imaging system.

  Conventionally, a CCD is known as a solid-state imaging device that converts an image signal into an electrical signal. This CCD has a photodiode array, and a pulse voltage is applied to the electric charge accumulated in each photodiode to read it out as an electric signal.

  In recent years, a CMOS area sensor in which peripheral circuits are integrally formed by a CMOS process has been used.

  The CMOS area sensor has advantages such as lower power consumption and lower driving power than the CCD, and future demand expansion is expected.

  A CMOS area sensor as a typical example of the photoelectric conversion device will be described with reference to FIG.

  FIG. 8 is a schematic cross-sectional view of the photodiode area 301 and the transfer MOS transistor area 302 of the CMOS area sensor.

  303 is an N-type silicon substrate, 304 is a P-type well, 307 is a gate electrode of a transfer MOS transistor, 308 is an N-type charge storage region of the photodiode, 309 is a surface P-type region for embedding the photodiode, 305 Is a field oxide film for element isolation, and 310 is an N-type high concentration region which forms a floating diffusion and functions as a drain region of the transfer MOS transistor 307.

  311 is a silicon oxide film that insulates the gate electrode from the first wiring layer, 312 is a contact plug, 313 is the first wiring layer, 314 is an interlayer insulating film that insulates the first wiring layer and the second wiring layer, Reference numeral 315 denotes a second wiring layer, 316 denotes an interlayer insulating film that insulates the second wiring layer and the third wiring layer, 317 denotes a third wiring layer, and 318 denotes a passivation film.

  A color filter layer (not shown) is formed on the passivation film 318, and a microlens for improving sensitivity is formed.

  Light incident from the surface enters the photodiode through an opening without the third wiring layer 317.

  The light is absorbed in the N-type charge storage region 308 or the P-type well 304 of the photodiode to generate electron / hole pairs. Among these, electrons are accumulated in the N-type charge accumulation region 308.

  The transfer MOS transistor portion of the CMOS area sensor is preferably designed so that electrons stored in the photodiode can be efficiently and preferably transferred completely to the floating diffusion portion.

  If there is a pixel with low transfer efficiency, the output of the corresponding pixel becomes smaller than that of a normal pixel, resulting in a defect called a black defect in which the output image becomes black.

  Furthermore, the output may vary with each shooting, and image degradation may occur as random noise.

  In addition, the transfer MOS transistor is connected to the photodiode, and a dark current is generated during the off-period of the transfer MOS transistor. When electrons leak into the photodiode, the output of the corresponding pixel becomes larger than that of a normal pixel. In some cases, the output image becomes white, which is called a white defect.

  In order to prevent the above problems, as a conventional technique of the transfer MOS structure, for example, a structure in which the work function of the gate electrode is controlled as in Patent Document 1 or a gate electrode is added as in Patent Document 2 Has been proposed.

JP 2001-196572 A JP 2004-039671 A

  However, in the structure of a conventional photoelectric conversion device, particularly a transfer MOS transistor of a CMOS area sensor, in order to improve the electron transfer efficiency of the photodiode, and preferably to transfer completely, the transfer between the transfer MOS transistor and the photodiode. It is necessary to provide an n-type diffusion layer (when the transfer MOS transistor is an nMOS), and the impurity concentration of the diffusion layer must be increased.

  Further, a high positive voltage must be applied to the gate electrode of the transfer MOS transistor during charge transfer.

On the other hand, the off-period of the transfer MOS transistor, that is, the electrons generated from the Si / SiO ₂ interface of the MOS transistor flow into the photodiode during charge accumulation, so that the channel layer near the interface is sufficiently accumulated with holes. It was necessary to apply a high voltage with an absolute value on the negative side until it reached the state.

  This voltage must be negative as the impurity concentration in the n-type region between the transfer MOS transistor and the photodiode is higher.

  As a result, in order to obtain a better image, it is necessary to apply a voltage having a large voltage difference between on and off to the gate electrode.

  For this reason, it is necessary to apply a high voltage to the gate electrode of the MOS transistor, and there is a concern that the dielectric breakdown of the gate insulating film and the characteristics of the MOS transistor may be deteriorated.

  In order to solve these problems, it is necessary to increase the thickness of the gate insulating film of the MOS transistor and increase the element size of the MOS transistor, which is an obstacle to the high integration and miniaturization of the CMOS area sensor.

  Further, in the structure described in Patent Document 1, since a special manufacturing process is added to the gate electrode of the transfer MOS transistor to control the work function, there is a problem that the manufacturing cost increases. By adding the gate electrode in this way, the number of elements per pixel increases, resulting in a problem that high integration is hindered.

  Therefore, the present invention has been made to solve the above-described problems. The transfer MOS transistor and the photo diode of the photoelectric conversion device that improve various characteristics such as the number of saturated charges, image scratches, and random noise of the photoelectric conversion device. A diode and a method for manufacturing the same are provided.

In order to solve the above problems, the present invention provides a first conductivity type semiconductor substrate and a first conductivity type provided in a first impurity region of a second conductivity type opposite to the first conductivity type. A photoelectric conversion element comprising a second impurity region and a third impurity region of a second conductivity type formed adjacent to the second impurity region, and disposed adjacent to the first impurity region, And a transfer MOS transistor for transferring charges accumulated in the second impurity region, wherein the channel impurity concentration of the transfer MOS transistor is in the range of 1E15 to 5E17 cm 3, and the second impurity region is 2.0μm from 0.2 depth and impurity concentration in the range of 1E18 cm ^-3 from 1E16, and a gate electrode under the gate electrode of the transfer MOS transistor It exists in the range 0 to 0.6μm from parts, the third impurity region is in the range from 0.05 to 1.0μm depth and impurity concentration in the range of 1E19 cm ^-3 from 5E16 The distance from the gate electrode of the transfer MOS transistor is in the range of 0 to 0.5 μm.

  Furthermore, the present invention is further characterized in that the first impurity region has a plurality of impurity concentration peaks.

The second impurity region may include fourth and fifth impurity regions having at least two different profiles, and the fourth impurity region may have a depth of 0.5 to 2.0 μm. And the impurity concentration is in the range of 1E16 to 2E17 cm ⁻³ , and is present in the range of 0 to 0.4 μm from the end of the gate electrode below the gate electrode of the transfer MOS transistor, and the fifth impurity The region has a depth of 0.2 to 1.0 μm, an impurity concentration of 1E16 to 1E18 cm ⁻³ , and 0.1 to 0.6 μm below the gate electrode of the transfer MOS transistor. It exists in the range.

  According to the present invention, the plurality of impurity concentration peaks in the first impurity region are such that the first impurity concentration peak is larger than the second impurity concentration peak, and the first impurity concentration peak is the second impurity concentration peak. It is characterized by being formed at a position deeper in the substrate than the peak.

  Further, the present invention is characterized in that the first impurity concentration peak has an impurity concentration that is three times or more of the second impurity concentration peak.

The present invention also provides an n-type semiconductor substrate, an n-type second impurity region provided in the p-type first impurity region, and a p-type formed adjacent to the second impurity region. A photoelectric conversion element including the third impurity region, and an nMOS transistor disposed adjacent to the first impurity region and configured to transfer charges accumulated in the second impurity region. In the device, the voltage for depleting the second impurity region is V1, the power supply voltage is V2, the gate potential of the transfer MOS transistor during the charge accumulation period is V3, and the gate of the transfer MOS transistor during the charge transfer period When the potential is V4, 0 <V1 <V2 / 2, −V2 /
2 <V3 <0, V2 / 2 <V4 <V2.

  The present invention also provides a p-type semiconductor substrate, a p-type second impurity region provided in the n-type first impurity region, and an n-type formed adjacent to the second impurity region. A photoelectric conversion element including the third impurity region, and a pMOS transistor disposed adjacent to the first impurity region and configured to transfer charges accumulated in the second impurity region. In the device, the voltage for depleting the second impurity region is V1, the power supply voltage is V2, the gate potential of the transfer MOS transistor during the charge accumulation period is V3, and the gate of the transfer MOS transistor during the charge transfer period When the potential is V4, 0 <V1 <V2 / 2, V2 / 2 <V3 <V2, and −V2 / 2 <V4 <0.

  Further, according to the present invention, during the charge accumulation period, a region in which charges having a conductivity type opposite to that of the second impurity region are arranged continuously from the second impurity region to the transfer MOS transistor. In the charge transfer period, a charge region having the same conductivity type as that of the second impurity region is continuously arranged from the second impurity region to the channel region of the transfer MOS transistor.

The present invention also provides a first conductivity type semiconductor substrate and a first conductivity provided in a first impurity region having a plurality of impurity concentration peaks of a second conductivity type opposite to the first conductivity type. A photoelectric conversion element including a second impurity region of a type and a third impurity region of a first conductivity type formed in contact with the second impurity region, and disposed adjacent to the second impurity region; A transfer MOS transistor for transferring the charge accumulated in the second impurity region, wherein the second impurity region is formed by a plurality of steps, Of the steps, the region formed in at least one step is formed so as to exist under the gate electrode of the transfer MOS transistor, and the third impurity region is formed by ion implantation to form a gate of the transfer MOS transistor. Characterized in that it is formed so as not to overlap the poles.

  The third impurity region may be ion-implanted from a direction at an angle of 20 to 30 degrees with respect to a normal direction of the semiconductor substrate.

  In the present invention, the second impurity region includes fourth and fifth impurity regions having at least two different profiles, and the fourth impurity region exists under the gate electrode of the transfer MOS transistor. As described above, the fifth impurity region is formed under the gate electrode of the transfer MOS transistor, and is formed by ion implantation from a direction at an angle of 0 to 7 degrees from the normal direction of the semiconductor substrate. It is characterized by being formed by ion implantation from an angle of 0 to 45 degrees from the normal direction of the semiconductor substrate.

  According to the present invention, when the transfer MOS transistor is on, that is, during charge transfer, the transfer efficiency of the charge accumulated in the charge accumulation region of the photodiode to the floating diffusion region is improved, and when the transfer MOS transistor is off, that is, It is possible to suppress the generation of dark current during charge accumulation, and it is possible to achieve both improvement in transfer efficiency and suppression of dark current during charge accumulation.Therefore, the number of saturated charges in the photoelectric conversion device, image scratches, random noise, etc. It is possible to improve various characteristics.

It is sectional drawing of the CMOS area sensor as one embodiment of this invention. It is sectional drawing to which the part of the photodiode and transfer MOS transistor of the CMOS area sensor as embodiment of this invention was expanded. It is a circuit diagram of a CMOS area sensor as an embodiment of the present invention. It is a graph which shows the characteristic which transfers an electric charge from a photodiode to a floating diffusion area | region. It is a graph which shows the relationship between the gate voltage at the time of OFF of a transfer MOS transistor, and dark current. It is sectional drawing for demonstrating the manufacturing method of embodiment of this invention. It is a block diagram which shows the case where the photoelectric conversion apparatus as embodiment of this invention is applied to a still video camera. It is sectional drawing of the conventional CMOS area sensor.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a schematic sectional view illustrating an embodiment of the present invention, and shows a photodiode portion 1 and a transfer MOS transistor portion 2 of a CMOS area sensor.

  In the following embodiments, the first conductivity type is N-type and the second conductivity type is P-type. However, the present invention is not limited to this, and the first conductivity type is P-type. The second conductivity type may be an N type.

  3 is an N-type silicon substrate, 4 is a P-type well (first impurity region), 7 is a gate electrode of a transfer MOS transistor, 8 is an N-type charge storage region (second impurity region) of a photodiode, 9 Is a surface P-type region (third impurity region to be a surface charge recombination region) for embedding the photodiode, 5 is a field oxide film for element isolation, and 10 is from the N-type charge storage region 8 This is an N-type high concentration region serving as a floating diffusion to which charges are transferred.

  11 is a silicon oxide film that insulates the gate electrode from the first wiring layer, 12 is a contact plug, 13 is the first wiring layer, 14 is an interlayer insulating film that insulates the first wiring layer and the second wiring layer, Reference numeral 15 denotes a second wiring layer, 16 denotes an interlayer insulating film that insulates the second wiring layer and the third wiring layer, 17 denotes a third wiring layer, and 18 denotes a passivation film.

  Further, a color filter layer (not shown) and a microlens for improving sensitivity may be formed on the passivation film 18.

  In this embodiment, three wiring layers are formed. However, depending on the specifications of the sensor, the wiring layers may be one layer or two layers in order to ensure optical characteristics.

  FIG. 2 is an enlarged cross-sectional view of the photodiode portion and the transfer MOS transistor portion of the present embodiment.

  The N-type charge accumulation region 8 is formed by ion implantation multiple times (in this embodiment, twice), and is represented by 8A (fourth impurity region) and 8B (fifth impurity region), respectively. Yes. Reference numeral 70 denotes a gate oxide film.

In this embodiment, the gate oxide film 70 is formed in a thickness range of 4 to 20 nm, and the channel concentration of the transfer MOS transistor, that is, the surface concentration of the P-type well 4 is formed in the range of 1E15 to 5E17 cm ^−3. Has been.

The charge storage region 8A has a depth of 0.5 to 2 μm and is disposed so as to exist under the gate electrode from the photodiode side end of the gate electrode, and exists in a range of 0 to 0.4 μm from the end of the gate electrode. The impurity concentration is in the range of 1E16 to 1E18 cm ⁻³ .

The charge storage region 8B has a depth of 0.2 to 1 μm and is disposed so as to exist below the gate electrode from the photodiode side end of the gate electrode, and within a range of 0.1 to 0.6 μm from the gate electrode end. The impurity concentration is formed in the range of 1E16 to 2E17 cm ⁻³ .

When the charge storage region is formed of one impurity region, it is formed with a depth of 0.2 to 2.0 m and an impurity concentration of 1E16 to 1E18 cm ⁻³ .

The surface P-type region 9 has a depth of 0.05 to 1 μm and is disposed away from the photodiode side end of the gate electrode (so as not to overlap the gate electrode), and from the gate electrode end to the surface P-type region 9 The distance is 0 to 0.5 μm (0 is not included), and the impurity concentration is in the range of 5E16 to 1E19 cm ⁻³ .

  FIG. 3 is a circuit diagram of the CMOS sensor according to the present embodiment.

  The CMOS sensor of the present embodiment is shown in a circuit diagram as shown in FIG.

  FIG. 4 is a graph showing the charge transfer characteristics of the photodiode having the above structure.

  A point a in FIG. 4 is a depletion voltage of the photodiode, and shows a voltage at which the charge accumulation region is almost completely depleted. In general, there is a correlation with the number of saturated charges that can be accumulated in a photodiode.

  The point b in FIG. 4 is a transferable voltage. If a voltage higher than the transferable voltage is applied to the gate electrode of the transfer MOS transistor, the charge of the photodiode is efficiently transferred to the floating diffusion region, and in some cases, completely transferred. Is possible.

  FIG. 5 is a graph showing the relationship between the voltage applied to the gate electrode of the transfer MOS transistor during charge accumulation and the dark current accumulated in the photodiode.

  By applying a voltage below the point c to the gate electrode, dark current generated during the accumulation period can be suppressed.

  As a result of the study by the present inventors, in the present embodiment, by setting each potential as follows based on the above description, the above effects, that is, improvement of transfer efficiency and suppression of dark current during charge accumulation are achieved. It is possible to achieve both.

  When the transfer MOS transistor is an nMOS, the voltage for depleting the photodiode serving as the light receiving portion is V1, the power supply voltage is V2, the gate potential of the transfer MOS transistor during the charge accumulation period is V3, and during the charge transfer period When the gate potential of the transfer MOS transistor is V4, 0 <V1 <V2 / 2, −V2 / 2 <V3 <0, V2 / 2 <V4 <V2. Here, the depletion voltage refers to a reverse bias voltage applied to the pn junction.

  When the transfer MOS transistor is a pMOS, the depletion voltage is V1, the power supply voltage is V2, the gate potential of the transfer MOS transistor during the charge accumulation period is V3, and the gate potential of the transfer MOS transistor during the charge transfer period is Assuming V4, 0 <V1 <V2 / 2, V2 / 2 <V3 <V2, and −V2 / 2 <V4 <0.

  FIG. 6 is a cross-sectional view showing the manufacturing process of the present embodiment.

  A well for pixel formation is formed on the n-type semiconductor substrate. A photoresist for forming a P-type well (first impurity region) for pixel formation is patterned and ion implantation is performed. (FIG. 6A) At this time, the well of this pixel region is formed by ion implantation under the condition that the following structure is formed.

The bottom well layer 507A has an impurity concentration peak of approximately 1 × 10 ¹⁷ cm ⁻³ and a peak depth of approximately 2.5 μm.

The well layer 507B has an impurity concentration peak of approximately 5 × 10 ¹⁵ cm ⁻³ and a peak depth of approximately 1.7 μm.

The well layer 507C has an impurity concentration peak of approximately 5 × 10 ¹⁵ cm ⁻³ and a peak depth of approximately 1.0 m.

The well layer 507D has an impurity concentration peak of approximately 2 × 10 ¹⁶ cm ⁻³ and a peak depth of approximately 0.7 μm.

In the shallowest region, there is a well layer 507E for determining the channel concentration. The impurity concentration peak is approximately 3 × 10 ¹⁶ cm ⁻³ and the peak depth is approximately 0.1 μm.

  The four layers of well layers 507A to 507D have the following functions, respectively.

  In the well layers 507B to 507D located in the shallow part, a connecting part for guiding optical carriers to the photodiode in the pixel is formed, and in the well layer 507A in the deepest part, a potential peak that determines the spectral sensitivity is formed.

  Here, by setting the concentration of the deepest well layer 507A higher than the concentration of the well layer 507B, preferably 3 times or more, more preferably 5 times or more, a potential barrier is formed between them, Since the carriers generated by the incident light can be efficiently guided to the photodiode without losing in the substrate direction, the sensitivity can be improved.

  Further, by controlling the concentration and depth of the diffusion layers of the well layers 507D and 507C, the number of saturated charges that can be held in the N-type charge storage region 511 to be formed later can be controlled.

  Further, by controlling the concentration and depth of the diffusion layer of the well layer 507E, it is possible to achieve both the characteristics of transferring charges from the photodiode to the floating diffusion and the dark current characteristics when off.

  In order to improve sensitivity, it is desirable to form deeper wells because the volume of the well layer that can absorb light increases, but increasing the number of ion implantations to achieve this is a departure from the viewpoint of shortening the construction period. End up.

  Therefore, the energy of ion implantation of each of the well layers 507A to 507D is such that the region between the well layers 507A to 507D is completely depleted by the built-in potential because the region of opposite conductivity type is completely depleted. Therefore, it is possible to form a well layer with a minimum number of ion implantations.

  In the present embodiment, the P-type well layer 507 composed of a plurality of layers has a five-layer structure of three connecting well layers 507B to 507D, the deepest well layer, and the channel region. The number of connecting well layers depends on the required sensitivity. Since the well depth should be set accordingly, the upper limit of the number of layers is not particularly set.

  Further, if at least two layers of connecting wells are formed, the effect of improving the sensitivity can be obtained.

Subsequently, the P-type well 508 and the N-type well 509, which are device forming regions (peripheral circuit regions) for circuit driving, are formed by patterning using different photomasks and introducing impurities. (Fig. 6b)
Here, the pixel region and the peripheral circuit region can be formed independently or shared with the pixel region. Further, there is no problem even if the order of forming the pixel region and the peripheral circuit region is changed.

Next, after a gate oxide film is formed to a thickness of 7 to 20 nm, polysilicon is deposited and a photoresist is patterned in a desired shape to form a polysilicon electrode 510. (Fig. 6c)
Next, a photodiode N-type charge storage region 511 (second impurity region) is formed by ion implantation.

  At this time, the N-type region is implanted from a direction inclined with respect to the normal direction of the semiconductor substrate so as to exist under the gate electrode of the transfer MOS transistor, and the angle ranges from 0 degrees to 7 degrees.

  The acceleration energy ranges from 350 to 1000 keV when the ion species to be implanted is As, and ranges from 250 to 750 keV when the ion species to be implanted is Ph.

  In this range, the film thickness of the polysilicon and the mask material is appropriately selected so that the ion species do not penetrate directly under the transfer MOS transistor.

  Further, if As, Ph, or Sb is ion-implanted in a region shallower than the diffusion layer to be implanted, the transfer characteristics can be controlled more easily.

  The ion implantation conditions for the shallow diffusion layer are preferably such that the ion implantation is performed with an acceleration energy that is about ½ of the conditions for forming the deep diffusion layer.

  The direction of implantation is performed so as to exist under the gate electrode of the transfer MOS transistor, and the angle is in the range of 0 to 45 degrees.

  Next, a surface charge accumulation region (third semiconductor region) is formed by ion implantation of B or BF2.

  At this time, the P-type region is implanted in a direction away from the gate electrode of the transfer MOS transistor (so as not to overlap the gate electrode), and the angle is in a direction range inclined by 7 to 45 degrees from the normal direction of the semiconductor substrate.

When conditions are set in more detail in the above embodiment, for example, when the thickness of the gate oxide film is 15 nm, the thickness of the gate electrode is 300 nm, and the channel concentration is 3E16 cm ⁻³ , the conditions for forming the P-type region are as follows: When the ion species is B, the acceleration energy is 15 keV, the implantation amount is 5E13 to 1E14 cm-2, and the implantation angle is 20 to 30 degrees in the direction away from the gate electrode of the transfer MOS transistor, the transfer characteristics and the dark current characteristics are good. Can be achieved.

  According to the present embodiment, the depletion voltage (voltage a) in FIG. 4 is 0.9 to 1.6 V, the transferable voltage (voltage b) is 2.5 to 3.5 V, and the dark current suppression voltage (FIG. The voltage c) can be controlled in the range of -1.5 to -0.5 V, and both transfer characteristics and dark current suppression can be achieved.

  In the present embodiment, the structure for accumulating electrons in the photodiode has been described, but the structure for accumulating holes has the same effect. In that case, all of the P-type layer and the N-type layer may be formed in reverse.

  Although the present embodiment has been described with reference to a CMOS area sensor, the same effect can be obtained when applied to a CCD. In that case, the floating diffusion 10 area is replaced with the VCCD.

  Since the manufacturing method after the contact opening process is the same as that of the conventional CMOS area sensor, the description thereof is omitted.

  In addition, by forming a plurality of well layers in the photodiode portion and making the concentration of the deepest well layer higher than that of the upper well layer, optical carriers absorbed in the well layer are efficiently lost without losing in the substrate direction. It can be led to a photodiode, and the sensitivity is improved.

  Next, an imaging system using the photoelectric conversion device of the above embodiment will be described.

  Based on FIG. 7, an example when the photoelectric conversion apparatus of the present invention is applied to a still camera will be described in detail.

  FIG. 7 is a block diagram showing a case where the photoelectric conversion device of the present invention is applied to a “still video camera”. The photoelectric conversion device of the above embodiment will be described as the solid-state imaging element 104.

  In FIG. 7, 101 is a barrier that serves as a lens switch and a main switch, 102 is a lens that forms an optical image of a subject on the solid-state image sensor 104, 103 is a diaphragm for changing the amount of light passing through the lens 102, and 104 is A solid-state image sensor for capturing an object imaged by the lens 102 as an image signal, 106 an A / D converter that performs analog-digital conversion of an image signal output from the solid-state image sensor 104, and 107 an A / D converter A signal processing unit 108 performs various corrections on the image data output from the device 106 and compresses the data. A solid-state imaging device 104, an imaging signal processing circuit 105, an A / D converter 106, and a signal processing unit 107 have A timing generator 109 for outputting a timing signal is an overall control / operation unit for controlling various operations and the entire still video camera. 110, a memory unit for temporarily storing image data, 111 an interface unit for recording or reading on a recording medium, and 112 a detachable semiconductor memory for recording or reading image data A recording medium 113 is an interface unit for communicating with an external computer or the like.

  Next, the operation of the still video camera at the time of shooting in the above configuration will be described.

  When the barrier 101 is opened, the main power supply is turned on, the control system power supply is turned on, and the power supply of the imaging system circuit such as the A / D converter 106 is turned on.

  Then, in order to control the exposure amount, the overall control / arithmetic unit 109 opens the diaphragm 103, and the signal output from the solid-state imaging device 104 is converted by the A / D converter 106 and then sent to the signal processing unit 107. Entered. Based on this data, exposure calculation is performed by the overall control / calculation unit 109.

  The brightness is determined based on the result of the photometry, and the overall control / calculation unit 109 controls the aperture according to the result.

  Next, based on the signal output from the solid-state image sensor 104, the high-frequency component is extracted and the distance to the subject is calculated by the overall control / calculation unit 109.

  Thereafter, the lens is driven to determine whether or not it is in focus. If it is determined that the lens is not in focus, the lens is driven again to perform distance measurement.

  Then, after the in-focus state is confirmed, the main exposure starts. When the exposure is completed, the image signal output from the solid-state image sensor 104 is A / D converted by the A / D converter 106 and is written to the memory unit by the overall control / calculation 109 through the signal processing unit 107.

  Thereafter, the data stored in the memory unit 110 is recorded on a removable recording medium 112 such as a semiconductor memory through the recording medium control I / F unit under the control of the overall control / arithmetic unit 109. Further, the image may be processed by directly inputting to a computer or the like through the external I / F unit 113.

  Since the present invention can improve the sensitivity of a CCD or CMOS area sensor, it can be used for a still camera or a video camera with good sensitivity.

1, 301, 502 Photodiode 2, 302 Charge transfer MOS transistor 3, 303, 501 Semiconductor substrate 4, 304, 507 P-type well 4A-4D, 507A-507E Well layer 5, 305, 505 Field oxide film 6,306 , 506 Channel stop layer 7, 307, 510 Transfer MOS gate electrode 70 Transfer MOS gate oxide film 8, 8A, 8B, 308, 511 Photodiode N-type charge storage region 9, 309, 512 Surface P-type region 10, 310 Drain n-type high concentration region 11, 311 Silicon oxide film 12, 312 Contact plug 13, 313 Metal first layer 14, 314 Metal first layer and metal second layer interlayer insulating film 15, 315 Metal second layer 16, 316 Metal Second layer and metal third layer interlayer insulation film 17, 317 Metal third layer 18, 318 Passivation film

The present invention relates to a method for manufacturing a photoelectric conversion device.

The invention described in this specification has been made to solve the above-described problems, and is a transfer of a photoelectric conversion device that improves various characteristics such as the number of saturated charges of the photoelectric conversion device, image scratches, and random noise. A MOS transistor, a photodiode, and a method for manufacturing the same are provided.

One of the invention described herein includes a semiconductor substrate of a first conductivity type, a first conductive provided on the first conductivity type opposite to conductivity type second conductive type first impurity region of the A photoelectric conversion element including a second impurity region of a type and a third impurity region of a second conductivity type formed adjacent to the second impurity region; and disposed adjacent to the first impurity region. And a transfer MOS transistor for transferring the charge accumulated in the second impurity region, the channel impurity concentration of the transfer MOS transistor is in the range of 1E15 to 5E17 cm 3, and impurity region is 2.0μm from 0.2 depth and impurity concentration in the range of 1E18 cm ^-3 from 1E16, and gate electrode terminal under the gate electrode of the transfer MOS transistor There range from 0 to 0.6μm from the third impurity region is in the range of 1.0μm from 0.05 depth and impurity concentration in the range of 1E19 cm ^-3 from 5E16, The distance from the gate electrode of the transfer MOS transistor is in the range of 0 to 0.5 μm.

One of the inventions described in this specification is further characterized in that the first impurity region has a plurality of impurity concentration peaks.

One of the inventions described in this specification is that the second impurity region includes fourth and fifth impurity regions having at least two different profiles, and the fourth impurity region has a depth. Is 0.5 to 2.0 μm, the impurity concentration is in the range of 1E16 to 2E17 cm ⁻³ , and is in the range of 0 to 0.4 μm from the end of the gate electrode under the gate electrode of the transfer MOS transistor. The fifth impurity region has a depth of 0.2 to 1.0 μm, an impurity concentration in the range of 1E16 to 1E18 cm ⁻³ , and below the gate electrode of the transfer MOS transistor It exists in the range of 0.1 to 0.6 μm.

One of the inventions described in this specification is that, among the plurality of impurity concentration peaks in the first impurity region, the first impurity concentration peak is larger than the second impurity concentration peak. The impurity concentration peak is formed deeper in the substrate than the second impurity concentration peak.

One of the inventions described in this specification is characterized in that the first impurity concentration peak has an impurity concentration three times or more that of the second impurity concentration peak.

One of the inventions described in this specification is an n-type semiconductor substrate, an n-type second impurity region provided in the p-type first impurity region, and the second impurity region. And a photoelectric conversion element having a p-type third impurity region formed adjacent to the first impurity region, and a charge disposed in the second impurity region disposed adjacent to the first impurity region. In this photoelectric conversion device, the voltage for depleting the second impurity region is V1, the power supply voltage is V2, the gate potential of the transfer MOS transistor during the charge accumulation period is V3, and charge transfer If the gate potential of the transfer MOS transistor during the period is V4, 0 <V1 <V2 / 2, −V2 / 2 <V3 <0, V2 / 2 <V4 <V2.

One of the inventions described in this specification is a p-type semiconductor substrate, a p-type second impurity region provided in the n-type first impurity region, and the second impurity region. A photoelectric conversion element including an n-type third impurity region formed adjacent to the first impurity region, and a charge disposed in the second impurity region disposed adjacent to the first impurity region. In this photoelectric conversion device, the voltage for depleting the second impurity region is V1, the power supply voltage is V2, the gate potential of the transfer MOS transistor during the charge accumulation period is V3, and charge transfer If the gate potential of the transfer MOS transistor during the period is V4, 0 <V1 <V2 / 2, V2 / 2 <V3 <V2, and −V2 / 2 <V4 <0.

One of the inventions described in this specification is that, during the charge accumulation period, charges having a conductivity type opposite to that of the second impurity region are arranged from the second impurity region to the transfer MOS transistor. In the charge transfer period, a charge region having the same conductivity type as the second impurity region is continuously formed from the second impurity region to the channel region of the transfer MOS transistor during the charge transfer period. It is characterized by being arranged.

One of the inventions described in this specification is a first impurity having a plurality of impurity concentration peaks of a first conductivity type semiconductor substrate and a second conductivity type opposite to the first conductivity type. A photoelectric conversion element comprising a first conductivity type second impurity region provided in the region and a first conductivity type third impurity region formed in contact with the second impurity region; A transfer MOS transistor disposed adjacent to the impurity region and configured to transfer the charge accumulated in the second impurity region, wherein the second impurity region includes a plurality of the second impurity regions. The region formed in at least one of the plurality of steps is formed to exist under the gate electrode of the transfer MOS transistor, and the third impurity region is formed by ion implantation. , Transfer M Characterized in that it is formed so as not to overlap with the gate electrode of the S transistor.

One of the inventions described in this specification is characterized in that the third impurity region is ion-implanted from a direction at an angle of 20 to 30 degrees with respect to a normal direction of the semiconductor substrate. To do.

Also, one of the invention described herein, the fourth and fifth includes an impurity region of the fourth impurity region of a second impurity region of at least two different profiles, the transfer The fifth impurity region is formed by ion implantation from a direction of an angle of 0 to 7 degrees from the normal direction of the semiconductor substrate so that the fifth impurity region exists under the gate electrode of the MOS transistor. It is characterized by being formed by ion implantation from a direction of an angle of 0 to 45 degrees from the normal direction of the semiconductor substrate so as to exist under the electrode.

According to one of the inventions described in this specification, when the transfer MOS transistor is turned on, that is, at the time of charge transfer, the transfer efficiency of the charge accumulated in the charge accumulation region of the photodiode to the floating diffusion region is improved, When the transfer MOS transistor is off, that is, when the charge is accumulated, dark current generation can be suppressed, and both transfer efficiency can be improved and dark current can be suppressed during charge accumulation. Various characteristics such as image scratches and random noise can be improved.

Claims (12)

A first conductivity type semiconductor substrate;
A second impurity region of a first conductivity type provided in a first impurity region of a second conductivity type opposite to the first conductivity type and a second impurity region formed adjacent to the second impurity region. A photoelectric conversion element comprising a third impurity region of two conductivity types;
A transfer MOS transistor disposed adjacent to the first impurity region and configured to transfer a charge accumulated in the second impurity region;
The channel impurity concentration of the transfer MOS transistor is in the range of 1E15 to 5E17 cm ⁻³ ;
The second impurity region has a depth of 0.2 to 2.0 μm, an impurity concentration in the range of 1E16 to 1E18 cm ⁻³ , and a gate electrode end below the gate electrode of the transfer MOS transistor Existing in the range of 0 to 0.6 μm,
The depth of the third impurity region is in the range of 0.05 to 1.0 μm, the impurity concentration is in the range of 5E16 to 1E19 cm ⁻³ , and the distance from the gate electrode of the transfer MOS transistor Is a range of 0 to 0.5 μm.   The photoelectric conversion device according to claim 1, wherein the first impurity region has a plurality of impurity concentration peaks. The second impurity region includes fourth and fifth impurity regions having at least two different profiles;
The fourth impurity region has a depth of 0.5 to 2.0 μm, an impurity concentration in the range of 1E16 to 2E17 cm ⁻³ , and a gate electrode under the gate electrode of the transfer MOS transistor. Exists in the range from 0 to 0.4 μm from the extreme part,
The fifth impurity region has a depth of 0.2 to 1.0 μm, an impurity concentration in the range of 1E16 to 1E18 cm ⁻³ , and 0.1 below the gate electrode of the transfer MOS transistor. The photoelectric conversion device according to claim 1, wherein the photoelectric conversion device exists in a range of from 0.6 to 0.6 μm.   The plurality of impurity concentration peaks in the first impurity region are such that the first impurity concentration peak is larger than the second impurity concentration peak, and the first impurity concentration peak is larger in the substrate than the second impurity concentration peak. The photoelectric conversion device according to claim 2, wherein the photoelectric conversion device is formed at a deep position.   The photoelectric conversion device according to claim 4, wherein the first impurity concentration peak has an impurity concentration that is three times or more the second impurity concentration peak. An n-type semiconductor substrate, an n-type second impurity region provided in the p-type first impurity region, and a p-type third impurity region formed adjacent to the second impurity region A photoelectric conversion device comprising: a photoelectric conversion element comprising: an nMOS transistor disposed adjacent to the first impurity region and transferring charges accumulated in the second impurity region;
The voltage for depleting the second impurity region is V1, the power supply voltage is V2, the gate potential of the transfer MOS transistor during the charge accumulation period is V3, and the gate potential of the transfer MOS transistor during the charge transfer period is V4. Then,
A photoelectric conversion device, wherein 0 <V1 <V2 / 2, −V2 / 2 <V3 <0, V2 / 2 <V4 <V2. A p-type semiconductor substrate, a p-type second impurity region provided in the n-type first impurity region, and an n-type third impurity region formed adjacent to the second impurity region A photoelectric conversion device comprising: a photoelectric conversion element comprising: a pMOS transistor disposed adjacent to the first impurity region and transferring the charge accumulated in the second impurity region;
The voltage for depleting the second impurity region is V1, the power supply voltage is V2, the gate potential of the transfer MOS transistor during the charge accumulation period is V3, and the gate potential of the transfer MOS transistor during the charge transfer period is V4. Then,
A photoelectric conversion device, wherein 0 <V1 <V2 / 2, V2 / 2 <V3 <V2, and −V2 / 2 <V4 <0.   During the charge accumulation period, a region in which charges having a conductivity type opposite to that of the second impurity region are continuously formed from the second impurity region to the transfer MOS transistor. The charge transfer period 8. The charge region of the same conductivity type as the second impurity region is continuously arranged from the second impurity region to the channel region of the transfer MOS transistor. The photoelectric conversion apparatus of crab. A first conductivity type semiconductor substrate;
A second impurity region of the first conductivity type provided in the first impurity region having a plurality of impurity concentration peaks of the second conductivity type opposite to the first conductivity type and the second impurity region; A photoelectric conversion element comprising a first impurity region of the first conductivity type formed in contact;
A transfer MOS transistor disposed adjacent to the second impurity region and configured to transfer charges accumulated in the second impurity region, and a method for manufacturing a photoelectric conversion device,
The second impurity region is formed by a plurality of steps, and a region formed by at least one of the plurality of steps is formed to exist under the gate electrode of the transfer MOS transistor,
The method of manufacturing a photoelectric conversion device, wherein the third impurity region is formed by ion implantation so as not to overlap a gate electrode of the transfer MOS transistor.   10. The method of manufacturing a photoelectric conversion device according to claim 9, wherein the third impurity region is ion-implanted from a direction at an angle of 20 to 30 degrees with respect to a normal direction of the semiconductor substrate. The second impurity region comprises fourth and fifth impurity regions having at least two different profiles;
The fourth impurity region is formed by ion implantation from an angle of 0 to 7 degrees from the normal direction of the semiconductor substrate so as to exist under the gate electrode of the transfer MOS transistor,
The fifth impurity region is formed by ion implantation from an angle of 0 to 45 degrees from the normal direction of the semiconductor substrate so as to exist under the gate electrode of the transfer MOS transistor. The manufacturing method of the photoelectric conversion apparatus of Claim 9.   A photoelectric conversion device according to claim 1, an optical system that forms an image of light on the photoelectric conversion device, and a signal processing circuit that processes an output signal from the photoelectric conversion device. A characteristic imaging system.