JP2013157399A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a gate electrode which has low gate resistance and a short gate length, and which can relax field concentration at the time of a high-voltage operation.SOLUTION: A field effect transistor according to the present embodiment comprises: a gate electrode 8; a dielectric film 9 which covers the gate electrode 8 and contacts the gate electrode 8, and which is composed of a silicon-containing material; and a field plate electrode 11 which is provided in an upper layer than the dielectric film 9 and on the gate electrode, and which is electrically connected with the gate electrode. The gate electrode 8 includes a metal layer 10 which is silicided on the side contacting the dielectric film 9. The gate electrode 8 and the field plate electrode 11 are electrically connected with each other via an electrode junction region 10 which is silicided by reaction between the dielectric film 9 and the gate electrode 8.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to an electrode structure of a semiconductor device, a gate structure of a field effect transistor, and a manufacturing method thereof.

  In a conventional heterojunction field effect transistor made of a semiconductor containing nitride, when the gate length is shortened as the frequency increases, the cross-sectional area of the gate electrode decreases and the gate resistance increases. In order to avoid this, the metal part is increased like an umbrella above the gate electrode, and the gate electrode cross-sectional area is increased to reduce the gate resistance while the substantial gate length in contact with the semiconductor layer is shortened. It was. Furthermore, a dielectric film is inserted between the increased metal part and the semiconductor layer to suppress a characteristic current collapse in a heterojunction field effect transistor made of a semiconductor containing nitride, and a high voltage is applied to the drain electrode. When an electric field is applied, the electric field concentrated on the gate electrode end on the drain electrode side is relaxed. For example, Non-Patent Document 1 discloses the above-described structure.

Yunju Sun, Lester F. Eastman "Large-Signal Performance of Deep Submicrometer AlGaN / AlN / GaN HEMTs With a Field-Modulating Plate", IEEE TRANSACTIONS ON ELECTRON DEVUTON 52, no. 8, pp 1689-1692

  As described above, in a heterojunction field effect transistor made of a semiconductor containing nitride, the gate length is made as short as possible, and the structure of the umbrella is opened to increase the cross-sectional area of the gate electrode, and the cross-sectional area In order to obtain a structure in which a dielectric film is inserted between an umbrella and a semiconductor that increases the thickness of the gate electrode, a dielectric film is formed on the semiconductor before the gate electrode is formed, and then the dielectric film in the region where the gate electrode is formed is dried. It was necessary to deposit the gate electrode so as to cover the region removed by etching and then removed. However, when such a method is adopted, there is a problem that damage is formed in the semiconductor layer during dry etching, and gate leakage current and current collapse characteristics deteriorate.

  Alternatively, a method of forming a dielectric film after forming the gate electrode can be considered, but it is difficult to insert the dielectric film in a region between the umbrella and the semiconductor. Another possible method is to form a dielectric film after forming the rectangular gate electrode, and then form the electrode again so as to cover the gate electrode after removing the dielectric film immediately above the gate electrode. However, it is possible to avoid dry etching damage to the semiconductor, but in this case, it is necessary to perform lithography on the gate electrode with a resolution narrower than that of the gate electrode, and the gate electrode becomes longer accordingly. There arises a problem that high frequency characteristics cannot be obtained.

  Accordingly, the present invention has been made to solve the above-described problems. A semiconductor device having a gate electrode that can reduce electric field concentration during high-voltage operation even when the gate resistance is low and the gate length is short. It is intended to provide.

  A semiconductor device according to the present invention is a semiconductor device including a field effect transistor, and the field effect transistor includes a gate electrode, a dielectric film made of a material containing silicon that covers the gate electrode and is in contact with the gate electrode, A field plate electrode that is an upper layer of the dielectric film and is electrically connected to the gate electrode on the front gate electrode. The gate electrode has a metal layer that is silicided on the side in contact with the dielectric film, The plate electrode is characterized in that the dielectric film and the gate electrode are electrically connected through an electrode junction region that is silicided by reaction.

  The semiconductor device according to the present invention, which is configured as described above, can provide a semiconductor device having a gate electrode that has a short channel, a low gate resistance, and can reduce electric field concentration during high-voltage operation. It becomes.

It is sectional drawing which shows the structure of the semiconductor device by Embodiment 1 of this invention. It is sectional drawing which shows an example of the manufacturing process of the semiconductor device by Embodiment 2 of this invention. It is sectional drawing which shows an example of the manufacturing process of the semiconductor device by Embodiment 2 of this invention. It is sectional drawing which shows an example of the manufacturing process of the semiconductor device by Embodiment 2 of this invention. It is sectional drawing which shows an example of the manufacturing process of the semiconductor device by Embodiment 2 of this invention. It is sectional drawing which shows an example of the manufacturing process of the semiconductor device by Embodiment 2 of this invention. It is sectional drawing which shows an example of the manufacturing process of the semiconductor device by Embodiment 2 of this invention.

Embodiment 1 FIG.
The overall configuration of the semiconductor device according to the first embodiment of the present invention will be described. FIG. 1 is a cross-sectional view schematically showing the semiconductor device of this embodiment. Specifically, it is an example of a semiconductor device having a heterojunction field effect transistor structure made of a nitride semiconductor. In the drawings, the same reference numerals denote the same or corresponding parts, and this is common throughout the entire specification. Further, the description of the constituent elements appearing in the whole specification is merely an example and is not limited to these descriptions.

  As shown in FIG. 1, the lowermost layer of the semiconductor device is a substrate 1, and a channel layer 3 made of a nitride semiconductor is formed thereon via a buffer layer 2, and a heterojunction with the channel layer 3 is formed thereon. A barrier layer 4 made of a nitride semiconductor is formed.

  A source electrode 5 and a drain electrode 6 are formed on the barrier layer 4. Further, the element isolation region 7 is formed outside the source electrode 5 and the drain electrode 6. The element isolation region 7 is formed from the barrier layer 4 to the depth reaching the channel layer 3. Further, a gate electrode 8 whose uppermost layer is made of platinum (Pt) is provided between the source electrode 5 and the drain electrode 6.

The gate electrode has platinum (Pt) as the uppermost layer, but may have a multilayer structure in which any one of the following metals, silicides, and nitride metals, or a combination thereof is formed in the lower layer. The metal may be selected from, for example, titanium (Ti), aluminum (Al), platinum (Pt), gold (Au), nickel (Ni), and palladium (Pd). The silicide may be selected from, for example, IrSi, PtSi, and NiSi ₂ . Examples of the nitride metal include TiN and WN.

  The uppermost layer of the gate electrode 8 does not necessarily need to be platinum, and may be any metal that can be silicided, such as gold, nickel, or iridium. That is, the gate electrode may be a metal layer that is silicided on the side where the gate electrode is in contact with the dielectric film, and may have a laminated structure including a metal layer or the like below this gate layer.

  Further, a dielectric film (surface protective film) 9 made of SiNx for protecting the source electrode 5, the drain electrode 6 and the barrier layer 4 is laminated thereon. The dielectric film 9 is not necessarily made of SiNx, and may be any dielectric film containing silicon, for example, SiOx, SiOxNy, or the like.

  At the interface between the gate electrode 8 and the dielectric film 9, there is an electrode connection region 10 made of platinum silicide formed in the dielectric film 9. Further, the electrode connection region 10 is in contact with and electrically connected to the field plate electrode 11. The field plate electrode 11 is an electrode for reducing gate resistance and relaxing electric field concentration at the gate electrode end on the drain electrode side.

  In the semiconductor device of this embodiment, the gate electrode 8 and the field plate electrode 11 can be electrically connected by adopting such a structure. In other words, when considering the wiring resistance for applying a voltage to the gate, in this embodiment, the field plate electrode 11 can be used for voltage application in addition to the gate electrode 8. This is advantageous for high-speed operation of the semiconductor device.

  Moreover, since there is an umbrella-shaped field plate electrode 11 that covers the gate electrode 8 above the gate electrode 8, there is an effect of relaxing the electrolytic concentration in the vicinity of the gate. Therefore, a semiconductor device having a gate electrode that can alleviate electric field concentration during high-voltage operation can be provided.

  Further, the conventional technique has a problem that the wiring resistance of the gate increases because the cross-sectional area cannot be increased when the gate length is shortened. However, in this embodiment, the gate dimension of the gate electrode 8 and the dimension of the field plate electrode 11 can be set independently. Therefore, even if the gate length is shortened, the wiring resistance does not increase. Further, since the gate length can be shortened, high frequency characteristics can be obtained as a transistor, which is advantageous for high-speed operation of a semiconductor device.

  In the above description, only the minimum necessary elements that operate as a transistor are described, but finally, the device is used in a structure in which wirings, via holes, and the like are formed.

  In the present embodiment, the structure of the nitride semiconductor layer has been described with reference to an example of three layers including a buffer layer, a channel layer, and a barrier layer. It is sufficient that at least one layer made of a nitride semiconductor is formed.

  In the above description, the transistor is taken as an example to describe that the dielectric film and the gate electrode react to generate a silicided electrode junction region, but the gate electrode is not necessarily required. That is, as long as the portion in contact with the dielectric film is a metal layer that is silicided, it can be applied to a substrate electrode, a source electrode, and a drain electrode that are generally used in semiconductor devices. Furthermore, such an electrode structure is not limited to a nitride semiconductor, but can also be applied to a silicon semiconductor.

Embodiment 2. FIG.
In the second embodiment, a method for manufacturing a semiconductor device will be described. Note that an example of a heterojunction field-effect transistor will be described as a semiconductor device.

  2 to 7 are cross-sectional views illustrating an example of a manufacturing process (manufacturing process) of the heterojunction field effect transistor according to the present embodiment.

  First, as shown in FIG. 2, the buffer layer 2, the channel layer 3, and the barrier layer 4 are epitaxially grown in order from the bottom by applying an epitaxial growth method such as MOCVD method or MBE method on the semiconductor substrate 1. For example, by applying an epitaxial growth method such as MOCVD method or MBE method on a semi-insulating SiC substrate, a buffer layer 2, a channel layer 3 made of GaN, and a barrier layer 4 made of Al0.28Ga0.72N are sequentially arranged from the bottom. Epitaxially grow.

  Next, as shown in FIG. 3, for example, a metal such as Ti, Al, Nb, Hf, Zr, Sr, Ni, Ta, Au, Mo, W, or a multilayer film composed of these is deposited by vapor deposition or sputtering. After deposition using a lift-off method or the like using a method, alloying is performed using an RTA method or the like to form the source electrode 5 and the drain electrode 6.

  Further, as shown in FIG. 4, element isolation regions 7 are formed by ion implantation in the channel layer 3 and the barrier layer 4 outside the region where the transistor is manufactured. In addition to the method of forming the element isolation region 7 by ion implantation, the element isolation region 7 can also be formed by etching or the like.

  Subsequently, as shown in FIG. 5, a gate electrode 8 is formed. Specifically, for example, a metal such as Ti, Al, Pt, Au, Ni, and Pd, a silicide such as IrSi, PtSi, and NiSi2, or a nitride metal such as TiN and WN, or a multilayer film made of these materials. Then, the structure under the gate electrode 8 is formed by a lift-off method or the like. Then, a metal layer is deposited on the upper layer of the lower structure by using a metal such as platinum, nickel, iridium or the like to be silicided by vapor deposition or sputtering. Thus, the gate electrode 8 is formed by a lift-off method or the like.

  Next, a dielectric film 9 is deposited as shown in FIG. Specifically, the dielectric film 9 containing silicon made of, for example, SiNx, SiOx, SiOxNy, or the like is deposited by using, for example, catalytic chemical vapor deposition, plasma chemical vapor deposition, or sputtering. When using the chemical vapor deposition method, for example, silane (SiH 4) is used as a source gas, and the dielectric film 9 is deposited at a substrate temperature of 200 to 400 ° C. and a deposition speed of 5 to 50 nm / min. At this time, the metal to be silicided such as platinum deposited on the uppermost layer of the gate electrode 8 reacts with silicon in the dielectric film 9 to form an electrode junction region 10 made of, for example, platinum silicide in the dielectric film 9. Note that in the case of using a sputtering method, heat treatment may be performed under the condition that platinum or the like is silicided.

  After that, as shown in FIG. 7, metal, silicide, or nitride metal is deposited by vapor deposition or sputtering, and the field plate electrode 11 is formed by lift-off or the like. Examples of the metal include Ti, Al, Pt, Au, Ni, and Pd. The silicide is IrSi, PtSi, NiSi2, or the like. Examples of the nitride metal include TiN and WN. Furthermore, the field plate electrode 11 may be composed of a multilayer film composed of these.

  Through the above steps, a heterojunction field effect transistor having the structure shown in FIG. 1 can be manufactured. In the above-described steps, only the minimum necessary elements that operate as a transistor are described, but finally, they are used as a device through a process of forming wirings, via holes, and the like.

  According to the method for manufacturing a semiconductor device of this embodiment, the gate electrode 8 and the field plate electrode 11 are electrically joined by the electrode joining region 10.

  Therefore, when considering the wiring resistance for applying a voltage to the gate, in this embodiment, the field plate electrode 11 is also used in addition to the gate electrode 8, so that the wiring resistance can be lowered and the transistor speed is increased. It is advantageous for the conversion. Moreover, since there is an umbrella-shaped field plate electrode 11 that covers the gate electrode 8 above the gate electrode 8, there is an effect of relaxing the electrolytic concentration in the vicinity of the gate.

  Furthermore, in the prior art, when the gate length is shortened, there is a problem that the cross-sectional area cannot be increased and the wiring resistance of the gate increases, but in this embodiment, the gate dimensions of the gate electrode 8 The size of the field plate electrode 11 can be set independently. Therefore, even if the gate length is shortened, the wiring resistance does not increase. Further, since the gate length can be shortened, high frequency characteristics can be obtained as a transistor.

  In addition, according to the present embodiment, since the gate electrode can be formed by a lift-off method or the like, it is not necessary to use a technique using dry etching that damages the semiconductor. Therefore, it is possible to suppress a phenomenon in which characteristics such as gate leakage current and current collapse due to dry etching deteriorate.

  In the above description, the transistor is taken as an example to describe that the dielectric film and the gate electrode react to generate a silicided electrode junction region, but the gate electrode is not necessarily required. That is, as long as the portion in contact with the dielectric film is a metal layer that is silicided, it can be applied to a substrate electrode, a source electrode, and a drain electrode that are generally used in semiconductor devices. Therefore, it is advantageous for increasing the speed of the semiconductor device.

  It should be understood that the above-described embodiment is illustrative in all respects and not restrictive. The scope of the present invention is shown not by the scope of the above-described embodiment but by the scope of the claims, and includes all modifications within the meaning and scope equivalent to the scope of the claims.

1 semi-insulating substrate, 2 buffer layer, 3 channel layer, 4 barrier layer,
5 source electrode, 6 drain electrode, 7 element isolation region, 8 gate electrode,
9 Dielectric film (surface protective film), 10 Electrode bonding area, 11 Field plate electrode.

Claims (6)

A semiconductor device comprising a field effect transistor,
The field effect transistor includes: a gate electrode; a dielectric film made of a material containing silicon that covers the gate electrode and is in contact with the gate electrode; and an upper layer of the dielectric film on the gate electrode. And a field plate electrode that conducts with
The gate electrode has a metal layer that is silicided on the side in contact with the dielectric film,
The semiconductor device according to claim 1, wherein the gate electrode and the field plate electrode are electrically connected through an electrode junction region that is silicided by the reaction between the dielectric film and the gate electrode. A semiconductor device comprising an electrode,
The electrode includes a dielectric film made of a material containing silicon that covers the electrode and is in contact with the electrode; and a field plate electrode that is an upper layer of the dielectric film and is electrically connected to the electrode on the electrode;
The electrode has a metal layer that is silicided on the side in contact with the dielectric film,
The semiconductor device according to claim 1, wherein the electrode and the field plate electrode are electrically connected via an electrode junction region where the dielectric film and the electrode react to form a silicide. The electrode or gate electrode is
A layer composed of a material selected from titanium, aluminum, platinum, gold, nickel, palladium, IrSi, PtSi, NiSi ₂ silicide, TiN, and WN;
A laminated structure with a layer made of a material selected from platinum, nickel or iridium metal,
3. The semiconductor device according to claim 1, wherein any one of the platinum, the nickel, and the iridium is disposed on a side where the electrode or the gate electrode is in contact with the dielectric film.   The semiconductor device according to claim 1, wherein the dielectric film is a film made of SiNx. A method of manufacturing a semiconductor device including a field effect transistor,
Forming a gate electrode by depositing a metal layer on which at least a part of the uppermost layer is silicided on a semiconductor substrate; and
A dielectric film deposition step of depositing a dielectric film containing silicon so as to cover the gate electrode while heating the semiconductor substrate at a predetermined temperature;
An electrode forming step of forming a field plate electrode by depositing a conductor layer so as to cover the dielectric film;
The method of manufacturing a semiconductor device, wherein the predetermined temperature in the dielectric film deposition step is a temperature at which the gate electrode and the dielectric film react to form a silicide. A method of manufacturing a semiconductor device comprising an electrode,
Forming an electrode by depositing a metal layer on which at least a part of the uppermost layer is silicided on a semiconductor substrate; and
A dielectric film deposition step of depositing a dielectric film containing silicon so as to cover the electrode while heating the semiconductor substrate at a predetermined temperature;
An electrode forming step of forming a field plate electrode by depositing a conductor layer so as to cover the dielectric film;
The method of manufacturing a semiconductor device, wherein the predetermined temperature in the dielectric film deposition step is a temperature at which the electrode and the dielectric film react to form a silicide.

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