JP2013143831A - Switching regulator and control method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the efficiency during light load and no-load by suppressing generation of step-down of voltage when a reverse current flows.SOLUTION: A switching regulator 100 comprises a comparator 120 executing PWM control, and having an inverted input terminal (-) to which an error output voltage from an error amplifier 110 is input, and a non-inverted input terminal (+) connected with a first offset circuit 170a and a second offset circuit 170b for applying a DC bias voltage to a slope voltage Vsl. When an offset voltage is set between two input terminals of the comparator 120, a second constant current ICC2 is fed to an offset resistor R4 by turning the second offset circuit 170b on, and an offset voltage is given by increasing the voltage drop over that when a first constant current ICC1 is flowing, thus adjusting the operation point of two input levels of the comparator 120.

Description

  The present invention relates to a switching regulator, and more particularly to a synchronous rectification step-down switching regulator and a control method thereof.

A switching regulator type power supply circuit has high-efficiency power conversion characteristics and is used as a power supply circuit for many electronic devices. In particular, in order to make it possible to use a battery used as a power source for a mobile phone or an automobile for a long time, a power supply circuit that reduces power consumption in a light load state such as a non-operating state or a standby state is desired.

Several methods are known for classifying switching regulators. For example, there are methods divided into a voltage mode type and a current mode type, and it is known that the current mode type is excellent in responsiveness.

Patent Document 1 relates to the present applicant, and in particular, when a circuit device of a portable device is turned off and enters a light load or no load state, the switching power supply device capable of operating the switching power supply device with high efficiency and a portable device. Disclosed is a switching regulator that provides a device and employs a current mode. The first embodiment suggests a configuration in which a voltage source that applies an offset voltage of, for example, 20 mV to a voltage value corresponding to a current value flowing through the inductor is connected to the inverting input terminal of the comparator. The second embodiment shows a configuration in which a voltage source that provides an offset voltage that is switched according to the output of the comparator is connected to the inverting input terminal of the comparator. The third embodiment suggests a configuration in which an offset voltage and a slope compensation voltage are further added to the voltage corresponding to the current flowing through the inductor at the inverting input terminal of the comparator.

Patent Document 2 discloses a current mode step-down DC-DC converter, which includes a slope compensation circuit and an offset circuit to stabilize the output voltage. Since the subharmonic oscillation does not occur when the on-duty is 50% or less, the slope compensation circuit does not perform the slope compensation. However, when the on-duty is 50% or more, the slope compensation is performed to prevent the subharmonic oscillation. The offset circuit is a circuit that outputs an offset current corresponding to the on-duty. The offset current is converted into a voltage by a resistance element and used as an offset voltage.

Patent Document 3 discloses a current detection circuit and a current mode switching regulator. In particular, the current detection circuit is entirely generated by CMOS, and the process can be simplified and the chip size can be reduced.

FIG. 11 shows a step-down switching regulator that has been studied in reaching the present invention. The switching regulator 1100 includes a switching transistor M1, an inductor L1, a capacitor C1, and a rectifying element M2D1. In addition, although the synchronous rectification transistor M2 and the diode D1 are shown as the rectifying element M2D1, any one of them is adopted. That is, when the synchronous rectification transistor M2 is employed, a synchronous rectification type switching regulator is configured, and when the diode D1 is selected, a diode rectification type switching regulator that is an asynchronous rectification type is configured.

The switching regulator 1100 further includes an error amplifier 110A, a comparator 120, a slope circuit 130, an oscillation circuit 140, a control circuit 150A, a current detection circuit 160, and a first offset circuit 170a.

FIG. 12 is a diagram showing the direction of the current flowing through the switching transistor M1 when the switching regulator 1100 shown in FIG. 11 is used, and particularly shows the case where the synchronous rectification transistor M2 in the rectifying element M2D1 is employed. The switching transistor M1 and the synchronous rectification transistor M2 are alternately turned on and off over time.

FIG. 12A shows the path of the load current If1 when the switching transistor M1 is on and the synchronous rectification transistor M2 is off, that is, in a normal state. FIG. 12B shows a state deviating from a normal state at a light load, that is, a defective state.

As shown in FIG. 12A, when the switching transistor M1 and the synchronous rectification transistor M2 are operating normally, the input voltage Vin is input to one end of the inductor L1 via the switching transistor M1. As a result, the load current If1 flows through the inductor L1. That is, when the switching transistor M1 is on in a normal state, the load current If1 flows in the order of the input voltage Vin → the switching transistor M1 → the inductor L1 → the capacitor C1. As a result, energy is stored in the inductor L1 and the capacitor C1, and an output voltage Vout is generated at one end of the capacitor C1, that is, the output terminal OUT.

FIG. 12B schematically shows the case where the switching transistor M1 is in the on state and the synchronous rectification transistor M2 is in the off state, as in FIG. However, in the PWM switching regulator, the switching transistor M1 cannot be driven sufficiently when the load is light or no load. Therefore, the load current Ir1 deviates from the normal state shown in FIG. Follow the current path. That is, when the switching regulator 1100 is lightly loaded, the switching transistor M1 cannot be sufficiently turned on, and the energy accumulated in the inductor L1 and the capacitor C1 is the load current Ir1, and the capacitor C1 → the inductor L1 → the switching transistor M1 → input. It flows in the path of the voltage Vin and follows the current path opposite to the normal current path. Since these conditions deviate from normal, some measures must be taken.

FIG. 13 shows a state where the on / off operation of the transistor is reversed from FIG. That is, the synchronous rectification transistor M2 is on and the switching transistor M1 is off. In the switching regulator 1100, as described above, the switching transistor M1 and the synchronous rectification transistor M2 are alternately turned on and off over time, and in FIG. 13A, the current flowing through the synchronous rectification transistor M2 is normal. FIG. 13B shows a state deviating from the normal state at a light load.

In FIG. 13A, since the synchronous rectification transistor M2 is in the on state and the switching transistor M1 is in the off state, the load current If2 flows through the inductor L1 from the ground potential GND side through the synchronous rectification transistor M2. . That is, the load current If2 flows through the path of the ground potential GND → the synchronous rectification transistor M2 → the inductor L1 → the capacitor C1. As a result, energy is stored in the inductor L1 and the capacitor C1, and an output voltage Vout is generated at one end of the capacitor C1, that is, the output terminal OUT.

FIG. 13A shows a case where a drive signal S2 sufficient to drive the synchronous rectification transistor M2 is supplied to the gate. That is, this is a case where the drive signal S2 having a pulse width sufficient to drive the synchronous rectification transistor M2 is supplied to the synchronous rectification transistor M2.

In FIG. 13B, the synchronous rectification transistor M2 is in the on state and the switching transistor M1 is in the off state, as in FIG. However, in the PWM switching regulator, the duty of the drive signals S1 and S2 supplied to the gates of the switching transistor M1 and the synchronous rectification transistor M2 changes according to the load weight. When the load becomes lighter, the duty of the PWM signal becomes smaller, and the synchronous rectification transistor M2 cannot be driven sufficiently. Therefore, the load current Ir2 deviates from the normal state shown in FIG. Will be followed. That is, when the switching regulator 1100 is lightly loaded, the pulse width of the PWM signal supplied to the synchronous rectification transistor M2 is small and cannot be turned on sufficiently, and the energy accumulated in the inductor L1 and the capacitor C1 is not loaded. The current Ir2 flows through a path of the capacitor C1, the inductor L1, the synchronous rectification transistor M2, and the ground potential GND, and follows a current path opposite to the normal current path. Since these conditions deviate from normal, some measures must be taken.

As described above with reference to FIGS. 12 and 13, in the case of a light load or no load, both the switching transistor M1 and the synchronous rectification transistor M2 have a current flowing in a path opposite to a normal current path. There arises a problem that normal PWM control cannot be executed.

14A to 14D show timing charts of the operation of the switching regulator 1100, particularly at a light load.

FIG. 14A shows the clock signal CLK output from the oscillation circuit 140, and the frequency is selected in the range of 50 KHz to 6 MHz, for example. The clock signal CLK is input to the slope circuit 130 and the control circuit 150A, and the control circuit 150A is set at a timing when the clock signal CLK is set to the high level.

FIG. 14B shows a waveform of the slope voltage Vsl. The slope voltage Vsl is generated by the slope circuit 130. For convenience of explanation, explanation of the current component and voltage component generated by the current detection circuit 160 is omitted. Here, when the on-resistance Ron1 of the switching transistor M1 and the load current Ir1 flowing from the switching output terminal SW toward the input voltage Vin, the slope voltage Vsl is the moment when the switching transistor M1 is turned on, that is, at times t1, t3, and t5. There arises a problem that the lifting voltage Vm (= Ron1 × Ir1) is lifted. In FIG. 14B, the error output voltage Ve is illustrated together with the slope voltage Vsl, and the lower limit value of the slope voltage Vsl is controlled to be substantially equal to the error output voltage Ve.

FIG. 14C shows the error output voltage Ve output to the output side of the error amplifier 110. The error output voltage Ve is given to the inverting input terminal (−) of the comparator 120. The error output voltage Ve is output by the error amplifier 110 with the feedback voltage Vfb being compared with the reference voltage Vref and having a magnitude corresponding to the comparison result.

The comparator 120 compares the error output voltage Ve and the slope voltage Vsl. When the slope voltage Vsl becomes smaller than the error output voltage Ve, a high level pulse signal Spw is output and input to the reset terminal R of the control circuit 150A. And act to reset.

FIG. 14D shows the switching voltage Vsw1 generated at the switching output terminal SW1. The switching voltage Vsw1 is generated so as to be at a high level when the switching transistor M1 is turned on and to be at a low level when the switching transistor M1 is turned off. The time during which the switching voltage Vsw1 is at the high level corresponds to the so-called PWM control on-duty, and the on-duty is controlled by the slope voltage Vsl and the error output voltage Ve.

As described above, in the light load state, the slope voltage Vsl deviates from the original normal size and shape due to the influence of the load currents Ir1 and Ir2. In such a deviated state, for example, the time until the slope voltage Vsl drops to the level of the error output voltage Ve becomes longer, and it becomes difficult to sufficiently reduce the output pulse width, that is, the pulse width of the switching voltage Vsw1. There is a problem that power is lost.

WO2005 / 079910 JP 2009-303360 A JP 2008-206238 A

The switching regulator of the present invention is similar to the technical idea disclosed in Patent Documents 1 to 3 above. That is, the present invention provides a switching regulator that can improve the efficiency at light load and no load. Specifically, an object is to suppress the generation of a so-called lift voltage Vm that occurs when a reverse current flows through the switching transistor.

In the present invention, the “slope circuit” is defined as a circuit that generates a triangular or sawtooth-shaped inclined voltage prepared to be input to one side of at least two input terminals of a comparator. Alternatively, “slope voltage” refers to a voltage generated by the slope circuit. The “slope voltage” is defined as a voltage that has a triangular shape or a saw-tooth shape and changes in voltage magnitude at least in part of the passage of time. The “offset circuit” is broadly defined as a circuit for adjusting or controlling a difference input voltage between two input terminals of the comparator. In a narrow sense, it is defined as a circuit that sets or adjusts and controls the DC bias voltage of the slope voltage. The “offset voltage” is a voltage generated by the offset circuit and is defined as a voltage for adjusting and controlling the DC bias voltage of the slope voltage.

The switching regulator of the present invention has the following configuration requirements.
(A) A switching transistor that is supplied with an input voltage and performs an on / off switching operation (b) A control circuit that performs on / off control of the switching transistor (c) An inductor that is supplied with a switching voltage extracted from the switching transistor and is supplied with a current ( d) Capacitor connected in series with inductor (e) Voltage dividing resistor for dividing output voltage taken out from series connection point of inductor and capacitor (f) Feedback voltage generated by voltage dividing resistor and reference voltage are input An error amplifier that outputs a voltage corresponding to the voltage difference between the two (g) An error output voltage and a slope voltage output from the error amplifier are input, and a pulse signal having a pulse width corresponding to the voltage difference between the two is output. The comparator (h) switch that supplies the output pulse signal to the control circuit First offset circuit and the second offset circuit for setting the average voltage of-loop voltage

  Furthermore, the switching regulator of the present invention sets the DC bias voltage of the slope voltage (Vsl) by combining the on / off operations of the first offset circuit (170a) and the second offset circuit (170b).

  Furthermore, in the switching regulator of the present invention, the second offset circuit (170b) has an offset switch (172), and the switching regulator (100) has the first offset circuit (170a) in an on state when the offset switch (172) is off. When the offset switch (172) is turned on, both the first offset circuit (170a) and the second offset circuit (170b) are placed in the on state.

  Furthermore, in the switching regulator of the present invention, the first offset circuit (170a) includes an offset resistor (R4) and a first constant current circuit (CC1), and the second offset circuit (170b) includes an offset resistor (R4) and a second resistor. It is constituted by a constant current circuit (CC2). The switching regulator according to claim 4.

  Furthermore, in the switching regulator according to the present invention, the offset switch is responsive to the switching voltage.

Further, in the switching regulator according to the present invention, the offset switch is responsive to an output voltage taken from the comparator.

According to another aspect of the present invention, there is provided a switching regulator control method comprising: a step in which a user intends to use the device; a step in which the user turns on the power to the device; a step in which the enable means is turned on; Selecting one of the timings, and switching the predetermined timing when the power of the device is turned off, and measuring time elapsed after switching A step of turning off the enable means when a predetermined time has passed, a step of turning on the power again without passing the predetermined time, a step of detecting that the power is turned on again,
Among the predetermined timings, the initial timing is switched.

  The switching regulator with the above configuration increases the duty by providing an offset voltage between the two inputs of the comparator that executes PWM control at light load or when the duty of the PWM signal becomes narrow. The efficiency of the switching regulator can be improved.

It is a circuit diagram which shows the basic concept of the switching regulator concerning this invention. It is a circuit diagram showing one embodiment of a switching regulator concerning the present invention. It is a circuit diagram which shows the offset circuit concerning this invention, and its peripheral circuit. It is a timing chart for demonstrating operation | movement of the switching regulator of this invention. It is a circuit diagram for demonstrating the control circuit concerning this invention. It is a timing chart for demonstrating the control circuit of this invention. It is a timing chart for demonstrating the standby mode and normal mode of this invention. 3 is a timing chart prepared for explaining a normal mode of the switching regulator according to the present invention. It is the flowchart prepared in order to demonstrate mode selection of the switching regulator concerning this invention. It is a flowchart for demonstrating the control method of the switching regulator concerning this invention. It is a circuit diagram which shows the basic concept of the conventional switching regulator. In the conventional switching regulator, it is the schematic diagram prepared in order to demonstrate the electric current which flows into a switching transistor. In the conventional switching regulator, it is the schematic diagram prepared in order to demonstrate the electric current which flows into the transistor for synchronous rectification. It is the timing chart prepared in order to demonstrate the circuit operation of the conventional switching regulator.

FIG. 1 is a circuit diagram for explaining the basic concept of a switching regulator according to the present invention. The switching regulator 100 shown in FIG. 1 differs from the switching regulator 1100 shown in FIG. 11 in having a second offset circuit 170b. The other circuits are almost the same as in FIG. Although the description partially overlaps that of FIG. 11, only FIG. 1 will be described.

The switching regulator 100 includes a switching transistor M1, an inductor L1, a capacitor C1, and a rectifying element M2D1. A synchronous rectifying transistor M2 and a diode D1 are shown as the rectifying element M2D1. In an actual switching regulator, either the synchronous rectification transistor M2 or the diode D1 is connected to the switching transistor M1. That is, when the synchronous rectification transistor M2 is employed, a synchronous rectification type switching regulator is configured, and when the diode D1 is selected, a diode rectification type switching regulator is configured.

The switching regulator 100 further includes a smoothing circuit in which an inductor L1 and a capacitor C1 are connected in series. Further, the error amplifier 110, the comparator 120, the slope circuit 130, the oscillation circuit 140, the control circuit 150, the current detection circuit 160, the first An offset circuit 170a and a second offset circuit 170b are included.

The first main electrode and the second main electrode of the switching transistor M1 are connected to the first power supply terminal VIN and the switching output terminal SW, respectively. The drive signal S1 is input to the control electrode of the switching transistor M1, so that the switching transistor M1 is turned on / off. Perform the action. A series connection body of the inductor L1 and the capacitor C1 is connected between the switching output terminal SW and the ground potential GND. That is, the switching transistor M1, the inductor L1, and the capacitor C1 are connected in series between the first power supply terminal VIN and the ground potential GND. The switching voltage Vsw derived to the switching output terminal SW is supplied to the series connection body of the inductor L1 and the capacitor C1, so that the output voltage Vout is generated at the output terminal VOUT.

An output voltage Vout is taken out as an output terminal OUT at a common connection point between the inductor L1 and the capacitor C1, and the output voltage Vout is supplied to a load connected to a subsequent stage of the output terminal OUT.

The error amplifier 110 compares the output voltage Vout derived to the output terminal OUT with the reference voltage Vref, and outputs an error output voltage Ve according to the comparison. The output voltage Vout is divided by two voltage dividing resistors R1 and R2, and a feedback voltage Vfb is generated at these common connection points. The feedback voltage Vfb is input to the inverting input terminal (−) of the error amplifier 110. The reference voltage vref can be generated by, for example, a band gap type constant voltage circuit.

The comparator 120 compares the error output voltage Ve with the signal output from the adder circuit 125, and outputs a signal corresponding to the comparison result as a pulse signal Spw. The error output voltage Ve and the signal output from the adder circuit 125 are input to the inverting input terminal (−) and the non-inverting input terminal (+) of the comparator 120, respectively. In the comparator 120, the error output voltage Ve input to the inverting input terminal (−), the slope voltage Vsl generated by the slope circuit 130, and the detection voltage Vcs generated by the current detection circuit 160 are added, and the addition is performed. When the overall voltage is higher than the error output voltage Ve, the low level is output to the output side of the comparator 120 as the pulse signal Spw when the high level is low.

The slope circuit 130 generates a triangular or sawtooth voltage in synchronization with the clock signal CLK, that is, a slope voltage. The slope voltage Vsl is input to the non-inverting input terminal (+) of the comparator 120, is compared with the error output voltage Ve, and is prepared to generate a pulse signal Spw having a pulse width corresponding to the difference between the two.

The oscillation circuit 140 is prepared for generating the slope voltage Vsl in the slope circuit 130, and is prepared for generating a set signal for setting the control circuit 150.

The control circuit 150 is prepared for driving and controlling the subsequent switching transistor M1, and includes a flip-flop, a logic unit, and a driver as will be described later.

The current detection circuit 160 is prepared for converting a current flowing through the switching transistor M1 or the inductor L1 into a voltage. The reason why the switching regulator 100 is called a current mode type is that it has a current detection circuit 160. Note that the current detection circuit 160 is not necessary when a voltage mode type switching regulator is configured instead of the current mode type.

The first offset circuit 170a includes a second power supply terminal PVIN, an offset resistor R4, and a first constant current circuit CC1 in order to give a predetermined DC bias voltage to the non-inverting input terminal (+) of the comparator 120, that is, the node N1. Yes. The first terminal of the offset resistor R4 is connected to the second power supply terminal PVIN, and the second terminal is connected to the non-inverting input terminal (+) of the comparator 120. The second terminal of the offset resistor R4 is also connected to the first terminal of the first constant current circuit CC1. The second terminal of the first constant current circuit CC1 is connected to the ground potential GND. When the input voltage supplied to the second power supply terminal PVIN is Vin, the resistance value of the offset resistor R4 is r4, and the DC bias voltage VN1 appearing at the node N1 is obtained, VN1 = Vin−r4 × ICC1.

  Similarly to the first offset circuit 170a, the second offset circuit 170b is also prepared for setting the non-inverting input terminal (+) of the comparator 120, that is, the DC bias voltage VN1 of the node N1. The DC bias voltage provided by the second offset circuit 170b is generated by the power supply voltage input to the second power supply terminal PVIN, the offset resistor R4, the second constant current circuit CC2, and the offset switch 172. The second offset circuit 170b is significantly different from the first offset circuit 170a in that it includes an offset switch 172. The offset switch 172 is controlled by the mode switching circuit 190. The DC bias voltage provided by the second offset circuit 170b responds to on / off of the mode switching circuit 190, and has a pulse shape, for example.

The offset circuit 170b is prepared for setting a difference voltage with respect to the DC bias voltage set by the offset circuit 170a, that is, for setting the offset voltage Vof. The offset voltage Vof is given at the timing when the pulse signal Spw or the drive signal S1 is turned on or off. By this function, that is, an offset voltage corresponding to the on-duty or off-duty of the PWM signal can be applied between the two input terminals of the comparator 120.

In summary, the structural characteristics of the switching regulator 100 shown in FIG. 1 are extracted from the switching transistor M1 that is supplied with the input voltage and performs on / off switching operation, the control circuit 150 that performs on / off control of the switching transistor M1, and the switching transistor M1. Inductor L1 to which current is supplied upon receiving the switching voltage Vsw, the capacitor C1 connected in series with the inductor L1, and the series connection point of the inductor L1 and capacitor C1, that is, the output voltage Vout taken out from the output terminal OUT Voltage divider resistors R1 and R2, a feedback voltage Vfb generated by the voltage divider resistors R1 and R2, and a reference voltage Vref, and an error amplifier 110 that outputs a voltage corresponding to the voltage difference between the two, and an error Output from amplifier 110 Error output voltage Ve and triangular or sawtooth slope voltage Vsl are input, a pulse signal Spw having a pulse width corresponding to the voltage difference between the two is output, and the output pulse signal Spw is output to the control circuit 150. A comparator 120 to be supplied and a first offset circuit 170a and a second offset circuit 170b for setting a DC bias voltage of the slope voltage Vsl are provided.

The addition circuit 125 adds the slope voltage output from the slope circuit 130 and the detection voltage Vcs output from the current detection circuit 160. Note that the adder circuit 125 is not necessarily essential for carrying out the present invention. When a voltage mode type switching regulator is configured without preparing the adder circuit 125, the adder circuit 125 becomes unnecessary.

FIG. 2 shows an embodiment of a switching regulator in which several circuit units are added to the switching regulator 100 shown in FIG. The switching regulator 200 constitutes a current mode type synchronous rectification step-down switching regulator (hereinafter referred to as a switching regulator). The main circuit portion of the switching regulator 200 shown in FIG. 2 can be integrated on the integrated circuit 10. The switching regulator 100 described in FIG. 1 can be formed on the integrated circuit 10 except for the inductor L1, the capacitors C1 and C3, and the microcomputer MPU as shown in FIG.

The integrated circuit 10 includes several external connection terminals. For example, a first power supply terminal VIN, a second power supply terminal PVIN, a switching output terminal SW, a second ground terminal GNDT, a first ground terminal PGNDT, a feedback terminal FB, and an enable terminal EN are prepared.

The input voltage Vin is input to the first power supply terminal VIN and the second power supply terminal PVIN. The first ground terminal GNDT and the second ground terminal PGNDT are set to the ground potential GND. The input voltage Vin input to the first power supply terminal VIN and the second power supply terminal PVIN is a relatively low voltage of 2.7 V to 5.5 V, for example, and the output voltage Vout extracted from the output terminal OUT is higher than the input voltage Vin. For example, it is set to a low range of 1.0 V to 1.8 V, for example. The power supply terminal for supplying the input voltage Vin is divided into two systems of the first power supply terminal VIN and the second power supply terminal PVIN because the circuit system for transmitting a so-called small signal (the first power supply terminal VIN is This is to prevent interference between the high current processing circuit system (in charge of the second power supply terminal PVIN) and particularly the influence of the high current processing circuit system on the small current circuit system. For the same reason, the ground potential GND is also divided into two systems, the first ground terminal GNDT and the second ground terminal PGNDT. When the ground potentials of the first ground terminal GNDT and the second ground terminal PGNDT are used without being distinguished, they are displayed as the ground potential GND.

The switching output terminal SW is connected to, for example, a common connection point between the drain electrode of the switching transistor M1 and the drain electrode of the synchronous rectification transistor M2, and is also connected to the first terminal of the inductor L1. The second terminal of the inductor L1 is connected to the first terminal of the capacitor C1, and the second terminal is connected to the ground potential GND. The ground potential GND to which the second terminal of the capacitor C1 is connected is on the second ground terminal PGNDT side to which the source of the synchronous rectification transistor M2 is connected.

The feedback terminal FB is prepared for feeding back the output voltage Vout to the error amplifier 120. Voltage dividing resistors R1 and R2 are connected in series between the feedback terminal FB and the ground potential GND, and a feedback voltage Vfb is generated at the common connection point. The feedback voltage Vfb is used as an inverting input terminal of the error amplifier 110 ( Input feedback to-). As a result, the feedback voltage Vfb is compared with the reference voltage Vref input to the non-inverting input terminal of the error amplifier 110, and is output as an error output voltage Ve resulting therefrom. In order to set the output voltage Vout output to the output terminal OUT to a predetermined level, the resistance ratio of the voltage dividing resistors R1 and R2 is adjusted.

An enable signal Ven output from a microcomputer MPU prepared separately from the integrated circuit 10 is input to the enable terminal EN, and the operation of the entire integrated circuit 10 is controlled. When the enable terminal EN is in the enabled state, the entire circuit operation built in the integrated circuit 10 is set to the on state, and in the disabled state, the entire operation of the integrated circuit 10 is turned off.

The integrated circuit 10 generates a divided voltage Vfb by dividing the output voltage Vout by dividing a switching transistor M1 made of an N-channel MOS transistor, a synchronous rectification transistor M2 made of the same N-channel MOS transistor, and the output voltage Vout. The piezoelectric resistors R1 and R2 are provided. The switching transistor M1 may be a P-channel MOS transistor. Further, a bipolar transistor may be used instead of the MOS transistor. In addition to the reference voltage generation circuit 110, the switching regulator 100 amplifies a voltage difference between the feedback voltage Vfb and the reference voltage Vref to generate and output an error output voltage Ve, and a slope voltage Sslope. And an output slope circuit 130. It is well known that forming the switching transistor M1 and the synchronous rectification transistor M2 with transistors of different polarities is one of the design matters, and the switching transistor M1 and the synchronous rectification transistor M2 are, for example, MMOS transistors. It can also be configured.

  The integrated circuit 10 further compares the error output voltage Ve generated by the error amplifier 110, the error output current i110, the resistor R3, and the capacitor C2 with the slope voltage Vsl, and has a pulse width corresponding to the error output voltage Ve. It has a comparator 120 that generates and outputs a pulse signal Spw, a slope circuit 130 that generates a slope voltage, an oscillation circuit 140, a control circuit 150, and a current detection circuit 160.

The control circuit 150 generates drive signals S1 and S2, respectively, and drives the switching transistor M1 and the synchronous rectification transistor M2.

The circuit operation of the control circuit 150 is controlled by protection signals SP1 and SP2 output from the protection circuit 180. A more specific circuit configuration of the control circuit 150 will be described later.

The integrated circuit 10 further includes a capacitor C2 and a resistor R3 prepared for phase compensation of the entire switching regulator 200, UVLO (Under
Voltage Lock Out) circuit 176 and protection circuit 180 are provided. The protection circuit 180 includes an overvoltage detection comparator 181, a short protection circuit 182, constant voltage sources 183 and 184, a UVLO / TSD (Thermal Shut Down) protection circuit 185, and a logic circuit 186.

Next, the operation of each circuit unit of the switching regulator 200 will be described with reference to FIG.

The source of the switching transistor M1 is connected to the second power supply terminal PVIN, and the drain is connected to the switching output terminal SW. The input voltage Vin is input to the second power supply terminal PVIN. The drain and source of the synchronous rectification transistor M2 are connected to the switch output terminal SW and the second ground terminal PGNDT, respectively. That is, the switching transistor M1 and the synchronous rectification transistor M2 are connected in series between the second power supply terminal PVIN and the second ground terminal PGNDT.

An inductor L1 and a capacitor C1 are connected in series between the switching output terminal SW and the ground potential GND. An output terminal OUT is provided at a common connection point between the inductor L1 and the capacitor C1, and an output voltage Vout is output. . The voltage dividing resistor R1 and the voltage dividing resistor R2 are connected in series between the feedback terminal FB and the ground potential GND. That is, the series connection body of the voltage dividing resistor is connected in parallel with the capacitor C1. As a result, the output voltage Vout generated at one end of the capacitor C1 is divided and input to the inverting input terminal (−) of the error amplifier 110 as the feedback voltage Vfb.

The first non-inverting input terminal (+) of the error amplifier 110 has a soft start signal 115 from the soft start circuit 115, and the second non-inverting input terminal (+) has a reference voltage from the reference voltage generation circuit 125. Each Vref is given. A feedback voltage Vfb is input to the inverting input terminal (−).

  The soft start circuit 115 is provided for gradually increasing the voltage input to the error amplifier 110 and adding a so-called soft start function for cutting off the reference voltage until the voltage exceeds a predetermined voltage. The function of the soft start circuit 115 prevents the output from the error amplifier 110 from changing suddenly, so that the switching regulator 200 can be stably operated. If the soft start circuit 115 is not prepared, a problem may occur that a spike-like current instantaneously flows in the capacitor C1 connected to the switching output terminal SW at the moment when the input voltage Vin is applied. Therefore, a soft start circuit is generally prepared for this type of switching regulator.

The soft start voltage Vss output from the soft start circuit 115 is a voltage that constantly increases with time since the operation start point of the soft start circuit 115, that is, the switching regulator 200 is started. For example, 1 V / ms is selected.

  A feedback voltage Vfb obtained by dividing the output voltage Vout by the voltage dividing resistors R1 and R2 is input to the inverting input terminal (−) of the error amplifier 110. The error amplifier 110 outputs a voltage based on a potential difference between a lower level voltage among the voltages input to the first and second non-inverting input terminals and a feedback voltage Vfb input to the inverting input terminal. Output.

  The output voltage from the error amplifier 110 is converted into a current and output as an error output current i110. The error output current i110 is not prepared separately from the error amplifier 110, but indicates that the output stage of the error amplifier 110 is output as a current. The error amplified current i110 is voltage-converted by the resistor R3 and the capacitor C2, and is input to the inverting input terminal (−) of the comparator 120 as the error output voltage Ve.

The capacitor C2 and the resistor R3 have a role of so-called I / V converter that converts a current into a voltage, and also have a role of phase compensation. That is, the resistor R3 and the capacitor C3 connected in series also form a phase compensation circuit unit. This phase compensation circuit unit is connected to the output side of the error amplifier 110, the size of the resistor R3 is, for example, 10 kΩ to 800 kΩ, and the size of the capacitor C2 is, for example, 1 to 30 pF.

The phase compensation circuit unit creates a zero cross point for phase compensation and returns the phase by the capacitor C2 and the resistor R3. The zero cross frequency f0 is a point where the phase returns 45 degrees, and is set to 1/5 to 1/20 of the switching frequency. For example, when the switching frequency is 200 kHz, the zero-cross frequency f0 is 40 kHz to 10 kHz. When the switching frequency is 1 MHz, the zero cross frequency f0 is 200 kHz to 50 kHz.

The zero cross frequency f0 can be expressed by f0 = 1 / (2 × π × c2 × r3) where c2 is the capacitance value of the capacitor C2 and r3 is the resistance value of the resistor R3.

The capacitor C3 is connected between the first power supply terminal VIN and the second power supply terminal PVIN and the ground potential GND, and is prepared for removing DC noise superimposed on the input voltage Vin. The input terminal for supplying the input voltage Vin is divided into two systems, the first power supply terminal VIN and the second power supply terminal PVIN. The circuit system for transmitting a small signal (the first power supply terminal VIN is in charge) This is because the circuit system through which a large current flows (in charge of the second power supply terminal PVIN) is DC-isolated. Similarly, two ground potentials are prepared for the external connection terminals GND and PGND for the same reason.

The slope voltage Vsl output from the slope circuit 130 and the detection voltage Vcs generated by the current detection circuit 160 are added to the non-inverting input terminal (+) of the comparator 120, that is, the node N 1 by the addition circuit 125. . Note that only the slope voltage Vsl may be input to the node N1 without preparing the current detection circuit 160 and the addition circuit 125.

The addition circuit 125 adds the slope voltage output from the slope circuit 130 and the detection voltage Vcs output from the current detection circuit 160. Note that the adder circuit 125 is not necessarily essential for carrying out the present invention. When a voltage mode type switching regulator is configured without preparing the adder circuit 125, the adder circuit 125 becomes unnecessary.

The slope circuit 130 is prepared for the comparator 120 to generate a triangular or sawtooth-shaped slope voltage in order to execute PWM control. Details of the slope circuit will be described later.

The comparator 120 performs a voltage comparison between the error output voltage Ve and the slope voltage Vsl. When the slope voltage Vsl becomes smaller than the error output voltage Ve, the comparator 120 outputs a high-level pulse signal Spw and resets the control circuit 150.

  The control circuit 150 includes a flip-flop, a logic unit, and a driver as will be described later. The control circuit 150 generates and outputs reset and set drive signals S1 and S2 based on the pulse signal Spw output from the comparator 120 and the clock signal CLK input from the oscillation circuit 140, respectively.

The on-duty of the switching transistor M1 varies sequentially according to the relative levels of the error output voltage Ve and the slope voltage Vsl. Specifically, as the output voltage Vout is lower than the reference voltage Vref, the on-duty of the switching transistor M1 increases, and as the output voltage Vout approaches the reference voltage Vref, the on-duty of the switching transistor M1 decreases.

The reference voltage generation circuit 175 receives the input voltage Vin from the first power supply terminal VIN, and generates the reference voltage Vref when the enable terminal EN is in an enabled state. The reference voltage Vref is, for example, a voltage selected from 0.3 V to 0.8 V, for example, in order to set a target value of the output voltage Vout. As the reference voltage generation circuit 110, a well-known band gap type constant voltage circuit can be adopted.

The UVLO circuit 176 is a so-called Under Voltage Lock Out, in order to prevent an unexpected malfunction caused by the integrated circuit 10 not operating normally when the input voltage Vin drops below a predetermined level. The circuit function is such that it does not turn on unless a predetermined voltage, for example, 4V is input. The UVLO circuit 176 receives an input voltage Vin and a reference voltage Vref, and realizes the above function by comparing the voltages.

  The protection circuit 180 includes an overvoltage detection comparator 181, a short protection circuit 182, a constant voltage source 183, 184, a UVLO / TSD (Thermal Shut Down) protection circuit 185, and a logic circuit 186. The protection signal SP1, based on the feedback voltage Vfb, is provided. SP2 is generated.

  The protection signal SP1 is an output of the logical sum operation circuit 186, and is a signal that stops the control circuit 150 in response to signals from the overvoltage detection comparator 181 and the UVLO / TSD protection circuit 185.

The feedback voltage Vfb is input to the non-inverting input terminal (+) of the overvoltage detection comparator 181, and a voltage selected from, for example, 110% to 130% of the reference voltage Vref is input from the constant voltage source 183 to the inverting input terminal. Has been. That is, the overvoltage detection comparator 181 has a role of preventing the switching regulator from being deteriorated when an excessive voltage is applied to the feedback voltage Vfb.

  The UVLO / TSD protection circuit 185 is a circuit unit having both a low voltage lockout function and a TSD function, that is, a heat cutoff function, and a signal for low voltage lockout is obtained from the UVLO circuit 176.

  The protection signal SP2 is an output of the short protection circuit 182. The short protection circuit 182 compares the feedback voltage Vfb with the constant voltage source 184 to detect that the circuit has caused an unexpected short circuit and to stop the control circuit 150 and prevent the circuit from deteriorating. Yes. The constant voltage source 184 is, for example, a voltage selected to be 0.6% to 0.8% of the reference voltage.

  The mode switching circuit 190 receives a drive signal S1 that is an input signal to the switching transistor M1, a pulse signal Spw that is an output signal of the comparator 120, and a mode signal Smo. The mode switching circuit 190 selects the drive signal S1 or the pulse signal Spw according to the mode signal Smo, and the output signal is input to the offset switch 172 that constitutes the second offset circuit 170b.

Note that the mode switching circuit 190 selects either the drive signal S1 for driving the switching transistor M1 or the output of the comparator 120, that is, the pulse signal Spw, and controls the offset switch 172 with the selected signal. The drive signal S1 is substantially equivalent to the switching voltage Vsw output from the switching output terminal SW.

  3 shows circuit connections among the comparator 120, the slope circuit 130, the first offset circuit 170a, and the second offset circuit 170b shown in FIGS. 1 and 2, and the slope circuit 130 and the second offset circuit 170b. A specific circuit is shown.

  The error output voltage Ve obtained by converting the error output current i110 output from the error amplifier 110 into a voltage by the resistor R3 and the capacitor C2 is input to the inverting input terminal (−) of the comparator 120.

  The slope voltage Vsl generated by the slope circuit 130 is input to the non-inverting input terminal (+) of the comparator 120 via the adder 125. Strictly speaking, the detection voltage Vcs generated by the current detection circuit 160 is superimposed on the slope voltage Vsl.

The DC bias voltage of the slope voltage Vsl is set by the first slope circuit 170a and the second slope circuit 170b.

The slope circuit 130 includes, for example, an inverter INV1, transistors M31, M32, and M33, a capacitor C4, a resistor R5, and a first current source IC1. The clock signal CLK is input to the input side of the inverter INV1, and the transistor M31 is turned on / off by the output of the inverter INV1. When the transistor M31 is off, the transistor M32 is on, and at this time, the capacitor C4 is charged by the first current source IC1. The charge charged in the capacitor C4 is discharged through the transistor M31 when the transistor M31 is turned on. Thus, by charging or discharging, a triangular or sawtooth voltage having a waveform and a magnitude substantially equal to the slope voltage Vsl is generated in the capacitor C4 in synchronization with the high level and low level of the clock signal.

The triangular or sawtooth voltage generated in the capacitor C4 is output from the transistor M33 and sent to the adder 125. The resistor R5 sets a current that flows through the transistor M33. Note that the circuit unit including the transistor M33 and the resistor R5 also has a circuit function of an adder, and also has a substitute function for the adder 125.

The first offset circuit 170a includes an offset resistor R4 and a first constant current circuit CC1. The first terminal and the second terminal of the offset resistor R4 are connected to the second voltage source PVIN and the first terminal of the first constant current circuit CC1, respectively. The second terminal of the first constant current circuit CC1 is connected to the ground potential GND. That is, the offset resistor R4 and the first constant current circuit CC1 are connected in series between the second power supply terminal PVIN and the ground potential GND.

A common connection point between the offset resistor R4 and the first constant current circuit CC1 is indicated by a node N1, and the node N1 is connected to the non-inverting input terminal (+) of the comparator 120. Therefore, the DC bias voltage set by the first offset circuit 170a is superimposed on the slope voltage Vsl at the node N1, that is, the non-inverting input terminal (+) of the comparator 120.

The second offset circuit 170b includes an offset resistor R4 shared with the first offset circuit 170a and a second constant current circuit CC2. Sharing the offset resistor R4 between the first offset circuit 170a and the second offset circuit 170b is convenient for accurately setting the magnitude of the offset voltage Vof.

The second constant current ICC2 generated by the second constant current circuit CC2 is determined by the second current source IC2 and the transistors M34 and M35. Here, assuming that the magnitudes of the transistors M34 and M35 are the same, the current flowing through the transistor M34, that is, the second constant current ICC2 is the same as the magnitude of the second current source IC2. However, the second current source ICC2 is controlled by the offset switch 172.

The offset switch 172 includes a transistor M36 and an inverter INV2. The inverter INV2 is not an essential component for configuring the offset switch 172, and is provided for setting the on / off timing of the transistor M36. When the transistor M36 is an NMOS transistor, the transistor M36 is turned on when the output of the inverter INV2 transitions from the low level to the high level, and is turned off when the output transitions from the high level to the low level.

As described above, the second constant current ICC2 flowing in the second offset circuit 170b is controlled by the offset switch 172. The second current source IC2 that influences the second constant current ICC2 all flows to the transistor M36 when the transistor M36 is on, and flows to the transistor M35 when the transistor M36 is off. When the second current source IC2 is supplied to the transistor M35, the second constant current ICC2 flows to the transistor M34 via the offset resistor R4.

The first constant current circuit CC1 used for the first offset circuit 170a can be substantially the same as that used for the second constant current circuit CC2. That is, a well-known current mirror circuit can be used.

Here, the DC bias voltage generated at the node N1 set by the first offset circuit 170a and the second offset circuit 170b, that is, the non-inverting input terminal (+) of the comparator 120 is obtained. This is nothing but finding the offset voltage Vof provided by the two offset circuits. Now, the input voltage Vin supplied to the second power supply terminal PVIN, the resistance value r4 of the offset resistor R4, the first constant current ICC1 flowing through the offset resistor R4, and the voltage at the node N1 when the second constant current ICC2 is not flowing. Is V1Na, VN1a = Vin−r4 × ICC1. Next, the voltage VN1b of the node N1 when the second constant current ICC2 is flowing is obtained. At this time, since the first constant current ICC1 also flows, the voltage VN1b = Vin−r4 × (ICC1 + ICC2). If the difference between the voltage VN1a and the voltage VN1b is defined as an offset voltage Vof, it can be expressed by an offset voltage Vof = V1Na−V1Nb = r4 × ICC2. That is, the offset voltage Vof is the product of the offset resistor R4 and the second constant current ICC2.

In summary, according to the present invention, the offset resistor R4 is shared by both the first offset circuit 170a and the second offset circuit 170b, and the first offset circuit 170a and the second offset circuit are configured by substantially the same circuit. Further, by providing both of them close to the integrated circuit 10, it is possible to generate the offset voltage Vof with extremely high accuracy.

The offset switch 172 is controlled by the mode switching circuit 190. The mode switching circuit 190 includes inverters 191, 193, logical product operation circuits 192, 194, and a logical sum circuit 195. A signal S191 that is opposite in phase to the drive signal S1 via the inverter 191 is input to the first input terminal of the AND circuit 192, and the mode signal Smo is input to the second input terminal of the AND circuit 192. As a result, the logical sum operation circuit 192 outputs a signal S192. Further, the mode signal Smo is input to the first input terminal of the AND operation circuit 194 via the inverter 193, and the pulse signal Spw is input to the second input terminal of the AND operation circuit 194. As a result, the AND operation The circuit 194 outputs a signal S194. Further, the signal S192 is input to the first input terminal of the OR circuit 195, and the signal S194 is input to the second input terminal thereof. As a result, the OR circuit 195 outputs the signal S195. In other words, the drive signal S1, the mode signal Smo, and the pulse signal Spw are input to the mode switching circuit 190, and the switching signal S195 is output. The switching signal S195 controls the offset switch 172.

(Normal mode, under heavy load)
FIG. 4 is a timing chart of each signal when the switching regulator 100 according to the present invention is used in a normal mode, that is, as a power source for controlling an electronic device such as a radio or a monitor.

FIG. 4A shows the clock signal CLK output from the oscillation circuit 150 shown in FIG. In the switching regulator 100, the flip-flop 151 incorporated in the control circuit 150 is set at the rising timing of the clock signal CLK, that is, at time t1. As a result, when the drive signals S1 and S2 become low level, the switching transistor M1 is turned on and the synchronous rectification transistor M2 is turned off. At this time, the switching voltage Vsw is in a high level state.

FIG. 4B shows the slope voltage Vsl, and FIG. 4C shows the error output voltage Ve. The voltage value of the slope voltage Vsl is a value determined by the input voltage Vin input from the second power supply terminal PVIN, the offset resistor R4, and the current I2 as an initial value until time t1. Subsequently, the clock signal CLK output from the oscillation circuit 150 is simultaneously input to the slope circuit 130 at time t1, and the slope voltage Vsl is changed from the low level to the high level of the clock signal CLK of the oscillation circuit 150. From the timing when this is detected, the voltage falls linearly while the switching transistor M1 is on.

FIG. 4D shows a pulse signal Spw that is a PWM signal. An error output voltage Ve corresponding to the output voltage Vout is output from the error amplifier 110. The comparator 120 compares the slope voltage Vsl with the error output voltage Ve and outputs a pulse signal Spw. The pulse signal Spw outputs a high level when Vsl <Ve, that is, at time t2, and resets the flip-flop 151 incorporated in the control circuit 150. As a result, when the drive signals S1 and S2 become high level, the switching transistor M1 is turned off and the synchronous rectification transistor M2 is turned on. At this time, as shown in FIG. 4E, the switching voltage Vsw is at a low level. In the present invention, the pulse signal Spw is used to generate an offset voltage, as will be described later.

At the same time, the slope circuit 130 at time t2 recognizes the rise of the pulse signal Spw and returns the slope voltage Vsl that has been linearly lowered to the initial value. Thereby, one cycle of operation is completed. The switching regulators 100 and 200 adjust the output voltage Vout by repeating this operation at times t3 to t4 and t5 to t6.

(Normal mode / light load)
When it is desired to reduce the output voltage Vout of the switching regulator 100 at light load, that is, when it is desired to reduce the pulse width, the output voltage Vout is reduced by reducing the on-duty of the switching transistor M1, that is, by reducing the on-duty. adjust. The light load in the present invention refers to a case where the current flowing through the load at the supply destination is, for example, several hundred mA or less.

When the switching regulator 100 is used as a power source for control of an electronic device such as a radio or a monitor, switching noise of a specific frequency (including harmonic components) generated by switching between the switching transistor M1 and the synchronous rectification transistor M2 is output voltage Vout. May affect the output of the radio or monitor that supplies. For example, the noise may be mixed with the output sound of the radio, or the monitor screen may flicker.

In such a case, the frequency when using the switching regulator 100 may be set to a value different from the output of the radio or monitor that supplies the output voltage Vout. For example, in the case of an AM radio, the switching regulator 100 may be operated at a frequency different from the reception band of the AM radio and the frequency change may be suppressed as much as possible. In other words, in order to prevent such superposition of switching noise, the operating frequency of the switching regulator 100 may be kept at a frequency that does not affect the device that supplies the output voltage Vout. For this reason, even when the output is reduced at light load, it is desirable not to lower the operating frequency by thinning the operating frequency, for example. For this purpose, it is necessary to make the pulse width as narrow as possible and continue to generate pulses.

When the supply destination of the output voltage Vout is a light load, there is a problem that the slope voltage Vsl is raised to the high potential side due to the backflow current as described in the description of the conventional example. As a result, the pulse width cannot be reduced, and the duty ratio cannot be set to a desired value. Then, the output voltage Vout outputs a voltage higher than the desired voltage. Subsequently, as a result of the feedback voltage Vfb entering the error amplifier 110, the error output voltage Ve is set so that the reset signal is output later. Generate. For this reason, a switching frequency will reduce. That is, there is a problem that the switching frequency changes because the pulse width cannot be reduced by the backflow current Ir1.

FIG. 5 shows an internal circuit of the control circuit 150 and a peripheral circuit portion. The control circuit 150 includes a flip-flop 151, a logic unit 152, and drivers 153 and 154. The clock signal CLK is input to the set terminal S of the flip-flop 151. When the clock signal CLK becomes high level, the flip-flop 151 is set. The output of the OR circuit 155 is input to the reset terminal R. Protection signals SP1 and SP2 are input to the logical sum circuit 155. When either of these signals is at a high level, the output of the logical sum circuit 155 is at a high level, and the flip-flop 151 is reset at the high level. The protection signals SP1 and SP2 are output from the protection circuit 180.

  The logic unit 152 and the drivers 153 and 154 in this embodiment generate drive signals S1 and S2 based on the output signal of the flip-flop 151, and the switching transistor M1 and the synchronous rectification transistor M2 are alternately turned on and off. Control. The logic unit 152 can be configured by combining an AND circuit, an OR circuit, a flip-flop, a level shifter, and the like. The logic unit 152 configured in this way performs a protection operation of the switching regulator in response to the protection signals SP1 and SP2. More specifically, for example, when a high level is input to the protection signal SP1 or the protection signal SP2, for example, both the switching transistor M1 and the synchronous rectification transistor M2 are turned off and the switching transistor M1 is turned on as a circuit protection operation. And control to turn off the synchronous rectification transistor M2. These protection operations may be determined according to the design specifications of the switching regulators 100 and 200. That is, the output current Vout can be quickly reduced through the synchronous rectification transistor M2 by controlling the switching transistor M1 to be turned on and the synchronous rectification transistor to be turned off. It is possible to prevent the deterioration of the Myco MPU and the inductor L1. In addition, if the switching transistor M1 and the synchronous rectification transistor M2 are both turned off, the synchronous rectification transistor M2 can be prevented from being destroyed by the backflow current.

FIG. 6 schematically shows various signals input to and output from the control circuit 150 shown in FIG. FIG. 5A shows a set signal, that is, a clock signal SS inputted to the set terminal S of the flip-flop 151. FIG. 5B shows the reset signal SR input to the reset terminal R of the flip-flop 151. FIG. 5C and FIG. 5D show the protection signals SP1 and SP2, respectively. The protection signals SP1 and SP2 are overvoltage protection or abnormality signals output from the protection circuit 180. FIG. 5E shows an output signal SQ output from the output terminal Q of the flip-flop 151. The output signal SQ changes from the low level to the high level at the rising edge of the clock signal SS, and changes from the high level to the low level at the rising edge of the reset signal SR. When the protection signals SP1 and SP2 are input, the output signal SQ transitions from a high level to a low level at the rising edge. 6F shows the drive signal S1 output from the driver 153, and FIG. 6G shows the drive signal S2 output from the driver 154. The drive signals S1 and S2 drive the switching transistor M1 and the synchronous rectification transistor M2, respectively. When both the switching transistor M1 and the synchronous rectification transistor M2 are N-channel MOS transistors or NPN bipolar transistors, the polarities of the drive signals S1 and S2 are set to be inverted.

FIG. 7 is a timing chart showing signals in the mode switching circuit 190. 7 is a timing chart prepared for explaining a difference between signals appearing at main nodes when the standby mode, that is, the pulse signal Spw is selected and when the normal mode, that is, the drive signal S1 is selected. From time t1 to t4, the standby mode is shown, and from time t5 to t8 is the normal mode.

FIG. 7A shows the clock signal CLK output from the oscillation circuit 140. Since they are not directly related to the standby mode and the normal mode, the signals of both are the same, and have two values of high level and low level.

FIG. 7B shows the pulse signal Spw output from the comparator 120. Since these signals are also output from locations that do not depend on the difference between the standby mode and the normal mode, the signals of both are the same and have two values of high level and low level.

FIG. 7C shows a drive signal S1 for driving the switching transistor M1. Since these signals are also output from locations that do not depend on the difference between the standby mode and the normal mode, the signals of both are the same and have two values of high level and low level.

FIG. 7D shows a signal S191 output to the inverter 191 shown in FIG. Since the signal S191 is obtained by inverting the polarity of the drive signal S1, they are equal regardless of the difference between the standby mode and the normal mode.

FIG. 7E shows a mode switching signal Smo input to the mode switching circuit 190 shown in FIG. Since the mode switching signal Smo is for switching between the standby mode and the normal mode, the signal levels of the two differ naturally. In one embodiment of the present invention, the mode signal Smo in the standby mode is set at a low level, and is set at a high level in the normal mode.

The mode signal Smo is a signal given from, for example, a microcomputer MPU that controls the switching regulator 100, and the device to which the switching regulator 100 supplies power is in a use state, that is, a heavy load state, or a light load state. This is a signal for selecting two states of high level or low level depending on whether the load is light. The microcomputer MPU senses the power supply state of the device to which the switching regulator 100 supplies power, and sends a high level or a low level to the switching regulator 100 as the mode signal Smo. The mode signal Smo may be provided with a microcomputer MPU inside the switching regulator 100, or may be configured to provide a signal to a control terminal, for example.

FIG. 7F shows a signal S192 that is the output of the AND circuit 192 shown in FIG. Since the signal S192 is an output obtained by performing an AND operation on the signal S191 and the mode signal Smo, the low level is maintained for the entire period, that is, from time t1 to time t4 in the standby mode. On the other hand, in the normal mode, the mode signal Smo is at the high level for the entire period from time t5 to time t8, so that the result is the same as the signal 191.

FIG. 7G shows a signal S194 that is the output of the AND circuit 194 shown in FIG. The signal S194 is an output obtained by ANDing the pulse signal Spw and the inverted signal of the mode signal Smo. Therefore, in the standby mode, the signal S194 is the same as the pulse signal Spw shown in FIG. 7B, and in the normal mode, the low level is maintained for the entire period, that is, from time t5 to time t8.

FIG. 7H shows a signal S195 that is the output of the OR circuit 195 shown in FIG. The signal S195 is a signal obtained by performing an OR operation on the signal S192 and the signal S194. Therefore, since either the signal S192 or the signal S194 is output, the signal S195 is the same as the signal S194 in the standby mode, and the signal S195 is the same as the signal S192 in the normal mode.

The circuit operation of the mode switching circuit 190 is summarized as follows. That is, when the mode signal Smo is at a low level, the pulse signal Spw is selected, and the mode switching circuit 190 outputs a signal in phase with the pulse signal Spw. When the mode signal Smo is at a high level, the drive signal S1 is selected, and the mode switching circuit 190 outputs a signal having a phase opposite to that of the drive signal S1. Note that the switching voltage Vsw may be used instead of the drive signal S1. The drive signal S1 appears at the gate of the switching transistor M1 and the switching voltage Vsw appears approximately at the source, with the only difference being the source of the switching transistor M1. The reason why the pulse signal Spw or the drive signal S1 is selected by the mode signal Smo is because both are related to the on / off operation of the switching transistor M1, and both are suitable for generating an offset voltage. It is.

The signal S195 is determined by the method as described above, the offset switch 172 is turned on / off in response to the high level or low level of the signal S195, and the second offset circuit 170b is operated by the on / off of the offset switch 172, so that the offset voltage Vof As a result, the offset value between the slope voltage Vsl and the error output voltage Ve can be changed at the timing when the signal S195 becomes high level.

  FIG. 8 is a diagram schematically showing the state of operation at such a light load. For example, when the load is light, the current flowing through the load at the supply destination is, for example, several hundred mA or less. FIG. 8 will be used to clarify how the switching regulator 100 according to the present invention solves the above-described problem.

FIG. 8A shows the clock signal CLK output from the oscillation circuit 140 shown in FIG. In the switching regulator 100, the flip-flop 151 incorporated in the control circuit 150 is set at the rising timing of the clock signal CLK, that is, at time t1. As a result, when the drive signals S1 and S2 become low level, the switching transistor M1 is turned on and the synchronous rectification transistor M2 is turned off. At this time, the switching voltage Vsw is in a high level state.

FIG. 8B shows the slope voltage Vsl, FIG. 8C shows the offset voltage Vof, and FIG. 8D shows the error output voltage Ve.

The offset voltage Vof shown in FIG. 8C is set based on the magnitude relationship between the slope voltage Vsl and the error output voltage Ve shown in FIG. That is, the transition from the high level to the low level occurs at the timing when the slope voltage Vsl changes, and the transition from the low level to the high level occurs at the timing when the slope voltage Vsl becomes lower than the error output voltage Ve.

The voltage value of the slope voltage Vsl is a value determined by the offset resistor R4 and the first constant current ICC1 as an initial value until time t1. Subsequently, the clock signal CLK output from the oscillation circuit 150 is simultaneously input to the slope circuit 130 at time t1, and the slope voltage Vsl is changed from the low level to the high level of the clock signal CLK of the oscillation circuit 150. From the timing when this is detected, the voltage falls linearly while the switching transistor M1 is on.

FIG. 8E shows an output S191, which is an inverted signal of the drive signal S1 for driving the switching transistor M1. An error output voltage Ve corresponding to the output voltage Vout is output from the error amplifier 110. The comparator 120 compares the slope voltage Vsl with the error output voltage Ve and outputs a pulse signal Spw. When the pulse signal Spw becomes (Vsl <Ve), that is, at time t2, a high level is output, and the flip-flop 161 incorporated in the control circuit 150 is reset. As a result, when the drive signals S1 and S2 become high level, the switching transistor M1 is turned off and the synchronous rectification transistor M2 is turned on. At this time, the switching voltage Vsw is in a low level state (FIG. 8 (f)).

Further, when the switching regulators 100 and 200 are lightly loaded, the mode signal Smo shown in FIG. 7E is selected to be high level as the light load mode. As a result, the signal S191 becomes high level when the drive signal S1 becomes high level, that is, when the switching transistor M1 is turned on. Accordingly, at this timing, that is, at time t1, the output of the slope circuit 130 and the second offset circuit 170b are brought into conduction. That is, the current flowing through the output node of the slope circuit 130 is caused by the conduction of the offset circuit at the timing when the drive signal S1 transitions from the low level to the high level, that is, the timing when the output S194 changes from the low level to the high level. As a result, the offset voltage is added to the slope voltage Vsl.

As a result, as shown at time t1 in FIG. 8, the slope voltage Vsl decreases relative to the error output voltage Ve, so that the output pulse width (pulse width of Vsw) is reduced compared to the conventional case. Power saving operation is possible.

The slope voltage Vslp shown in FIG. 8B is generated when the conventional switching regulator 1100 prepared for comparison is used.

  When the output voltage Vout decreases and the light load state is entered, the error output voltage Ve increases, and the difference between the slope voltage Vsl and the error output voltage Ve decreases. Thereby, since the on-duty of the switching voltage Vsw becomes small, the value of the output voltage Vout can be made small.

As described above, in the switching regulator 100, the switching transistor M1 and the synchronous rectification transistor M2 are repeatedly turned on and off in a complementary manner, and continue to pass current. This is because the current flows in the inductor L1 when the switching transistor M1 is on and the energy is accumulated, and when the switching transistor M1 is subsequently turned off and the synchronous rectification transistor M2 is turned on, the current continues to flow due to the energy accumulated in the inductor L1. It has become.

However, when the load is light, the energy stored in the inductor L1 is small when the switching transistor M1 is on, so the energy stored is small. Therefore, when the subsequent switching transistor M1 is turned off and the synchronous rectification transistor M2 is turned on, on the contrary, a so-called reverse current Ir1 flowing from the capacitor C2 to the ground via the synchronous rectification transistor M2 flows by the voltage accumulated in the capacitor C2. . At this time, energy due to the reverse current Ir1 is accumulated in the inductor L1. Therefore, when the switching transistor M1 is turned on and the synchronous rectification transistor M2 is turned off in the subsequent step, the instantaneous reverse current Iad causes Vsw to instantaneously change. It is higher than the input voltage Vin. That is, the switching voltage Vsw at the moment when the switching transistor M1 is turned on becomes a value that can be expressed by (Vsw = Vin + Ron1 × Ir1). Ron1 is the on-resistance of the switching transistor M1, its magnitude is, for example, 10 to 100 mΩ, and the backflow current Ir1 is, for example, 100 to 1000 mA.

  Since the slope voltage Vsl is generated from the switching voltage Vsw as described above, at the moment when the switching transistor M1 is turned on, that is, at times t1, t3, and t5 in FIG. It will end up. As a result, the time until the slope voltage Vsl decreases to the error output voltage Ve becomes longer, and the time until the pulse width is sufficiently reduced becomes longer.

  In the light load mode of the present invention, the slope voltage Vsl is reduced by the offset voltage Vof at the instant when the switching transistor M1 is turned on, that is, at times t1, t4, and t7 in FIG. Since the width can be quickly reduced, the occurrence of abnormal oscillation due to the switching frequency can be suppressed.

Specifically, when the offset addition operation by the offset circuit is not performed, the pulse width is from time t1 to time t3, that is, pulse width W1, from time t4 to time t6, that is, pulse width W4, and from time t7 to time t8. In other words, when the offset is added, the switching voltage Vsw having the pulse widths W2, W5, and W8 is generated. Therefore, the switching transistor M1 has the pulse widths W3, W6, and W9, respectively. The on-time is shortened and the operating frequency does not change, so that the problem of superimposing switching noise as described above does not occur.

(Standby mode)
When the switching regulator 100 is not used, for example, when the switching regulator 100 is used as a power source for an automobile, the switching regulator 100 consumes as much power as possible when the engine is stopped and the accessory power source is not energized. It is desirable not to. However, if the power supply is completely shut down, there will be a problem that it takes a long time to restart and remote control operation becomes impossible. From this point, it is desirable to continue supplying power for several minutes after the engine is stopped.

  In order to continue supplying power, it is desirable to continue to operate in a power saving state because problems such as a battery rising occur when the current consumption is large. As a result, for example, when the engine is turned off and a convenience store or the like is returned and a few minutes later, the navigation system or DVD can be watched immediately.

  FIG. 9 is a timing chart when the switching regulator 100 according to the present invention is used in the standby mode, that is, the power saving mode. In the standby mode, the mode signal Smo shown in FIG. 7E is at a low level.

FIG. 9A shows the clock signal CLK output from the oscillation circuit 150 shown in FIG. In the switching regulator 100, the flip-flop 151 incorporated in the control circuit 150 is set at the rising timing of the clock signal CLK, that is, at time t1. As a result, control is performed such that the switching transistor M1 is turned on and the synchronous rectification transistor M2 is turned off when the drive signals S1 and S2 become low level. At this time, the switching voltage Vsw is in a high level state.

9B shows the slope voltage Vsl, FIG. 9C shows the offset voltage Vof, and FIG. 9D shows the error output voltage Ve. The voltage value of the slope voltage Vsl is a value determined by the offset resistor R4 and the first constant current ICC1 as an initial value until time t1. Subsequently, the clock signal CLK output from the oscillation circuit 140 is simultaneously input to the slope circuit 130 at time t1, and the slope voltage Vsl is changed from the low level to the high level of the clock signal CLK of the oscillation circuit 140. From the timing when this is detected, the voltage falls linearly while the switching transistor M1 is on.

FIG. 9E shows a pulse signal Spw. An error output voltage Ve corresponding to the output voltage Vout is output from the error amplifier 110. The comparator 120 compares the slope voltage Vsl with the error output voltage Ve and outputs a pulse signal Spw. When the pulse signal Spw becomes (Vsl <Ve), that is, at time t2, a high level is output, and the flip-flop 151 incorporated in the control circuit 150 is reset. As a result, when the drive signals S1 and S2 become high level, the switching transistor M1 is turned off and the synchronous rectification transistor M2 is turned on. At this time, the switching voltage Vsw is in a low level state (FIG. 9 (e)).

Further, in the standby mode, the output node of the slope circuit 130 and the second offset circuit 170b are brought into conduction at the above timing, that is, at time t2 (Vsl <Ve). As described with reference to FIGS. 3 and 7, when the mode signal Smo is at a low level, a signal having a phase opposite to that of the pulse signal Spw is input to the offset switch 172 as the output S195. That is, at the timing when the pulse signal Spw transitions from the high level to the low level, that is, the timing when the signal S195 changes from the low level to the high level, the second offset circuit 170b becomes conductive, and the value of the current flowing through the output node of the slope circuit 130 is as described above. Thus, the offset voltage Vof is added. As a result, as shown at time t2 in FIG. 9, the slope voltage Vsl becomes lower than the error output voltage Ve.

During this time, the pulse signal Spw is maintained at a high level. As a result, the reset signal is always input to the flip-flop 151 of the control circuit 150. As a result, even when the clock signal CLK becomes high level, the control circuit 150 is not set, so that no pulse is generated and no power is consumed.

  As the output voltage Vout gradually decreases, the error output voltage Ve also gradually decreases. The inclination in this case is 1 to 10 mV / ms, for example. During this period, even if the clock signal CLK becomes high level as described above, the switching voltage Vsw does not become high level, that is, no output pulse is generated, so that power is not consumed. The frequency of the clock signal CLK is, for example, about 50 KHz to 6 MHz, the magnitude of the offset voltage added at this time is, for example, 10 to 100 mV, and the falling gradient of the error output voltage Ve is 1 to 10 mV / msec. Therefore, for example, no output is generated for 10 to 100 milliseconds. That is, power consumption is reduced.

  After the elapse of the period, when (Vsl> Ve) is reached at time t11 in FIG. 9, the slope voltage Vsl receives the pulse signal Spw output from the comparator 120 and returns to the initial voltage. In this state, when the clock signal CLK becomes high level, the control circuit 150 is set. As a result, when the drive signals S1 and S2 become low level, the switching transistor M1 is turned on and the synchronous rectification transistor M2 is turned off. At this time, the switching voltage Vsw is in a high level state. The clock signal CLK output from the oscillation circuit 150 is also input to the slope circuit 130 at the same time, and the slope voltage Vsl is switched from the timing at which it is detected that the clock signal CLK has transitioned from the low level to the high level. While the transistor M1 is on, the operation returns to the normal operation that linearly descends.

  As described above, the switching regulators 100 and 200 according to the present invention perform switching with high efficiency and stable operation by selecting an appropriate timing for changing the offset voltage Vof according to the operation of the offset switch 172 and the mode switching circuit 190. A regulator is provided. The switching between the normal mode and the standby mode in the description so far has been switched according to the high level / low level of the mode switching means Smode as described above. The mode signal Smo applied to the mode switching circuit 190 may be supplied from an external device, the switching regulator 100 may be supplied from the microcomputer MPU, or a new mode terminal may be provided in the integrated circuit 10. May be supplied.

FIG. 10 is a flowchart prepared for explaining a control method of the switching regulator 100 according to the present invention shown in FIG. Although FIG. 11 shows a control method particularly when the switching regulator 100 is used as an in-vehicle power supply device, the present invention is not limited to this. The switching regulator 100 is incorporated, for example, as a power source of a car audio device as a device, and is controlled by the microcomputer MPU. Hereinafter, a description will be given with reference to FIGS. 1, 2, 3, and 10.

  Step ST710 shows a start in controlling the switching regulator of the present invention. The start state refers to, for example, a state in which a user gets into an automobile, that is, a step intended to use a device equipped with a switching regulator. In step ST711, the user starts the engine. When the engine is started and power is supplied from the accessory power supply path of the automobile to, for example, an audio device (not shown), an enable signal is sent from the microcomputer MPU to the enable terminal EN. Thereby, in step ST712, it will be in an enable state, and as shown to step ST713, each power supply output will be in an ON state.

  In step ST714, the microcomputer MPU selects a mode and selects a normal mode. In the normal mode, the mode signal Smo shown in FIGS. 3 and 7 is set to a high level. In step ST715, for example, as a normal car information operation, the switching regulators 100 and 200 supply power to a load (not shown) of an audio device (not shown). Such power supply to the audio device corresponds to the normal mode, and this normal mode can be considered as the first mode.

  Step ST716 shows a state where the user parks a car, for example, in a parking lot and turns off the engine. In step S717, the microcomputer MPU senses that the engine has been turned off and indicates a state in which the standby mode is selected. In the standby mode, the mode signal Smo is given a low level. The standby mode can be considered as the second mode.

In step ST718, the microcomputer MPU measures the time after the vehicle engine is stopped, and determines whether or not a predetermined time, for example, 10 minutes has elapsed. Until the determination is executed, the standby mode is continued. During the standby mode, the enable terminal EN shown in FIG. 2 is in an enabled state.

In step ST718, when the microcomputer MPU detects that the engine is turned on again within the predetermined time, the process proceeds to step ST714 and returns to the normal operation. If the engine is not turned on again within the predetermined time, the microcomputer MPU determines that the automobile is in a completely stopped state, and the process proceeds to step ST719. In step ST719, the enable terminal EN is disabled, and power supply to each part of the switching regulator 100 is stopped. In the subsequent step ST720, the flowchart is completed.

Although FIG. 10 shows the measurement of the time when the standby mode is executed, the time when the normal mode is executed may be measured. In any case, the time during which at least one of the modes is executed may be measured.

Further, FIG. 10 shows that the normal mode is switched when the standby mode is within a predetermined time, and the switching regulator is disabled, that is, the switching regulator is turned off when the standby mode has passed the predetermined time. It was. However, it is also possible to measure the time during which the normal mode is executed and shift to the standby mode or the disabled state based on the predetermined time.

That is, when the normal mode or the standby mode is within a predetermined time, the current mode is continued, and when the predetermined time is exceeded, the current mode is switched to, for example, the standby mode or the normal mode. You may do it.

Further, the method of detecting the engine operating state and selecting the mode is not limited to the above, and signals from other peripheral devices provided in the automobile such as a keyless entry can be appropriately used.

  Since the switching regulator and the control method of the present invention can provide optimum operation in a heavy load, a light load, and a standby mode by a switching mechanism built in an integrated circuit, for example, the industrial applicability is extremely large.

DESCRIPTION OF SYMBOLS 10 Integrated circuit 100,200 Switching regulator 110 Error amplifier 115 Soft start circuit 120 Comparator 125 Adder 130 Slope circuit 140 Oscillation circuit 150 Control circuit 160 Current detection circuit 170a 1st offset circuit 170b 2nd offset circuit 172 Offset switch 174 Mode change switch 180 protection circuit 181 comparator 182 short protection circuit 183, 184 constant voltage source 185 UVLO / TSD protection circuit 186 logic circuit 190 mode switching circuit 191, 193, INV1, INV2 inverter 192, 194 AND operation circuit 195 OR operation circuit C1, C2, C3, C4 Capacitor D1 Diode L1 Inductor M1 Switching transistor M2 Synchronous rectification transistor M31, M32, M33, M34, M35, M36 Transistor OUT Output terminal PVIN Second power supply terminal R1, R2 Voltage dividing resistor R3 Resistor R4 Offset resistor S1, S2 Drive signal Smo Mode switching signal SP1, SP2 Protection signal Spw Pulse signal VIN First 1 power supply terminal Vin input voltage Vout output voltage Vsl slope voltage Vsw switching voltage

Claims (14)

A switching transistor that is supplied with an input voltage and performs an on / off switching operation, a control circuit that performs on / off control of the switching transistor, an inductor that receives a switching voltage extracted from the switching transistor and that is supplied with a current, and the inductor A capacitor connected in series, a voltage dividing resistor that divides an output voltage taken from a series connection point of the inductor and the capacitor, a feedback voltage and a reference voltage generated by the voltage dividing resistor, and these are input. An error amplifier that outputs a voltage corresponding to the voltage difference between the two, an error output voltage output from the error amplifier, and a triangular or sawtooth slope voltage are input and has a pulse width corresponding to the voltage difference between the two. Output a pulse signal and control the output pulse signal Switching regulator comprising a comparator supplied to road, the first offset circuit and the second offset circuit for setting a DC bias voltage of the slope voltage.   The switching regulator according to claim 1, wherein the error amplifier outputs an error output current, and the error output current is converted into the error output voltage by a resistor and a capacitor. The switching regulator according to claim 1, further comprising an undervoltage lockout circuit, wherein the undervoltage lockout circuit stops the operation of the switching regulator when the input voltage drops below a predetermined level.   4. The switching regulator according to claim 3, wherein the low voltage lockout circuit is controlled by a microcomputer.   The switching regulator according to claim 1, wherein the DC bias voltage of the slope voltage is set by combining ON / OFF operations of the first offset circuit and the second offset circuit.   The second offset circuit includes an offset switch, and the switching regulator has the first offset circuit on when the offset switch is off, and the first offset circuit and the switching regulator when the offset switch is on. The switching regulator according to claim 5, wherein both of the second offset circuits are placed in an on state.   The switching regulator according to claim 5, wherein the first offset circuit includes an offset resistor and a first constant current circuit, and the second offset circuit includes the offset resistor and a second constant current circuit.   The switching regulator according to claim 7, wherein when the offset switch is turned on, a current generated by both the first constant current circuit and the second constant current circuit flows through the offset resistor.   The switching regulator according to claim 8, wherein the offset switch is responsive to a high level or a low level of a drive signal that drives the switching transistor. The switching regulator according to claim 9, wherein the offset switch is responsive to a high level or a low level of a pulse signal extracted from the comparator.   The offset switch is controlled by a mode changeover switch to which the pulse signal output from the comparator, the drive signal for driving the switching transistor, and a mode signal for outputting either of these signals are input. The switching regulator according to claim 9 or 10, wherein:   The switching regulator according to claim 11, further comprising an overvoltage detection comparator that compares a feedback voltage fed back to the error amplifier with a constant voltage source, and stops the operation of the control circuit according to an output of the overvoltage detection comparator. A method for controlling a switching regulator according to any one of claims 1 to 12, wherein a user intends to use a device equipped with the switching regulator;
The user turning on the device;
Receiving the power on and causing the device to execute a first mode;
Executing a second mode different from the second mode;
Measuring the time when at least one of the first mode and the second mode has elapsed; and
A step of switching the first mode or the second mode to another mode when the first mode or the second mode exceeds a predetermined time, or the first mode or the second mode is a predetermined time A switching regulator control method comprising either one of the step of continuing the first mode or the second mode when the value is within the range. 14. The switching regulator control method according to claim 13, wherein the first mode and the second mode are controlled by a microcomputer.

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