JP2013141014A - Group iii nitride semiconductor element manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a group III nitride semiconductor element which achieves favorable ohmic contact between a (000-1) plane side of a group III nitride semiconductor layer and an electrode, and which can operate at lower voltage.SOLUTION: A manufacturing method of a group III nitride semiconductor element having a group III nitride semiconductor layer, comprises: a step of performing anisotropic etching on a predetermined region on a (000-1) plane side of the group III nitride semiconductor layer to form a plurality of polygonal pyramid-shaped projections; a step of performing isotropic etching on the predetermined region to transform the projections to a plurality of salients each having dome-shaped roundness; and a step of forming an electrode on a top face of the predetermined region having the salients.

Description

  The present invention relates to a group III nitride semiconductor device and a method for manufacturing the same.

  Group III nitrides such as field effect transistors (FETs) and light emitting diodes (LEDs) in which element portions are formed of group III nitride semiconductors using Al, Ga, In or the like as group III elements and N as group V elements Semiconductor devices have been studied.

  Group III nitride semiconductors such as GaN and AlGaN usually have a hexagonal wurtzite crystal structure. When a group III nitride semiconductor such as GaN is epitaxially grown on a heterogeneous substrate such as sapphire, the layer is usually grown in the c-axis direction, and the surface of the grown layer is called a so-called Ga plane (0001) plane. Thus, the opposite side (the side in contact with the substrate) becomes a (000-1) plane called a so-called N plane. In addition, a group III nitride semiconductor substrate such as a GaN substrate usually has a (0001) plane on one side and a (000-1) plane on the opposite side.

  Here, in Patent Document 1, an active element portion made of a group III nitride semiconductor layer is formed on the (0001) plane of an n-type GaN substrate, a p-electrode is formed on the active element portion, and ( In a group III nitride semiconductor device in which an n electrode is formed on the (000-1) plane side, a polygonal pyramid having a specific facet surface on the surface by wet etching or the like on the (000-1) plane side of the n-type GaN substrate. A technique is described in which a good ohmic contact is obtained by forming a protrusion and forming an n-electrode such as Ti / Al or Ti / Au so as to cover the protrusion.

  By the way, GaN substrates and SiC substrates are still expensive, and are generally grown on sapphire substrates because there is no large-diameter and inexpensive conductive single crystal substrate.

  However, the sapphire substrate is insulative and no current flows. For this reason, in the conventional device, a part of the semiconductor laminate composed of the n-type group III nitride semiconductor layer, the active layer, and the p-type group III nitride semiconductor layer, which are sequentially grown on the sapphire substrate, is removed. The n-type group III nitride semiconductor layer is exposed. Then, an n-side electrode and a p-side electrode are arranged on the exposed n-type group III nitride semiconductor layer and p-type group III nitride semiconductor layer, respectively, and a lateral structure is formed in which a current flows laterally. Adopted.

  On the other hand, in recent years, a technique for obtaining an element having a vertical structure as described below has been studied. First, a buffer layer is formed on a sapphire substrate to be removed by, for example, laser irradiation or etching, and then a semiconductor stacked body including an n-type group III nitride semiconductor layer, an active layer, and a p-type group III nitride semiconductor layer is formed. To do. Next, after forming a conductive support body for supporting the semiconductor laminated body on the semiconductor laminate, the buffer layer is selectively dissolved by decomposition or etching by laser irradiation, and the sapphire substrate is peeled off (lifted off). Then, an element is formed by sandwiching the support body and the semiconductor stacked body between a pair of electrodes. The buffer layer here is a buffer layer for epitaxial growth of the semiconductor stacked body, and also serves as a lift-off layer for peeling the semiconductor stacked body from the sapphire substrate. Such a method of manufacturing a group III nitride semiconductor device is called a laser lift-off method or a chemical lift-off method.

JP 2004-71657 A

  In the lateral structure element, both the n-side electrode and the p-side electrode are formed on the (0001) plane side of the n-type group III nitride semiconductor layer and the p-type group III nitride semiconductor layer, respectively. However, in the device having the vertical structure, the p-side electrode is formed on the (0001) plane side of the p-type group III nitride semiconductor layer, but the n-side electrode is (000−) of the n-type group III nitride semiconductor layer. 1) It is formed on the surface side.

  According to the study by the present inventors, not only in the case of a group III nitride semiconductor substrate as in Patent Document 1, but also in the case where an electrode is formed on a group III nitride semiconductor layer, the (0001) plane side is formed. It has been clarified that the obtained ohmic contact property differs depending on whether it is formed on the (000-1) plane side. That is, in the case of the vertical structure, sufficient ohmic contact between the n-type group III nitride semiconductor layer on the (000-1) plane side and the n-side electrode cannot be obtained, and the n-side electrode has a high resistance, that is, a high resistance. There was a problem of voltage.

  Further, the present inventors have examined that a polygonal pyramid having a specific facet surface on the surface is obtained by performing wet etching on the (000-1) plane of the n-type group III nitride semiconductor layer exposed along with the removal of the lift-off layer. When a large number of protrusions of a shape are formed and an n-side electrode is formed thereon, sufficient ohmic contact between the n-type group III nitride semiconductor layer and the n-side electrode is not obtained, but rather no protrusion is formed. It turned out to be higher resistance than the case.

  Accordingly, in view of the above problems, the present invention provides a group III nitride semiconductor device in which an electrode is formed on the (000-1) plane side of a group III nitride semiconductor, and the (000-1) plane side of the group III nitride semiconductor layer. It is an object of the present invention to provide a group III nitride semiconductor device that realizes good ohmic contact between the electrode and the electrode and can operate at a lower voltage, and a method for manufacturing the same.

In order to achieve the above object, the gist of the present invention is as follows.
(1) A group III nitride semiconductor device having a group III nitride semiconductor layer, wherein a plurality of dome-shaped rounds are provided in a predetermined region on the (000-1) plane side of the group III nitride semiconductor layer. A group III nitride semiconductor device having a convex portion and an electrode on the upper surface of the predetermined region.

  (2) The group III nitride semiconductor device according to the above (1), wherein the bottom of the valley formed by the adjacent convex portions is a corner.

  (3) The group III nitride semiconductor device according to (1) or (2), wherein the surface of the convex portion is a random surface whose facet surface cannot be specified.

  (4) A group III nitride semiconductor device having a support body, and a first conductivity type group III nitride semiconductor layer, an active layer, and a second conductivity type group III nitride semiconductor layer sequentially positioned on the support body. The second conductivity type group III nitride semiconductor layer has a (000-1) plane side opposite to the support body, and the second conductivity type group III nitride semiconductor layer (000-1) plane. A group III nitride semiconductor device comprising a plurality of convex portions having a dome-shaped round shape in a predetermined region on the side, and an electrode on an upper surface of the predetermined region.

  (5) The group III nitride semiconductor device according to (4), wherein the second conductivity type is n-type.

  (6) The group III nitride semiconductor device according to (4) or (5), wherein the electrode is a Ti / Al electrode.

  (7) A method for producing a group III nitride semiconductor device having a group III nitride semiconductor layer, wherein anisotropic etching is performed on a predetermined region on the (000-1) plane side of the group III nitride semiconductor layer, A step of forming a plurality of polygonal pyramidal projections, a step of subjecting the predetermined region to isotropic etching to change the projection into a plurality of convex portions having a dome-shaped round shape, and a predetermined step having the convex portions And a step of forming an electrode on the upper surface of the region. A method for manufacturing a group III nitride semiconductor device, comprising:

  (8) The method for producing a group III nitride semiconductor device according to (7), wherein the anisotropic etching is wet etching in which a surface of the protrusion is a facet surface other than the (000-1) plane.

  (9) The group III nitride according to (8), wherein the facet plane is any one of (10-1-1) plane, (10-1-2) plane, and (10-1-3) plane A method for manufacturing a semiconductor device.

  (10) The method for producing a group III nitride semiconductor device according to (8) or (9), wherein an alkaline solution is used for the anisotropic etching.

  (11) The group III nitride semiconductor according to any one of (8) to (10), wherein the isotropic etching is dry etching in which a surface of the convex portion is a random surface whose facet surface cannot be specified. Device manufacturing method.

  (12) The step of forming the electrode includes a step of forming a protective film on the upper surface of the predetermined region, a step of applying a resist on the protective film, and removing the resist at the electrode formation site by a photolithography method, The group III nitride semiconductor device according to any one of the above (7) to (11), which includes a step of removing the protective film at the electrode forming portion and a step of forming an electrode at the electrode forming portion. Manufacturing method.

  (13) A step of forming a lift-off layer, a second conductivity type group III nitride semiconductor layer, an active layer, and a first conductivity type group III nitride semiconductor layer in this order on the growth substrate; and the first conductivity type group III A step of forming a support body on the nitride semiconductor layer, a step of peeling the growth substrate from the second conductive group III nitride semiconductor layer by removing the lift-off layer, and (000-1 ) Anisotropic etching is performed on a predetermined region of the exposed second conductivity type group III nitride semiconductor layer on the surface side to form a plurality of polygonal pyramidal projections, and isotropic etching is performed on the predetermined region. And a step of changing the protrusions into a plurality of convex portions having a dome-shaped round shape, and a step of forming an electrode on the upper surface of the predetermined region having the convex portions. A method for manufacturing a nitride semiconductor device.

  According to the group III nitride semiconductor device of the present invention, a plurality of convex portions having a dome-shaped round shape are provided in a predetermined region on the (000-1) plane side of the group III nitride semiconductor layer. An electrode was provided on the upper surface. As a result, a good ohmic contact between the (000-1) plane side of the group III nitride semiconductor layer and the electrode can be realized, and a group III nitride semiconductor device operable at a lower voltage can be obtained. .

  According to the method for manufacturing a group III nitride semiconductor device of the present invention, anisotropic etching and subsequent isotropic etching are performed on a predetermined region on the (000-1) plane side of the group III nitride semiconductor layer. Thus, the surface of the convex portion can be effectively formed. Therefore, a good ohmic contact between the (000-1) plane side of the group III nitride semiconductor layer and the electrode can be realized, and a group III nitride semiconductor device operable at a lower voltage can be obtained.

1 is a schematic cross-sectional view of a group III nitride semiconductor device 100 according to an embodiment of the present invention. (A)-(G) show each process of the manufacturing method of the group III nitride semiconductor element by one Embodiment of this invention with a schematic cross section. (A), (B) is sectional drawing which shows typically the surface shape of the n-type group III nitride layer 110 in the process shown to FIG.2 (E), (F), respectively, (C) is ( It is a conceptual diagram which shows the measuring method of the convex part of B). (A) and (B) schematically show the surface shape of the n-type group III nitride layer 110 in the conventional group III nitride semiconductor device, respectively. (A)-(F) are schematic cross sections which show an example of the electrode formation process shown to FIG. 2 (G). It is a SEM image of Example 1, (A) is what image | photographed the surface of the n-type group III nitride layer before n-side electrode formation in an oblique view, (B) is electrode formation after n-side electrode formation This is a photograph of a cross section near the surface. It is a SEM image of the comparative example 3, (A) is what image | photographed the surface of the n-type group III nitride layer before n-side electrode formation in an oblique view, (B) is electrode formation after n-side electrode formation This is a photograph of a cross section near the surface. It is a SEM image of the comparative example 4, (A) is what image | photographed the surface of the n-type group III nitride layer before n-side electrode formation in an oblique view, (B) is electrode formation after n-side electrode formation This is a photograph of a cross section near the surface. It is a SEM image of Example 6, (A) is what image | photographed the surface of the n-type group III nitride layer before n-side electrode formation in an oblique view, (B) is electrode formation after n-side electrode formation This is a photograph of a cross section near the surface. It is a SEM image of Example 7, (A) is what image | photographed the surface of the n-type group III nitride layer before n-side electrode formation in an oblique view, (B) is electrode formation after n-side electrode formation This is a photograph of a cross section near the surface. It is a SEM image of the comparative example 5, and the surface of the n-type group III nitride layer before n-side electrode formation is imaged with an oblique field of view.

  Hereinafter, the present invention will be described in more detail with reference to the drawings. In the schematic cross-sectional view of the semiconductor element, for convenience of explanation, other layers are exaggerated in the thickness direction at a ratio different from the actual state with respect to the support body.

(Group III nitride semiconductor devices)
A group III nitride semiconductor device 100 (hereinafter also simply referred to as “device” 100) according to an embodiment of the present invention will be described with reference to FIG. The element 100 includes a support body 116, a p-type group III nitride semiconductor layer 114 (hereinafter simply referred to as “p layer”), an active layer 112, and an n-type group III nitride semiconductor, which are sequentially positioned on the support body 116. A layer 110 (hereinafter, simply referred to as an “n layer”). An n-side electrode 128 is located on the n layer 110 and is electrically connected to the n layer. The support body 116 has conductivity, and also serves as a p-side electrode that is electrically connected to the p layer 114. The details of the superlattice buffer layer 108 and the AlN buffer layer 106 located on the outer periphery of the n layer 110 and the mask 118 covering the periphery of each semiconductor layer and the peripheral portion of the surface of the support body 116 will be described later.

  Here, among the pair of surfaces, the n layer 110 has a (0001) plane on the support body 116 side and a (000-1) plane on the opposite side to the support body 116. The n layer 110 has a plurality of convex portions 124 having a dome-shaped roundness in a predetermined region 120 on the (000-1) plane side of the n layer 110, and an n-side electrode 128 on the upper surface of the predetermined region. .

  According to this configuration, the inventors have shown that the (000-1) plane side of the n layer 110 is flat and the (000-1) plane is exposed, as shown in FIG. As shown in FIG. 4A, the n-layer 110 and the n-layer 110 have a projection of a polygonal pyramid on the (000-1) plane side and a facet plane other than the (000-1) plane is exposed. It has been found that the ohmic contact with the n-side electrode 128 can be improved and the device can be operated at a lower voltage.

(Manufacturing method of group III nitride semiconductor device)
A method for manufacturing a group III nitride semiconductor device according to an embodiment of the present invention for suitably manufacturing the device 100 will be described with reference to FIGS. First, as shown in FIG. 2A, a lift-off layer 104 is formed on a growth substrate 102, an AlN buffer layer 106 and a superlattice buffer layer 108 are sequentially formed thereon, and an n-type is further formed thereon. A group III nitride semiconductor layer 110, an active layer 112, and a p-type group III nitride semiconductor layer 114 are formed in this order. The superlattice buffer layer 108 is formed to alleviate the lattice mismatch with the n layer 110 formed thereon and to improve the crystal quality of the n layer 110.

  Next, lattice-like grooves in which the growth substrate 102 is exposed at the bottom surface are formed in the stacked semiconductor layers 106 to 114 to form semiconductor structures independent of each other. FIG. 2B shows only one semiconductor structure section partitioned by grooves. Then, as shown in FIG. 2B, a support body 116 is formed on the p layer 114. The support body 116 supports the stacked semiconductor layers after the growth substrate 102 described below is peeled off.

  Next, as shown in FIG. 2C, the growth substrate 102 is separated from the n layer 110, the superlattice buffer layer 108, the AlN buffer layer 106, and the like by removing the lift-off layer 104 by a chemical lift-off method.

Next, as shown in FIG. 2D, a mask 118 is formed to cover the peripheral portion of the AlN buffer layer 106 surface, the periphery of each semiconductor layer, and the peripheral portion of the surface of the support body 116. The mask 118 is made of an insulating film such as SiO ₂ or SiN, and protects the covered portion from anisotropic etching and isotropic etching described later.

  Next, as shown in FIG. 2E, anisotropic etching, for example, wet etching with an alkaline solution such as a 2.38 mass% tetramethylammonium hydroxide (TMAH) solution is not covered with the mask 118 and exposed. The AlN buffer layer 106 in the predetermined region 120 is applied. As the etching proceeds, the AlN buffer layer 106 and the superlattice buffer layer 108 are removed, and the n layer 110 is exposed.

  At this time, the (000-1) plane side of the n layer 110 is exposed. When a group III nitride semiconductor is epitaxially grown, as described above, the layer grows in the c-axis direction, and the surface of the grown layer becomes a (0001) plane called a so-called Ga plane, and the opposite side (side in contact with the support body) Becomes the (000-1) plane called the so-called N-plane. Therefore, in the layer formation stage of FIG. 2A, the surface of the n layer 110 in contact with the superlattice buffer layer 108 is the (000-1) plane, and the surface on which the active layer 112 is grown is the (0001) plane. It is.

  In FIG. 2E, anisotropic etching is continuously performed on the predetermined region 120 of the exposed n layer 110 on the (000-1) plane side. When anisotropic etching is performed on the (000-1) plane side of the n layer 110, a plurality of polygonal pyramid-shaped protrusions 122 are formed on the surface of the n layer 110 as shown in FIG. Since group III nitride semiconductors are hexagonal, hexagonal pyramidal protrusions are usually formed. The anisotropic etching is wet etching in which the surface of the protrusion 122 is a facet surface other than the (000-1) plane. When the etching solution is an alkaline solution as in the present embodiment, it has been reported so far that the facet surface exposed on the surface of the protrusion 122 is a (10-1-1) surface or a surface equivalent thereto.

  Next, as shown in FIG. 2F, isotropic etching is performed on the predetermined region 120. Then, as shown in FIG. 3B, the plurality of protrusions 122 change to a plurality of convex portions 124 having a dome-shaped roundness. Isotropic etching is, for example, dry etching such as reactive ion etching (RIE). As a result of isotropic etching, the surface of the convex portion 124 shown in FIG. 3B becomes a random surface whose facet surface cannot be specified.

  In a state where the n layer 110 has the convex portion 124 of FIG. 3B on the (000-1) plane side, the n-side electrode 128 is formed on the upper surface of the predetermined region 120 of the n layer 110 as shown in FIG. Form. The element 100 of this embodiment is completed through the above steps.

  The characteristic configuration of the present invention inherent in the embodiment of the element 100 and the method for manufacturing the element 100 will be described together with the function and effect thereof.

  As shown in FIGS. 2 (E) to (G) and FIGS. 3 (A) and 3 (B), the method for producing a group III nitride semiconductor device according to the present invention comprises (000-1) of a group III nitride semiconductor layer. ) Applying anisotropic etching to a predetermined region on the surface side to form a plurality of polygonal pyramidal protrusions; applying isotropic etching to the predetermined region; and forming the protrusions into a plurality of dome-shaped rounded protrusions And a step of forming an electrode on the upper surface of the predetermined region having the convex portion. The group III nitride semiconductor device of the present invention can be obtained by, for example, the above manufacturing method, and has a dome-shaped roundness in a predetermined region on the (000-1) plane side of the group III nitride semiconductor layer. It has a some convex part and has an electrode on the upper surface of the said predetermined area | region, It is characterized by the above-mentioned.

  When the step of exposing the surface of the n layer 110 shown in FIG. 2E is performed only by isotropic etching, the surface of the n layer 110 becomes flat as shown in FIG. 1) The surface is exposed. Further, when the same process is performed only by anisotropic etching, the surface of the n layer 110 becomes a polygonal pyramid (hexagonal pyramidal) protrusion 122 as shown in FIG. It has been reported that the surface of the protrusion 122 is a (10-1-1) plane or a plane equivalent thereto. According to the study by the present inventors, when an n-side electrode is formed on each of the two n-layer 110 surfaces, a sufficient ohmic contact cannot be obtained, and the voltage between two n-side electrodes is measured. As a result, the voltage became high. This means that the voltage at which the element can operate is also high.

  On the other hand, when the n-side electrode is arranged on the surface of the n layer 110 having a plurality of convex portions 124 having a dome-shaped roundness on the (000-1) plane side as in the element 100, good ohmic contact is achieved. As a result, the voltage between the two n-side electrodes was sufficiently low as compared with the above two cases. Such a convex surface can be effectively formed by applying anisotropic etching and subsequent isotropic etching to a predetermined region on the (000-1) plane side of the group III nitride semiconductor layer. It was. By such an element 100 and a manufacturing method thereof, good ohmic contact between the (000-1) plane side of the group III nitride semiconductor layer and the electrode is realized, and the element can be operated at a lower voltage.

  In addition, although the effect | action which the voltage between two n side electrodes falls by the said characteristic structure is not fully elucidated, it is thought that relevance is low at least with the contact area with the n side electrode of n layer. Although the surface area of the n layer is not so much different between the case of FIG. 4A and the case of FIG. 3B of the present invention, the difference in voltage between the two points on the n-side electrode is remarkable. Because there is.

  In this manufacturing method, isotropic etching may be performed for the purpose of removing all or part of the AlN layer 106 and the superlattice buffer layer 108 before anisotropic etching and subsequent isotropic etching. Good.

  The growth substrate 102 is preferably a sapphire substrate or an AlN template substrate in which an AlN film is formed on a sapphire substrate. What is necessary is just to select suitably by the kind of lift-off layer to form, the composition of Al, Ga, In of the semiconductor laminated body which consists of a group III nitride semiconductor, the quality of a LED chip, cost, etc.

  The lift-off layer 104 is not particularly limited as long as it is a material that can be dissolved with an etching solution, and examples thereof include metals other than Group III such as CrN and metal nitride buffer layers.

The AlN buffer layer 106, the superlattice buffer layer 108, the n layer 110, the active layer 112, and the p layer 114 can be sequentially epitaxially grown on the lift-off layer 104 by, for example, the MOCVD method. The superlattice buffer layer 108 is formed by alternately stacking two Al _x Ga _1-x N (0 ≦ x ≦ 1) having different Al compositions x. The n layer 110 and the p layer 114 are made of any group III nitride semiconductor such as AlInGaN, and are made of a clad layer sandwiching the active layer and a contact layer in contact with the n side electrode and the p side electrode, respectively. The active layer 112 can be a light emitting layer in which a multiple quantum well (MQW) structure is formed of a group III nitride semiconductor. In this case, the element 100 is an LED. Usually, the thickness of each of the AlN buffer layer 106, the superlattice buffer layer 108, the n layer 110, the active layer 112, and the p layer 114 is 0.6-2 μm, 0.6-3 μm, 1-4 μm, 1-100 nm, The thickness is about 0.1 to 1 μm.

  The support body 116 may be formed of a conductive silicon substrate, a CuW alloy substrate, a Mo substrate, or the like by a bonding method, or may be formed by wet or dry plating. For example, in the electroplating of Cu or Au, Cu, Ni, Au or the like can be used as the connection layer. The support body 116 can also serve as a p-side electrode.

  The etching solution that can be used for the chemical lift-off method is not particularly limited. When the lift-off layer is CrN, an etchant having selectivity with respect to CrN such as ceric ammonium nitrate solution or potassium permanganate solution can be used. When the lift-off layer is ScN, Hf, or Zr, a selective acidic etching solution can be used.

For the mask 118, for example, SiO ₂ or SiN can be used. The formation method is not particularly limited. For example, after depositing SiO ₂ by CVD on the entire surface of the AlN buffer layer 106, the periphery of each semiconductor layer, and the peripheral portion of the surface of the support body 116, only the predetermined region 120 is exposed. A state shown in FIG. 2D can be obtained by forming a metal mask (for example, Ni) and etching SiO _{2 in the} predetermined region 120 by RIE.

  The anisotropic etching is not particularly limited as long as a polygonal pyramidal convex portion can be formed on the (000-1) plane side of the group III nitride semiconductor layer. For example, 2.38 mass% tetramethylammonium hydroxide (TMAH) ) Wet etching with an alkaline solution such as a solution, NaOH solution or KOH solution. In this case, the convex portion has a hexagonal pyramid shape, the surface of the convex portion (six side surfaces of the hexagonal pyramid) has a planar shape, and this surface is mainly a (10-1-1) plane. It should be noted that the literature (Appl. Phys. Lett., Vol. 73, No.) describes that (10-1-2) plane and (10-1-3) plane appear depending on other etching solutions (phosphoric acid and the like). 18, 2 November 1998). However, the (10-1-1) plane is more preferable because the angle of the convex portion is large and the valley is deep.

  The processing conditions for the anisotropic etching are not particularly limited as long as a polygonal pyramidal convex portion can be formed on the (000-1) plane side of the group III nitride semiconductor layer. In this embodiment, it is necessary to remove the AlN buffer layer 106 and the superlattice buffer layer 108 and to form a convex portion on the n layer 110. Although depending on the thicknesses of the AlN buffer layer 106 and the superlattice buffer layer 108, in the case of a 2.38 mass% TMAH solution, the anisotropic etching treatment time is preferably 1 minute or more, and 5-60 minutes A range is more preferred.

  When isotropic etching is performed on a flat surface, the etching proceeds at a uniform rate regardless of the position in the surface. However, when applied to the surface having the polygonal pyramidal convex portion of FIG. 3A as in this manufacturing method, the etching progresses at the top where physical adsorption and separation are easier than the bottom of the convex portion. Tend to be early. Therefore, in this manufacturing method, by performing isotropic etching following anisotropic etching, the protrusion 122 can be changed to a convex portion 124 having a round top.

  The height of the convex portion is 0.1 to 3 μm, but is not necessarily uniform. Moreover, although the convex part is distributed over the whole area | region which performed anisotropic etching and isotropic etching process, if it sees locally, the area | region which is not necessarily distributed uniformly also exists. However, the round shape has uniformity, that is, the convex portions having roundness distributed over the whole area subjected to anisotropic etching and isotropic etching processing are similarly dome-shaped, and As shown in FIG. 3B, the bottom 126 of the valley formed by the adjacent convex portions 124 is a corner.

  The reason why the bottom 126 of the valley becomes a corner is that anisotropic etching is performed in the first stage of the two-stage etching. That is, compared with the case where the convex portion is formed using a mask pattern or the like, the bottom of the valley formed at a depth of 3 μm at the maximum by the combination of anisotropic etching and isotropic etching in the present invention, The corners are formed by anisotropic etching, and a finer and more complicated random surface can be formed. Therefore, the area of the random surface in contact with the ohmic electrode is large, and the effect of improving the ohmic contact property is high.

  Since the convex portion 124 inherits part of the regularity of the shape by anisotropic etching and the bottom portion 126 of the valley is a corner, as shown in FIG. 3C, the bottom portion 126 of the valley is connected to the cross section of the convex portion. And a horizontal line is drawn to the height (h / 3) of one third of the height (h) from the base to the apex of the convex portion, and the intersection of the convex portion and the bottom 126 of the valley You can draw a triangle with the straight line as the side. Therefore, the “dome-shaped roundness” in this specification means that the height from the bottom to the top of the convex portion is lower than the height from the bottom to the top of the circumscribed triangle, that is, circumscribes. The angle θ2 from the base of the triangle to the top of the convex portion is smaller than the angle θ1 from the base of the triangle to the top, and it is formed non-linearly from the base to the top of the convex portion. The difference (θ1−θ2) between the two angles (average values) is, for example, 3 to 30 degrees. The cross section of the convex portion is preferably a shape that is rounded convex toward the outside of the convex portion from the bottom to the top of the convex portion.

  For isotropic etching, for example, dry etching such as reactive ion etching (RIE) can be used. In the case of RIE, a gas such as chlorine, silicon tetrachloride, or boron trichloride can be used when etching a nitride semiconductor.

  From the viewpoint of reliably forming the dome-shaped convex portion as described above, the treatment time for isotropic etching is preferably 3 minutes or more, more preferably 5 minutes or more, although depending on conditions other than time.

  As the electrode material of the n-side electrode 128, Al, Cr, Ti, Ni, Pt, Au or the like is used. However, since it is easy to obtain stable ohmic characteristics, a Ti / Al electrode is preferable, for example, formed by sputtering. can do.

  In the present embodiment, the first conductivity type is p-type and the second conductivity type is n-type. This is because the resistance of the p-type layer is high and the current is difficult to spread, so that the light emission efficiency can be easily improved by using an n-type layer having a lower resistance as the light extraction side.

  A method for forming the n-side electrode 128 illustrated in FIG. 2G is not particularly limited, but can be formed by a lift-off method using a resist as a mask. When this lift-off method is used, the method shown in FIG. 5 is particularly preferable. FIG. 5 is an enlarged cross-sectional view of an electrode formation site on the n layer 110.

First, as shown in FIG. 5A, a protective film 130 is formed on the upper surface of at least the predetermined region 120 of the n layer 110. The protective film 130 is formed by forming an insulating film of SiO ₂ or SiN by the CVD method in the same manner as the mask 118.

  Next, as shown in FIG. 5B, a resist 132 is applied over the protective film 130, and as shown in FIG. 5C, the resist at the electrode formation portion 134 is removed by photolithography. At this time, since the surface of the n layer 110 is covered with the protective film 130, an alkaline solution such as 2.38 mass% TMAH used for removing the resist does not contact the n layer 110. Therefore, it is preferable because the surface state of the n layer 110, that is, the surface of the convex portion 124 can be maintained as a random surface formed by isotropic etching.

  Next, as shown in FIG. 5D, the protective film 130 at the electrode formation portion 134 is removed. This removal can be performed by using any etching solution that does not erode the n-layer 110, although the protective film such as BHF or HF has etching properties.

  Next, as shown in FIG. 5E, an n-side electrode 128 such as a Ti / Al electrode is formed on the electrode forming portion 134 by sputtering. Note that the electrode material deposited on the resist 132 can be removed while removing the resist 132 with acetone or the like as shown in FIG.

  Finally, in order to form a good ohmic contact between the n layer and the n-side electrode, annealing is performed at a temperature of about 400 to 600 ° C. in a vacuum.

  The above is an example of a typical embodiment, and the present invention is not limited to this embodiment, and can be modified as appropriate without departing from the scope of the claims.

Example 1
The group III nitride semiconductor LED device shown in FIG. 1 was produced by the manufacturing method shown in FIGS. Specifically, first, an AlN single crystal layer (thickness: 1 μm) was grown on a sapphire substrate for growth by using MOCVD to produce an AlN (0001) template. A film of Sc (thickness: 8 nm) was formed on this growth substrate by sputtering, and then nitriding was performed in an MOCVD apparatus to form a ScN layer as a lift-off layer.

Thereafter, as a semiconductor layer on the lift-off layer, an AlN layer (thickness: 1 μm), a superlattice buffer layer (a laminate of AlN / GaN, thickness: 1 μm), an n-type group III nitride semiconductor layer (Al _0.3 Ga _0.7 N layer (thickness: 2 μm), light emitting layer (AlInGaN-based MQW layer, thickness: 0.2 μm), p-type group III nitride semiconductor layer (Al _0.3 Ga _0.7 N layer, thickness) Thickness: 0.4 μm) and a p-type GaN contact layer (thickness: 0.05 μm) were sequentially laminated.

  Thereafter, a part of the semiconductor layer is removed by RIE to form a lattice-shaped groove so that a part of the sapphire substrate is exposed, thereby forming a plurality of independent semiconductor structures having a square cross-sectional shape. Formed.

  A p-type ohmic electrode (Ni / Au, thickness: 200/3000 mm) was formed on the p-type contact layer. A bonding layer (Ti / Pt / Au, thickness: 100/2000/7000 mm) was formed thereon. After that, the Si substrate of the support body in which Ti / Pt / Au / Sn / Au and the thickness: 100/2000/1000/2000/7000? As the bonding layer is formed and the bonding layers are combined and thermocompression bonded to form the Si substrate. And the semiconductor structure were joined.

  Thereafter, the sapphire substrate for growth was peeled off using a chemical lift-off method. The etching solution was a ceric ammonium nitrate solution having selectivity for the ScN layer.

Next, SiO ₂ (thickness: 3 μm) is formed by plasma CVD on the entire surface of the AlN buffer layer, the periphery of each semiconductor layer, and the periphery of the surface of the support body, and then a Ni mask is formed by sputtering. did. The Ni mask was formed by forming a resist pattern by photolithography and removing the Ni film by wet etching only at the portion where the n layer was exposed. Thereafter, SiO ₂ exposed by RIE was etched and removed.

Next, the formation process of the n layer surface will be described. Etching was performed under the conditions shown in Table 1 using the formed SiO ₂ as a mask to remove the AlN buffer layer and the superlattice buffer layer and to expose the surface of the n layer. The anisotropic etching of Table 1 used 2.38 mass% TMAH solution. The isotropic etching shown in Table 1 was RIE, and specific conditions were a pressure of 0.1 Pa, ICP and BIAS output of 400 W, Cl ₂ gas of 7.5 sccm, and BCl ₃ gas of 7.5 sccm. As shown in Table 1, in Example 1, anisotropic etching was performed at 40 ° C. for 10 minutes, and then RIE was performed for 20 minutes. Thereafter, washing with pure water was performed. The above etching is performed on the side where the growth substrate is peeled off, and the exposed n layer is the (000-1) plane side of the n layer.

Thereafter, a Ti / Al electrode was formed on the n layer exposed by the following method. First, SiO ₂ (thickness: 0.1 [mu] m) by a plasma CVD method on the exposed n layer was formed. Thereafter, a photoresist was applied onto SiO ₂ and the resist at the electrode forming portion was removed by a photolithography method. For removing the resist, a 2.38 mass% TMAH solution was used. Then, by treating for 1 min at BHF solution to remove SiO ₂ electrode formation region. Thereafter, a Ti / Al (thickness: 20 nm / 600 nm) electrode was formed by sputtering. The photoresist and Ti / Al deposited thereon were removed with acetone. Finally, annealing was performed at 400 ° C. in a vacuum. In Example 1, since there is SiO ₂ as a protective film, the n-layer is not subjected to anisotropic etching with a TMAH solution when the resist is removed.

(Examples 2-7, Comparative Examples 1-4)
A group III nitride semiconductor LED device was produced in the same manner as in Example 1 except that the formation process of the n-layer surface was as described in Table 1.

(Comparative Example 5)
The formation process of the n-layer surface is as shown in Table 1, and a group III nitride semiconductor LED was formed in the same manner as in Example 1 except that SiO ₂ was not formed and removed when forming the Ti / Al electrode. An element was produced. In this case, since the 2.38 mass% TMAH solution comes into contact with the n layer at the time of removing the resist at the electrode formation site, anisotropic etching is further performed on the surface of the n layer at the electrode formation site after the n layer formation process.

<Observation by SEM>
For each test example, the n-layer surface was observed from an oblique field of view by a scanning electron microscope (SEM) after the n-layer surface formation process and before the n-side electrode formation. Further, after forming the n-side electrode and after heat treatment, a cross section near the n-side electrode forming surface was photographed. FIGS. 6 to 10 representatively show SEM images of Example 1, Comparative Example 3, Comparative Example 4, Example 6, and Example 7, respectively. (A) is an image of an oblique view before forming the n-side electrode, and (B) is an image of a cross section after the heat treatment after forming the n-side electrode. In FIG. 11, the image of the diagonal visual field before the n side electrode formation of the comparative example 5 is shown.

  In Example 1, as shown in FIGS. 6A and 6B, a plurality of convex portions having a dome-shaped roundness on the surface of the n layer could be observed. Further, as is apparent from FIG. 6B, the bottom of the valley formed by the adjacent convex portions is cornered. In order to measure the degree of roundness, the triangle described in FIG. 3C is drawn on this convex part, and an angle θ1 from the base of the triangle to the vertex of the triangle and a straight line from the base of the triangle to the top of the convex part. A total of 10 angles θ2 were measured, and the average value was calculated. In Example 1, θ1 was 62 degrees and θ2 was 51 degrees. In Example 6, θ1 was 64 degrees and θ2 was 50 degrees. Examples 2 to 5 and 7 also have the same angle, θ1 is approximately 60 degrees, and θ2 is approximately 50 degrees.

  Further, in Example 7 in which the processing time of isotropic etching is 1 minute, as shown in FIG. 10, a convex portion having a dome-shaped round shape and a convex portion having a triangular cross-sectional shape (FIG. 10 (A ) Are relatively large convex portions, and the ratio is about 1/3). Although the shape change is insufficient when the treatment time is 1 minute, it is clear from the comparison with Comparative Example 2 that there is an effect of reducing the voltage by forming the convex portion having a rounded dome shape. On the other hand, in Examples 1 to 6 in which the processing time of isotropic etching was 5 minutes or more, almost all had a dome-shaped roundness. And the surface of the convex part which has the dome-shaped roundness of the shape of these Examples 1 to 7 is not considered to be a facet of a polar face or a semipolar face as reported by anisotropic etching. It is clear that the surface is a random surface that cannot be specified.

  In Comparative Example 3, since anisotropic etching was not performed after anisotropic etching, a plurality of hexagonal pyramidal protrusions were formed on the surface of the n layer as shown in FIGS. 7 (A) and 7 (B). It has been reported so far that the (10-1-1) plane is exposed by wet etching, and from FIG. 7, the side surface of the protrusion has an angle of about 60 degrees with respect to the bottom, and the surface of the protrusion is (10-1- 1) It can be estimated that it is a surface. The same was true for Comparative Examples 1 and 2.

  In Comparative Example 4, since only isotropic etching was performed, as shown in FIGS. 8A and 8B, the surface of the n layer became flat and the (000-1) plane was exposed.

  In Comparative Example 5, the n-layer surface electrode formation site was changed to a 2.38 mass% TMAH solution when the resist at the site where the Ti / Al electrode was formed was removed by photolithography after the n-layer formation process. Contact and anisotropic etching is performed. As a result, as shown in FIG. 11, on the surface of the n layer after removing the resist at the electrode formation site, a finer convex portion is formed on the top of the convex portion, which is not a convex portion having a dome-shaped roundness. It was. This minute convex portion is considered to be generated because a portion of the random surface exposed by isotropic etching, which has a weak connection between atoms and is easily etched by an anisotropic etching solution, is preferentially etched. Although the time required for removing the resist at the electrode formation site (anisotropic etching time) is as short as 90 seconds, the voltage between n and n is larger than that in Example 5, so that it has the effect of reducing the contact resistance. It was confirmed that the surface was changed by anisotropic etching, and the surface mainly formed by anisotropic etching was regenerated on the surface.

<Measurement of voltage between two n-side electrodes>
Square electrodes with one side of 100 μm were arranged with an interval of 50 μm. The voltage value when a current of 20 mA was passed between the electrodes was measured. The results are shown in Table 1.

  In each example, the voltage between the n electrodes could be remarkably reduced as compared with the comparative example. In particular, Examples 1 to 6, in which almost all the convex portions have a dome shape, were further reduced than Example 7.

  According to the present invention, a group III nitride semiconductor device that realizes good ohmic contact between the (000-1) plane side of the group III nitride semiconductor layer and the electrode and can operate at a lower voltage, and a method for manufacturing the same. Can be provided.

100 Group III nitride semiconductor device 102 Growth substrate 104 Lift-off layer 106 AlN buffer layer 108 Superlattice buffer layer 110 n-type (second conductivity type) Group III nitride semiconductor layer 112 Active layer 114 p-type (first conductivity type) Group III nitride semiconductor layer 116 Support body (p-side electrode)
118 Mask 120 Predetermined Area 122 Polygonal Conical Projection 124 Projection 126 Valley Bottom 128 N-side Electrode 130 Protective Film 132 Resist 134 Electrode Formation Site

Claims (7)

A method for producing a group III nitride semiconductor device having a group III nitride semiconductor layer,
Applying anisotropic etching to a predetermined region on the (000-1) plane side of the group III nitride semiconductor layer to form a plurality of polygonal pyramidal protrusions;
Applying isotropic etching to the predetermined region, and changing the protrusions into a plurality of convex portions having a dome-shaped roundness;
Forming an electrode on an upper surface of the predetermined region having the convex portion;
A method for producing a group III nitride semiconductor device comprising:   2. The method of manufacturing a group III nitride semiconductor device according to claim 1, wherein the anisotropic etching is wet etching in which a surface of the protrusion is a facet surface other than a (000-1) plane.   The group III nitride semiconductor device according to claim 2, wherein the facet plane is any one of a (10-1-1) plane, a (10-1-2) plane, and a (10-1-3) plane. Method.   4. The method for producing a group III nitride semiconductor device according to claim 2, wherein an alkaline solution is used for the anisotropic etching.   5. The method for manufacturing a group III nitride semiconductor device according to claim 2, wherein the isotropic etching is dry etching in which a surface of the convex portion is a random surface whose facet surface cannot be specified. The step of forming the electrode includes:
Forming a protective film on the upper surface of the predetermined region;
Applying a resist on the protective film, and removing the resist at the electrode formation site by a photolithography method;
Removing the protective film at the electrode formation site;
Forming an electrode at the electrode forming site;
The manufacturing method of the group III nitride semiconductor element of any one of Claims 1-5 which have these. Forming a lift-off layer, a second conductive group III nitride semiconductor layer, an active layer and a first conductive group III nitride semiconductor layer in this order on a growth substrate;
Forming a support on the first conductivity type group III nitride semiconductor layer;
Removing the lift-off layer to separate the growth substrate from the second conductivity type group III nitride semiconductor layer;
Applying anisotropic etching to a predetermined region of the exposed second conductivity type group III nitride semiconductor layer on the (000-1) plane side to form a plurality of polygonal pyramidal projections;
Applying isotropic etching to the predetermined region, and changing the protrusions into a plurality of convex portions having a dome-shaped roundness;
Forming an electrode on an upper surface of the predetermined region having the convex portion;
A method for producing a group III nitride semiconductor device comprising: