JP2013135018A - Light-emitting element - Google Patents

Light-emitting element Download PDF

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JP2013135018A
JP2013135018A JP2011282755A JP2011282755A JP2013135018A JP 2013135018 A JP2013135018 A JP 2013135018A JP 2011282755 A JP2011282755 A JP 2011282755A JP 2011282755 A JP2011282755 A JP 2011282755A JP 2013135018 A JP2013135018 A JP 2013135018A
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semiconductor layer
light emitting
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Arei Niwa
丹羽愛玲
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Sanken Electric Co Ltd
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Abstract

PROBLEM TO BE SOLVED: To provide a light-emitting element which prevents damages on a luminous region caused by an excessive load applied in bonding.SOLUTION: A light-emitting element comprises: a semiconductor light-emitting function layer formed on a substrate 11, in which a first semiconductor layer having a first conductivity type and a second semiconductor layer having a second conductivity type opposite to the first conductivity type are formed; and two electrodes 51, 52 used for energization for causing the semiconductor light-emitting function layer to emit light, and formed on a principal surface of the semiconductor light-emitting function layer on the side where the second semiconductor layer is formed. The second semiconductor layer is removed from the principal surface side immediately below pads of the two electrodes 51, 52 which are connected with the outside.

Description

本発明は、半導体層を構成材料とする発光素子の構造に関する。 The present invention relates to a structure of a light emitting element using a semiconductor layer as a constituent material.

発光素子(LED)は、各種の目的に使用されている。例えば、これを用いた照明機器は、従来の白熱電球や蛍光灯と比べて低消費電力かつ低発熱性のために、これらを将来的に置換することが期待されている。ここで、LEDにおけるp型半導体層やn型半導体層は、通常、エピタキシャル成長やイオン注入等によって形成される。p側に接続された電極とn側に接続された電極間にpn接合の順方向電流を流すことによってこの発光素子を発光させることができる。   Light emitting elements (LEDs) are used for various purposes. For example, lighting equipment using this is expected to be replaced in the future because of low power consumption and low heat generation compared to conventional incandescent bulbs and fluorescent lamps. Here, the p-type semiconductor layer and the n-type semiconductor layer in the LED are usually formed by epitaxial growth, ion implantation, or the like. The light emitting element can emit light by passing a forward current of a pn junction between the electrode connected to the p side and the electrode connected to the n side.

素子を実装基板上に実装する際には、実装基板と素子とをはんだ等で接続し、このはんだ接続によって素子との間の電気的接続も行う、いわゆるフリップチップ接続という方式が採用される場合が多い。発光素子においても同様であり、この場合には、基板と反対側に光が発せられる構成とされる場合が多い。   When a device is mounted on a mounting board, a so-called flip-chip connection method is adopted in which the mounting substrate and the element are connected by solder or the like, and electrical connection between the element is also made by this solder connection. There are many. The same applies to the light emitting element. In this case, the light emitting element is often configured to emit light to the side opposite to the substrate.

このようなフリップチップ接続方式においては、フリップボンディングの際にバンプボールが用いられ、過度の荷重がp側に接続された電極及びn側に接続された電極に加わることがある。特許文献1は、このようなフリップボンディングの際の過度の荷重による発光素子の発光領域の損傷を防止する技術が開示されている。   In such a flip-chip connection method, bump balls are used in flip bonding, and an excessive load may be applied to the electrode connected to the p side and the electrode connected to the n side. Patent Document 1 discloses a technique for preventing damage to a light emitting region of a light emitting element due to an excessive load during such flip bonding.

図1は、従来技術に係る発光素子である。サブマウント200のリードパターン上に
バンプボール300を介してフリップボンディングされる窒化物系半導体発光素子において、基板101と、前記基板上にバッファ層、n型窒化物半導体層103、活性層105及びp型窒化物半導体層107が順次形成された発光構造物と、前記発光構造物上に形成された透明電極109、p型電極110a、およびn型電極110bと、前記電極が形成された結果物の上に形成され、前記サブマウントのp型リードパターン201a、n型リードパターン201bとバンプボールを介して接続する部分に該当する電極表面を露出させる保護膜120と、前記保護膜を介して露出された電極表面に形成された格子形状の緩衝膜130とを備えたものである。この緩衝膜130により、バンプボールの臨界値以上の過度な荷重による発光素子の発光領域の損傷を防止できるという効果を有する。
FIG. 1 shows a light emitting device according to the prior art. In the nitride semiconductor light emitting device flip-bonded onto the lead pattern of the submount 200 via the bump ball 300, the substrate 101, and the buffer layer, the n-type nitride semiconductor layer 103, the active layer 105, and the p on the substrate. A light emitting structure in which a type nitride semiconductor layer 107 is sequentially formed, a transparent electrode 109, a p-type electrode 110a and an n-type electrode 110b formed on the light emitting structure, and a resultant structure in which the electrode is formed. A protective film 120 formed on the submount and exposing a surface of the electrode corresponding to a portion connected to the p-type lead pattern 201a and the n-type lead pattern 201b of the submount via a bump ball; and exposed through the protective film. And a lattice-shaped buffer film 130 formed on the surface of the electrode. The buffer film 130 has an effect of preventing the light emitting region of the light emitting element from being damaged by an excessive load exceeding the critical value of the bump ball.

しかしながら、従来技術では緩衝膜130を備えることで、緩衝膜130を備えない場合に対しては効果を有するものの、バンプボールの臨界値以上の過度な荷重による発光素子の発光領域の損傷を防止する点については十分とはいえず、信頼性上、最適なものではなかった。 However, although the conventional technology has the buffer film 130, it has an effect on the case where the buffer film 130 is not provided, but prevents the light emitting region of the light emitting element from being damaged by an excessive load exceeding the critical value of the bump ball. The point was not enough and was not optimal in terms of reliability.

特許第4428716号公報Japanese Patent No. 4428716

本発明は、上記問題点に鑑みてなされたものであり、その目的は、ボンディングの際の過度な荷重による発光領域の損傷を防止できる発光素子を提供することにある。   The present invention has been made in view of the above problems, and an object of the present invention is to provide a light emitting element capable of preventing damage to a light emitting region due to an excessive load during bonding.

上記課題を解決するため、本発明は、
基板上に第1の導電型をもつ第1の半導体層上に前記第1の導電型とは逆の導電型である第2の導電型をもつ第2の半導体層が形成された半導体発光機能層が用いられ、当該半導体発光機能層を発光させるための通電に用いられる2つの電極が共に前記半導体発光機能層における前記第2の半導体層が形成された側の主面上に形成された発光素子であって、 前記半導体発光機能層の一方の端部において前記第2の半導体層が前記主面側から除去された箇所で、前記第1の半導体層と接続するように形成された第1の電極と、 前記第2の半導体層の表面において、他方の端部の側から前記一方の端部の側に向かって延伸して形成された透明電極を具備し、 前記他方の端部に形成される第2の電極は、外部と接続されるパッド部と前記第1の電極へ向かって延伸する延伸部を有し、前記パッド部の直下において前記第2の半導体層が前記主面側から除去され、前記第1の電極と前記第2の電極間において、絶縁層を介して前記延伸部と前記透明電極が接続されることを特徴とする。
In order to solve the above problems, the present invention provides:
A semiconductor light emitting function in which a second semiconductor layer having a second conductivity type, which is a conductivity type opposite to the first conductivity type, is formed on a first semiconductor layer having a first conductivity type on a substrate. Layer, and two electrodes used for energization for causing the semiconductor light emitting functional layer to emit light are both formed on the main surface of the semiconductor light emitting functional layer on the side where the second semiconductor layer is formed. A first element formed so as to be connected to the first semiconductor layer at a position where the second semiconductor layer is removed from the main surface side at one end of the semiconductor light emitting functional layer. And a transparent electrode formed to extend from the other end side toward the one end portion on the surface of the second semiconductor layer, and formed at the other end portion. The second electrode is a pad portion connected to the outside and the first electrode The second semiconductor layer is removed from the main surface side immediately below the pad portion, and an insulating layer is interposed between the first electrode and the second electrode. The extending portion and the transparent electrode are connected.

ボンディングの際の過度な荷重による発光領域の損傷を防止した発光素子を提供できる。 It is possible to provide a light emitting element that prevents damage to a light emitting region due to an excessive load during bonding.

従来の半導体発光素子を概略的に示す断面図である。It is sectional drawing which shows the conventional semiconductor light-emitting device roughly. 本発明の実施例1に係る発光素子を示す断面図である。It is sectional drawing which shows the light emitting element which concerns on Example 1 of this invention. 本発明の実施例1に係る発光素子を実装基板上に配置した図である。It is the figure which has arrange | positioned the light emitting element which concerns on Example 1 of this invention on the mounting board | substrate. 本発明の実施例2に係る発光素子を実装基板上に配置した図である。It is the figure which has arrange | positioned the light emitting element which concerns on Example 2 of this invention on the mounting board | substrate.

次に、本発明の実施形態を、図面を参照して具体的に説明する。なお、ここで示す実施形態は一例であって、本発明はここに示す実施形態に限定される趣旨ではない。 Next, embodiments of the present invention will be specifically described with reference to the drawings. In addition, embodiment shown here is an example and this invention is not the meaning limited to embodiment shown here.

図2は、本発明の実施例1に係る発光素子の断面図を示したものである。図2に示されるように、半導体層20は、基板11上に形成される。この半導体層20は、基板11側からn型GaN層(以下、n型層と略)21、MQW(Multi Quantum Well)層23、p型GaN層(以下、p型層と略)22からなる積層構造をもつ。この構成における主たる発光層はMQW層23である。また、基板11としては、例えば、サファイア等、GaNをこの上にヘテロエピタキシャル成長させることのできる絶縁性の材料を用いることができる。
半導体層20の一方の端部(図2において右端部)側の領域においては、p型層22とMQW層23とが部分的に除去され、同様に、外部と接続されるp側電極51のパッド部直下の領域においてもp型層22とMQW層23とが部分的に除去されている。半導体層20の上には、透明電極30、絶縁層40、p側電極(アノード)51、n側電極(カソード)52が形成されている。
FIG. 2 shows a cross-sectional view of the light emitting device according to Example 1 of the present invention. As shown in FIG. 2, the semiconductor layer 20 is formed on the substrate 11. The semiconductor layer 20 includes an n-type GaN layer (hereinafter abbreviated as n-type layer) 21, an MQW (Multi Quantum Well) layer 23, and a p-type GaN layer (hereinafter abbreviated as p-type layer) 22 from the substrate 11 side. Has a laminated structure. The main light emitting layer in this configuration is the MQW layer 23. As the substrate 11, for example, an insulating material capable of heteroepitaxially growing GaN thereon can be used, such as sapphire.
In the region on one end (right end in FIG. 2) side of the semiconductor layer 20, the p-type layer 22 and the MQW layer 23 are partially removed, and similarly, the p-side electrode 51 connected to the outside The p-type layer 22 and the MQW layer 23 are partially removed also in the region immediately below the pad portion. A transparent electrode 30, an insulating layer 40, a p-side electrode (anode) 51, and an n-side electrode (cathode) 52 are formed on the semiconductor layer 20.

半導体層20中のn型層21、MQW層23、p型層22は、MBE(Molecular Beam Epitaxy)法、あるいはMOCVD(Metal Organic Chemical Vapor Deposition)法によって、基板11上にエピタキシャル成長させることができる。n型層21にはドナーとなる不純物が、p型層22にはアクセプタとなる不純物が適宜ドーピングされる。n型層21の厚さは例えば5.0μm、p型層22の厚さは例えば0.2μm程度とすることができる。また、MQW層23は、例えば数nm〜数10nmの厚さのInGaN、GaN薄膜が複数積層された構造をもち、InGaN、GaNの各層はn型層21、p型層22と同様にエピタキシャル成長により形成される。 The n-type layer 21, the MQW layer 23, and the p-type layer 22 in the semiconductor layer 20 can be epitaxially grown on the substrate 11 by an MBE (Molecular Beam Epitaxy) method or an MOCVD (Metal Organic Chemical Vapor Deposition) method. The n-type layer 21 is appropriately doped with an impurity serving as a donor, and the p-type layer 22 is appropriately doped with an impurity serving as an acceptor. The thickness of the n-type layer 21 can be set to, for example, 5.0 μm, and the thickness of the p-type layer 22 can be set to, for example, about 0.2 μm. Further, the MQW layer 23 has a structure in which a plurality of InGaN and GaN thin films having a thickness of, for example, several nm to several tens of nm are stacked, and each layer of InGaN and GaN is epitaxially grown in the same manner as the n-type layer 21 and the p-type layer 22. It is formed.

透明電極30は、p型層22とオーミック接触が可能で、かつ半導体層20が発する光に対して透明な材料として、例えばITO(Indium−Tin−Oxide)やZnO(Zinc−Oxide)等で構成される。なお、p型層22との間のオーミック性や密着性等を向上させるために、これらの間に、光が充分透過する程度に薄いチタン(Ti)層やニッケル(Ni)層を挿入することもできる。透明電極30のパターニングは、エッチング法、あるいは、所望の箇所以外にフォトレジスト等のマスクを形成してから全面に上記の透明電極材料を成膜し、後でマスクを除去することによって所望の箇所以外の透明電極材料を除去する方法(リフトオフ法)、のいずれかの方法を用いることができる。 The transparent electrode 30 is made of, for example, ITO (Indium-Tin-Oxide) or ZnO (Zinc-Oxide) as a material that can make ohmic contact with the p-type layer 22 and is transparent to light emitted from the semiconductor layer 20. Is done. In addition, in order to improve the ohmic property and adhesion between the p-type layer 22 and the like, a thin titanium (Ti) layer or nickel (Ni) layer is inserted between them so that light is sufficiently transmitted. You can also. The patterning of the transparent electrode 30 is performed by an etching method or by forming a mask such as a photoresist other than a desired portion, forming the transparent electrode material on the entire surface, and then removing the mask later. Any method of removing the transparent electrode material other than the above (lift-off method) can be used.

絶縁層40は、充分な絶縁性をもち、かつ半導体層20が発する光に対して透明な材料で構成され、例えば酸化シリコン(SiO)で構成される。
半導体層20の一方の端部(図2において右端部)側の領域において、この絶縁層40は開口が形成され、露出したn型層21とn側電極52が接続される。また、半導体層20の他方の端部(図2において左端部)に形成されるp側電極51及びn側電極52間においても複数の開口が形成され、n側電極52方向に延伸するp側電極51の延伸部と透明電極30が接続される。
絶縁層40の形成は、例えばCVD(Chemical Vapor Deposition)法等を用いることにより、図2に示される段差部においても、これを被覆性よく形成することが可能である。そのパターニングはエッチング法により行われる。
The insulating layer 40 is made of a material that has sufficient insulating properties and is transparent to the light emitted from the semiconductor layer 20, and is made of, for example, silicon oxide (SiO 2 ).
In the region on one end (right end in FIG. 2) side of the semiconductor layer 20, an opening is formed in the insulating layer 40, and the exposed n-type layer 21 and the n-side electrode 52 are connected. Also, a plurality of openings are formed between the p-side electrode 51 and the n-side electrode 52 formed at the other end portion (left end portion in FIG. 2) of the semiconductor layer 20, and the p-side extends in the direction of the n-side electrode 52. The extending part of the electrode 51 and the transparent electrode 30 are connected.
The insulating layer 40 can be formed with good coverage even at the stepped portion shown in FIG. 2 by using, for example, a CVD (Chemical Vapor Deposition) method. The patterning is performed by an etching method.

p側電極51は、金(Au)等の導電性の高い金属で形成される。n側電極52は、n型層21とオーミック接触がとれる材料で構成される。p側電極51、n側電極52のパターニングは、透明電極30のパターニングと同様に行うことができる。 The p-side electrode 51 is made of a highly conductive metal such as gold (Au). The n-side electrode 52 is made of a material that can make ohmic contact with the n-type layer 21. The p-side electrode 51 and the n-side electrode 52 can be patterned in the same manner as the patterning of the transparent electrode 30.

この構成により、p側電極51は透明電極30を介してp型層22と接続され、n側電極52はn型層21に直接接続される。これにより、p側電極51に正、n側電極52に負の電圧を印加することにより、半導体層20中の発光層(主にMQW層23)を発光させることができる。 With this configuration, the p-side electrode 51 is connected to the p-type layer 22 via the transparent electrode 30, and the n-side electrode 52 is directly connected to the n-type layer 21. Thus, by applying a positive voltage to the p-side electrode 51 and a negative voltage to the n-side electrode 52, the light emitting layer (mainly the MQW layer 23) in the semiconductor layer 20 can emit light.

ここで特徴的なのは、p側電極51は外部と接続されるパッド部とn側電極52方向へ延伸する延伸部とから成るが、p側電極51のパッド部直下の領域においても透明電極30、p型層22及びMQW層23が部分的に除去されていることである。p側電極51のパッド部直下の領域においてはpn接合が形成されないため、図3に示すようにフリップボンディングの際にp側電極51のパッド部に過度の荷重が加わったとしても、発光素子の発光領域はその荷重による影響を受けないため、発光領域の損傷を防止することができる。 What is characteristic here is that the p-side electrode 51 includes a pad portion connected to the outside and an extending portion extending in the direction of the n-side electrode 52, but the transparent electrode 30, even in the region immediately below the pad portion of the p-side electrode 51, That is, the p-type layer 22 and the MQW layer 23 are partially removed. Since a pn junction is not formed in a region immediately below the pad portion of the p-side electrode 51, even if an excessive load is applied to the pad portion of the p-side electrode 51 during flip bonding as shown in FIG. Since the light emitting region is not affected by the load, damage to the light emitting region can be prevented.

図4は、本発明の実施例2に係る発光素子を実装基板上に配置した図である。実施例1では、p側電極51のパッド部直下の領域において、p型層22とMQW層23とが部分的に除去されているが、実施例2では、さらにn型層21も基板11に達するまで除去されている点が異なる。なお、その他の構造は、実施例1に係る発光素子と同様である。
p側電極51のパッド部直下の領域においては半導体層20自体が形成されないため、フリップボンディングの際にp側電極51のパッド部に過度の荷重が加わったとしても、発光素子の発光領域はその荷重の影響を受けず、発光領域の損傷の抑制をより一層高めることが可能となる。
FIG. 4 is a diagram in which a light emitting device according to Example 2 of the present invention is arranged on a mounting substrate. In the first embodiment, the p-type layer 22 and the MQW layer 23 are partially removed in the region immediately below the pad portion of the p-side electrode 51, but in the second embodiment, the n-type layer 21 is also formed on the substrate 11. The difference is that it is removed until it reaches. Other structures are the same as those of the light emitting device according to Example 1.
Since the semiconductor layer 20 itself is not formed in the region immediately below the pad portion of the p-side electrode 51, even if an excessive load is applied to the pad portion of the p-side electrode 51 during flip bonding, the light emitting region of the light emitting element It is possible to further increase the suppression of damage to the light emitting region without being affected by the load.

上記のように、本発明は実施例によって記載したが、この開示の一部をなす論述及び図面はこの発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施形態、実施例及び運用技術が明らかとなろう。
既に述べた実施例の説明においては、p側電極51のパッド部直下の領域における半導体層20を部分的に除去する例を示したが、n側電極52のパッド部直下の領域における半導体層20をn側電極52とn型層21が接続できる範囲で除去することで、フリップボンディングの際にp側電極51だけでなく、n側電極52に過度の荷重が加わった場合においても、発光素子の発光領域の損傷を抑制することが可能である。
また、本実施例においてはフリップタイプの例を示してきたが、フリップタイプではない発光素子においても同様の構造とすることで、例えばワイヤボンディング等の際にp側電極及びn側電極に過度の荷重が加わった場合においても、発光素子の発光領域の損傷を防止できることは明らかである。
このように、本発明はここで記載していない様々な実施例を含むことは勿論である。したがって、本発明の技術的範囲は上記の説明から妥当な特許請求の範囲に係る発明特定事項によってのみ定められるものである。
Although the present invention has been described by way of example as described above, it should not be understood that the discussion and drawings that form part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.
In the description of the embodiment already described, the example in which the semiconductor layer 20 in the region immediately below the pad portion of the p-side electrode 51 is partially removed has been shown, but the semiconductor layer 20 in the region immediately below the pad portion of the n-side electrode 52 has been shown. Is removed within a range in which the n-side electrode 52 and the n-type layer 21 can be connected, so that not only the p-side electrode 51 but also an excessive load is applied to the n-side electrode 52 during flip bonding. It is possible to suppress damage to the light emitting region.
Further, in this embodiment, an example of a flip type has been shown, but a light emitting element that is not a flip type also has a similar structure, so that, for example, an excessive amount is applied to the p-side electrode and the n-side electrode during wire bonding or the like. Obviously, even when a load is applied, damage to the light emitting region of the light emitting element can be prevented.
As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

11 半導体基板
20 半導体層
21 n型GaN層
22 p型GaN層
23 MQW層
30 透明電極
40 絶縁層
51 p側電極
52 n側電極
60 実装基板
70 配線
80 はんだ(導電型バンプボール)
11 Semiconductor substrate 20 Semiconductor layer 21 n-type GaN layer 22 p-type GaN layer 23 MQW layer 30 Transparent electrode 40 Insulating layer 51 p-side electrode 52 n-side electrode 60 Mounting substrate 70 Wiring 80 Solder (conducting bump ball)

Claims (3)

基板上に第1の導電型をもつ第1の半導体層上に前記第1の導電型とは逆の導電型である第2の導電型をもつ第2の半導体層が形成された半導体発光機能層が用いられ、当該半導体発光機能層を発光させるための通電に用いられる2つの電極が共に前記半導体発光機能層における前記第2の半導体層が形成された側の主面上に形成された発光素子であって、 前記半導体発光機能層の一方の端部において前記第2の半導体層が前記主面側から除去された箇所で、前記第1の半導体層と接続するように形成された第1の電極と、 前記第2の半導体層の表面において、他方の端部の側から前記一方の端部の側に向かって延伸して形成された透明電極を具備し、 前記他方の端部に形成される第2の電極は、外部と接続されるパッド部と前記第1の電極へ向かって延伸する延伸部を有し、前記パッド部の直下において前記第2の半導体層が前記主面側から除去され、前記第1の電極と前記第2の電極間において、絶縁層を介して前記延伸部と前記透明電極が接続されることを特徴とする発光素子。 A semiconductor light emitting function in which a second semiconductor layer having a second conductivity type, which is a conductivity type opposite to the first conductivity type, is formed on a first semiconductor layer having a first conductivity type on a substrate. Layer, and two electrodes used for energization for causing the semiconductor light emitting functional layer to emit light are both formed on the main surface of the semiconductor light emitting functional layer on the side where the second semiconductor layer is formed. A first element formed so as to be connected to the first semiconductor layer at a position where the second semiconductor layer is removed from the main surface side at one end of the semiconductor light emitting functional layer. And a transparent electrode formed to extend from the other end side toward the one end portion on the surface of the second semiconductor layer, and formed at the other end portion. The second electrode is connected to the pad portion connected to the outside and the first electrode. An extension portion extending toward the surface, the second semiconductor layer is removed from the main surface side immediately below the pad portion, and an insulating layer is interposed between the first electrode and the second electrode. The extending portion and the transparent electrode are connected to each other. さらに、前記他方の端部に形成される第2の電極の前記パッド部直下において、前記第2の半導体層とともに、前記第1の半導体層が前記主面側から除去されたことを特徴とする請求項1に記載の発光素子。   Further, the first semiconductor layer is removed from the main surface side together with the second semiconductor layer immediately below the pad portion of the second electrode formed at the other end portion. The light emitting device according to claim 1. 前記第1の半導体層はn型窒化物半導体で構成され、前記第2の半導体層はp型窒化物半導体で構成されたことを特徴とする請求項1または2のいずれか1項に記載の発光素子。






3. The device according to claim 1, wherein the first semiconductor layer is made of an n-type nitride semiconductor, and the second semiconductor layer is made of a p-type nitride semiconductor. 4. Light emitting element.






JP2011282755A 2011-12-26 2011-12-26 Light-emitting element Pending JP2013135018A (en)

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Publication number Priority date Publication date Assignee Title
CN105720138A (en) * 2016-02-22 2016-06-29 厦门市三安光电科技有限公司 Light emitting diode and manufacturing method therefor

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Publication number Priority date Publication date Assignee Title
JP2004281581A (en) * 2003-03-13 2004-10-07 Rohm Co Ltd Semiconductor light emitting element
JP2011142324A (en) * 2010-01-07 2011-07-21 Seoul Opto Devices Co Ltd Light emitting diode having a plurality of electrode pads

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004281581A (en) * 2003-03-13 2004-10-07 Rohm Co Ltd Semiconductor light emitting element
JP2011142324A (en) * 2010-01-07 2011-07-21 Seoul Opto Devices Co Ltd Light emitting diode having a plurality of electrode pads

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105720138A (en) * 2016-02-22 2016-06-29 厦门市三安光电科技有限公司 Light emitting diode and manufacturing method therefor

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