JP2013131626A - Wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board which achieves high electric insulation reliability between conductor patterns which are exposed from a solder resist layer and located close to each other.SOLUTION: The wiring board includes: an insulation substrate 1; a first conductor pattern 6a and a second conductor pattern 6b which are formed on a surface of the insulation substrate 1 so as to be located close to each other; a solder resist layer 3 which is deposited on the surface of the insulation substrate 1 and has openings 3b exposing the first conductor pattern 6a and the second conductor pattern 6b, the solder resist layer 3 where an opening edge of each opening 3b is formed traversing between the first conductor pattern 6a and the second conductor pattern 6b; and an electroless plating metal layer deposited on surfaces of the first conductor pattern 6a and the second conductor pattern 6b which are exposed from the openings 3b. The opening edge has bending parts A, each of which bends so as to form a V shape toward the outer side or the inner side of the opening 3b between the first conductor pattern 6a and the second conductor pattern 6b.

Description

  The present invention relates to a wiring board on which a semiconductor element such as a semiconductor integrated circuit element is mounted.

  FIG. 5 shows a conventional wiring board 20 for mounting a semiconductor element S such as a semiconductor integrated circuit element. As shown in FIG. 5, the conventional wiring substrate 20 is formed by arranging a plurality of wiring conductors 12 from the upper surface to the lower surface of the insulating substrate 11 having a mounting portion 11a for mounting the semiconductor element S at the center of the upper surface. . Further, a solder resist layer 13 is deposited on the upper and lower surfaces of the insulating substrate 11 so that a part of the wiring conductor 12 is exposed. The insulating substrate 11 and the solder resist layer 13 are made of a resin-based insulating material including a thermosetting resin such as an epoxy resin. Moreover, the wiring conductor 12 consists of copper-type metal materials, such as copper foil and copper plating, for example.

  A part of the wiring conductor 12 is exposed on the mounting portion 11 a to form a semiconductor element connection pad 14. An electrode T of the semiconductor element S is connected to the semiconductor element connection pad 14 via solder. Further, another part of the wiring conductor 12 is exposed on the lower surface of the insulating substrate 11 to form an external connection pad 15. The external connection pad 15 is connected to a wiring conductor of an external electric circuit board via solder. Note that these semiconductor element connection pads 14 and external connection pads 15 are connected to each other via wiring conductors 12 disposed inside the insulating substrate 11.

  Further, an inspection pad 16 made of a part of the wiring conductor 12 is disposed on the outer peripheral portion of the upper surface of the insulating substrate 11. The inspection pad 16 has a first conductor pattern 16a and a second conductor pattern 16b that are paired with each other. Each of the first conductor pattern 16 a and the second conductor pattern 16 b is electrically connected to a specific semiconductor element connection pad 14. Then, after connecting the electrode T of the semiconductor element S to the semiconductor element connection pad 14, the state of the operation of the semiconductor element S is confirmed by connecting and measuring the probe of the electrical inspection device to the inspection pad 16. Can do.

  Of the solder resist layers 13 deposited on the upper and lower surfaces of the insulating substrate 11, the solder resist layer 13 on the upper surface side is an opening 13 a that individually exposes the semiconductor element connection pads 14 and the first conductors of the inspection pads 16. An opening 13b that exposes a pair of the pattern 16a and the second conductor pattern 16b in a lump is provided. Further, the solder resist layer 13 on the lower surface side has an opening 13c through which the external connection pad 15 is individually exposed.

  In this wiring substrate 20, a nickel plating layer and a gold plating layer are sequentially coated by an electroless plating method on the exposed surface from the solder resist layer 13 in the semiconductor element connection pad 14, the external connection pad 15, and the inspection pad 16. May be worn. By depositing these plating layers, the oxidative corrosion of the semiconductor element connection pad 14, the external connection pad 15, and the inspection pad 16 is prevented, and the connection between the semiconductor element connection pad 14 and the electrode T of the semiconductor element S and the outside. The connection between the connection pad 15 and the wiring conductor of the external electric circuit board and the connection between the inspection pad 16 and the probe of the electrical inspection apparatus are good.

  In order to sequentially deposit the nickel plating layer and the gold plating layer on the surface of the semiconductor element connection pad 14, the external connection pad 15 and the inspection pad 16 exposed from the solder resist layer 13 by electroless plating, The method described is adopted.

  First, a wiring substrate 20 is prepared on which a solder resist layer 13 that exposes the semiconductor element connection pads 14, the external connection pads 15, and the inspection pads 16 is attached.

  Next, the wiring substrate 20 is washed to remove dirt and oxide films on the exposed surfaces of the semiconductor element connection pads 14, the external connection pads 15, and the inspection pads 16. Various types of cleaning such as alkali cleaning, acid cleaning, and pure water cleaning are used for cleaning.

  Next, a palladium catalyst for electroless plating is applied to the exposed surfaces of the cleaned semiconductor element connection pads 14, external connection pads 15, and inspection pads 16. In order to apply the palladium catalyst, a method is adopted in which the wiring board 20 is immersed in the palladium catalyst solution for a predetermined time and then pulled up from the catalyst solution.

  Next, an electroless nickel plating layer is deposited on the surfaces of the semiconductor element connection pad 14, the external connection pad 15, and the inspection pad 16 to which the catalyst is applied. In order to deposit the electroless nickel plating layer, a method in which the wiring board 20 is immersed in the electroless nickel plating solution for a predetermined time and then pulled up from the electroless nickel plating solution is employed.

  Next, the electroless gold plating layer is deposited on the surfaces of the semiconductor element connection pad 14, the external connection pad 15, and the inspection pad 16 to which the electroless nickel plating layer is deposited. In order to deposit the electroless gold plating layer, a method in which the wiring board 20 is immersed in the electroless gold plating solution for a predetermined time and then pulled up from the electroless gold plating solution is employed.

  As described above, the nickel plating layer and the gold plating layer are deposited on the surfaces of the semiconductor element connection pad 14, the external connection pad 15, and the inspection pad 16 exposed from the solder resist layer 13 by the electroless plating method. In addition, the immersion of the wiring board 20 in a palladium catalyst solution, an electroless nickel plating solution, or an electroless gold plating solution is performed in a state where the wiring board 20 is set up vertically. Therefore, the pulling is also performed in a vertically standing state, and after the pulling, it is dried after washing with pure water.

  However, recent wiring boards have been developed with high density and fine wiring, and even in the test pad 16, the first conductor pattern 16a and the second conductor pattern 16b have a narrow distance of, for example, 30 μm or less. Has begun to appear. As described above, when the distance between the first conductor pattern 16a and the second conductor pattern 16b is as narrow as 30 μm or less, electrical insulation between the first conductor pattern 16a and the second conductor pattern 16b is performed. In some cases, the properties were impaired.

  Therefore, as a result of detailed observation by the present inventor, as shown in FIG. 6, when the wiring substrate 20 is pulled up after being immersed in a palladium catalyst solution, an electroless nickel plating solution, or an electroless gold plating solution, the first On the lower end side of the opening 13b of the solder resist layer 13 that exposes the conductor pattern 16a and the second conductor pattern 16b, the first conductor pattern 16a and the second conductor pattern without the catalyst solution or the plating solution being discharged well. Residue R remains between the first conductive pattern 16a and the second conductive pattern 16b, and a small amount of plated metal layer is deposited between the first conductive pattern 16a and the second conductive pattern 16b, thereby reducing electrical insulation. I understood.

JP 2011-129903 A

  An object of the present invention is to provide a wiring board having high electrical insulation reliability between adjacent conductor patterns exposed from a solder resist layer.

  The wiring board of the present invention is attached to the surface of the insulating substrate, the first conductor pattern and the second conductor pattern formed adjacent to each other on the surface of the insulating substrate, and the surface of the insulating substrate, An opening that exposes part of the first conductor pattern and the second conductor pattern is formed, and an opening edge of the opening crosses between the first conductor pattern and the second conductor pattern. A solder resist layer and an electroless plating metal layer deposited on the surfaces of the first conductor pattern and the second conductor pattern exposed from the opening, The opening edge has a bent portion that is bent in a V shape toward the outer side or the inner side of the opening portion between the first conductor pattern and the second conductor pattern.

  According to the wiring wiring of the present invention, the opening edge of the solder resist layer that crosses between the first conductor pattern and the second conductor pattern formed adjacent to each other is formed between the first conductor pattern and the second conductor. Since it has a bent part that bends in a V shape toward the outside or inside of the opening of the solder resist layer between the pattern and the pattern, the wiring board is made into a palladium catalyst solution, an electroless nickel plating solution, or an electroless gold plating solution. When it is pulled up after being immersed, the catalyst solution and the plating solution are well discharged from between the first conductor pattern and the second conductor pattern along the bent portion. Therefore, a trace amount of the plated metal layer is not deposited between the first conductor pattern and the second conductor pattern due to the residue of the catalyst solution or the plating solution, and the electrical insulation reliability between the two is not increased. A high wiring board can be provided.

FIG. 1 is a cross-sectional view and a top view showing an example of an embodiment of a wiring board according to the present invention. FIG. 2 is an enlarged view of a main part of the wiring board shown in FIG. FIG. 3 is a cross-sectional view and a top view showing another example of the embodiment of the wiring board of the present invention. FIG. 4 is an enlarged view of a main part of the wiring board shown in FIG. FIG. 5 is a cross-sectional view and a top view of a conventional wiring board. FIG. 6 is an enlarged view of a main part of the wiring board shown in FIG.

  Next, an example of an embodiment of the wiring board of the present invention will be described with reference to the accompanying drawings. As shown in FIG. 1, the wiring substrate 10 of this example mainly includes an insulating substrate 1, a wiring conductor 2, and a solder resist layer 3.

  The insulating substrate 1 is a substantially rectangular flat plate and is made of a resin-based insulating material. Examples of the resin insulating material include an insulating material obtained by impregnating a glass cloth with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin, or an inorganic insulating filler such as a silicon oxide powder in a thermosetting resin such as an epoxy resin. An insulating material in which is dispersed is preferably used.

  A mounting portion 1 a for mounting the semiconductor element S is formed at the center of the upper surface of the insulating substrate 1. The lower surface of the insulating substrate 1 serves as an external connection surface for connection to an external electric circuit substrate.

  The wiring conductor 2 is made of a copper foil or a copper plating layer having a thickness of about 10 to 20 μm, and is attached from the upper surface to the lower surface of the insulating substrate 1. A part of the wiring conductor 2 is exposed on the mounting portion 1 a of the insulating substrate 1 to form a plurality of semiconductor element connection pads 4. The semiconductor element connection pad 4 is, for example, a circle having a diameter of about 50 to 100 μm. The electrode T of the semiconductor element S is connected to the semiconductor element connection pad 4. Another part of the wiring conductor 2 is exposed on the lower surface of the insulating substrate 1 to form a plurality of external connection pads 5. The external connection pad 5 has a circular shape with a diameter of about 300 to 1000 μm, for example. The external connection pad 5 is connected to a wiring conductor of an external electric circuit board. Note that these semiconductor element connection pads 4 and external connection pads 5 are electrically connected to each other via wiring conductors 2 disposed inside the insulating substrate 1.

  Further, an inspection pad 6 made of a part of the wiring conductor 2 is disposed on the outer peripheral portion of the upper surface of the insulating substrate 1. The inspection pad 6 has a first conductor pattern 6a and a second conductor pattern 6b arranged in pairs. Each of the first conductor pattern 6 a and the second conductor pattern 6 b is electrically connected to a specific semiconductor element connection pad 4. The first conductor pattern 6a and the second conductor pattern 6b have a width of about 20 to 50 μm, and are arranged with an interval of about 20 to 30 μm. Then, after the electrode T of the semiconductor element S is connected to the semiconductor element connection pad 4, the operation state of the semiconductor element S is confirmed by connecting and measuring the probe of the electrical inspection apparatus to the inspection pad 6. Can do.

  The solder resist layer 3 is applied to the upper and lower surfaces of the insulating substrate 1. The solder resist layer 3 on the upper surface side exposes a pair of the first conductor pattern 6a and the second conductor pattern 6b of the opening 3a for individually exposing the semiconductor element connection pads 4 and the test pad 6. And an opening 3b. The solder resist layer 3 on the lower surface side has an opening 3c for exposing the external connection pads 5 individually. Such a solder resist layer 3 is made of a resin-based electrically insulating material having a thickness of about 10 to 30 μm. As the resin-based electrical insulating material for forming the solder resist layer 3, for example, a material obtained by curing a thermosetting resin having photosensitivity such as an acrylic-modified epoxy resin is preferably used.

  An electroless nickel plating layer and an electroless gold plating layer (not shown) are sequentially deposited on the surfaces of the semiconductor element connection pad 4, the external connection pad 5, and the inspection pad 6 exposed from the solder resist layer 3. The thickness of the electroless nickel plating layer is about 0.1 to 3 μm. The thickness of the electroless gold plating layer is about 0.02 to 0.2 μm. By depositing these plating layers, the oxidative corrosion of the semiconductor element connection pad 4, the external connection pad 5, and the inspection pad 6 is prevented, and the connection between the semiconductor element connection pad 4 and the electrode T of the semiconductor element S and the outside. The connection between the connection pad 5 and the wiring conductor of the external electric circuit board and the connection between the inspection pad 6 and the probe of the electrical inspection apparatus are good.

  In order to deposit the electroless nickel plating layer and the electroless gold plating layer on the surfaces of the semiconductor element connection pad 4, the external connection pad 5, and the inspection pad 6 exposed from the solder resist layer 3, it is the same as the conventional method. The method is adopted.

  That is, first, a wiring base 10 is prepared on which a solder resist layer 3 for exposing the semiconductor element connection pads 4, the external connection pads 5, and the inspection pads 6 is applied.

  Next, the wiring substrate 10 is washed to remove the dirt and oxide film on the exposed surfaces of the semiconductor element connection pads 4, the external connection pads 5, and the test pads 6. Various types of cleaning such as alkali cleaning, acid cleaning, and pure water cleaning are used for cleaning.

  Next, a palladium catalyst for electroless plating is applied to the exposed surfaces of the cleaned semiconductor element connection pads 4, external connection pads 5, and inspection pads 6. In order to apply the palladium catalyst, a method is adopted in which the wiring substrate 10 is immersed in the palladium catalyst solution for a predetermined time and then pulled up from the catalyst solution.

  Next, an electroless nickel plating layer is deposited on the surfaces of the semiconductor element connection pad 4, the external connection pad 5 and the inspection pad 6 to which the catalyst is applied. In order to deposit the electroless nickel plating layer, a method in which the wiring substrate 10 is immersed in the electroless nickel plating solution for a predetermined time and then pulled up from the electroless nickel plating solution is employed.

  Next, the electroless gold plating layer is deposited on the surfaces of the semiconductor element connection pad 4, the external connection pad 5 and the inspection pad 6 to which the electroless nickel plating layer is deposited. In order to deposit the electroless gold plating layer, a method in which the wiring substrate 10 is immersed in the electroless gold plating solution for a predetermined time and then pulled up from the electroless gold plating solution is employed.

  As described above, the electroless nickel plating layer and the electroless gold plating layer are deposited on the surfaces of the semiconductor element connection pad 4, the external connection pad 5, and the inspection pad 6 exposed from the solder resist layer 3. In addition, the immersion of the wiring board 10 in a palladium catalyst solution, an electroless nickel plating solution, or an electroless gold plating solution is performed in a state where the wiring substrate 10 is set up vertically. Therefore, the pulling is also performed in a vertically standing state, and after the pulling, it is dried after washing with pure water.

  By the way, in the wiring board 10 of the present example, the opening portion is located at a position where the opening edge of the opening portion 3b of the solder resist 3 exposing the inspection pad 6 crosses between the first conductor pattern 6a and the second conductor pattern 6b. A bent portion A that is bent in a V shape toward the outside of 3b is formed. Thus, the opening edge of the opening 3b has a bent portion A that bends in a V shape toward the outside of the opening 3b between the first conductor pattern 6a and the second conductor pattern 6b. As shown in FIG. 2, when the wiring substrate 10 is dipped in a palladium catalyst solution, an electroless nickel plating solution, or an electroless gold plating solution and then pulled up, the first conductor pattern 6a and the second conductor pattern 6b are On the lower end side of the opening 3b of the solder resist layer 3 to be exposed, the catalyst solution or the plating solution is discharged from between the first conductor pattern 6a and the second conductor pattern 6b through the bent portion A. Therefore, a trace amount of the plated metal layer does not deposit between the first conductor pattern 6a and the second conductor pattern 6b due to the residue R of the catalyst solution or the plating solution, and electrical insulation between the two. A highly reliable wiring board 10 can be provided.

  The bent portion A bent in a V shape tends to have difficulty in forming the bent portion A in a good shape if the width W is less than 15 μm, and if the width W exceeds 50 μm, the first conductor pattern 6a or The area where the second conductor pattern 6b is exposed in the bent portion A is increased, and the exposed shapes of the first conductor pattern 6a and the second conductor pattern 6b are distorted. Therefore, the width W of the bent portion A is preferably in the range of 15 to 50 μm. Further, when the depth D of the bent portion A is less than 15 μm, it is difficult to ensure sufficient electrical insulation reliability between the first conductor pattern 6a and the second conductor pattern 6b, and exceeds 50 μm. And the depth D of the bent part A becomes unnecessarily deep. Therefore, the depth D of the bent portion A is preferably in the range of 15 to 50 μm. Further, it is difficult for the bent portion A to form the bent portion A in a good shape when the angle θ is less than 30 degrees, and when the angle θ exceeds 90 degrees, the first conductor pattern 6a and the second conductor pattern are formed. It becomes difficult to ensure sufficient electrical insulation reliability with 6b. Therefore, the angle θ of the bent portion A is preferably in the range of 30 to 60 degrees.

  In addition, this invention is not limited to an example of embodiment mentioned above, It cannot be overemphasized that a various change is possible if it is the range which does not deviate from the summary of this invention. For example, in the example of the embodiment described above, the bent portion A in which the opening edge of the opening 3b is bent in a V shape toward the outside of the opening 3b between the first conductor pattern 6a and the second conductor pattern 6b. However, as shown in FIG. 3, the opening edge of the opening 3b is V-shaped toward the inside of the opening 3b between the first conductor pattern 6a and the second conductor pattern 6b. You may have the bending part B which bends. 3 and 4, the same parts as those shown in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof is omitted. Also in this case, as shown in FIG. 4, when the wiring board 10 is dipped in a palladium catalyst solution, an electroless nickel plating solution, or an electroless gold plating solution and then pulled up, the first conductor pattern 6a and the second conductor On the lower end side of the opening 3b of the solder resist layer 3 exposing the pattern 6b, the catalyst solution or the plating solution is discharged from between the first conductor pattern 6a and the second conductor pattern 6b through the bent portion B. The Therefore, a trace amount of the plated metal layer does not deposit between the first conductor pattern 6a and the second conductor pattern 6b due to the residue R of the catalyst solution or the plating solution, and electrical insulation between the two. A highly reliable wiring board 10 can be provided.

  The bent portion B bent in a V-shape can sufficiently secure the electrical insulation reliability between the first conductor pattern 6a and the second conductor pattern 6b when the width W is less than 20 μm. When it exceeds 50 μm, the area covering the first conductor pattern 6a and the second conductor pattern 6b increases, and the exposed shape of the first conductor pattern 6a and the second conductor pattern 6b is distorted. Become. Therefore, the width W of the bent portion B is preferably in the range of 20 to 50 μm. Further, if the height H of the bent portion B is less than 10 μm, it is difficult to ensure sufficient electrical insulation reliability between the first conductor pattern 6a and the second conductor pattern 6b, and exceeds 50 μm. And the height H of the bent portion B becomes unnecessarily high. Therefore, the height H of the bent portion B is preferably in the range of 10 to 50 μm. Further, when the angle θ is less than 30 degrees, the bent portion B tends to be difficult to form the bent portion B in a good shape, and when the angle θ exceeds 120 degrees, the first conductor pattern 6a and the first conductor pattern 6a It becomes difficult to ensure sufficient electrical insulation reliability between the two conductor patterns 6b. Therefore, the angle θ of the bent portion B is preferably in the range of 30 to 120 degrees.

DESCRIPTION OF SYMBOLS 1 Insulating board 2 Wiring conductor 3 Solder resist layer 3b Opening part 6a 1st conductor pattern 6b 2nd conductor pattern 10 Wiring board A, B Bending part

Claims (1)

  An insulating substrate; a first conductor pattern and a second conductor pattern formed adjacent to each other on a surface of the insulating substrate; and a surface of the insulating substrate, the first conductor pattern and the first conductor pattern A solder resist layer that has an opening that exposes a part of the two conductor patterns and an opening edge of the opening crosses between the first conductor pattern and the second conductor pattern; An electroless plating metal layer deposited on the surfaces of the first conductor pattern and the second conductor pattern exposed from the opening, wherein the opening edge has the first edge A wiring board having a bent portion bent in a V shape toward the outer side or the inner side of the opening between the conductive pattern and the second conductive pattern.

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