JP2013131605A - Multilayer printed wiring board including anisotropic conductive film - Google Patents

Multilayer printed wiring board including anisotropic conductive film Download PDF

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JP2013131605A
JP2013131605A JP2011279666A JP2011279666A JP2013131605A JP 2013131605 A JP2013131605 A JP 2013131605A JP 2011279666 A JP2011279666 A JP 2011279666A JP 2011279666 A JP2011279666 A JP 2011279666A JP 2013131605 A JP2013131605 A JP 2013131605A
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anisotropic conductive
printed wiring
wiring board
multilayer printed
conductive film
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JP5925482B2 (en
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Miho Terada
美帆 寺田
Kazuki Fujisawa
一樹 藤沢
Seiji Yamamoto
誠二 山本
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Nippon CMK Corp
CMK Corp
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CMK Corp
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Abstract

PROBLEM TO BE SOLVED: To provide a multilayer printed wiring board holding many metal particles, and thereby capable of suppressing an increase in conductive resistance value after reflow.SOLUTION: In a multilayer printed wiring board, a first insulating substrate including, on one face thereof, a wiring pattern and a projecting bump formed in a part of the wiring pattern and a second insulating substrate including, on a face facing the wiring pattern on the first insulating substrate, a wiring pattern and a receiving conductor land receiving the projecting bump are disposed to face each other, a metal particle-containing anisotropic conductive film is held between at least a tip of the projecting bump and the receiving conductor land, and an interlayer insulating resin layer is disposed on a side of the projecting bump.

Description

本発明は、層間接続部の一部に異方性導電膜を利用した一括積層法により製造された多層プリント配線板に関する。   The present invention relates to a multilayer printed wiring board manufactured by a batch lamination method using an anisotropic conductive film as a part of an interlayer connection.

携帯用電子機器によっては、比較的短納期を要求される多層プリント配線板も多くなってきている。顧客要求の短納期に対応すべく、一括積層法による多層プリント配線板も数多く製造されている。   In some portable electronic devices, there are an increasing number of multilayer printed wiring boards that require a relatively short delivery time. Many multi-layer printed wiring boards using the batch lamination method have been manufactured in order to meet customer demand for short delivery times.

図4は、従来技術を示すもので、絶縁基板701の両面に厚い回路702aと702b、薄い回路703a、703bを形成し、その上下にシート状の異方性導電フィルム704aと704bを介して最外層の導体回路706aと706bの間に導電性粒子705a、705bが挟まれ、層間の導通が得られたビルドアップ基板700となっている(特許文献1参照)。   FIG. 4 shows the prior art, in which thick circuits 702a and 702b and thin circuits 703a and 703b are formed on both surfaces of an insulating substrate 701, and the upper and lower sides thereof are sandwiched through sheet-like anisotropic conductive films 704a and 704b. Conductive particles 705a and 705b are sandwiched between conductor circuits 706a and 706b in the outer layer to form a buildup substrate 700 in which conduction between layers is obtained (see Patent Document 1).

図5に示す従来技術のプリント配線板800は、銅箔により配線パターン801が形成されている。その配線パターン801以外の基板表面には、後に接続部を形成すべき部分を除いたほぼ全面に、エポキシ樹脂による絶縁性樹脂802が積層されている。後に接続部を形成すべき部分には銅箔露出部より狭く点状または凸状に銅を含む導電体ペーストの凸部803が形成されている。この導電体ペーストの凸部803は、鉛や銀など他の材料でもよく、導電性を有するものであればよい。この導電体ペーストの印刷は、乾燥後に周囲の絶縁性樹脂802の高さよりも突出する形になるように厚く印刷する。当該凸部803を完全被覆し、絶縁樹脂802と同じ高さまで異方性導電樹脂804が形成され、一括積層することによりプリント配線板800を得ることができる(特許文献2参照)。   A printed wiring board 800 of the prior art shown in FIG. 5 has a wiring pattern 801 formed of copper foil. On the surface of the substrate other than the wiring pattern 801, an insulating resin 802 made of an epoxy resin is laminated on almost the entire surface excluding a portion where a connection portion is to be formed later. A portion where a connection portion is to be formed later is formed with a convex portion 803 of a conductive paste containing copper narrower than the exposed portion of the copper foil in a dotted or convex shape. The convex portion 803 of the conductive paste may be made of other materials such as lead and silver, and may be any conductive material. The conductor paste is printed thickly so as to protrude beyond the height of the surrounding insulating resin 802 after drying. The convex portion 803 is completely covered, the anisotropic conductive resin 804 is formed to the same height as the insulating resin 802, and the printed wiring board 800 can be obtained by stacking together (see Patent Document 2).

特開2001−326469号公報JP 2001-326469 A 特開平11−112150号公報Japanese Patent Laid-Open No. 11-112150

図4に示した従来技術は、シート状の異方性導電フィルム704a,704bを凸状のビアや回路と上層の導体層との間に挟持することにより層間の導通抵抗値を得るものである。しかし、積層工程にて、圧力を基板に掛けた際に異方性導電フィルムの樹脂が層間接続部外に排出されると共に、金属粒子も層間接続部外に相当数の金属粒子が流れてしまうため、必要な金属粒子を凸状のビアや回路と上層の導体層との間で挟持することができず、リフロー後の導通抵抗値の変化率が大きく安定しないという問題点が発生していた。   The prior art shown in FIG. 4 obtains a conductive resistance value between layers by sandwiching sheet-like anisotropic conductive films 704a and 704b between convex vias or circuits and an upper conductor layer. . However, when a pressure is applied to the substrate in the lamination process, the resin of the anisotropic conductive film is discharged out of the interlayer connection portion, and a considerable number of metal particles also flow out of the interlayer connection portion. Therefore, the necessary metal particles cannot be sandwiched between the convex via or circuit and the upper conductor layer, and the rate of change in the conduction resistance value after reflow is greatly unstable. .

図5に示した従来技術は、層間接続部のみに異方性導電ペーストを塗布し、他の層間絶縁層部分は、エポキシ樹脂からなるプリント配線板である。しかし、層絶縁層部分と層間接続部に塗布された異方性導電ペーストの厚みに差がないため、凸状に形成された導電ペーストに挟持される際に、異方性導電膜の樹脂分が、積層プレス工程の圧力で層間接続部外に排出されると共に、金属粒子も一緒に流れてしまうため、必要な数の金属粒子を凸状に形成された導電ペーストと銅箔間に挟持することができず、リフロー後の導通抵抗値の変化率が上昇するという問題が発生していた。   In the prior art shown in FIG. 5, an anisotropic conductive paste is applied only to an interlayer connection portion, and the other interlayer insulating layer portion is a printed wiring board made of an epoxy resin. However, since there is no difference in the thickness of the anisotropic conductive paste applied to the layer insulating layer portion and the interlayer connection portion, when sandwiched between the conductive paste formed in a convex shape, However, since the metal particles are discharged together with the pressure of the laminating press process and the metal particles also flow together, the necessary number of metal particles are sandwiched between the conductive paste formed in a convex shape and the copper foil. In other words, there is a problem that the rate of change of the conduction resistance value after reflow increases.

本発明は、上記の如き従来の問題を、一方の面に、配線パターンと当該配線パターンの一部に形成された凸状のバンプとを備えている第1の絶縁基板と、当該第1の絶縁基板の配線パターンと対向する面に、配線パターンと前記凸状のバンプを受ける受け導体ランドとを備えている第2の絶縁基板とが対向配置され、かつ当該凸状のバンプの少なくとも先端部と受け導体ランドとの間に、金属粒子を含む異方性導電膜が挟持されていると共に、当該凸状のバンプの側方には層間絶縁樹脂層が配置されていることを特徴とする多層プリント配線板により解決したものである。   The present invention solves the above-described conventional problems by providing a first insulating substrate including a wiring pattern and a convex bump formed on a part of the wiring pattern on one surface, and the first insulating substrate. A second insulating substrate having a wiring pattern and a receiving conductor land that receives the convex bump is disposed opposite to a surface of the insulating substrate facing the wiring pattern, and at least a tip portion of the convex bump. And a receiving conductor land, an anisotropic conductive film containing metal particles is sandwiched, and an interlayer insulating resin layer is disposed on the side of the convex bump. This is solved by a printed wiring board.

本発明によれば、凸状のバンプと受け導体ランドとの間に異方性導電膜が層間絶縁層よりも薄く形成される結果、当該凸状のバンプの先端部分と受け導体ランド間に多くの金属粒子が挟持されると共に、異方性導電膜に含有されている樹脂で凸状のバンプと受け導体ランド間が接合されているため、導通抵抗値の変化率を抑制することが可能となる。   According to the present invention, the anisotropic conductive film is formed thinner than the interlayer insulating layer between the convex bump and the receiving conductor land, and as a result, there are many between the tip portion of the convex bump and the receiving conductor land. Since the metal particles are sandwiched between the bumps and the receiving conductor lands by the resin contained in the anisotropic conductive film, the rate of change in the conduction resistance value can be suppressed. Become.

本発明多層プリント配線板の製造例を示す概略断面工程説明図。The schematic cross-sectional process explanatory drawing which shows the manufacture example of this invention multilayer printed wiring board. 図1に引き続く概略断面工程説明図。FIG. 2 is a schematic cross-sectional process explanatory diagram subsequent to FIG. 1. 本発明の多層プリント配線板の概略断面説明図。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic sectional explanatory view of a multilayer printed wiring board according to the present invention. 従来の多層プリント配線板の概略断面説明図。Schematic cross-sectional explanatory drawing of the conventional multilayer printed wiring board. 他の従来の多層プリント配線板の概略断面説明図。The schematic cross-section explanatory drawing of another conventional multilayer printed wiring board.

以下、本発明多層プリント配線板の製造例を図1(a)〜(d)及び図2(e)〜(f)を用いて説明すると共に、本発明多層プリント配線板の構造例を図3を用いて説明する。   Hereinafter, manufacturing examples of the multilayer printed wiring board of the present invention will be described with reference to FIGS. 1A to 1D and FIGS. 2E to 2F, and structural examples of the multilayer printed wiring board of the present invention will be described with reference to FIG. Will be described.

図1(a)に示すように、まず表裏両面に導体層を備えた絶縁基板100を用意し、その一方の面に配線パターン101を形成すると共に、前記配線パターン101の一部で層間接続部に該当する部分に凸状のバンプ102を配置する。当該バンプの高さは配線パターン101上で30〜40μm程度、またバンプ径はφ100〜250μm程度が好ましい。
次いで、絶縁基板100の表裏の導体層に粗化処理を施す。当該粗化処理工程としては、物理研磨や化学研磨が適宜選択されるが、安定した粗化層(図示せず)を形成するために、化学研磨処理を施すことが好ましい(例えば、第二銅錯体と有機酸塩とを配合した液によってエッチングすることが、粗化面が均一な凹凸になり層間絶縁樹脂と導体層の密着性を向上させるためには有効である)。
尚、当該絶縁基板100の表裏は、ビアフィルによる銅めっきの充填あるいは導電性ペーストにより接続されている。
As shown in FIG. 1A, first, an insulating substrate 100 having conductor layers on both front and back surfaces is prepared, and a wiring pattern 101 is formed on one surface thereof. Convex bumps 102 are disposed in the portions corresponding to the above. The height of the bump is preferably about 30 to 40 μm on the wiring pattern 101 and the bump diameter is preferably about φ100 to 250 μm.
Next, a roughening process is performed on the front and back conductor layers of the insulating substrate 100. As the roughening treatment step, physical polishing or chemical polishing is appropriately selected. However, in order to form a stable roughening layer (not shown), it is preferable to perform chemical polishing treatment (for example, cupric copper). Etching with a solution in which a complex and an organic acid salt are mixed is effective in order to improve the adhesion between the interlayer insulating resin and the conductor layer because the roughened surface has uniform irregularities.
In addition, the front and back of the said insulating substrate 100 are connected by the filling of copper plating by a via fill or a conductive paste.

次いで、図1(b)に示すように、絶縁基板100の凸状のバンプ102の箇所に当該バンプ径よりも50〜150μm大きく開口させた状態で絶縁樹脂103を塗布する。当該塗布工程で塗布された絶縁樹脂103の厚みは、層間絶縁抵抗を確保するため、配線パターン101上で70〜80μm程度が好ましい。絶縁樹脂103の塗布方法や樹脂の組成によっては、絶縁樹脂103を複数回に分けて形成することも可能である。(例えば、スクリーン印刷法で、凸状のバンプ部分をバンプ径より開口させたスクリーン版を使用し、絶縁樹脂103を塗布することで第1絶縁層を形成、仮乾燥後、同じ工程で開口径を絞った状態で第2絶縁層を形成することで層間絶縁樹脂層の厚みを安定的に確保することもできる)。
ここで、層間絶縁樹脂103は、主に球形の無機フィラーが50〜70wt%混入されているものが望ましい。層間絶縁樹脂103に無機フィラーが混入されることで、次工程の積層工程で異方性導電樹脂104と層間絶縁樹脂103の樹脂の流動性を制御することが可能となる。また、層間絶縁樹脂103に無機フィラーが含有していることで、完成後の多層プリント配線板としての層間絶縁層の温度変化による線膨張係数を小さく押さえることができる。層間接続樹脂の熱による収縮を押さえることで層間接続部に与える影響が少なく、導通抵抗値の変化率の安定化に繋がる。
Next, as shown in FIG. 1B, the insulating resin 103 is applied to the convex bumps 102 of the insulating substrate 100 in a state where the bumps are opened by 50 to 150 μm larger than the bump diameter. The thickness of the insulating resin 103 applied in the applying process is preferably about 70 to 80 μm on the wiring pattern 101 in order to ensure interlayer insulation resistance. Depending on the application method of the insulating resin 103 and the resin composition, the insulating resin 103 can be formed in a plurality of times. (For example, by screen printing, using a screen plate having convex bump portions opened from the bump diameter, the first insulating layer is formed by applying the insulating resin 103, and after temporary drying, the opening diameter is the same in the same step. The thickness of the interlayer insulating resin layer can also be stably secured by forming the second insulating layer in a state where the pressure is reduced.
Here, it is desirable that the interlayer insulating resin 103 is mainly mixed with 50 to 70 wt% of a spherical inorganic filler. By mixing the inorganic filler into the interlayer insulating resin 103, the fluidity of the anisotropic conductive resin 104 and the resin of the interlayer insulating resin 103 can be controlled in the subsequent stacking process. Further, since the interlayer insulating resin 103 contains an inorganic filler, the coefficient of linear expansion due to a temperature change of the interlayer insulating layer as a completed multilayer printed wiring board can be reduced. By suppressing the shrinkage due to heat of the interlayer connection resin, there is little influence on the interlayer connection portion, which leads to stabilization of the change rate of the conduction resistance value.

次いで、塗布した絶縁樹脂103を100℃〜130℃で15分〜80分間仮乾燥した後、図1(c)に示すように、凸状のバンプ102部分に金属粒子105を含む異方性導電樹脂104を塗布する。当該異方性導電樹脂104は、塗布した状態で20〜30μmの厚みで形成されることが好ましい。特に、次工程の積層工程で、異方性導電樹脂104に含まれる樹脂分と一緒に金属粒子105が層間接続部外に排出されることを防ぐためにも凸状のバンプ102の先端部分に異方性導電樹脂104を薄く塗布(塗布状態で20〜30μm)することが、導通抵抗値の変化率を抑える上で有効である。
次いで、異方性導電樹脂104を100℃〜130℃で10分〜50分間仮乾燥する。
Next, the applied insulating resin 103 is temporarily dried at 100 ° C. to 130 ° C. for 15 minutes to 80 minutes, and then, as shown in FIG. 1C, the anisotropic conductive material including the metal particles 105 in the convex bump 102 portion. Resin 104 is applied. The anisotropic conductive resin 104 is preferably formed with a thickness of 20 to 30 μm in a coated state. In particular, in order to prevent the metal particles 105 from being discharged out of the interlayer connection portion together with the resin component contained in the anisotropic conductive resin 104 in the subsequent lamination step, the tip of the convex bump 102 is different. It is effective to thinly apply the anisotropic conductive resin 104 (20 to 30 μm in the applied state) in order to suppress the change rate of the conduction resistance value.
Next, the anisotropic conductive resin 104 is temporarily dried at 100 to 130 ° C. for 10 to 50 minutes.

次いで、図1(d)に示すように、絶縁基板100に設けられた凸状のバンプ102に対向する受け導体ランド106を備えた絶縁基板200を用意する。当該絶縁基板200は、凸状のバンプ102と対向する面に、予め配線パターン101や受け導体ランド106が形成されている。当該絶縁基板200に設けられた導体層も物理的あるいは化学的研磨により粗化処理を施すが、安定した粗化層(図示せず)を形成するために、化学研磨処理を施すことが好ましい。(例えば、第二銅錯体と有機酸塩とを配合した液によってエッチングすることが、粗化面が均一な凹凸になり層間絶縁樹脂と導体層の密着性を向上させるためには有効である)。
尚、当該絶縁基板200の表裏は、ビアフィルによる銅めっきの充填あるいは導電性ペーストにより接続さている。
Next, as shown in FIG. 1D, an insulating substrate 200 including a receiving conductor land 106 facing the convex bump 102 provided on the insulating substrate 100 is prepared. The insulating substrate 200 has a wiring pattern 101 and a receiving conductor land 106 formed in advance on the surface facing the convex bump 102. Although the conductor layer provided on the insulating substrate 200 is also roughened by physical or chemical polishing, it is preferable to perform chemical polishing to form a stable roughened layer (not shown). (For example, etching with a liquid containing a cupric complex and an organic acid salt is effective for improving the adhesion between the interlayer insulating resin and the conductor layer because the roughened surface has uniform irregularities) .
The front and back surfaces of the insulating substrate 200 are connected by filling with copper plating with via fill or conductive paste.

次いで、絶縁基板100に設けられた凸状のバンプ102と絶縁基板200に設けられた受け導体ランド106の位置決めをするが、この位置決め方法としては、例えば光学カメラで位置決めマークを認識する方法やX線カメラによる穴位置での位置決め方法が適宜選択される。あるいは、次工程のピンラミネーションによる積層方法などで位置決めしても構わない。
次いで、積層プレスで積層する。積層条件は、使用されるエポキシ樹脂の組成に応じて適宜選択される。例えば、高温時の保持条件(本硬化条件)として、180℃45分以上、保持温度までの昇温速度として3℃/分程度が好ましい。
当該積層工程での加熱・加圧によって、異方性導電樹脂104が層間絶縁樹脂103より先に溶融粘度が低くなることで、異方性導電樹脂104に含まれる余分な樹脂が、層間接続部外に排出されるので、図2(e)に示すように、凸状のバンプ102と受け導体ランド106間に必要な数の金属粒子105が挟持される結果、導通抵抗値の変化率を抑制する効果がある。
Next, the convex bumps 102 provided on the insulating substrate 100 and the receiving conductor lands 106 provided on the insulating substrate 200 are positioned. As this positioning method, for example, a method of recognizing a positioning mark with an optical camera or X A positioning method at the hole position by the line camera is appropriately selected. Or you may position by the lamination | stacking method by the pin lamination of the next process.
Subsequently, it laminates with a lamination press. Lamination conditions are appropriately selected according to the composition of the epoxy resin used. For example, the holding condition at high temperature (main curing condition) is preferably 180 ° C. for 45 minutes or more, and the heating rate up to the holding temperature is preferably about 3 ° C./min.
Due to the heating / pressurization in the lamination step, the anisotropic conductive resin 104 has a lower melt viscosity than the interlayer insulating resin 103, so that the excess resin contained in the anisotropic conductive resin 104 is removed from the interlayer connection portion. As shown in FIG. 2E, the required number of metal particles 105 are sandwiched between the convex bumps 102 and the receiving conductor lands 106, thereby suppressing the rate of change in the conduction resistance value. There is an effect to.

次いで、図2(f)に示すように、積層工程後、貫通穴を形成し、全面にパネルめっきを施し、貫通めっきスルーホール301を形成し、フォトマスクによるエッチング工程により、外層の配線パターン302形成を施し、さらに、外層のソルダーレジスト303を形成する工程を経て本発明の4層多層プリント配線板300を得ることができる。   Next, as shown in FIG. 2F, after the laminating process, through holes are formed, panel plating is performed on the entire surface, through plated through holes 301 are formed, and an outer layer wiring pattern 302 is formed by a photomask etching process. The four-layer multilayer printed wiring board 300 of the present invention can be obtained through a process of forming and further forming a solder resist 303 as an outer layer.

次に、上記の製造工程で得られた本発明の多層プリント配線板300の構造について、その概略断面説明図を示す図3を用いて説明する。   Next, the structure of the multilayer printed wiring board 300 of the present invention obtained in the above manufacturing process will be described with reference to FIG.

100は第1の絶縁基板で、一方の面に、配線パターン101と当該配線パターン101の一部に形成された凸状のバンプ102とを備えている。
200は、第2の絶縁基板で、前記第1の絶縁基板100の配線パターン101と対向する面に、配線パターン101と当該第1の絶縁基板100の凸状のバンプ102を受ける導体ランド106とを備えている。
これら第1の絶縁基板100と第2の絶縁基板200の表裏は、それぞれビアフィルによる銅めっきの充填あるいは導電ペーストにより接続されている。
当該第1の絶縁基板100と第2の絶縁基板200は対向配置され、凸状のバンプ102の少なくとも先端部と受け導体ランド106との間に、金属粒子105を含む異方性導電膜204が挟持されていると共に、当該凸状のバンプ102の側方には層間絶縁樹脂層203が配置されている。
Reference numeral 100 denotes a first insulating substrate having a wiring pattern 101 and a convex bump 102 formed on a part of the wiring pattern 101 on one surface.
Reference numeral 200 denotes a second insulating substrate, and a conductor land 106 that receives the wiring pattern 101 and the convex bumps 102 of the first insulating substrate 100 on a surface facing the wiring pattern 101 of the first insulating substrate 100. It has.
The front and back surfaces of the first insulating substrate 100 and the second insulating substrate 200 are connected to each other by filling with copper plating with via fill or conductive paste.
The first insulating substrate 100 and the second insulating substrate 200 are arranged to face each other, and an anisotropic conductive film 204 including metal particles 105 is provided between at least the tip portion of the convex bump 102 and the receiving conductor land 106. While being sandwiched, an interlayer insulating resin layer 203 is disposed on the side of the convex bump 102.

当該第1の絶縁基板100と第2の絶縁基板200は、さらに、表裏の導通接続として、貫通めっきスルーホール301と最外層配線パターン302とソルダーレジスト303を備え、全体として4層の多層プリント配線板300となっている。   The first insulating substrate 100 and the second insulating substrate 200 further include a through-plating through hole 301, an outermost layer wiring pattern 302, and a solder resist 303 as a conductive connection between the front and back sides, and a multilayer printed wiring having four layers as a whole. It is a plate 300.

斯かる多層プリント配線板300の構成により、凸状のバンプ102と受け導体ランド106間に多くの金属粒子105が挟持されると共に、異方性導樹脂104に含有されている樹脂で凸状のバンプ102と受け導体ランド106間が接合されているため、初期の導通抵抗値からリフロー後の導通抵抗値が極端に上昇するのを抑制することが可能となる。   With such a configuration of the multilayer printed wiring board 300, a large number of metal particles 105 are sandwiched between the convex bumps 102 and the receiving conductor lands 106, and a convex shape is formed by the resin contained in the anisotropic conductive resin 104. Since the bumps 102 and the receiving conductor lands 106 are joined, it is possible to prevent the conduction resistance value after reflowing from extremely increasing from the initial conduction resistance value.

前記異方性導電膜204としては、金属粒子105、エポキシ樹脂、硬化剤及び溶剤の組成物からなるものが望ましい。すなわち、異方性導電膜204に無機フィラーが含まれないことによって、金属粒子105と凸状のバンプ102と受け導体ランド106間の接触の妨げになることを防止する作用がある。このことにより、より多くの金属粒子105を凸状のバンプ102と受け導体ランド106間に挟持することが可能となり、導通抵抗値の安定化に繋がる。   The anisotropic conductive film 204 is preferably made of a composition of metal particles 105, an epoxy resin, a curing agent, and a solvent. That is, since the anisotropic conductive film 204 does not contain an inorganic filler, there is an effect of preventing the metal particles 105, the convex bumps 102, and the receiving conductor lands 106 from being disturbed. As a result, more metal particles 105 can be sandwiched between the convex bumps 102 and the receiving conductor lands 106, leading to stabilization of the conduction resistance value.

また、当該異方性導電膜204としては、層間絶縁樹脂層203に含まれる樹脂と同じ樹脂を含有するものが望ましい。すなわち、異方性導電膜204に含有されている樹脂と層間絶縁樹脂層203に含まれる樹脂とを同一の樹脂にすることによって、積層工程時の圧力で層間接続部外に排出された樹脂が混ざり合っても相溶性もよく、絶縁信頼性に不具合が生じない。   The anisotropic conductive film 204 preferably contains the same resin as that contained in the interlayer insulating resin layer 203. That is, by making the resin contained in the anisotropic conductive film 204 and the resin contained in the interlayer insulating resin layer 203 the same resin, the resin discharged to the outside of the interlayer connection portion by the pressure during the lamination process can be reduced. Even if mixed, compatibility is good and there is no problem in insulation reliability.

また、当該異方性導電膜204としては、積層工程時の温度たる70℃〜180℃で軟化している粘度が、層間絶縁樹脂層203よりも低いものが望ましい。すなわち、異方性導電膜204の方が、層間絶縁樹脂層203よりも上記記載の温度で軟化している粘度が低いため、層間接続部外に異方性導電膜204に含まれる余分な樹脂が排出されることで、凸状のバンプ102と受け導体ランド106間で必要な導電粒子を挟持し、安定した導通抵抗値を確保することが可能となる。   In addition, the anisotropic conductive film 204 preferably has a viscosity that is lower than that of the interlayer insulating resin layer 203, which is softened at a temperature of 70 ° C. to 180 ° C., which is a temperature during the lamination process. That is, since the anisotropic conductive film 204 is softer at the above-described temperature than the interlayer insulating resin layer 203, the excess resin contained in the anisotropic conductive film 204 outside the interlayer connection portion. As a result, the necessary conductive particles are sandwiched between the convex bump 102 and the receiving conductor land 106, and a stable conduction resistance value can be secured.

また、当該異方性導電膜204に含まれる金属粒子105としては、前記凸状のバンプ102又は前記受けランド106が形成されている銅めっき及び/又は銅箔より硬いものが望ましい。すなわち、凸状のバンプ102及び/又は受け導体ランド106よりも硬い金属粒子105を用いることで、凸状のバンプ102又は受け導体ランド106に金属粒子105が食い込むため、導通抵抗値が安定する。   The metal particles 105 contained in the anisotropic conductive film 204 are preferably harder than copper plating and / or copper foil on which the convex bumps 102 or the receiving lands 106 are formed. That is, by using metal particles 105 that are harder than the convex bumps 102 and / or the receiving conductor lands 106, the metal particles 105 bite into the convex bumps 102 or the receiving conductor lands 106, so that the conduction resistance value is stabilized.

また、当該異方性導電膜204に含まれる金属粒子105としては、金コーティングされているものが望ましい。すなわち、金属粒子105が金コーティングされていることで、金属の表面酸化を抑制し、初期の導通抵抗値の安定化によりリフロー後の導通変化率が抑制されることが可能となる。   The metal particles 105 contained in the anisotropic conductive film 204 are preferably gold-coated. That is, since the metal particles 105 are coated with gold, the surface oxidation of the metal can be suppressed, and the conduction change rate after reflow can be suppressed by stabilizing the initial conduction resistance value.

以上のように、両面絶縁基板100と両面絶縁基板200の間に異方性導電樹脂104と層間絶縁樹脂103を設け、一括積層することで本発明の4層のプリント配線板を得ることができる。特に、層間接続部は、凸状のバンプ102と受け導体ランド106間に異方性導電樹脂104を挟持することによって一括積層部分の導通抵抗を得ることができる。   As described above, the four-layer printed wiring board of the present invention can be obtained by providing the anisotropic conductive resin 104 and the interlayer insulating resin 103 between the double-sided insulating substrate 100 and the double-sided insulating substrate 200 and laminating them together. . In particular, the interlayer connection portion can obtain the conduction resistance of the collectively laminated portion by sandwiching the anisotropic conductive resin 104 between the convex bumps 102 and the receiving conductor lands 106.

本発明は、この4層基板に限定されることはなく、例えば、4層多層プリント配線板の上下に両面の絶縁基板100を用意し、層間接続部と層間絶縁層部に各々異方性導電樹脂104と層間絶縁樹脂103を塗布し、一括積層することで8層の多層プリント配線板を得ることもできる(図示せず)。さらに、両面絶縁基板200の上に両面絶縁基板100を3枚用意し、当該絶縁基板100には、層間接続部と層間絶縁層部に各々異方性導電樹脂104と層間絶縁樹脂103を塗布し、一括積層することで8層の多層プリント配線板を得ることもできる(図示せず)。すなわち、絶縁基板100と他の絶縁基板を適宜組み合わせることによって、必要な構成の多層プリント配線板を得ることができることは言うまでもない。   The present invention is not limited to this four-layer substrate. For example, two-sided insulating substrates 100 are prepared on the upper and lower sides of a four-layer multilayer printed wiring board, and anisotropic conductive layers are respectively formed in the interlayer connection portion and the interlayer insulating layer portion. An 8-layer multilayer printed wiring board can also be obtained by applying the resin 104 and the interlayer insulating resin 103 and laminating them together (not shown). Further, three double-sided insulating substrates 100 are prepared on the double-sided insulating substrate 200, and anisotropic conductive resin 104 and interlayer insulating resin 103 are applied to the insulating substrate 100 on the interlayer connection portion and the interlayer insulating layer portion, respectively. Also, an eight-layer multilayer printed wiring board can be obtained by stacking together (not shown). That is, it is needless to say that a multilayer printed wiring board having a necessary configuration can be obtained by appropriately combining the insulating substrate 100 and another insulating substrate.

試験例
下記試験基板1〜5(n=10)について、初期の導通抵抗値とリフロー後の導通抵抗値の変化率を測定した。尚、リフロー条件として、ピーク温度260℃で2回処理を行なった。その結果は表1のとおりであった。
Test Example For the following test substrates 1 to 5 (n = 10), the initial conduction resistance value and the change rate of the conduction resistance value after reflow were measured. In addition, as reflow conditions, the treatment was performed twice at a peak temperature of 260 ° C. The results are shown in Table 1.

試験基板1:金コーティングした金属粒子、エポキシ樹脂(層間絶縁樹脂層に含まれる樹脂と同一)、硬化剤及び溶剤の組成物からなる異方性導電膜を、第1の絶縁基板の凸状バンプに25μmの厚みで形成した図3に示される4層のプリント配線板
試験基板2:異方性導電膜の厚みを70μm(層間絶縁樹脂層の厚さと同一)とした以外は試験基板1と同一
試験基板3:異方性導電膜に使用されるエポキシ樹脂の組成と層間絶縁樹脂層に使われるエポキシ樹脂の組成とを違うものにした以外は試験基板1と同一
試験基板4:異方性導電樹脂に更に無機フィラーを含有させた以外は試験基板1と同一
試験基板5:金コーティングしていない金属粒子を用いた以外は試験基板と同一
Test substrate 1: An anisotropic conductive film made of a composition of gold-coated metal particles, epoxy resin (same as resin contained in an interlayer insulating resin layer), curing agent and solvent, and convex bumps of the first insulating substrate 3 printed circuit board test substrate 2 shown in FIG. 3 formed to a thickness of 25 μm: same as test substrate 1 except that the thickness of the anisotropic conductive film is 70 μm (same as the thickness of the interlayer insulating resin layer) Test substrate 3: Same as test substrate 4, except that the composition of the epoxy resin used for the anisotropic conductive film and the composition of the epoxy resin used for the interlayer insulating resin layer are different. Same as test substrate 1 except that the resin further contains an inorganic filler. Test substrate 5: Same as test substrate except that metal particles not coated with gold are used.

上記表1から、異方性導電膜としては、金コーティングした金属粒子と層間絶縁樹脂層に含まれる樹脂と同一の樹脂を含有し、無機フィラーを含有しない組成物を用い、層間絶縁樹脂層より薄く形成した方が、リフロー後の導通変化率をより抑制できることが明らかである。   From Table 1 above, as the anisotropic conductive film, a composition containing the same metal resin as that contained in the gold-coated metal particles and the interlayer insulating resin layer and containing no inorganic filler was used. It is clear that the thinner one can further suppress the conduction change rate after reflow.

100:第1の絶縁基板
101:配線パターン
102:凸状のバンプ
103:層間絶縁樹脂
104:異方性導電樹脂
105:金属粒子
106:受け導体ランド
203:層間絶縁樹脂層
204:異方性導電膜
300:多層プリント配線板
301:貫通めっきスルーホール
302:最外層の配線パターン
303:外層のソルダーレジスト
100: first insulating substrate 101: wiring pattern 102: convex bump 103: interlayer insulating resin 104: anisotropic conductive resin 105: metal particles 106: receiving conductor land 203: interlayer insulating resin layer 204: anisotropic conductive Film 300: Multilayer printed wiring board 301: Through-plating through hole 302: Outermost layer wiring pattern 303: Outer layer solder resist

Claims (6)

一方の面に、配線パターンと当該配線パターンの一部に形成された凸状のバンプとを備えている第1の絶縁基板と、当該第1の絶縁基板の配線パターンと対向する面に、配線パターンと前記凸状のバンプを受ける受け導体ランドとを備えている第2の絶縁基板とが対向配置され、かつ当該凸状のバンプの少なくとも先端部と受け導体ランドとの間に、金属粒子を含む異方性導電膜が挟持されていると共に、当該凸状のバンプの側方には層間絶縁樹脂層が配置されていることを特徴とする多層プリント配線板。   A first insulating substrate having a wiring pattern and convex bumps formed on a part of the wiring pattern on one surface, and a wiring on a surface facing the wiring pattern of the first insulating substrate. A second insulating substrate having a pattern and a receiving conductor land that receives the convex bump is disposed oppositely, and metal particles are disposed between at least the tip of the convex bump and the receiving conductor land. A multilayer printed wiring board, wherein an anisotropic conductive film is sandwiched, and an interlayer insulating resin layer is disposed on a side of the convex bump. 前記記載の異方性導電膜が、金属粒子、エポキシ樹脂、硬化剤及び溶剤の組成物からなることを特徴とする請求項1に記載の多層プリント配線板。   The multilayer printed wiring board according to claim 1, wherein the anisotropic conductive film is composed of a composition of metal particles, an epoxy resin, a curing agent, and a solvent. 前記記載の異方性導電膜が、層間絶縁樹脂層に含まれる樹脂と同じ樹脂を含有していることを特徴とする請求項1又は2に記載の多層プリント配線板。   The multilayer printed wiring board according to claim 1, wherein the anisotropic conductive film contains the same resin as that contained in the interlayer insulating resin layer. 前記記載の異方性導電膜の積層工程時の温度たる70℃〜180℃で軟化している粘度が、層間絶縁樹脂よりも低いことを特徴とする請求項1〜3の何れか1項に記載の多層プリント配線板。   The viscosity which has been softened at 70 ° C. to 180 ° C., which is the temperature during the lamination step of the anisotropic conductive film, is lower than that of the interlayer insulating resin. The multilayer printed wiring board as described. 異方性導電膜に含まれる金属粒子が、前記凸状のバンプ又は前記受け導体ランドの銅めっき及び/又は銅箔より硬いことを特徴とする請求項1〜4の何れか1項に記載の多層プリント配線板。   5. The metal particle contained in the anisotropic conductive film is harder than copper plating and / or copper foil of the convex bump or the receiving conductor land. 6. Multilayer printed wiring board. 前記記載の異方性導電膜に含まれる金属粒子が、金コーティングされていることを特徴とする請求項1〜5の何れか1項に記載の多層プリント配線板。   The multilayer printed wiring board according to any one of claims 1 to 5, wherein the metal particles contained in the anisotropic conductive film are coated with gold.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10284817A (en) * 1997-04-03 1998-10-23 Hitachi Chem Co Ltd Circuit connecting structure
JP2009016414A (en) * 2007-07-02 2009-01-22 Panasonic Corp Electronic circuit device and electronic apparatus using the same, and manufacturing method of the electronic circuit device
JP2009170898A (en) * 2007-12-17 2009-07-30 Hitachi Chem Co Ltd Circuit connecting material and connecting structure of circuit member
JP2011055005A (en) * 2010-12-09 2011-03-17 Sony Chemical & Information Device Corp Junction body, and method of manufacturing junction body

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10284817A (en) * 1997-04-03 1998-10-23 Hitachi Chem Co Ltd Circuit connecting structure
JP2009016414A (en) * 2007-07-02 2009-01-22 Panasonic Corp Electronic circuit device and electronic apparatus using the same, and manufacturing method of the electronic circuit device
JP2009170898A (en) * 2007-12-17 2009-07-30 Hitachi Chem Co Ltd Circuit connecting material and connecting structure of circuit member
JP2011055005A (en) * 2010-12-09 2011-03-17 Sony Chemical & Information Device Corp Junction body, and method of manufacturing junction body

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