JP2013125801A - エッチング方法及び半導体装置の製造方法 - Google Patents
エッチング方法及び半導体装置の製造方法 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
- H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
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Abstract
【解決手段】 実施形態に係るエッチング方法によれば、半導体基板1上に、第1の金属元素を含む被エッチング膜3が形成される。前記被エッチング膜3上に、第2の金属元素を含有するカーバイド層4が形成される。前記カーバイド層4がエッチングされる。前記カーバイド層4をマスクとして、前記被エッチング膜3がエッチングされる。
【選択図】図1
Description
第1の実施形態に係るエッチング方法について以下説明する。
第2の実施形態においては、半導体装置の製造方法について以下説明する。本実施形態は、第1の実施形態に係るエッチング方法を半導体装置としての磁気ランダムアクセスメモリの製造方法に適用したものである。
以上の製造工程により、第2の実施形態に係る半導体装置として磁気ランダムアクセスメモリを形成する。
2…層間絶縁膜
3…被エッチング膜
4…カーバイド層
5…ハードマスク層
6…磁気抵抗効果素子
7…下部電極
8…配向制御膜
9…第1の磁性層
10…第1の界面磁性層
11…非磁性層
12…第2の界面磁性層
13…第2の磁性層
14…上部電極
16…素子分離絶縁膜
17…ゲート絶縁膜
18…ゲート電極
19…窒化膜
20…スペーサ膜
21…第1の絶縁膜
22…第1のコンタクトプラグ
23…窒化膜
24…第2のコンタクトプラグ
25…第2の絶縁膜
26…第3のコンタクトプラグ
27…第4のコンタクトプラグ
28…酸化膜
29…第1の配線
30…第3の絶縁膜
31…ビアプラグ
32…酸化膜
33…第2の配線
S…ソース領域
D…ドレイン領域
WL…ワード線
Claims (5)
- 半導体基板上に第1の金属元素を含む被エッチング膜を形成する工程と、
前記被エッチング膜上に第2の金属元素を含有するカーバイド層を形成する工程と、
前記カーバイド層をエッチングする工程と、
前記カーバイド層をマスクとして前記被エッチング膜をエッチングする工程と、
を有するエッチング方法。 - 前記第1の金属元素は、Pt、Au、Ag、Ir、Pd、Rh、Ru又はOsから選ばれる元素であり、前記第2の金属元素は、Ti、Ta、W、Mo、Nb又はHfから選ばれる元素であることを特徴とする請求項1に記載のエッチング方法。
- 前記被エッチング膜のエッチングは、Cl2ガス及びO2ガスを供給した状態でプラズマエッチングであることを特徴とする請求項1又は請求項2に記載のエッチング方法。
- 基板上方に下部電極、磁気抵抗効果素子、及び上部電極から構成され、第1の金属元素を含む積層構造を形成する工程と、
前記積層構造上に前記第1の金属元素を含有するカーバイド層を形成する工程と、
前記カーバイド層をエッチングする工程と、
前記カーバイド層をマスクとして、前記上部電極、前記磁気抵抗効果素子、及び前記下部電極をエッチングする工程と、
を有する半導体装置の製造方法。 - 前記第1の金属元素は、Pt、Au、Ag、Ir、Pd、Rh、Ru又はOsから選ばれる元素であり、前記第2の金属元素は、Ti、Ta、W、Mo、Nb又はHfから選ばれる元素であることを特徴とする請求項4に記載の半導体装置の製造方法。
Priority Applications (2)
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JP2011272844A JP2013125801A (ja) | 2011-12-13 | 2011-12-13 | エッチング方法及び半導体装置の製造方法 |
US13/713,388 US20130149795A1 (en) | 2011-12-13 | 2012-12-13 | Etching method and method of manufacturing semiconductor device |
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JP2011272844A JP2013125801A (ja) | 2011-12-13 | 2011-12-13 | エッチング方法及び半導体装置の製造方法 |
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JP (1) | JP2013125801A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111009462A (zh) * | 2019-12-17 | 2020-04-14 | 中国科学院微电子研究所 | 一种钽掩模的制备方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH04303928A (ja) * | 1991-03-30 | 1992-10-27 | Toshiba Corp | 薄膜パターン形成方法 |
JP2002510452A (ja) * | 1997-06-30 | 2002-04-02 | サン・マイクロシステムズ・インコーポレーテッド | 高性能多層スイッチ要素用探索エンジン・アーキテクチャ |
JP2006278456A (ja) * | 2005-03-28 | 2006-10-12 | Ulvac Japan Ltd | トンネル接合素子のエッチング加工方法 |
WO2010050337A1 (ja) * | 2008-10-31 | 2010-05-06 | 日本電気株式会社 | エッチング方法及び薄膜デバイス |
WO2010090127A1 (ja) * | 2009-02-06 | 2010-08-12 | キヤノンアネルバ株式会社 | プラズマ処理装置、プラズマ処理方法、および被処理基板を備える素子の製造方法 |
Family Cites Families (5)
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US6984529B2 (en) * | 2003-09-10 | 2006-01-10 | Infineon Technologies Ag | Fabrication process for a magnetic tunnel junction device |
KR20100090493A (ko) * | 2009-02-06 | 2010-08-16 | 삼성전자주식회사 | 비휘발성 메모리 장치 및 그 제조 방법 |
US8835324B2 (en) * | 2011-07-01 | 2014-09-16 | United Microelectronics Corp. | Method for forming contact holes |
US8536063B2 (en) * | 2011-08-30 | 2013-09-17 | Avalanche Technology Inc. | MRAM etching processes |
US8652969B2 (en) * | 2011-10-26 | 2014-02-18 | International Business Machines Corporation | High aspect ratio and reduced undercut trench etch process for a semiconductor substrate |
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2011
- 2011-12-13 JP JP2011272844A patent/JP2013125801A/ja active Pending
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2012
- 2012-12-13 US US13/713,388 patent/US20130149795A1/en not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04303928A (ja) * | 1991-03-30 | 1992-10-27 | Toshiba Corp | 薄膜パターン形成方法 |
JP2002510452A (ja) * | 1997-06-30 | 2002-04-02 | サン・マイクロシステムズ・インコーポレーテッド | 高性能多層スイッチ要素用探索エンジン・アーキテクチャ |
JP2006278456A (ja) * | 2005-03-28 | 2006-10-12 | Ulvac Japan Ltd | トンネル接合素子のエッチング加工方法 |
WO2010050337A1 (ja) * | 2008-10-31 | 2010-05-06 | 日本電気株式会社 | エッチング方法及び薄膜デバイス |
WO2010090127A1 (ja) * | 2009-02-06 | 2010-08-12 | キヤノンアネルバ株式会社 | プラズマ処理装置、プラズマ処理方法、および被処理基板を備える素子の製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111009462A (zh) * | 2019-12-17 | 2020-04-14 | 中国科学院微电子研究所 | 一种钽掩模的制备方法 |
CN111009462B (zh) * | 2019-12-17 | 2022-11-15 | 中国科学院微电子研究所 | 一种钽掩模的制备方法 |
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