JP2013110882A - Charge pump circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid latch-up of a MOS transistor occurring when a voltage having a reverse polarity to a target voltage is applied to an output terminal due to, for example, a supply fault.SOLUTION: Bulk-voltage switching MOS transistors M1 and M2 are respectively provided between a bulk terminal and the ground and between a source and the bulk terminal of the transfer MOS transistor N1 interposed between a flying capacitor Cin and an output capacitor Cout. When an output voltage VOUT is smaller than a reference voltage Vref1, the MOS transistor M1 is turned off and the MOS transistor M2 is turned on, and then the output voltage VOUT is supplied to the bulk terminal. When the output voltage VOUT is less than or equal to the reference voltage Vref1, the MOS transistor M1 is turned on and the MOS transistor M2 is turned off, and then a ground voltage is supplied to the bulk terminal.

Description

  The present invention relates to a charge pump circuit.

Conventionally, charge pump circuits are often used as circuits for driving liquid crystal panels and LEDs. This charge pump circuit is a circuit that takes a voltage of a battery or the like as an input voltage and boosts the input voltage to a negative voltage or boosts the input voltage to a positive voltage higher than the battery voltage.
FIG. 3 is a circuit diagram showing an example of a conventional charge pump circuit, which is a circuit for generating a negative voltage.

  The charge pump circuit 100 shown in FIG. 3 receives the input voltage Vin and stores charge in the flying capacitor Cin, charge MOS transistors P1 and N2 that are switches for storing charge in the flying capacitor Cin, and the flying capacitor Cin. Output capacitor Cout that stores the stored charge and outputs it as an output voltage, transfer MOS transistors N1 and N3 that are switches for transferring the charge stored in the flying capacitor Cin to the output capacitor Cout, and the MOS transistors N1 to N3 And Drivers 1 to 4 that drive P1 and P1, respectively.

The charge MOS transistor P1 is a P-channel MOS transistor, and the charge MOS transistor N2 and the transfer MOS transistors N1 and N3 are N-channel MOS transistors.
The input voltage Vin is supplied to the source of the charge MOS transistor P1, and the drain of the charge MOS transistor P1 is connected to one end of the flying capacitor Cin and to the ground through the transfer MOS transistor N3.

The other end of the flying capacitor Cin is connected to one end of the output capacitor Cout via the transfer MOS transistor N1 and to the ground via the charge MOS transistor N2. The other end of the output capacitor Cout is connected to the ground.
Then, the potential of the output terminal T1 provided between the transfer MOS transistor N1 and the output capacitor Cout, that is, the voltage across the output capacitor Cout is output as the output voltage VOUT. In the charge pump circuit 100 of FIG. 3, the input voltage Vin is a positive voltage “VDD”, and the output voltage VOUT is a negative voltage “−VDD”.

  The charge pump circuit 100 of FIG. 3 turns on the charge MOS transistors P1 and N2 by the drivers Driver1 to 4 and turns off the transfer MOS transistors N1 and N3, thereby applying the input voltage Vin to the flying capacitor Cin to store charges. . Next, the charge MOS transistors P1 and N2 are turned off and the transfer MOS transistors N1 and N3 are turned on to transfer the charge stored in the flying capacitor Cin to the output capacitor Cout. By repeating the above operation, the output voltage VOUT is boosted to a negative voltage.

  Such a charge pump circuit is described in Patent Document 1, for example.

JP 2009-38850 A

By the way, in the conventional charge pump circuit 100, a voltage having a polarity opposite to the target output voltage (“−VDD” in the case of FIG. 3) is applied to the output terminal T1 due to a power fault (short to positive voltage). If done, latch-up can occur.
With reference to FIG. 4, a latch-up operation that occurs when the output terminal T1 is grounded to a voltage having a polarity opposite to the target output voltage (“−VDD”) will be described with reference to FIG.

FIG. 4 is a diagram for explaining the principle of latch-up generation in the charge pump circuit 100 that generates the conventional negative voltage shown in FIG.
FIG. 4 illustrates a case where the output terminal T1 is grounded to the positive voltage “VDD” whose absolute value is relatively large and latch-up is likely to occur.
The output voltage VOUT is normally applied to the bulk (P +) of the transfer MOS transistor N1 that transfers a charge for generating a negative voltage to the output capacitor Cout.

Therefore, if the output terminal T1 is grounded, the N well (D-NWELL: deep) for separating the bulk (P +) of the transfer MOS transistor N1, the drain (N +) of the transfer MOS transistor N1, and the base (PSUB). The parasitic bipolar transistor B1 formed by the N well is turned on.
When the parasitic bipolar transistor B1 is turned on, the voltage of the N well (D-NWELL: N-type low concentration well) becomes lower than the voltage of the base (PSUB), and the bulk (P +) and N well of the MOS transistor N1. The parasitic bipolar transistor B2 formed by (D-NWELL) and the base (PSUB) is turned on.

  Both the parasitic bipolar transistor B1 and the parasitic bipolar transistor B2 have a thyristor structure, and latchup may occur when the parasitic bipolar transistor B1 and the parasitic bipolar transistor B2 are turned on. That is, as indicated by the arrows in FIG. 4, an overcurrent flows from the output terminal T1 toward the flying capacitor Cin and from the output terminal T1 toward the base (PSUB). Therefore, when latch-up occurs, an overcurrent flows through the transfer MOS transistor N1, and the transfer MOS transistor N1 may operate differently from normal operation.

  The present invention has been made in view of the above points. Even when a voltage having a polarity opposite to the target output voltage is applied to the output terminal, the transfer MOS transistor on the output capacitor side is latched up. An object of the present invention is to provide a charge pump circuit capable of avoiding this.

  A charge pump circuit according to a first aspect of the present invention includes a charge MOS transistor that is interposed between a charge capacitor and ground, is controlled to be in an on state, and stores charge in the charge capacitor, and the charge capacitor; The input voltage is converted into a target voltage and inserted between the output capacitor and stored as an output voltage, and the charge MOS transistor is alternately turned on to transfer the charge of the charge capacitor to the output capacitor. A transfer MOS transistor, and a first bulk voltage control unit that switches a bulk voltage to the transfer MOS transistor, wherein the first bulk voltage control unit has a polarity of the output voltage and a polarity of the target voltage. When they match, the output voltage is used as the bulk voltage. And the polarity of said target voltage of the output voltage is characterized by supplying a ground voltage when a mismatch as the bulk voltage.

  The charge pump circuit according to claim 2 is the charge pump circuit according to claim 1, wherein the first bulk voltage control unit is a first bulk voltage interposed between a bulk of the transfer MOS transistor and a ground. A switching transistor, a second bulk voltage switching transistor interposed between a bulk of the transfer MOS transistor and a terminal on the output capacitor side of the transfer MOS transistor, a polarity of the output voltage, and a polarity of the target voltage A first control signal generating section that generates a first control signal that turns off the first bulk voltage switching transistor when the two coincide with each other and turns on when the first bulk voltage switching transistors do not coincide with each other, and the polarity of the output voltage and the polarity of the target voltage When the second bulk voltage switching transistor is Is characterized by comprising a second control signal generator for generating a second control signal for turning off when a mismatch and down, a.

A charge pump circuit according to a third aspect is the charge pump circuit according to the second aspect, wherein the second control signal generation unit compares the output voltage with a first reference voltage and compares the comparison result with the second control signal. It is characterized in that the comparator is used as the control signal.
A charge pump circuit according to a fourth aspect of the present invention is the charge pump circuit according to the second or third aspect, wherein the first control signal generator shifts the level of the second control signal and performs the first control. It is a level shifter that generates a signal.

  A charge pump circuit according to a fifth aspect of the invention is the charge pump circuit according to any one of the first to fourth aspects, further comprising a second bulk voltage control unit that switches a bulk voltage to the charge MOS transistor. The second bulk voltage controller supplies the source voltage of the charge MOS transistor as the bulk voltage when the polarity of the output voltage matches the polarity of the target voltage, and the polarity of the output voltage and the target voltage When the polarity of the voltage does not match, a ground voltage is supplied as the bulk voltage.

  A charge pump circuit according to a sixth aspect is the charge pump circuit according to the fifth aspect, wherein the second bulk voltage control unit is a third bulk voltage inserted between a bulk of the charge MOS transistor and a ground. The switching transistor, a fourth bulk voltage switching transistor interposed between the bulk of the charge MOS transistor and the source of the charge MOS transistor, and the polarity of the output voltage and the polarity of the target voltage match A third control signal generating section that generates a third control signal that is turned on when the third bulk voltage switching transistor is off and does not match, and the polarity of the output voltage matches the polarity of the target voltage The fourth bulk voltage switching transistor is turned on and turned off when they do not match. It is characterized by comprising a fourth control signal generator for generating the control signal.

A charge pump circuit according to a seventh aspect is the charge pump circuit according to the sixth aspect, wherein the fourth control signal generator compares the output voltage with a second reference voltage, and compares the comparison result with the fourth voltage. It is characterized in that the comparator is used as the control signal.
The charge pump circuit according to claim 8 is the charge pump circuit according to claim 6 or claim 7, wherein the third control signal generator shifts the level of the fourth control signal and performs the third control. It is a level shifter that generates a signal.

  According to the present invention, since the bulk voltage of the transfer MOS transistor inserted between the charging capacitor and the output capacitor is switched according to the polarity of the output voltage, the output voltage of the output voltage is connected to the output terminal of the output voltage. Latch-up of the transfer MOS transistor that occurs when a voltage having a polarity opposite to the target voltage is applied can be avoided.

1 is a circuit diagram illustrating an example of a charge pump circuit according to a first embodiment of the present invention. It is a circuit diagram which shows an example of the charge pump circuit in the 2nd Embodiment of this invention. It is a circuit diagram which shows an example of the conventional charge pump circuit which produces | generates a negative voltage. It is explanatory drawing for demonstrating the conventional latch-up generation | occurrence | production principle.

Embodiments of the present invention will be described below with reference to the drawings.
(First embodiment)
First, a first embodiment will be described.
<Configuration>
FIG. 1 is a circuit diagram showing an example of a configuration of a charge pump circuit 1 according to an embodiment of the present invention.
The charge pump circuit 1 includes bulk voltage switching MOS transistors M1 and M2 for switching the bulk voltage of the transfer MOS transistor N1 on the output capacitor Cout side in the conventional charge pump circuit 100 shown in FIG. 3, and a bulk corresponding to the output voltage VOUT. And a control circuit Cont1 for outputting a control signal for controlling on / off of the voltage switching MOS transistors M1 and M2. However, transfer MOS transistor N1 and bulk voltage switching MOS transistors M1 and M2 are N-channel MOS transistors. With this configuration, the latch-up of the transfer MOS transistor N1 can be prevented. In FIG. 1, the same reference numerals are given to the same parts as those in the prior art.

  That is, as shown in FIG. 1, the input voltage Vin is supplied to the source of the charge MOS transistor P1 made of a P-channel MOS transistor, the drain of the charge MOS transistor P1 is connected to one end of the flying capacitor Cin, and N It is connected to the ground via a transfer MOS transistor N3 made up of a channel type MOS transistor. An input voltage Vin is supplied to the bulk terminal of the charge MOS transistor P1, and the bulk terminal of the transfer MOS transistor N3 is connected to the ground.

  The other end of the flying capacitor Cin is connected to one end of the output capacitor Cout via a transfer MOS transistor N1 made of an N-channel MOS transistor, and connected to the ground via a charge MOS transistor N2 made of an N-channel MOS transistor. Is done. The other end of the output capacitor Cout is connected to the ground. An output voltage VOUT or a ground voltage is supplied to the bulk terminal of the transfer MOS transistor N1. The bulk terminal of the charge MOS transistor N2 is connected to the source.

Then, the potential of the output terminal T1 provided between the transfer MOS transistor N1 and the output capacitor Cout, that is, the voltage across the output capacitor Cout is output as the output voltage VOUT. In the charge pump circuit 1 of FIG. 1, the input voltage Vin is a positive voltage “VDD”, and the output voltage VOUT is a negative voltage “−VDD”.
Further, the bulk voltage switching transistors M1 and M2 connected in series are connected between the source of the transfer MOS transistor N1 and the ground, the drain of the bulk voltage switching transistor M1 is connected to the ground, and the bulk voltage switching transistor M2 is connected to the ground. The source is connected to the source of the transfer MOS transistor N1.

The potential at the connection point between the bulk voltage switching transistors M1 and M2 is supplied to the bulk terminals of the bulk voltage switching transistors M1 and M2, and is also supplied to the bulk terminal of the transfer MOS transistor N1.
The bulk voltage switching transistors M1 and M2 are controlled by the control circuit Cont1.

The control circuit Cont1 includes a comparator Comp1 that compares the reference voltage Vref1 and the output voltage VOUT, and a level shifter Lv1 that level-shifts the output voltage of the comparator Comp1.
The output of the comparator Comp1 is input to the gate of the bulk voltage switching transistor M2, and is also input to the level shifter Lv1.

The output of the level shifter Lv1 is input to the gate of the bulk voltage switching transistor M1.
The comparator Comp1 compares the reference voltage Vref1 and the output voltage VOUT, and outputs a high level voltage signal when the reference voltage Vref1 is larger than the output voltage VOUT, and conversely, when the reference voltage Vref1 is equal to or lower than the reference voltage Vref1. Is output.

Here, the reference voltage Vref1 is a voltage for determining that the output terminal T1 has been faulted, and is a voltage corresponding to a bulk terminal voltage at which latch-up of the transfer MOS transistor N1 can occur.
The level shifter Lv1 is composed of, for example, a CMOS inverter circuit, and operates using the constant voltage Vdd and the output voltage VOUT as a power supply voltage. When a high level voltage signal is input from the comparator Comp1, it is inverted and converted into a low level voltage signal (ie, output voltage VOUT) and output. When a low-level voltage signal is input from the comparator Comp1, it is inverted and converted into a high-level voltage signal (that is, the power supply voltage Vdd) and output.

  With the above configuration, the control circuit Cont1 outputs the output voltage VOUT, which is a negative voltage, from the level shifter Lv1 to the gate of the bulk switching MOS transistor M1 during the normal operation, thereby turning off the bulk switching MOS transistor M1, and the bulk switching MOS transistor A high-level voltage signal composed of the positive power supply voltage of the comparator Comp1 is output from the comparator Comp1 to the gate of M2, and the bulk switching MOS transistor M2 is turned on.

As described above, during normal operation, the control circuit Cont1 outputs a negative voltage to the gate of the bulk switching MOS transistor M1, thereby turning off the bulk switching MOS transistor M1 completely.
Further, when the output terminal T1 is grounded, the control circuit Cont1 outputs the power supply voltage Vdd, which is the positive voltage of the level shifter Lv1, from the level shifter Lv1 to the gate of the bulk voltage switching MOS transistor M1, and then the bulk voltage switching MOS transistor M1 Is turned on, and the ground voltage, which is the power supply voltage on the low potential side of the comparator Comp1, is output to the gate of the bulk voltage switching MOS transistor M2 to turn off the bulk voltage switching MOS transistor M2.

The control circuit Cont1 is not limited to the above-described configuration as long as it can output a voltage that can turn on and off the bulk voltage switching MOS transistors M1 and M2.
The transfer MOS transistors N1 and N3 and the charge MOS transistors P1 and N2 are controlled by drivers Driver 1 to 4, respectively. The drivers 1 and 2 and the level shifter Lv1 operate using the high-potential-side power supply voltage and the voltage between the output voltages VOUT as a power supply voltage, respectively, and the drivers 3 and 4 and the comparator Comp1 are each a high-potential power supply composed of a constant voltage. The voltage between the voltage and the ground operates as a power supply voltage.
The drivers Driver 1 to 4 are controlled by a host device (not shown).

<Operation>
Next, the operation of the charge pump circuit 1 according to the first embodiment of the present invention will be described.
However, in order to simplify the description, in this embodiment, the positive voltage “VDD” is set to “10V”, the input voltage Vin is set to “VDD” (that is, “10V”), and the target output voltage VOUT is set to “−”. VDD (that is, “−10V”) ”. Further, description will be made assuming that the power supply voltage on the high potential side of the comparator Comp1, the drivers Driver1 and Driver2 is “5V”, and the reference voltage Vref1 is “1V”.

(Normal operation)
First, a description will be given of the case where the output terminal T1 is not short-circuited to the input voltage Vin (“VDD”) (ie, the normal operation).
Each MOS transistor is driven and controlled by a host device (not shown) through drivers Driver 1 to 4, first, the charge MOS transistor P1 and the charge MOS transistor N2 are controlled to be turned on, and the transfer MOS transistors N1 and N3 are controlled to be turned off. As a result, the input voltage Vin is applied to the flying capacitor Cin to store charges.

Next, the charge MOS transistors P1 and N2 are controlled to be turned off and the transfer MOS transistors N1 and N3 are controlled to be turned on, whereby the charge stored in the flying capacitor Cin is transferred to the output capacitor Cout.
Here, T2 is a terminal inserted between the flying capacitor Cin and the charge MOS transistor P1, and T3 is a terminal inserted between the flying capacitor Cin, the transfer MOS transistor N1, and the charge MOS transistor N2.

The terminals T2 and T3 are connection terminals when the flying capacitor Cin is externally attached. That is, the charge pump circuit 1 may realize the flying capacitor Cin with an external component. These terminals T2 and T3 are terminals for externally connecting the flying capacitor Cin.
When the on-resistance value of each MOS transistor is “0”, the terminal T2 alternately takes values of “10V” and “0V”, and the terminal T3 alternately takes values of “0V” and “−10V”.

By repeating the above operation alternately, the output voltage VOUT is boosted to a negative voltage, and the negative voltage “−10 V” is output to the output terminal T1.
The control circuit Cont1 receives the output voltage VOUT, that is, the negative voltage “−10 V”, and the negative voltage “−10 V” is input to the comparator Comp1 and the level shifter Lv1.

The comparator Comp1 compares the input output voltage VOUT, that is, the negative voltage “−10 V” with the reference voltage “1 V”. Since the negative voltage “−10 V” is smaller than the reference voltage “1 V”, the comparator Comp1 outputs a high level voltage signal, that is, “5 V” to the gate of the bulk voltage switching MOS transistor M2 and the level shifter Lv1.
The level shifter Lv1 converts and inverts the input high level voltage signal “5V” and outputs “−10 V” which is a low level to the gate of the bulk voltage switching MOS transistor M1.

Therefore, the bulk voltage switching MOS transistor M1 that switches the bulk voltage of the transfer MOS transistor N1 is turned off, and the MOS transistor M2 is turned on. As a result, the output voltage VOUT is supplied to the bulk terminal of the transfer MOS transistor N1.
Further, by outputting “−10 V” which is a negative voltage to the gate of the bulk voltage switching MOS transistor M1, the bulk voltage switching MOS transistor M1 can be completely turned off. That is, since the bulk voltage switching MOS transistor M1 can be completely turned off by the level shifter Lv1, it is possible to more reliably prevent the ground voltage from being transmitted to the output terminal T1.

(When preventing latch-up)
Next, while the output terminal T1 is outputting a negative voltage (“−VDD”), the “input voltage Vin, that is, VDD (“ 10V ”), which is opposite in polarity to the output terminal T1“ −VDD (“−10 V”) ”. The operation in the case of a power failure in ")", that is, the operation for preventing latch-up will be described.
As described above, in the normal operation, since the bulk voltage switching MOS transistor M2 is turned on and the bulk voltage switching MOS transistor M1 is turned off, the bulk node of the transfer MOS transistor N1 is connected to the output voltage VOUT (“−” of the output terminal T1. VDD ").
In this state, when the output terminal T1 is grounded to “input voltage Vin, that is, VDD (“ 10V ”)”, VDD (“10V”) is input to the control circuit Cont1 as the output signal VOUT.

The comparator Comp1 compares VDD (“10V”) with the reference voltage “1V” and outputs, for example, “0V”, which is a low level voltage signal, to the gate of the bulk voltage switching MOS transistor M2 and the level shifter Lv1. The level shifter Lv1 converts the level of the input low level “0V”, inverts it to “10V”, and outputs it to the gate of the bulk voltage switching MOS transistor M1. For this reason, the bulk voltage switching MOS transistor M1 is turned on and M2 is turned off.
When the bulk voltage switching MOS transistor M1 is turned on and M2 is turned off, the ground voltage is supplied to the transfer MOS transistor N1, and the bulk voltage becomes “0V”.

  As a result, the drain voltage of the transfer MOS transistor N1 becomes higher than the bulk voltage of the transfer MOS transistor N1. That is, the forward voltage of the diode formed between the drain and bulk of the transfer MOS transistor N1 becomes a negative voltage. That is, the above-described parasitic (P +) of the transfer MOS transistor N1, the drain (N +) of the transfer MOS transistor N1, and the N well (D-NWELL) for separation from the base (PSUB) described with reference to FIG. The voltage between the base and emitter of the bipolar transistor becomes a negative voltage, and no current flows between the base and emitter. As a result, latch-up of the transfer MOS transistor N1 when the output terminal T1 is grounded can be prevented.

  The ground voltage is applied to the bulk of the transfer MOS transistor N3, and the input voltage Vin (VDD) is applied to the bulk of the charge MOS transistor P1, so that the transfer MOS transistor N3 and the charge MOS transistor N3 are charged. In the MOS transistor P1, latch-up does not occur due to a power fault at the output terminal T1.

  In the above description, the positive voltage “VDD” having the same absolute value as the negative voltage “−VDD” is described as an example, but the positive voltage “VDD” having the same absolute value as the negative voltage “−VDD” has been described. Regardless of the magnitude of the absolute value, the latch-up avoiding operation can be performed in the same manner as described above even if the voltage to be grounded and the output voltage VOUT are opposite in polarity. Can be prevented.

  As described above, the charge pump circuit 1 according to the first embodiment has the above-described configuration and operation. The transfer MOS transistor on the output capacitor side that is generated when the voltage having the opposite polarity to the output voltage VOUT is applied to the output terminal T1. There is an effect that the latch-up of N1 can be prevented.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIG.
<Configuration>
First, the configuration of the charge pump circuit 2 in the second embodiment will be described. FIG. 2 is a circuit diagram showing an example of the charge pump circuit 2 in the second embodiment.
The charge pump circuit 2 according to the second embodiment is different from the charge pump circuit 1 according to the first embodiment shown in FIG. 1 in that a bulk voltage switching MOS for switching the bulk voltage of the charge MOS transistor N2 on the output capacitor Cout side. Transistors M3 and M4 and a control circuit Cont2 that outputs a control signal for controlling on / off of the bulk voltage switching MOS transistors M3 and M4 according to the voltage of the terminal T3 and the output voltage VOUT are provided.

The same parts as those of the charge pump circuit 1 in the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.
In the charge pump circuit 2, as shown in FIG. 2, bulk voltage switching MOS transistors M3 and M4 connected in series are connected between the source and drain of the charge MOS transistor N2.

The control circuit Cont2 has the same configuration as the control circuit Cont1 in the first embodiment, and compares the reference voltage Vref2, the terminal T3 and the source voltage of the transfer MOS transistor N1, and the output of the comparator Comp2. A level shifter Lv2 for level shifting the voltage.
The output of the comparator Comp2 is input to the gate of the bulk voltage switching transistor M4 and also input to the level shifter Lv2.

Further, the output of the level shifter Lv2 is input to the gate of the bulk voltage switching transistor M3.
The comparator Comp2 compares the reference voltage Vref2 with the source voltage of the terminal T3 and the transfer MOS transistor N1 (that is, the voltage according to the output voltage VOUT and the voltage of the terminal T3), and the reference voltage Vref2 is compared with the terminal T3 and the transfer MOS transistor. When the voltage is higher than the voltage between N1, a high level voltage signal (for example, 5V which is the high potential side power supply voltage of the comparator Comp2) is output, and conversely, when the voltage is equal to or lower than the reference voltage Vref2, a low level voltage signal (for example, the comparator A ground potential (for example, 0 V) which is a low-potential side power supply voltage of Comp2 is output.

Here, the reference voltage Vref2 is a voltage for determining that the output terminal T1 or the terminal T3 has been grounded, and is a voltage corresponding to a bulk terminal voltage at which the latch-up of the charge MOS transistor N2 can occur.
The level shifter Lv2 is formed of a CMOS inverter circuit, for example, similarly to the level shifter Lv1, and operates using the constant voltage Vdd and the voltage between the output voltages VOUT as the power supply voltage. When a high level voltage signal (for example, 5 V) is input from the comparator Comp2, it is inverted, converted into a low level voltage signal, and output. That is, the output voltage VOUT (in this case, “−10 V”), which is the low-potential side power supply voltage of the level shifter Lv2, is output. When a low-level voltage signal is input from the comparator Comp2, it is inverted and converted into a high-level voltage signal (that is, the power supply voltage Vdd) and output.

  With the above configuration, during normal operation, the control circuit Cont2 outputs the output voltage VOUT, which is a negative voltage, to the gate of the bulk switching MOS transistor M3 to turn off the bulk switching MOS transistor M3, and to the gate of the bulk switching MOS transistor M4. Then, the comparator Comp2 outputs a high level voltage signal composed of the positive power supply voltage of the comparator Comp2, and controls the bulk switching MOS transistor M4 to be turned on.

As described above, during normal operation, the control circuit Cont2 outputs a negative voltage to the gate of the bulk switching MOS transistor M3, thereby controlling the bulk switching MOS transistor M3 completely off.
The control circuit Cont2 outputs the power supply voltage Vdd, which is a positive voltage of the level shifter Lv2, to the gate of the bulk voltage switching MOS transistor M3 when the output terminal T1 or the terminal T3 is grounded, and the bulk voltage switching MOS transistor M3. Is turned on, and a ground voltage which is a power source voltage on the low potential side of the comparator Comp2 is output to the gate of the bulk voltage switching MOS transistor M4 to control the bulk voltage switching MOS transistor M4 to be turned off.
The control circuit Cont2 is not limited to the configuration described above as long as it can output a voltage that can turn on and off the bulk voltage switching MOS transistors M3 and M4.

<Operation>
Next, the operation of the charge pump circuit 2 according to the second embodiment of the present invention will be described. However, in order to simplify the description, the positive voltage VDD is “10 V”, the input voltage Vin is “VDD”, and the output voltage VOUT is “−VDD”. Further, description will be made assuming that the power supply voltages of the comparators Comp1 and Comp2, the drivers Driver1 and Driver2 are “5V”, and the reference voltages Vref1 and Vref2 are “1V”, respectively.

(Normal operation)
Detailed description of portions overlapping with the charge pump circuit 1 of the first embodiment will be omitted.
During normal operation, the charge pump circuit 2 alternately turns on and off the charge MOS transistor P1 and the charge MOS transistor N2 and the transfer MOS transistors N1 and N3 by the drivers Driver 1 to 4 as in the first embodiment. Then, the electric charge stored in the flying capacitor Cin is transferred to the output capacitor Cout, and the output voltage VOUT is boosted to a negative voltage.

  At this time, the voltage between the terminal T3 and the transfer MOS transistor N1 is input to the control circuit Cont2 and is input to the comparator Comp2 and the level shifter Lv2. Since the voltage at the terminal T3 repeats “0V” and “−10V” as each MOS transistor is controlled to be turned on / off, the voltage between the terminal T3 and the transfer MOS transistor N1 is “0V” and “−10V”. Take the voltage between.

  The comparator Comp2 is smaller than the reference voltage Vref2 (“1V”) when the voltage at the terminal T3 is “0V” or “−10V”, that is, the voltage between the terminal T3 and the transfer MOS transistor N1 is the reference voltage. Since it is smaller than Vref2 (“1V”), a high-level voltage signal is output. That is, the power supply voltage “5 V” on the high potential side of the comparator Comp2 is output to the gate of the bulk voltage switching MOS transistor M4 and the level shifter Lv2.

The level shifter Lv2 inverts the high-level voltage signal “5V” and outputs “−10V” (that is, the low-potential side power supply voltage VOUT of the level shifter Lv2) to the gate of the bulk voltage switching MOS transistor M3. .
Therefore, the MOS transistor M3 that switches the bulk voltage of the charge MOS transistor N2 is turned off, and the bulk voltage switching MOS transistor M4 is turned on. As a result, the voltage at the terminal T3 is supplied to the bulk terminal of the charge MOS transistor N2.

(When preventing latch-up)
In this state, when the output terminal T1 is grounded to the positive voltage VDD (“10V”) that is the input voltage Vin, the positive voltage VDD is input to the control circuits Cont1 and Cont2.
As described in the first embodiment, when the output terminal T1 is in power, the bulk voltage switching MOS transistor M1 is turned on and the bulk voltage switching MOS transistor M2 is turned off. Therefore, the bulk voltage of the transfer MOS transistor N1 becomes “0V”, the forward voltage of the diode formed between the drain and the bulk of the transfer MOS transistor N1 becomes a negative voltage, and the current flows between the base and emitter of the parasitic bipolar transistor. Does not flow. For this reason, the latch-up of the transfer MOS transistor N1 when the output terminal T1 is grounded can be prevented.

Furthermore, the charge pump circuit 2 of the second embodiment can also prevent latch-up of the charge MOS transistor N2 on the output capacitor Cout side when the terminal T3 has a power fault. Hereinafter, an operation when the terminal T3 is grounded to the positive voltage VDD will be described.
When the terminal T3 is grounded to VDD (positive voltage “10V”), the comparator Comp2 compares VDD (“10V”) with the reference voltage Vref2 “1V”, and the voltage signal “0V” which is a low level. Is output to the gate of the bulk voltage switching MOS transistor M4 and the level shifter Lv2. The level shifter Lv2 converts the level of the low level voltage signal “0V” and inverts it, and outputs the voltage signal of “10V” at the high level to the gate of the bulk voltage switching MOS transistor M3. As a result, the bulk voltage switching MOS transistor M3 is turned on, the bulk voltage switching MOS transistor M4 is turned off, and the bulk voltage of the charge MOS transistor N2 becomes “0V”. In the charge MOS transistor N2, the drain voltage becomes higher than the bulk voltage. That is, the forward voltage of the drain-bulk diode of the charge MOS transistor N2 becomes a negative voltage. That is, the voltage between the base and emitter of the parasitic bipolar transistor becomes a negative voltage, and no current flows between the base and emitter. For this reason, the latch-up of the charge MOS transistor N2 when the terminal T3 is grounded can be prevented.

In the above description, the case where the voltage to be grounded is the positive voltage “VDD” having the same absolute value as the negative voltage “−VDD” has been described as an example. However, the voltage is not limited to “VDD” and is opposite to the output voltage VOUT. If it is polarity, latch-up can be prevented.
Here, when the output terminal T1 is grounded, the transfer MOS transistor N1 is turned on and off, and the grounded voltage is not easily transmitted to the output voltage VOUT side. Therefore, the charge MOS transistor N2 is latched more than the transfer MOS transistor N1. Although it is difficult to up, N2 may also latch up.

Further, the charge pump circuit 2 may realize the flying capacitor Cin with an external component. In this case, the terminal T3 that connects the flying capacitor Cin may go to the power.
As described above, by providing the bulk voltage switching MOS transistors M3 and M4 that switch the bulk voltage of the charge MOS transistor N2, the bulk voltage of the charge MOS transistor N2 can also be controlled. Therefore, the charge pump of the second embodiment The circuit 2 can not only prevent the transfer MOS transistor N1 on the output capacitor Cout side, which is generated when a voltage having a polarity opposite to the target output voltage VOUT is applied to the output terminal T1, but also the output terminal T1 has a power fault. In this case, it is possible to prevent the charge MOS transistor N2 on the output capacitor Cout side from being latched up.

Further, it is possible to prevent latch-up of the charge MOS transistor N2 that occurs when a voltage having a polarity opposite to that of the output voltage VOUT is applied to the source of the charge MOS transistor N2 on the output capacitor Cout side, such as when the terminal T3 has a power fault. The effect that it is possible can also be acquired.
Here, in each of the above embodiments, the flying capacitor Cin corresponds to the charging capacitor, and the bulk voltage switching MOS transistors M1 and M2 and the control circuit Cont1 correspond to the first bulk voltage control unit.

The bulk voltage switching MOS transistor M1 corresponds to the first bulk voltage switching transistor, the bulk voltage switching MOS transistor M2 corresponds to the second bulk voltage switching transistor, the level shifter Lv1 corresponds to the first control signal generation unit, The comparator Comp1 corresponds to the second control signal generation unit.
The bulk voltage switching MOS transistors M3 and M4 and the control circuit Cont2 correspond to the second bulk voltage control unit, the bulk voltage switching MOS transistor M3 corresponds to the third bulk voltage switching transistor, and the bulk voltage switching MOS transistor M4. Corresponds to the fourth bulk voltage switching transistor, the level shifter Lv2 corresponds to the third control signal generator, and the comparator Comp2 corresponds to the fourth control signal generator.

  The charge pump circuit of the present invention can be suitably used in the field of power supply systems.

1, 2 Charge pump circuit Cont1, Cont2 Control circuit P1, N2 Charge MOS transistor N1, N3 Transfer MOS transistor Cin Flying capacitor Cout Output capacitor M1-M4 Bulk voltage switching MOS transistor Lv1, Lv2 Level shifter Comp1, Comp2 comparator

Claims (8)

A charge MOS transistor that is interposed between the charging capacitor and the ground and is controlled to be turned on to store electric charge in the charging capacitor;
The charge capacitor and an output capacitor in which an input voltage is converted into a target voltage and stored as an output voltage are interposed between the charge capacitor and the charge MOS transistor. A transfer MOS transistor for transfer to the output capacitor;
A first bulk voltage controller that switches a bulk voltage to the transfer MOS transistor,
The first bulk voltage control unit supplies the output voltage as the bulk voltage when the polarity of the output voltage matches the polarity of the target voltage, and the polarity of the output voltage and the polarity of the target voltage are A charge pump circuit that supplies a ground voltage as the bulk voltage when they do not match. The first bulk voltage controller includes:
A first bulk voltage switching transistor interposed between the bulk of the transfer MOS transistor and ground;
A second bulk voltage switching transistor interposed between the bulk of the transfer MOS transistor and a terminal on the output capacitor side of the transfer MOS transistor;
A first control signal generating unit that generates a first control signal that turns off the first bulk voltage switching transistor when the polarity of the output voltage matches the polarity of the target voltage and turns on when the polarity does not match; ,
A second control signal generating unit that generates a second control signal that turns on the second bulk voltage switching transistor when the polarity of the output voltage matches the polarity of the target voltage and turns off when the polarity does not match; ,
The charge pump circuit according to claim 1, further comprising:   3. The charge pump according to claim 2, wherein the second control signal generation unit is a comparator that compares the output voltage with a first reference voltage and uses the comparison result as the second control signal. circuit.   4. The charge pump circuit according to claim 2, wherein the first control signal generation unit is a level shifter that generates the first control signal by level-shifting the second control signal. . A second bulk voltage control unit that switches a bulk voltage to the charge MOS transistor;
The second bulk voltage controller supplies the source voltage of the charge MOS transistor as the bulk voltage when the polarity of the output voltage matches the polarity of the target voltage, and the polarity of the output voltage and the target voltage 5. The charge pump circuit according to claim 1, wherein a ground voltage is supplied as the bulk voltage when the polarities of the two are inconsistent with each other. 6. The second bulk voltage controller is
A third bulk voltage switching transistor interposed between the bulk of the charge MOS transistor and ground;
A fourth bulk voltage switching transistor interposed between the bulk of the charge MOS transistor and the source of the charge MOS transistor;
A third control signal generator for generating a third control signal that turns off the third bulk voltage switching transistor when the polarity of the output voltage matches the polarity of the target voltage and turns on when the polarity does not match; ,
A fourth control signal generation unit that generates a fourth control signal that turns on the fourth bulk voltage switching transistor when the polarity of the output voltage matches the polarity of the target voltage, and turns off when the polarity does not match; ,
The charge pump circuit according to claim 5, further comprising:   7. The charge pump according to claim 6, wherein the fourth control signal generation unit is a comparator that compares the output voltage with a second reference voltage and uses the comparison result as the fourth control signal. circuit.   8. The charge pump circuit according to claim 6, wherein the third control signal generation unit is a level shifter that generates the third control signal by level-shifting the fourth control signal. .

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