JP2013110596A - Double source follower circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a double source follower circuit that implements both high speed rise and fall of an output signal without requiring an increased amount of current flowing through a current source.SOLUTION: The double source follower circuit includes: a source follower circuit including an nMOSFET 102; a source follower circuit including a pMOSFET 101 different in polarity from the nMOSFET 102; an input terminal 111 for inputting an input signal into the source follower circuit including the nMOSFET 102 and the source follower circuit including the pMOSFET 101; and a common output terminal 112 for outputting an output signal from the source follower circuit including the nMOSFET 102 and the source follower circuit including the pMOSFET 101.

Description

  The present invention relates to a source follower circuit including two MOS transistors whose drains are grounded.

A source follower circuit is an amplifier circuit that biases a drain terminal to a fixed potential, inputs a signal to a gate, and obtains an output signal from the source terminal. The source follower circuit has a gain of about 1 but is used as an output buffer because of its low output resistance. As a conventional technique of such a source follower circuit, for example, it is described in Non-Patent Document 1.
FIG. 10 is a diagram for explaining the above-described conventional technique, and shows a source follower circuit using an N-type MOSFET (hereinafter referred to as nMOSFET). The source follower circuit shown in FIG. 10 includes a transistor MN whose gate terminal is connected to the input terminal VIN, a current source 1021 connected to the source terminal of the transistor MN, and a capacitive element 1022 which is a load capacitive element. It is out. The current IBN flows by the current source 1021, and the capacitance value of the capacitive element 1022 is CL. The output terminal VOUT of the source follower circuit is connected to the current source 1021 and the capacitive element 1022.

  FIG. 11 is a diagram for explaining the operation of the source follower circuit shown in FIG. FIG. 11 is a diagram in which a signal input to the input terminal VIN and a signal output from the output terminal VOUT are written in the circuit shown in FIG. The signal input to the input terminal VIN and the signal output from the output terminal VOUT are both pulsed voltage signals that change so as to have rising and falling edges. In this specification, attention is paid to a signal having a voltage value having a relatively large rising peak value, and such a signal is hereinafter referred to as a “large signal pulse”.

In the large signal pulses SIN1 and SOUT1 shown in FIG. 11, the horizontal direction indicates time and the vertical direction indicates voltage value. For this reason, in either of the large signal pulses SIN1 and SOUT1, the rising or falling time is represented by the slope during the change of the large signal pulse. The steeper the slope, the shorter the rise time or the fall time of the large signal pulse.
As shown in FIG. 11, when the large signal pulse SIN1 at the moment of rising is input to the input terminal VIN, the voltage between the gate and the source of the transistor MN greatly increases. At this time, a large current IMN flows instantaneously through the transistor MN, and the capacitor element 1022 is charged by a difference current between the large current IMN and the current IBN.

When the capacitor 1022 is charged, the potential of the output terminal VOUT rises. At this time, the current (IMN-IBN) for charging the capacitor 1022 is large, and the rising time of the large signal pulse SOUT1 output from the output terminal VOUT is short.
FIG. 12 is a diagram for explaining the operation of the source follower circuit shown in FIG. 10 when the large signal pulse SIN2 at the moment of falling is inputted. In the large signal pulses SIN2 and SOUT2 shown in FIG. 12, the horizontal direction indicates time and the vertical direction indicates voltage values, similarly to SIN1 and SOUT1.

  When the large signal pulse SIN2 at the moment of falling to the source follower circuit is input, the voltage between the gate and source of the transistor MN instantaneously becomes lower than the threshold value, and the transistor MN is turned off. For this reason, the capacitor 1022 is discharged by the current IBN, so that the potential of the output terminal VOUT drops. At this time, since the current that discharges the capacitive element 1022 is a constant current, the falling time of the large signal pulse SOUT2 output from the output terminal VOUT is longer than the falling time of SIN2.

  FIG. 13 is a diagram showing a conventional source follower circuit using a P-type MOSFET (hereinafter referred to as pMOSFET). The source follower circuit shown in FIG. 13 includes a transistor MP whose gate terminal is connected to the input terminal VIN, a current source 1021 connected to the source terminal of the transistor MP, and a capacitive element 1022. The current IBP flows by the current source 1021, and the capacitance value of the capacitive element 1022 is CL. The output terminal VOUT of the source follower circuit is connected to the current source 1021 and the capacitive element 1022.

FIG. 14 is a diagram for explaining the operation of the source follower circuit shown in FIG. 13 when the large signal pulse SIN3 at the moment of rising is inputted. In the large signal pulses SIN3 and SOUT3 shown in FIG. 12, the horizontal direction indicates time and the vertical direction indicates voltage value.
When the large signal pulse SIN3 is input to the source follower circuit, the voltage between the gate and source of the transistor MP instantaneously falls below the threshold value, and the transistor MP is turned off. For this reason, the capacitor 1022 is charged by the current IBP, whereby the potential of the output terminal VOUT rises. At this time, since the current discharging the capacitive element 1022 is a constant current, the rise time of the large current pulse SOUT3 output from the output terminal VOUT is longer than the rise time of SIN3.

FIG. 15 is a diagram for explaining the operation of the source follower circuit shown in FIG. 13 when the large signal pulse SIN4 at the moment of falling is inputted. In the large signal pulses SIN4 and SOUT4 shown in FIG. 15, the horizontal direction indicates time and the vertical direction indicates voltage value.
As shown in FIG. 15, when the large signal pulse SIN4 at the moment of falling to the input terminal VIN is input, the voltage between the gate and the source of the transistor MP greatly increases. At this time, a large current IMP flows instantaneously through the transistor MP, and the capacitive element 1022 is discharged by a current difference between the large current IMP and the current IBP.

As the capacitive element 1022 is discharged, the potential of the output terminal VOUT decreases. At this time, the current (IMP-IBP) discharged by the capacitive element 1022 is large, and the fall time of the large signal pulse S4 output from the output terminal VOUT is short.
As described above, in the output signal when a large signal pulse is input to the source follower circuit using nMOSFET, the fall time becomes longer than the rise time. In addition, in the output signal when a large signal is input to the source follower circuit using the pMOSFET, the rise time is longer than the fall time. That is, in the conventional source follower circuit, one of rising or falling of a signal responding to a large signal is delayed.

Analog CMOS Integrated Circuit Design Fundamentals December 15, 2007, 9th edition, pp. 218-225, translator Tadahiro Kuroda, publisher, Takehiko Koshiro, publisher Maruzen Co., Ltd.

However, the source follower circuit can operate at higher speed as the rise time or fall time of the output pulse signal is shorter. For this reason, the source follower circuit is required to speed up both rising and falling of the output signal.
In order to speed up both rising and falling of the output signal, it can be considered that the current IBP flowing through the current source 1021 shown in FIGS. However, flowing a large current to the current source is not desirable because it increases the power consumption of the source follower circuit.

  The present invention has been made in view of the above points, and provides a double source follower circuit capable of speeding up the rise and fall of an output signal without increasing the amount of current flowing by a current source. With the goal.

  A double source follower circuit according to one embodiment of the present invention includes a first source follower circuit including a first MOS transistor (for example, the nMOSFET 102 illustrated in FIG. 1) and a second MOS transistor (for example, illustrated in FIG. 1) having a polarity different from that of the first MOS transistor. Common to the first source follower circuit and the second source follower circuit, which input an input signal to the second source follower circuit including the pMOSFET 101), the first source follower circuit, and the second source follower circuit. Common to the first source follower circuit and the second source follower circuit that output an output signal from an input terminal (for example, the input terminal 111 shown in FIG. 1), the first source follower circuit, and the second source follower circuit. Common output terminals (for example, the output terminal 112 shown in FIG. 1). And wherein the door.

In the double source follower circuit of one embodiment of the present invention, the common input terminal is directly connected to the input terminal of the first source follower circuit, and a capacitor (for example, shown in FIG. 1) is connected to the input terminal of the second source follower circuit. It is desirable to be connected through a capacitive element 121).
In the double source follower circuit of one embodiment of the present invention, it is preferable that an input terminal (for example, the bias terminal 122 illustrated in FIG. 1) of the second source follower circuit is biased to a desired potential.

  In the double source follower circuit of one embodiment of the present invention, the common output terminal is directly connected to one of the output terminal of the first source follower circuit or the output terminal of the second source follower circuit, and the common output terminal is directly It is desirable to connect to the other output terminal that is not connected via a capacitive element (for example, the capacitive element 507 shown in FIG. 5, for example, the capacitive element 607 shown in FIG. 6).

  In the double source follower circuit of one embodiment of the present invention, the common output terminal includes an output terminal of the first source follower circuit (for example, a drain (terminal) of the nMOSFET 102 illustrated in FIG. 5) and an output of the second source follower circuit. It is desirable to be connected to a terminal (for example, the drain (terminal) of the pMOSFET shown in FIG. 5) via a capacitive element (for example, the capacitive elements 107 and 108 shown in FIG. 1).

  The double source follower circuit of one embodiment of the present invention includes an output terminal of the first source follower circuit (for example, the drain (terminal) of the nMOSFET 102 illustrated in FIG. 1) or an output terminal of the second source follower circuit (for example, FIG. 1). The drain (terminal) of the pMOSFET 101 shown is preferably biased to a desired potential (for example, the bias terminal 113 shown in FIG. 1).

  The double source follower circuit according to one embodiment of the present invention includes a third source follower circuit including a third MOS transistor (for example, the nMOSFET 102b illustrated in FIG. 4) having the same polarity as the first MOS transistor, and a second source follower circuit having the same polarity as the second MOS transistor. A reverse polarity input signal having a polarity opposite to that of the input signal is input to a fourth source follower circuit including a 4MOS transistor (for example, the pMOSFET 101b shown in FIG. 4), the third source follower circuit, and the fourth source follower circuit. A common reverse polarity input terminal common to the third source follower circuit and the fourth source follower circuit (for example, the input terminal 111b shown in FIG. 4), the third source follower circuit, and the fourth source follower circuit to The third source channel that outputs a reverse polarity signal having a polarity opposite to that of the output signal. Lower circuit, (output terminal 112b shown in example FIG. 4) common opposite polarity output terminal common to the fourth source follower circuit, it is desirable to further include a.

  According to the present invention, whether the output signal rises or falls, one of the first MOS transistor and the second MOS transistor rises and the current for falling can be compensated. For this reason, it is possible to provide a double source follower circuit in which the output signal rises and falls quickly without delaying the input signal, regardless of whether the large signal pulse is input at the moment of rising or falling.

It is a figure for demonstrating the double source follower circuit of 1st Embodiment of this invention. FIG. 2 is a diagram in which a large signal pulse at the moment of rising is entered in the circuit shown in FIG. 1. FIG. 2 is a diagram in which a large signal pulse at the time of falling is written in the circuit shown in FIG. 1. It is a figure for demonstrating the double source follower circuit of 2nd Embodiment of this invention. It is a figure for demonstrating the double source follower circuit of 3rd Embodiment of this invention. It is a figure for demonstrating the double source follower circuit of 4th Embodiment of this invention. It is a figure for demonstrating the double source follower circuit of 5th Embodiment of this invention. It is a figure for demonstrating the double source follower circuit of 6th Embodiment of this invention. It is a figure for demonstrating the double source follower circuit of 7th Embodiment of this invention. It is a figure for demonstrating the conventional source follower circuit using N type MOSFET. It is a figure for demonstrating operation | movement when the large signal pulse of the moment of rising to the source follower circuit shown in FIG. 10 is input. It is a figure for demonstrating operation | movement when the large signal pulse of the moment which falls in the source follower circuit shown in FIG. 10 is input. It is a figure for demonstrating the conventional source follower circuit using P-type MOSFET. 14 is a diagram for explaining an operation when a large signal pulse at the moment of rising to the source follower circuit shown in FIG. 13 is input. FIG. 14 is a diagram for explaining an operation when a large signal pulse at the moment of falling is input to the source follower circuit shown in FIG.

  Hereinafter, first to seventh embodiments of the present invention will be described. The source follower circuit according to the present invention includes a source follower circuit including a pMOSFET and a source follower circuit including an nMOSFET. For this reason, the source follower circuits of the first to seventh embodiments are referred to as a double source follower circuit in this specification.

(First embodiment)
Circuit Configuration FIG. 1 is a diagram for explaining a double source follower circuit according to a first embodiment of the present invention. The double source follower circuit of the first embodiment includes a pMOSFET 101, an nMOSFET 102, resistance elements 105 and 110, DC-cut capacitance elements 106, 107, and 108, a load capacitance element capacitance element 109, and current sources 103 and 104. .

The double source follower circuit shown in FIG. 1 includes two source follower circuits including a source follower circuit including a pMOSFET 101 and a source follower circuit including an nMOSFET 102. In both the pMOSFET 101 and the nMOSFET 102, the gate (gate terminal connected to the gate) is the input terminal of the source follower circuit. The output terminal of the source follower circuit including the pMOSFET 101 is the source of the pMOSFET 101 (source terminal connected to the source), and the output terminal of the source follower circuit including the nMOSFET 102 is the drain of the nMOSFET 102 (drain terminal connected to the drain). .
In the first embodiment, the third embodiment to the seventh embodiment of the present specification, the pMOSFET 101 and the current source 103 are one source follower circuit, and the nMOSFET 102 and the current source 104 are one source follower circuit. The input terminal and output terminal of the MOSFET are the input terminal and output terminal of the corresponding source follower circuit, respectively.

  The pMOSFET 101 and the nMOSFET 102 are both provided between the ground terminal VSS and the power supply terminal VDD. A current source 103 is provided at a node 117 between the source of the pMOSFET 101 and the power supply terminal VDD. A current source 104 is provided at a node 118 between the source of the nMOSFET 102 and the power supply terminal VDD. The drains of the pMOSFET 101 and the nMOSFET 102 are grounded to the ground terminal VSS, and both the pMOSFET 101 and the nMOSFET 102 constitute a source follower circuit. The current flowing through the current source 103 is denoted as IBP, and the current flowing through the current source 104 is denoted as IBN.

  One end of a resistance element 105 is connected to the gate terminal of the pMOSFET 101. The other end of the resistance element 105 is connected to the bias terminal 122. The gate terminal of the nMOSFET 102 is connected to the input terminal 111. An input voltage VIN is input to the input terminal 111. The gate of the pMOSFET 101 and the gate terminal of the nMOSFET 102 are connected by a node 121. The capacitor 121 is provided at the node 121. The input terminal 111 is an input terminal common to the pMOSFET 101 and the nMOSFET 102.

One end of a node 119 is connected to the node 117, and the other end of the node 119 is connected to an output terminal 112 common to the pMOSFET 101 and the nMOSFET 102. The value of the output voltage output from the output terminal 112 is denoted as VOUT.
One end of the node 120 is connected to the node 118, and the other end of the node 120 is connected to the bias terminal 113. The output terminal 112 is an output terminal common to the pMOSFET 101 and the nMOSFET 102.

  A node 116 is connected to the nodes 119 and 120, and the nodes 119 and 120 are connected to each other by the node 116. At the node 119, the capacitive element 107 is provided between the source of the pMOSFET 101 and the connection point 119 a with the node 116. The capacitance of the capacitive element 107 is C2. In the node 120, the capacitor 108 is provided between the drain of the nMOSFET 102 and the connection point 120 a between the node 116.

Further, in the node 119, the node 115 is connected between the connection point 119a and the output terminal 112, and the other end of the node 115 is grounded. A capacitor 109 is provided at the node 115. A resistance element 110 is provided at a node 120 between the connection point 120 a and the bias terminal 113.
In such a double source follower circuit, the gate of the nMOSFET 102 is directly connected to the input terminal 111, and the gate terminal of the pMOSFET 101 is connected to the input terminal 111 via the capacitive element 106. The DC level of the gate terminal of the pMOSFET 101 is biased by an appropriate potential supplied from the bias terminal 122 via the resistance element 105.

  The outputs of the source follower circuit using the pMOSFET 101 and the source follower circuit using the nMOSFET 102 are coupled via the capacitive elements 107 and 108, respectively, and connected to the output terminal 112 of the double source follower circuit. The DC level of the output terminal of the nMOSFET 102 is biased by an appropriate potential supplied from the bias terminal 113 via the resistance element 110.

Operation Next, the behavior of the double source follower circuit shown in FIG. 1 when a large signal pulse is input will be described.
FIG. 2 is a diagram in which large signal pulses are written in the circuit shown in FIG. The large signal pulse is a voltage signal having a relatively large value and a signal having a pulse waveform. In the large signal pulses shown in FIG. 2, the length in the horizontal direction indicates time, and the length in the vertical direction indicates the voltage value. For this reason, it is shown that the larger the signal pulse with a steep slope, the shorter the rise and fall times.

In FIG. 2, the large signal pulse at the moment of rising shown in FIG. When the large signal pulse shown in FIG. 2B is input to the input terminal 111, the gate-source voltage of the nMOSFET rises. At this time, a current IMN flows through the nMOSFET 102 instantaneously.
Since the voltage value of the large signal pulse is relatively large, the gate-source voltage of the nMOSFET 102 rises greatly, and the current IMN flowing through the nMOSFET 102 becomes a large current. The capacitive element 108 and the capacitive element 109 are charged by the differential current between the current IMN and the current IBN.

  Also, the large signal pulse shown in FIG. 2B is input to the gate terminal of the pMOSFET 101 via the capacitive element 106 as shown in FIG. At this time, the gate-source voltage of the pMOSFET 101 instantaneously falls below the threshold value, and the pMOSFET 101 is turned off. For this reason, charges are accumulated in the capacitive element 107 by the current IBP flowing from the current source 103. The charge accumulated in the capacitor 107 charges the capacitor 109.

  With the above operation, in the first embodiment, the capacitive element 109 can be charged with the current of IMN-IBN + IBP, and the output voltage VOUT output as a large signal pulse can be increased. Since the large signal pulse is a relatively large voltage signal, the current for charging the capacitor 109 is large, and the output voltage VOUT (large signal pulse) rises in a short time as shown in FIG. become.

  FIG. 3 is a diagram in which large signal pulses are entered in the circuit shown in FIG. In FIG. 3, the large signal pulse at the falling instant shown in FIG. When the large signal pulse shown in FIG. 3E is input, the voltage between the gate and source of the nMOSFET 102 instantaneously falls below the threshold value, and the nMOSFET 102 is turned off. Therefore, the electric charge accumulated in the capacitive element 109 by the current IBN is discharged through the capacitive element 108.

  Further, the large signal pulse is input to the gate terminal of the pMOSFET 101 via the capacitive element 106 as shown in FIG. At this time, the gate-source voltage of the pMOSFET 101 rises, and the current IMP flows instantaneously through the pMOSFET 101. Since the value of the large signal pulse is relatively large, the voltage between the gate and source of the pMOSFET 101 also increases greatly, and the current IMP becomes a large current.

  The difference current between the current IMP and the current source IBP discharges the capacitive element 109 through the capacitive element 107. With the above operation, in the first embodiment, the current IMP−IBP + IBN is discharged from the capacitive element 109, and the output voltage VOUT output as a large signal pulse decreases. Since the value of the current IMP−IBP + IBN is large, as shown in FIG. 3F, the output voltage VOUT (large signal pulse) falls within a short time.

As described above, according to the first embodiment, when the capacitor 109 is charged, the pMOSFET 101 can compensate for the charging current so that the output signal VOUT rises without delaying the rising of the input signal VIN. . In addition, when the capacitive element 109 is discharged, the nMOSFET 102 can supplement the discharge current so that the output signal VOUT falls without delaying the falling of the input signal VIN. Therefore, the first embodiment can provide a source follower circuit in which the output signal VOUT rises and falls at a high speed when any large signal pulse is input at the moment of rising or falling.
The first embodiment is not limited to the configuration described above. For example, instead of the current sources 103 and 104, a resistance element that operates so that the current is constant may be provided.

(Second Embodiment)
Circuit Configuration Next, a second embodiment of the present invention will be described. The double source follower circuit of the second embodiment is configured by configuring the double source follower circuit described in the first embodiment as a differential circuit.
FIG. 4 is a diagram for explaining a double source follower circuit according to a second embodiment of the present invention. In the second embodiment to the seventh embodiment described below in this specification, components having the same functions as those shown in FIG. 1 are denoted by the same reference symbols as those shown in FIG. A part of the explanation is omitted.
The double source follower circuit of the second embodiment includes pMOSFETs 101a and 101b, nMOSFETs 102a and 102b, resistance elements 105a, 105b, 110a and 110b, DC-cut capacitance elements 106a, 106b, 107a, 107b, 108a and 108b, and load capacitance elements. It includes certain capacitive elements 109a and 109b and current sources 103a, 103b, 104a and 104b. In the second embodiment, the pMOSFET 101 and the current source 103a are one source follower circuit, the pMOSFET 101b and the current source 103b are one source follower circuit, the nMOSFET 102a and the current source 104a are one source follower circuit, and the nMOSFET 102b and the current source 104b are One source follower circuit is used.

  Further, in the second embodiment shown in FIG. 4, among the configurations described above, the configuration with “a” attached to the reference operates when the input signal VINN is input to the input terminal 111a. The configuration with “b” in the reference sign operates when the input signal VINP is input to the input terminal 111b. The output signal VON is output from the output terminal 112a by the operation having the configuration with the symbol “a”, and the output signal VOP is output from the output terminal 112b by the operation having the configuration having the code “b”.

The input terminal 111a is connected to the gate terminal of the nMOSFET 102a, and is connected to the gate terminal of the pMOSFET 101a via the capacitive element 106a. The DC level of the gate terminal of the pMOSFET 101a is biased by an appropriate voltage supplied from the bias terminal 122 via the resistance element 105a.
The input terminal 111b is connected to the gate terminal of the nMOSFET 102b, and is connected to the gate terminal of the pMOSFET 101b via the capacitive element 106b. The DC level of the gate terminal of the pMOSFET 101b is biased by an appropriate potential supplied from the bias terminal 122 via the resistance element 105b.

The source terminal of the nMOSFET 102a and the source terminal of the pMOSFET 101a are coupled via capacitive elements 107a and 108a. The capacitive elements 107a and 108a are connected to the output terminal 112a. The DC level of the output terminal 112a is biased by an appropriate potential supplied from the bias terminal 113 via the resistance element 110a.
The drain terminal of the nMOSFET 102b and the source terminal of the pMOSFET 101b are coupled via the capacitive elements 107b and 108b and connected to the output terminal 112b. The DC level of the output terminal 112b is biased by an appropriate potential supplied from the bias terminal via the resistance element 110b.

Operation The differential signal with the polarity reversed is input to the double source follower circuit of the second embodiment described above. The configuration with “a” and the configuration with “b” in the figure operate in the same manner as in the first embodiment by corresponding signals. As a result, the output signal VON is output from the output terminal 112a, and the output signal VOP is output from the output terminal 112b.
(Third embodiment)
Next, a third embodiment of the present invention will be described.
FIG. 5 is a diagram for explaining the double source follower circuit according to the third embodiment. The double source follower circuit of the third embodiment shown in FIG. 5 is different from that of the first embodiment in that a DC-cut capacitive element 507 is provided instead of the capacitive elements 107 and 108 shown in FIG. In the third embodiment, the node 510 connected to the drain of the nMOSFET 102 is connected to the output terminal 112 via the capacitive element 507.

  According to the third embodiment, the DC level of the output terminal 112 is determined by the output of the source follower circuit using the pMOSFET 101. Therefore, the bias source 113 shown in FIG. 1 is not necessary in the double source follower circuit of the third embodiment. Further, in the third embodiment, a capacitive element 507 is provided instead of the capacitive elements 107 and 108 shown in FIG. Furthermore, since the resistance element 110 shown in FIG. 1 is not necessary, the number of parts of the element can be reduced, and the circuit can be reduced in size.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described.
FIG. 6 is a diagram for explaining a double source follower circuit according to a fourth embodiment of the present invention. In the fourth embodiment, the output terminal of the nMOSFET 102 of the third embodiment shown in FIG. 5 is used as the output terminal 112 of the double source follower circuit. The node 616 connected to the output terminal of the pMOSFET 101 is connected to the output terminal 112 via the DC-cut capacitive element 607.

  According to such a fourth embodiment, the DC level of the output terminal 112 is determined by the output of the source follower circuit using the nMOSFET 102. Therefore, the double source follower circuit of the fourth embodiment does not require the bias terminal 113 shown in FIG. Furthermore, in the fourth embodiment, a capacitive element 607 is provided instead of the capacitive elements 107 and 108 shown in FIG. Furthermore, since the resistance element 110 shown in FIG. 1 is not necessary, the number of parts of the element can be reduced, and the circuit can be reduced in size.

(Fifth embodiment)
Next, a fifth embodiment of the present invention will be described.
FIG. 7 is a diagram for explaining a double source follower circuit according to a fifth embodiment of the present invention. The fifth embodiment is different from the configuration shown in FIG. 1 in that the input terminal of the pMOSFET 101 is connected to the input terminal 111 of the double source follower circuit. In the fifth embodiment, the input terminal of the nMOSFET 102 is connected to the input terminal 111 via the capacitive element 106.

(Sixth embodiment)
Next, a sixth embodiment of the present invention will be described.
FIG. 8 is a diagram for explaining a double source follower circuit according to a sixth embodiment of the present invention. The sixth embodiment differs from the configuration shown in FIG. 5 in that the input terminal of the pMOSFET 101 is directly connected to the input terminal 111 of the double source follower circuit. In the sixth embodiment, the input terminal of the nMOSFET 102 is connected to the input terminal 111 via the capacitive element 106.

(Seventh embodiment)
Next, a seventh embodiment of the present invention will be described.
FIG. 9 is a diagram for explaining a double source follower circuit according to a seventh embodiment of the present invention. The seventh embodiment is different from the configuration shown in FIG. 6 in that the output terminal of the pMOSFET 102 is directly connected to the output terminal 112 of the double source follower circuit. In the seventh embodiment, the output terminal of the pMOSFET 101 is connected to the output terminal 112 via the capacitive element 607.

According to the first to seventh embodiments of the present invention described above, when a pulse voltage having a relatively large peak value is input, the source follower circuit in which the output voltage rises at high speed at both the rising and falling edges of the pulse. Can be provided. Therefore, according to Embodiments 1 to 7, it is possible to provide a source follower circuit that operates at high speed.
Further, according to the present invention, such a configuration can be realized by a double source follower including two source follower circuits. For this reason, it is not necessary to supply a large current to the MOS transistor of the source follower circuit, and the power consumption can be suppressed.

  It should be noted that the scope of the present invention is not limited to the illustrated and described exemplary embodiments, but includes all embodiments that provide the same effects as those intended by the present invention. Further, the scope of the present invention is not limited to the combination of features of the invention defined by claim 1 but can be defined by any desired combination of specific features among all the disclosed features. .

  Since the double source follower circuit of the present invention can operate at a high frequency, it is suitable for a radio device or the like used at a high frequency.

106-108 capacitive elements 103, 104, 103a, 104a current sources 105, 110, 105a, 105b, 110a, 110b resistive elements 106, 107, 108, 109, 106a, 106b, 107a, 107b 108a, 108b, 507, 607 capacitive elements 111, 111a, 111b Input terminal 112, 112a, 112b Output terminal 113, 122 Bias terminal 116, 117, 118, 119, 120, 121, 510, 616 Node 119a, 120a Connection point

Claims (7)

A first source follower circuit including a first MOS transistor;
A second source follower circuit including a second MOS transistor having a polarity different from that of the first MOS transistor;
A common input terminal common to the first source follower circuit and the second source follower circuit for inputting an input signal to the first source follower circuit and the second source follower circuit;
A common output terminal common to the first source follower circuit and the second source follower circuit, which outputs an output signal from the first source follower circuit and the second source follower circuit;
A double source follower circuit comprising:   2. The double according to claim 1, wherein the common input terminal is directly connected to an input terminal of the first source follower circuit, and is connected to an input terminal of the second source follower circuit via a capacitive element. Source follower circuit.   The double source follower circuit according to claim 1, wherein an input terminal of the second source follower circuit is biased to a desired potential.   The common output terminal is directly connected to one of the output terminal of the first source follower circuit or the output terminal of the second source follower circuit, and the common output terminal is not directly connected to the other output terminal. The double source follower circuit according to claim 1, wherein the double source follower circuit is connected via an element.   The common output terminal is connected to the output terminal of the first source follower circuit and the output terminal of the second source follower circuit, respectively, via a capacitive element. The double source follower circuit described in the section.   6. The double source follower circuit according to claim 5, wherein an output terminal of the first source follower circuit or an output terminal of the second source follower circuit is biased to a desired potential. A third source follower circuit including a third MOS transistor having the same polarity as the first MOS transistor;
A fourth source follower circuit including a fourth MOS transistor having the same polarity as the second MOS transistor;
A common reverse polarity common to the third source follower circuit and the fourth source follower circuit, wherein a reverse polarity input signal having a polarity opposite to that of the input signal is input to the third source follower circuit and the fourth source follower circuit. An input terminal;
A common reverse polarity output terminal common to the third source follower circuit and the fourth source follower circuit that outputs a reverse polarity signal having a reverse polarity to the output signal from the third source follower circuit and the fourth source follower circuit. When,
The double source follower circuit according to claim 1, further comprising:

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