JP2013110213A - Electronic device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To bond a metal bump reliably in Fan-out type WLP.SOLUTION: In an electronic device 1, a package component 5 is mounted on a circuit board 2 via a metal bump 4. In the package component 5, a semiconductor chip 11 is covered with a resin 21, and the metal bump 4 can be arranged on the outside of the region of the semiconductor chip 11 by a re-wiring layer 31. A plurality of copper columns 25 are arranged in the resin 21, and one metal bump 4 is arranged under each column 25. When mounting the package component 5 on the circuit board 2, ultrasonic waves is applied to the package component 5 from above and made to propagate with no loss by means of the column 25 thus melting the metal bump 4.

Description

  The present invention relates to an electronic device and a method for manufacturing the same.

  When packaging a semiconductor chip, a CSP (Chip-Size Package) that is mounted almost in the size of the semiconductor chip without using wire bonding may be employed. By adopting CSP, it is possible to achieve both high-density mounting and manufacturing cost reduction. In recent years, the fine pitch of CSP itself is accelerating, and the mounting form has changed from using a resin interposer to WLP (Wafer Level Package).

  Here, WLP is a form of CSP that processes up to the final process of the package at the wafer level, and dices and separates after the final test of pass / fail judgment. For this reason, it is possible to reduce the mounting area to the actual chip size at a lower cost than in the case of using the conventional package technology. Here, WLP may be called WL-CSP (Wafer Level CSP) or W-CSP (Wafer CSP).

  In the conventional WLP, for example, the terminals of the semiconductor chip are arranged on the entire surface of the chip (Fan-in). However, with the increase in the number of terminals of semiconductor chips, it has become difficult to arrange terminals only in the chip area. For this reason, in recent years, a method of rearranging (Fan-out) the terminals outside the area of the semiconductor chip has been developed. The Fan-out type WLP is a pseudo-chip in which a semiconductor chip is embedded in a mold resin composition, an outermost layer of a circuit of the semiconductor chip is flush with a surface of the mold resin composition, and the semiconductor chip is embedded in a resin. Rebuild the board. Further, a wiring layer (Fan-out layer) is formed on the mold resin composition beyond the region of the semiconductor chip. Subsequently, electrode pads are arranged over the entire surface layer of the Fan-out layer, metal bumps are formed on each electrode pad, and then separated into individual pieces.

JP 2001-217381

Here, in the fan-out type WLP, since the thermal expansion coefficient of the semiconductor chip and the resin surrounding the semiconductor chip are different, the semiconductor chip and the circuit board are joined at a low temperature of 150 ° C. or less to prevent the occurrence of cracks and the like. It is preferable. As a method for bonding the semiconductor chip and the circuit board at a low temperature, there is ultrasonic bonding. However, in the Fan-out type WLP, the ultrasonic wave is easy to propagate through the portion of the semiconductor chip having a large elastic modulus, but the ultrasonic wave is difficult to propagate because the resin portion is soft and has a low elastic modulus. As described above, in the conventional Fan-out type WLP, since the propagation of ultrasonic waves is likely to be uneven depending on the location, it is difficult to uniformly join a plurality of metal bumps.
The present invention has been made in view of such circumstances, and an object thereof is to ensure that metal bumps can be bonded in a fan-out type WLP.

According to one aspect of the embodiment, a semiconductor chip having a wiring layer including a semiconductor circuit, a resin that covers the semiconductor chip and exposes an outermost layer of the wiring layer, and a rewiring layer that covers the resin and the wiring layer And a conductive bump connected to the wiring of the rewiring layer, and disposed within the resin, formed above the bump and on the insulating film of the rewiring layer, and having an elastic modulus higher than that of the resin. And an ultrasonic wave propagation member having a large diameter.

  Further, according to another aspect of the embodiment, the step of forming the ultrasonic wave propagation member above the support member, and the semiconductor chip is disposed above the support member with the wiring layer on which the semiconductor circuit is formed facing downward A step of covering the ultrasonic wave propagation member and the semiconductor chip with a resin having a lower elastic modulus than the ultrasonic wave propagation member, and the semiconductor chip and the ultrasonic wave propagation member covered with the resin from the support member. Removing and forming a rewiring layer covering the wiring layer of the semiconductor chip and the resin surface; and a conductive bump on the rewiring layer; at least one of the bumps is located below the ultrasonic wave propagation member And the bump is placed on an electrode pad of another substrate, and an ultrasonic wave is applied to the bump through the semiconductor chip and the ultrasonic wave propagation member to melt the bump. So, a method of manufacturing an electronic device characterized by comprising the a step of electrically connecting the circuit of the electrode pad and the redistribution layer of the other substrate is provided.

  The ultrasonic wave is propagated to the metal bump through the ultrasonic wave propagation member, so that the attenuation of the ultrasonic wave can be suppressed. Therefore, the metal bump can be reliably melted at a low temperature. The reliability of bonding using metal bumps is improved, and variations in bonding strength between metal bumps can be prevented.

FIG. 1 is a cross-sectional view showing an example of an electronic device according to the first embodiment of the present invention. FIG. 2 is a plan view showing an example of the electronic device according to the first embodiment of the present invention. FIG. 3A is a cross-sectional view (part 1) illustrating the example of the manufacturing process of the electronic device according to the first embodiment of the invention. FIG. 3B is a cross-sectional view (part 2) illustrating the example of the manufacturing process of the electronic device according to the first embodiment of the invention. FIG. 3C is a cross-sectional view (part 3) illustrating the example of the manufacturing process of the electronic device according to the first embodiment of the invention. FIG. 3D is a sectional view (No. 4) showing an example of the manufacturing process of the electronic device according to the first embodiment of the invention. FIG. 4 is a plan view showing an example of a resin substrate according to the first embodiment of the present invention. FIG. 5A is a cross-sectional view (part 1) illustrating an example of the manufacturing process of the rewiring layer of the electronic device according to the first embodiment of the present invention. FIG. 5B is a sectional view (No. 2) showing the example of the manufacturing process of the rewiring layer of the electronic device according to the first embodiment of the invention. FIG. 5C is a cross-sectional view (part 3) illustrating the example of the manufacturing process of the rewiring layer of the electronic device according to the first embodiment of the invention. FIG. 5D is a sectional view (No. 4) showing an example of the manufacturing process of the rewiring layer of the electronic device according to the first embodiment of the invention. FIG. 5E is a sectional view (No. 5) showing an example of the manufacturing process of the rewiring layer of the electronic device according to the first embodiment of the invention. FIG. 5F is a sectional view (No. 6) showing an example of the manufacturing process of the rewiring layer of the electronic device according to the first embodiment of the invention. FIG. 6 is a diagram showing an example of a manufacturing process of the electronic device according to the first embodiment of the present invention. FIG. 7A is a cross-sectional view (part 1) illustrating an example of the manufacturing process of the electronic device according to the second embodiment of the present invention. FIG. 7B is a cross-sectional view (part 2) illustrating the example of the manufacturing process of the electronic device according to the second embodiment of the present invention. FIG. 7C is a cross-sectional view (part 3) illustrating the example of the manufacturing process of the electronic device according to the second embodiment of the present invention. FIG. 7D is a sectional view (No. 4) showing an example of the manufacturing process of the electronic device according to the second embodiment of the present invention. FIG. 8A is a cross-sectional view (part 1) illustrating an example of the manufacturing process of the electronic device according to the third embodiment of the present invention. FIG. 8B is a cross-sectional view (part 2) illustrating the example of the manufacturing process of the electronic device according to the third embodiment of the present invention. FIG. 8C is a cross-sectional view (part 3) illustrating the example of the manufacturing process of the electronic device according to the third embodiment of the present invention. FIG. 8D is a cross-sectional view (part 4) illustrating the example of the manufacturing process of the electronic device according to the third embodiment of the present invention. FIG. 9 is a cross-sectional view showing an example of an electronic device according to the fourth embodiment of the present invention. FIG. 10 is a plan view showing an example of an electronic apparatus according to the fourth embodiment of the present invention. FIG. 11A is a cross-sectional view (part 1) illustrating an example of the manufacturing process of the electronic device according to the fourth embodiment of the present disclosure. FIG. 11B is a cross-sectional view (part 2) illustrating the example of the manufacturing process of the electronic device according to the fourth embodiment of the present invention. FIG. 11C is a cross-sectional view (part 3) illustrating the example of the manufacturing process of the electronic device according to the fourth embodiment of the present invention. FIG. 11D is a sectional view (No. 4) showing an example of the manufacturing process of the electronic device according to the fourth embodiment of the present invention. FIG. 11E is a sectional view (No. 5) showing an example of the manufacturing process of the electronic device according to the fourth embodiment of the present invention. FIG. 12A is a sectional view (No. 1) showing an example of a manufacturing process of an electronic device according to the fifth embodiment of the invention. FIG. 12B is a cross-sectional view (part 2) illustrating the example of the manufacturing process of the electronic device according to the fifth embodiment of the invention.

The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
The foregoing general description and the following detailed description are exemplary and explanatory only and are not intended to limit the invention.

(First embodiment)
As shown in FIG. 1, the electronic device 1 includes a circuit board 2, and a package component 5 (semiconductor device) is mounted on the electrode pads 3 on the circuit board 2 using conductive metal bumps 4. Has been. Here, the circuit board 2 is manufactured using a resin substrate or a ceramic substrate, and the thickness thereof is preferably 0.1 mm or more, for example. A plurality of electrode pads 3 are arranged on the circuit board 2 and are electrically connected to a circuit (not shown) formed on the circuit board 2.

In the package component 5, the semiconductor chip 11 is embedded in the resin 21. The semiconductor chip 11 includes a wiring layer 1 having at least one circuit on one surface of a substrate 12 such as silicon.
3 is formed. In the wiring layer 13, semiconductor elements such as transistors and other semiconductor circuits are formed. The semiconductor chip 11 is arranged so that the wiring layer 13 faces the circuit board 2, that is, in a face-down state, and all the side surfaces of the semiconductor chip 11 and the surface opposite to the surface on which the wiring layer 13 is formed. (The other surface) is covered with the resin 21. The lower surface of the resin 21 and the outermost layer of the wiring layer 13 of the semiconductor chip 11 are arranged on the same surface. The resin 21 is formed by curing the mold resin composition, and the mold resin composition contains, for example, an inorganic filler typified by a silica filler having a maximum particle size of about 75 μm.

  Further, a rewiring layer 31 is formed on the package component 5 so as to cover the surfaces of the wiring layer 13 and the resin 21. The rewiring layer 31 has a multilayer wiring structure in which a wiring pattern 32 is formed. By the rewiring layer 31, the electrode pads 14 formed on the wiring layer 13 of the semiconductor chip 11 and the metal bumps 4 are electrically connected. Accordingly, the wiring layer 13 of the semiconductor chip 11 is electrically connected to a circuit (not shown) of the circuit board 2 via the rewiring layer 31 and the metal bump 4. The outermost layer of the rewiring layer 31 is covered with a resin protective film 71 except for the position where the metal bumps 4 are arranged. As described above, in the package component 5, the plurality of metal bumps 4 are arranged outside the region of the semiconductor chip 11 by the rewiring layer 31.

  Here, as shown in the plan views of FIGS. 1 and 2, a plurality of ultrasonic vibration propagation columns 25 (ultrasonic propagation members) are embedded in the resin 21. Each column 25 has a cylindrical shape, and a plurality of columns 25 are arranged so as to surround the semiconductor chip 11. The arrangement of the pillars 25 is matched with the arrangement of the lower metal bumps 4. That is, one column 25 is disposed above one metal bump 4. The upper end of each column 25 is exposed from the resin 21. The lower end of each column 25 is in contact with the insulating film 51 of the rewiring layer 31, and the wiring pattern 32 is not formed in this portion. For this reason, the pillar 25 is not electrically connected to the semiconductor chip 11 or the rewiring layer 31. Such a pillar 25 is manufactured from a metal material containing at least copper, aluminum, nickel, titanium, molybdenum, cobalt, tungsten, for example. The outer diameter of the column 25 in plan view is larger than the maximum diameter of the metal bump 4. The planar shape of the column 25 may be another shape such as a triangular column or a polygonal column. Further, the arrangement of the pillars 25 is not limited to the example shown in FIG.

Next, the manufacturing process of the electronic device 1 will be described below.
First, steps required until a sectional structure shown in FIG.
For example, an adhesive sheet 42 having adhesive layers on both sides is pasted on a support substrate 41 (support member) made of stainless steel. On the adhesive sheet 42, for example, a copper foil 43 having a thickness of 0.45 mm is pasted. Further, after applying a resist film (not shown) on the copper foil 43, the resist film is exposed and developed to form a resist pattern 44. The resist pattern 44 is formed in an island shape in accordance with the formation position of the pillar 25 shown in FIG.

Next, steps required until a structure shown in FIG.
The copper foil 43 is etched using the resist pattern 44 to form a plurality of pillars 25. The remaining resist pattern 44 is removed by ashing or chemical treatment. The outer diameter of the pillar 25 is preferably, for example, a diameter (φ) of 0.1 mm and a height of 0.4 mm or more.

  Next, the semiconductor chip 11 is attached to a predetermined position of the adhesive sheet 42 in a face-down state. The semiconductor chip 11 is positioned and arranged in a space between the plurality of pillars 25. The semiconductor chip 11 has a size of, for example, 5 mm × 5 mm and a thickness of 0.1 mm to 0.5 mm.

Next, steps required until a structure illustrated in FIG.
The mold resin composition is supplied onto the adhesive sheet 42, and the plurality of pillars 25 and the semiconductor chip 11 are filled with the mold resin composition. Thereafter, the mold resin composition is hardened by heat treatment.
Thereby, a resin substrate 45 in which the plurality of pillars 25 and the semiconductor chip 11 are embedded in the resin 21 is formed. For example, when a plurality of semiconductor chips 11 are arranged on the adhesive sheet 42 at a predetermined interval, a resin substrate 45 as shown in a plan view in FIG. 4 is formed. In the resin substrate 45, a plurality of semiconductor chips 11 are arranged at equal intervals, and a plurality of pillars 25 are arranged around each semiconductor chip 11. The thickness of the resin substrate is preferably 0.1 mm or more thicker than the thickness of the semiconductor chip 11, but the same thickness may be used. The number and arrangement of the semiconductor chips 11 are not limited to FIG.

  The resin substrate 45 has a diameter (φ) of 100 mm, for example, and a thickness equal to or greater than the thickness of the semiconductor chip 11, for example, 0.5 mm. Next, as shown in FIG. 3D, the upper surface of the resin substrate 45 is back-ground by, for example, 0.05 mm, and the pillars 25 are exposed from the upper surface of the resin 21. At this time, since the height of the semiconductor chip 11 is lower than the pillar 25, the semiconductor chip 11 remains buried in the resin 21. Thereafter, the resin substrate 45 is removed from the adhesive sheet 42 and the support substrate 41.

Next, the rewiring layer 31 is formed on the lower surface of the resin substrate 45, that is, the surface of the semiconductor chip 11 on the wiring layer 13 side. An example of a method for forming the rewiring layer 31 will be described below.
First, steps required until a sectional structure shown in FIG. FIG. 5A is an enlarged cross-sectional view showing a part of the wiring layer 13 of the semiconductor chip 11 and a part of the pillar 25. The semiconductor chip 11 is arranged with the wiring layer 13 facing upward.

  First, the insulating film 51 is formed on the outermost layer of the wiring layer 13 of the semiconductor chip 11 by spin coating. The insulating film 51 is formed not only on the wiring layer 13 including the electrode pads 14 but also on the pillars 25 and the resin 21. Examples of the material for the insulating film 51 include photosensitive resins such as photosensitive epoxy, photosensitive polybenzoxazole, and photosensitive polyimide. The insulating film 51 may be formed using other resin materials.

  For example, when the insulating film 51 is formed of a photosensitive epoxy varnish, it is pre-baked after applying the photosensitive epoxy varnish. Thereafter, the photosensitive epoxy varnish is exposed and developed using a resist pattern (not shown). As a result, an opening 51A is formed on the electrode pad 14 with a diameter (φ) of 40 μm. Thereafter, the photosensitive epoxy varnish is heat treated and cured. Further, if necessary, the photosensitive epoxy varnish is exposed to oxygen plasma. As a result, the insulating film 51 is formed to a thickness of 8 μm, for example.

Next, steps required until a sectional structure shown in FIG.
First, titanium is formed to a thickness of 0.1 μm on the insulating film 51 as a metal adhesion layer 53 by a sputtering method. The metal adhesion layer 53 is selected from titanium, chromium and the like. Further, on the metal adhesion layer 53, for example, copper is deposited to a thickness of 0.3 μm as a seed layer 54 by sputtering. Thereafter, a photoresist pattern 55 is formed on the seed layer 54. The photoresist pattern 55 is formed, for example, by applying a resist film to the entire surface of the seed layer 54, and exposing and developing the resist film. The photoresist pattern 55 has at least one opening 55A in accordance with the position where the electrode pad 15 is formed. Here, the opening 55 </ b> A is not formed on the pillar 25. This is because the circuit pattern is not electrically connected to the pillar 25.

Further, steps required until a sectional structure shown in FIG.
A copper film is grown in the opening 55A by electrolytic plating using the seed layer 54. As a result, a via 57 electrically connected to the electrode pad 14 and a copper wiring 58 connected to the electrode pad 14 through the via 57 are formed. Thereafter, the photoresist pattern 55 is peeled off by ashing or chemical treatment. Further, the seed layer 54 and the metal adhesion layer 53 remaining under the photoresist pattern 55 are removed by wet etching or dry etching. If necessary, the copper wiring 58 may be subjected to a surface treatment or the like for the purpose of improving the adhesion. As a result, a first wiring layer 59 having a copper wiring 58 electrically connected to the electrode pad 14 via the via 57 is formed.

Further, steps required until a sectional structure shown in FIG.
An insulating film 61 is formed on the first wiring layer 59. The insulating film 61 is formed by the same process using the same material as the first insulating film 51, for example, a photosensitive epoxy varnish. Further, the insulating film 61 is patterned to form an opening 61A at a predetermined position on the copper wiring 58. A part of the copper wiring 58 is exposed through the opening 61A.

  Thereafter, a metal adhesion film 62 such as titanium and a seed layer 63 made of copper are sequentially formed on the entire surface of the insulating film 61 including the exposed portion of the copper wiring 58 by a sputtering method. Further, after a resist film is formed thereon by coating, the resist film is exposed and developed to form a photoresist pattern 64. In the photoresist pattern 64, at least one opening 64A is formed above the copper wiring 58.

Next, steps required until a sectional structure shown in FIG.
Copper is grown in the openings 64A of the photoresist pattern 64 by electrolytic plating. As a result, an electrode pad 69 is formed on the copper wiring 58. Thereafter, the photoresist pattern 64, the seed layer 63 and the metal adhesion layer 53 under the photoresist pattern 64 are removed by, for example, wet etching. Thereby, an electrode pad 69 electrically connected to the wiring 58 is formed.

Next, steps required until a sectional structure shown in FIG.
A protective film 71 is formed on the entire surface of the insulating film 61 including the electrode pads 69. The protective film 71 is formed by the same process using the same material as that of the first insulating film 51, for example, a photosensitive epoxy varnish. Further, the protective film 71 is patterned to form an opening 71A that exposes the electrode pad 69.

  Further, gold is formed as a seed layer 75 on the entire surface of the electrode pad 69 and the protective film 71 by sputtering. A resist film having a thickness of 30 μm is formed on the seed layer 75. A resist pattern 76 is formed by patterning the resist film. The resist pattern 76 has an opening 76 </ b> A above the electrode pad 69. Further, a gold film 77 is grown on the seed layer 75 using the resist pattern 76 by an electrolytic plating method.

  Thereafter, the resist pattern 76 and the seed layer 75 under the resist pattern 76 are removed by, for example, wet etching. As a result, the metal bump 4 made of the gold film 77 is formed on the electrode pad 69. The metal bump 4 is formed with a diameter (φ) of 40 μm and a height of 25 μm, for example. Here, the metal bumps 4 are formed as plating bumps or stud bumps containing at least gold or copper. The rewiring layer 31 is formed through the steps so far.

  Here, the number of wiring layers of the rewiring layer 31 can be arbitrarily changed. In order to increase the total number of wirings, a desired multilayer wiring is formed by repeating the processes from the application, development and curing of the photosensitive resin to the surface treatment of the copper wiring 58 a desired number of times. When the resin substrate 45 is divided into pieces according to the number of the semiconductor chips 11, a plurality of package components 5 are formed.

Next, as shown in FIG. 6, the separated package component 5 is placed on the circuit board 2. At this time, the metal bumps 4 of the package component 5 are positioned and placed on the electrode pads 3 on the circuit board 2.

  In this state, ultrasonic waves are applied from above the package component 5 to melt the metal bumps 4 and bond the metal bumps 4 and the electrode pads 3 as shown in FIG. The ultrasonic bonding conditions are, for example, a load of 20 N to 50 N, a frequency of 40 kHz to 100 kHz, a temperature of 25 ° C. to 150 ° C., and an ultrasonic wave application time of 0.5 seconds to 3 seconds. In the region where the semiconductor chip 11 is disposed, the elastic modulus of the semiconductor chip 11 is larger than that of the resin 21, so that ultrasonic waves are more easily propagated than in the region where only the resin 21 is provided. Accordingly, the metal bumps 4 below the semiconductor chip 11 are reliably melted by application of ultrasonic waves and bonded to the electrode pads 3.

  Further, the metal bumps 4 arranged outside the semiconductor chip 11 have pillars 25 arranged above them. Since the elastic modulus of the pillar 25 is larger than that of the semiconductor chip 11, ultrasonic waves are more easily propagated than in the region of the resin 21 alone. The ease of propagation of ultrasonic waves in the column 25 is about the same as or higher than that of the semiconductor chip 11. Therefore, the metal bumps 4 below the pillars 25 are reliably melted and applied to the electrode pads 3 by applying ultrasonic waves. Since the size of the pillar 25 and the size of the semiconductor chip 11 are larger than the maximum diameter of the metal bump 4, the ultrasonic wave irradiated from above is reliably transmitted to the entire metal bump 4 and melts the metal bump 4. As a result, the package component 5 is mounted on the circuit board 2 via the metal bumps 4 melted by ultrasonic waves, and the electronic device 1 is formed.

  Here, as an example, a plurality of copper pillars 25 having a diameter of 0.1 mm and a height of 0.45 mm are formed around a semiconductor chip 11 having a thickness of 0.4 mm and a thickness of 5 mm × 5 mm, and a thickness of 0.5 μm is formed. A resin substrate 45 having a diameter of 100 mm was produced and a bonding experiment was performed. A wiring pattern was formed by using photosensitive epoxy varnish for the insulating films 51, 61, 71 of the rewiring layer 31, using titanium for the metal adhesion layers 53, 62 and copper for the seed layers 54, 63. The metal bumps 4 had a diameter (φ) of 40 μm and a height of 25 μm. After the metal bumps 4 were formed, they were back grinded to expose the upper ends of the pillars 25, and were separated into individual pieces after the thickness was 0.45 mm.

  At the time of ultrasonic bonding, the substrate temperature was 100 ° C., the load was 40 N, and 60 kHz ultrasonic waves were applied for 2 seconds. As a result, the metal bumps 4 were joined with sufficient strength. Conventionally, since there is a difference in the propagation of ultrasonic waves in the resin 21 and the semiconductor chip 11, the bonding strength of the metal bumps 4 below the resin 21 relative to the bonding strength of the metal bumps 4 below the semiconductor chip 11. It was easy to fall or the joining strength varied. Also, some metal bumps 4 under the resin 21 may be peeled off. On the other hand, in this embodiment, the loss of ultrasonic vibration can be reduced and the variation in the molten state can be suppressed, so that uniform and high bonding strength can be obtained in all the metal bumps 4.

  As described above, in this embodiment, since the column 25 that allows the ultrasonic wave to propagate more easily than the resin 21 is disposed above the metal bump 4, the ultrasonic wave can be propagated with a small loss. For this reason, the metal bumps 4 arranged below the pillars 25 can be reliably melted by applying ultrasonic waves. Therefore, the circuit board 2 and the package component 5 can be reliably bonded with uniform strength regardless of the location even in a region other than the region below the semiconductor chip 11. In addition, since the joining by applying ultrasonic waves can be surely performed, the package component 5 and the circuit board 2 can be mounted at a low temperature.

Furthermore, since the diameter of the pillar 25 is equal to or larger than the maximum diameter of the metal bump 4, the ultrasonic wave propagated through the metal bump 4 can be irradiated to the entire metal bump 4. For this reason, the metal bump 4 can be reliably melted. Since the column 25 penetrates the resin 21, the propagation loss of ultrasonic waves can be reduced as compared with the case where the column 25 is covered with the resin 21. Since the pillar 25 is not electrically connected to the semiconductor chip 11 and the redistribution layer 31, it does not affect the circuit characteristics of the electronic device 1.
Further, since the pillars 25 are formed by etching the copper foil, a large number of pillars 25 can be easily formed in a desired shape and arrangement.

  Here, the electronic device 1 is preferably an electronic component selected from at least one of a semiconductor element, a MEMS element, a sensor element, a passive component, and an element in which a thin-film passive component is formed on an inorganic material. The number of electronic components included in the separated package component may be one or plural.

  Further, after the step shown in FIG. 3C, before the resin 21 is back-ground, the support substrate 41 and the adhesive sheet 42 may be removed, and the rewiring layer 31 may be formed through the steps shown in FIGS. 5A to 5F. In this case, after forming the metal bump 4 or immediately before forming the metal bump 4, the resin 21 on the opposite side is back-ground.

Further, the resin 21 and the semiconductor chip 11 may have the same thickness. In this case, after the resin substrate 45 is once formed, the back surface of the resin substrate 45 is polished or ground until the semiconductor chip 11 is exposed.
Further, the joining using the ultrasonic propagation column 25 can be used for joining the package parts 5 or joining the circuit boards. In these cases, the pillars 25 are formed on the substrate arranged on the ultrasonic wave application side so as to coincide with the arrangement of the metal bumps.

(Second Embodiment)
The second embodiment will be described in detail with reference to the drawings. The same components as those in the first embodiment are denoted by the same reference numerals. Moreover, the description which overlaps with 1st Embodiment is abbreviate | omitted.
As shown in FIG. 1, in the electronic device 1 of this embodiment, a column 81 made of an insulator is embedded in a resin 21. The material of the column 81 may be a material having a larger elastic modulus than the resin 21, and more preferably a material close to the elastic modulus of the semiconductor chip 11 is used.

Next, a method for manufacturing the electronic device 1 according to this embodiment will be described below.
First, as shown in FIG. 7A, after the adhesive sheet 42 is attached on the support substrate 41, the semiconductor chip 11 is positioned and attached on the adhesive sheet 42. Subsequently, as shown in FIG. 7B, a plurality of columns 81 are attached on the adhesive sheet 42. The column 81 is manufactured from ceramics, for example, and is positioned and arranged by a mounter (not shown).

  Subsequently, as illustrated in FIG. 7C, the resin 21 is formed on the adhesive sheet 42 so as to cover the semiconductor chip 11 and the column 81. Thereby, the resin substrate 45 is formed. Next, as shown in FIG. 7D, the upper surface of the resin substrate 45 is back-ground, and the pillar 81 is exposed from the upper surface. At this time, since the height of the semiconductor chip 11 is lower than the pillar 25, the semiconductor chip 11 remains buried in the resin 21. Thereafter, the resin substrate 45 is removed from the adhesive sheet 42 and the support substrate 41. The subsequent processes are the same as those in the first embodiment.

Here, as an example, a plurality of ceramic pillars 25 having a diameter of 0.1 mm and a height of 0.45 mm are formed around a semiconductor chip 11 having a thickness of 0.4 mm and a thickness of 5 mm × 5 mm, and a thickness of 0.5 μm. A resin substrate 45 having a diameter of 100 mm was produced and a bonding experiment was performed. A wiring pattern was formed using photosensitive polybenzoxazole varnish for the insulating films 51, 61, 71 of the rewiring layer 31, chromium for the metal adhesion layers 53, 62, and copper for the seed layers 54, 63. The metal bump 4 formed on the rewiring layer 31 has a diameter (φ) of 40 μm and a height of 25 μm. After the metal bump 4 is formed, it is back-ground to expose the upper end of the pillar 25 and has a thickness of 0.45 mm. Later it was singulated. At the time of ultrasonic bonding, the substrate heating is 100 ° C., the load is 40 N, and 60 kHz.
Was applied for 2 seconds. As a result, the metal bumps 4 were joined with sufficient strength.

  As described above, in this embodiment, since the loss of ultrasonic vibration is suppressed by the column 25 made of an insulating material, variation in the bonding strength of the metal bumps 4 can be suppressed. Accordingly, uniform and high bonding strength can be obtained in all the metal bumps 4. Other operations and effects are the same as those in the first embodiment. Here, since the column 81 is manufactured from an insulating material such as ceramics, the column 81 does not affect the circuit characteristics of the electronic device 1 even when the electronic device 1 is a high-frequency device.

  Here, after the step shown in FIG. 7C, before the resin 21 is back-ground, the support substrate 41 and the adhesive sheet 42 may be removed, and the rewiring layer 31 may be formed through the steps shown in FIGS. 5A to 5F. . In this case, after forming the metal bumps 4 or immediately before forming the metal bumps 4, the resin 21 on the opposite side is back-ground to expose the ends of the columns 81.

(Third embodiment)
A third embodiment will be described in detail with reference to the drawings. The same components as those in the first and second embodiments are denoted by the same reference numerals. Moreover, the description which overlaps with 1st and 2nd embodiment is abbreviate | omitted.
This embodiment is characterized by mounting other circuit components in addition to the semiconductor chip 11.

As shown in FIG. 8A, after the adhesive sheet 42 is attached on the support substrate 41, the semiconductor chip 11 and the electronic components 91 and 92 are positioned and arranged on the adhesive sheet 42. As the electronic components 91 and 92, for example, components such as capacitors, capacitors, resistors, etc., which have a higher elastic modulus than the resin 21 are used. Subsequently, as shown in FIG. 8B, at least one pillar 81 is arranged at a predetermined position using a mounter (not shown).
Further, as shown in FIG. 8C, the mold resin composition is applied onto the adhesive sheet 42 and then cured to form the resin 21. Thereafter, the support substrate 41 and the adhesive sheet 42 are removed from the resin 21.

  Subsequently, as shown in FIG. 8D, a rewiring layer 95 is formed on the rewiring layer 31 of the semiconductor chip 11 and on the surface of the resin 21 around it. The formation method of the rewiring layer 95 is the same as that of the rewiring layer 31 of the first embodiment. In the rewiring layer 95, in addition to the wiring 32 connected to the semiconductor chip 11, the wiring 33 electrically connected to the electronic components 91 and 92 is formed. Further, the metal bump 4 is formed either below the semiconductor chip 11, below the pillar 81, or below the electronic components 91 and 92. That is, the arrangement of the metal bumps 4 is determined in accordance with the arrangement of the semiconductor chip 11, the pillar 81, and the electronic components 91 and 92. The subsequent steps are the same as those in the first and second embodiments.

As described above, in this embodiment, since the electronic components 91 and 92 having an elastic modulus larger than that of the resin 21 are disposed above the metal bump 4, the same operation as that of the first and second embodiments. And effects are obtained.
Here, the ultrasonic wave propagation member may be the pillar 25 of the first embodiment. In this case, the plurality of pillars 25 are formed on the adhesive sheet 42 by the manufacturing method described with reference to FIGS. 3A and 3B, and then the semiconductor chip 11 and the electronic components 91 and 92 are mounted.

(Fourth embodiment)
A fourth embodiment will be described in detail with reference to the drawings. The same components as those in any of the first to third embodiments are denoted by the same reference numerals. Also, the description overlapping with any of the first to third embodiments is omitted.

  As shown in FIG. 9, in the electronic device 100 of this embodiment, a semiconductor chip 11 and electronic components 91 and 92 are embedded in a resin 21. Further, in the resin 21, a frame body 101 is embedded as an ultrasonic wave propagation member so as to surround the semiconductor chip 11 and the electronic components 91 and 92.

  As shown in the plan view of FIG. 10, the frame body 101 has a quadrangular outer shape, and one opening 101A is formed at the center. The semiconductor chip 11 and the electronic component 91, 92 is arranged. The height of the frame body 101 is 0.4 mm or more, for example. When the frame body 101 is manufactured from a metal, a material containing at least copper, aluminum, nickel, titanium, molybdenum, cobalt, and tungsten is used. In the case where the frame body 101 is manufactured from a semiconductor material, a material containing at least silicon, gallium arsenide, gallium nitride, and silicon germanium is used. The material of the frame 101 may be any material having a larger elastic modulus than the resin 21, and more preferably a material close to the elastic modulus of the semiconductor chip 11 is used.

A method for manufacturing the electronic device 1 according to this embodiment will be described below.
First, steps required until a structure shown in FIG. 11A is obtained.
An adhesive sheet 42 is affixed on a support substrate 41 made of stainless steel. Further, for example, a copper foil 43 having a thickness of 0.45 mm is pasted on the adhesive sheet 42. After applying a resist film (not shown) on the copper foil 43, the resist film is exposed and developed to form a photoresist pattern 102. The photoresist pattern 102 is formed in a frame shape in accordance with the formation position of the frame body 101 shown in FIG.

Next, steps required until a structure illustrated in FIG.
The copper foil 43 is etched using the photoresist pattern 102 to form the frame body 101. The remaining resist pattern 44 is removed by ashing or chemical treatment. Further, the semiconductor chip 11 and the electronic components 91 and 92 are inserted into the opening 101 </ b> A of the frame body 101 by a mounter (not shown) and attached to the adhesive sheet 42.

  Thereafter, the same steps as those in the first embodiment are performed. That is, as shown in FIG. 11C, a mold resin composition is supplied onto the adhesive sheet 42, and the semiconductor chip 11, the electronic components 91 and 92, and the frame body 101 are filled and then thermally cured to obtain a resin. 21 is formed. The upper surface of the resin substrate 45 thus formed is back-ground by, for example, 0.05 mm, and the frame body 101 is exposed from the upper surface of the resin substrate 45 as shown in FIG. 11D. The semiconductor chip 11 and the electronic components 91 and 92 remain buried in the resin 21. Further, the resin substrate 45 is peeled off from the adhesive sheet 42, and the rewiring layer 31 is formed on the surface 45A of the resin substrate 45 where the semiconductor chip 11 is exposed in the same manner as the steps shown in FIGS. 5A to 5F and FIG.

  Thereafter, when the resin substrate 45 is divided into pieces according to the number of the semiconductor chips 11, a plurality of package components 105 as shown in FIG. 11E are formed. Thereafter, the separated package component 105 is placed on the circuit board 2. At this time, the metal bumps 4 of the package component 105 are positioned and placed on the electrode pads 3 on the circuit board 2.

  In this state, when ultrasonic waves are applied from above the package component 105 to melt the metal bumps 4, the metal bumps 4 and the electrode pads 3 are joined as shown in FIG. 9. As the ultrasonic bonding conditions, for example, an ultrasonic wave is applied at a load of 40 N, a frequency of 60 kHz, and a temperature of 100 ° C. for 2 seconds.

Here, the frame body 101 covers the top of the plurality of metal bumps 4, and the elastic modulus of the frame body 101 is larger than that of the semiconductor chip 11. Therefore, the ultrasonic wave is more easily propagated in the region where the frame body 101 is disposed than in the region including only the resin 21. The ease of propagation of ultrasonic waves in the frame 101 is about the same as or higher than that of the semiconductor chip 11. Accordingly, the metal bumps 4 below the pillars 25 are reliably melted by ultrasonic irradiation and bonded to the electrode pads 3. Since the size of the frame 101 and the size of the semiconductor chip 11 are larger than the maximum diameter of the metal bump 4, the ultrasonic wave applied from above is reliably propagated to the entire metal bump 4 and melts the metal bump 4. . As a result, the package component 5 is mounted on the circuit board 2 via the metal bumps 4 melted by ultrasonic waves, and the electronic device 1 is formed.

  As described above, in this embodiment, since one frame body 101 is disposed so as to cover the plurality of metal bumps 4, it is easy to propagate ultrasonic waves to the metal bumps 4 below the frame body 101. As a result, the metal bump 4 can be reliably bonded to another component, for example, the circuit board 2.

  Here, the electronic device 100 and the package component 105 may be covered with the resin 21 without exposing the frame body 101 on the upper surface of the resin 21. In such an electronic device 100, the same operation and effect as described above can be obtained. Furthermore, since the grinding amount of the resin 21 can be reduced, work efficiency is improved.

(Fifth embodiment)
The fifth embodiment will be described in detail with reference to the drawings. The same components as those in any of the first to fourth embodiments are denoted by the same reference numerals. Further, the description overlapping with any of the first to fourth embodiments is omitted.

  This embodiment is characterized in that the manufacturing method is different from that of the fourth embodiment. That is, as shown in FIG. 12A, the semiconductor chip 11 and the electronic components 91 and 92 are first positioned and attached onto the adhesive sheet 42 attached to the support substrate 41. Subsequently, as shown in FIG. 12B, a frame body 111 molded in advance into a predetermined shape using a mounter is disposed on the adhesive sheet 42. The frame body 111 is made of, for example, aluminum or silicon.

  Thereafter, the same steps as those in the first embodiment are performed. That is, as shown in FIG. 11C, a mold resin composition is supplied onto the adhesive sheet 42, the semiconductor chip 11, the electronic components 91 and 92, and the frame body 111 are filled and then thermally cured to form the resin 21. . Further, as shown in FIG. 11D, the upper surface of the resin substrate 45 is back-ground by, for example, 0.05 mm to expose the frame body 111 from the upper surface. Subsequently, the rewiring layer 31 is formed on the surface of the resin substrate 45 where the semiconductor chip 11 is exposed, in the same manner as the steps shown in FIGS. 5A to 5F and FIG.

  Thereafter, the resin substrate 45 is divided into pieces according to the number of the semiconductor chips 11 to form a plurality of package parts 105. Thereafter, the separated package component 105 is placed on the circuit board 2. At this time, the metal bumps 4 of the package component 105 are positioned and placed on the electrode pads 3 on the circuit board 2.

  As described above, in this embodiment, since one frame body 111 is disposed so as to cover the plurality of metal bumps 4, it is easy to propagate ultrasonic waves to the metal bumps 4 below the frame body 111. As a result, the metal bump 4 can be reliably bonded to another component, for example, the circuit board 2. Since the pre-formed frame 111 is arranged on the adhesive sheet 42, the etching process can be omitted and the manufacturing efficiency is good.

Here, the electronic devices 1 and 100 may include both the columns 25 and 81 and the frames 101 and 111 as the ultrasonic wave propagation member. The resin 25 may be back-ground until the semiconductor chip 10 is exposed. In this case, the package components 5 and 105 are covered with the resin 25 only on the side surfaces of the semiconductor chip 10.

  All examples and conditional expressions given here are intended to help the reader understand the inventions and concepts that have contributed to the promotion of technology, and such examples and It is to be construed without being limited to the conditions, and the organization of such examples in the specification is not related to showing the superiority or inferiority of the present invention. While embodiments of the present invention have been described in detail, various changes, substitutions and variations can be made thereto without departing from the spirit and scope of the present invention.

The features of the above embodiment will be added below.
(Supplementary Note 1) A semiconductor chip having a wiring layer including a semiconductor circuit, a resin that covers the semiconductor chip and exposes an outermost layer of the wiring layer, a rewiring layer that covers the resin and the wiring layer, and the rewiring A conductive bump connected to the wiring of the layer, and disposed in the resin, formed above the bump and on the insulating film of the rewiring layer, and has an ultrasonic wave propagation having a higher elastic modulus than the resin And an electronic device.
(Additional remark 2) The said ultrasonic propagation member is manufactured using the metal, ceramics, or a semiconductor material, The electronic device of Additional remark 1 characterized by the above-mentioned.
(Supplementary note 3) The electronic device according to Supplementary note 1 or 2, wherein a width of the ultrasonic wave propagation member is larger than a maximum diameter of the bump.
(Supplementary note 4) The electronic device according to any one of supplementary notes 1 to 3, wherein the ultrasonic wave propagation member penetrates the resin.
(Supplementary Note 5) The electronic device according to any one of Supplementary Notes 1 to 4, wherein the ultrasonic wave propagation member is a pillar disposed one above the bump.
(Supplementary note 6) The supplementary notes 1 to 4, wherein the ultrasonic wave propagation member is a frame that covers a plurality of the bumps and has an opening in the center where the semiconductor chip can be placed. The electronic device as described in any one.
(Supplementary Note 7) A step of forming an ultrasonic wave propagation member above the support member, a step of arranging a semiconductor chip with the wiring layer on which the semiconductor circuit is formed facing downward above the support member, and the ultrasonic wave propagation A step of covering the ultrasonic wave propagation member and the semiconductor chip with a resin having a lower elastic modulus than the member; and removing the semiconductor chip and the ultrasonic wave propagation member covered with the resin from the support member; And a step of forming a rewiring layer covering the resin surface, and a step of forming a conductive bump on the rewiring layer so that at least one of the bumps is positioned below the ultrasonic wave propagation member, The bump is placed on an electrode pad of another substrate, and an ultrasonic wave is applied to the bump through the semiconductor chip and the ultrasonic wave propagation member to melt the bump. And a step of electrically connecting the electrode pad and the circuit of the rewiring layer.
(Appendix 8) The ultrasonic wave propagation member is formed by patterning the film after disposing a conductive film above the support member, and the semiconductor chip is formed on the support member after the ultrasonic wave propagation member is formed. 8. The method of manufacturing an electronic device according to appendix 7, wherein the electronic device is disposed above the upper surface of the electronic device.
(Supplementary note 9) The method for manufacturing an electronic device according to supplementary note 7, wherein the ultrasonic wave propagation member is disposed above the support member after the semiconductor chip is disposed above the support member. (Additional remark 10) The diameter of the said bump is formed smaller than the said ultrasonic propagation member, The manufacturing method of the electronic device as described in any one of additional remark 6 thru | or appendix 8.

1,100 Electronic device 4 Metal bump 5,105 Package component 10 Semiconductor chip 13 Wiring layer 21 Resin 25 Pillar (ultrasonic propagation member)
31 Rewiring layer 32 Wiring pattern 41 Support substrate (supporting member)
51 Insulating Film 101, 111 Ultrasonic Propagation Member 101A Opening

Claims (6)

A semiconductor chip having a wiring layer including a semiconductor circuit;
A resin that covers the semiconductor chip and exposes the outermost layer of the wiring layer;
A rewiring layer covering the resin and the wiring layer;
A conductive bump connected to the wiring of the rewiring layer;
An ultrasonic wave propagation member disposed in the resin, formed above the bump and on the insulating film of the rewiring layer, and having a larger elastic modulus than the resin;
An electronic device comprising:   The electronic device according to claim 1, wherein the ultrasonic wave propagation member is manufactured using a metal, a ceramic, or a semiconductor material.   The electronic device according to claim 1, wherein a width of the ultrasonic wave propagation member is larger than a maximum diameter of the bump.   4. The electronic device according to claim 1, wherein the ultrasonic wave propagation member is a column arranged one by one above the one bump. 5.   4. The frame according to claim 1, wherein the ultrasonic wave propagation member is a frame that covers an upper portion of the plurality of bumps and has an opening in the center where the semiconductor chip can be placed. The electronic device according to one item. Forming an ultrasonic wave propagation member above the support member;
Placing the semiconductor chip above the support member with the wiring layer on which the semiconductor circuit is formed facing downward;
Covering the ultrasonic wave propagation member and the semiconductor chip with a resin having a lower elastic modulus than the ultrasonic wave propagation member;
Removing the semiconductor chip and the ultrasonic wave propagation member covered with the resin from the support member, and forming a wiring layer of the semiconductor chip and a rewiring layer covering the resin surface;
Forming conductive bumps on the redistribution layer such that at least one of the bumps is positioned below the ultrasonic wave propagation member;
The bump is placed on an electrode pad of another substrate, an ultrasonic wave is applied to the bump through the semiconductor chip and the ultrasonic wave propagation member and melted, and the electrode pad of the other substrate and the rewiring Electrically connecting the circuit of the layer;
A method for manufacturing an electronic device, comprising:

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