JP2013110208A - Optical semiconductor element and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an optical semiconductor element which can reduce a threshold current value while achieving a high optical gain, and provide a manufacturing method of the optical semiconductor element.SOLUTION: An optical semiconductor element comprises: a plurality of quantum dot layers 12 formed above a substrate; and intermediate layers positioned among the plurality of quantum dot layers 12. A composition of a quantum dot 12a included in the quantum dot layer 12 is represented as InGaAsSb(0<x≤1, 0<y≤1). The intermediate layer includes: InGaAsP layers 13, 15 in which a composition of each is represented as InGaAsP(0<a<1, 0<b<1) and each has a thickness of not less then 10 nm and not more than 40 nm; and an InP layer 14 positioned at a height of not less than 10 nm and less than 40 nm from bottoms of the InGaAsP layers 13, 15 and having a thickness of not less than 0.3 nm and not more than 2 nm.

Description

  The present invention relates to an optical semiconductor element and a method for manufacturing the same.

  In order to operate an optical semiconductor element such as a semiconductor laser for optical communication at a high temperature, it is important to prevent leakage of carriers from the oscillation level due to thermal excitation. For this purpose, a discrete energy level is required. It is effective to apply quantum dots having the active layer. Promising optical semiconductor devices used in the 1.55 μm band, which is important for long-distance optical communications, include a plurality of self-formed InAs quantum dot layers (quantum dot layers) above the InP substrate and the active layer. Has been. In forming InAs quantum dots on the InP substrate, it is known to use an InGaAsP intermediate layer having a higher refractive index than InP in order to increase optical gain and form an optical waveguide. The thickness of the InGaAsP intermediate layer is set to 10 nm or more at which no wave function coupling occurs between the quantum dot layers.

  However, with such a conventional technique, it is difficult to reduce the threshold current value.

JP 2009-65141 A

S. Anantathanasarn et al., Journal of Crystal Growth 298 (2007) 553-557 Jang et al., Appl. Phys. Lett., Vol. 85, No. 17, 25 (2004) F. Genz et al., J. Vac. Sci. Technol. B 28, 4, Jul / Aug 2010 P.J.Poole et al., Journal of Crystal Growth 311 (2009) 1482-1486

  An object of the present invention is to provide an optical semiconductor element capable of reducing a threshold current value while obtaining a high optical gain, and a manufacturing method thereof.

In one aspect of the optical semiconductor element, a substrate, a plurality of quantum dot layers formed above the substrate, and an intermediate layer positioned between the plurality of quantum dot layers are provided. The composition of the quantum dots contained in the quantum dot layer is represented by In _x Ga _1-x As _y Sb _1-y (0 <x ≦ 1, 0 <y ≦ 1). The intermediate layer includes an InGaAsP layer having _a composition represented by In _a Ga _1-a As _b P _1-b (0 <a <1, 0 <b <1) and a thickness of 10 nm to 40 nm. And an InP layer having a thickness of 0.3 nm or more and 2 nm or less located at a height of 10 nm or more and less than 40 nm from the bottom surface of the InGaAsP layer.

In another aspect of the optical semiconductor element, a substrate, a plurality of quantum dot layers formed above the substrate, and an intermediate layer positioned between the plurality of quantum dot layers are provided. The composition of the quantum dots contained in the quantum dot layer is represented by In _x Ga _1-x As _y Sb _1-y (0 <x ≦ 1, 0 <y ≦ 1). The intermediate layer includes an InGaAsP layer having _a composition represented by In _a Ga _1-a As _b P _1-b (0 <a <1, 0 <b <1) and a thickness of 10 nm to 40 nm. An InP layer formed on the InGaAsP layer and having a thickness of 0.3 nm to 2 nm.

In one aspect of the method for manufacturing an optical semiconductor element, a plurality of quantum dot layers and an intermediate layer positioned between the plurality of quantum dot layers are formed above the substrate. The composition of the quantum dots contained in the quantum dot layer is represented by In _x Ga _1-x As _y Sb _1-y (0 <x ≦ 1, 0 <y ≦ 1). When forming the intermediate layer, the composition is represented by In _a Ga _{1 -a} As _b P _{1 -b} (0 <a <1, 0 <b <1), and the thickness is 10 nm or more and 40 nm or less. An InGaAsP layer and an InP layer having a thickness of 0.3 nm or more and 2 nm or less are formed at a height of 10 nm or more and less than 40 nm from the bottom surface of the InGaAsP layer.

In another aspect of the method for manufacturing an optical semiconductor element, a plurality of quantum dot layers and an intermediate layer positioned between the plurality of quantum dot layers are formed above the substrate. The composition of the quantum dots contained in the quantum dot layer is represented by In _x Ga _1-x As _y Sb _1-y (0 <x ≦ 1, 0 <y ≦ 1). When forming the intermediate layer, the composition is represented by In _a Ga _{1 -a} As _b P _{1 -b} (0 <a <1, 0 <b <1), and the thickness is 10 nm or more and 40 nm or less. An InGaAsP layer is formed, and an InP layer having a thickness of 0.3 nm to 2 nm is formed on the InGaAsP layer.

  According to the above optical semiconductor element or the like, since an appropriate intermediate layer is provided between the quantum dot layers, the threshold current value is obtained while suppressing the variation in the surface density of the quantum dots between the quantum dot layers and obtaining a high optical gain. Can be reduced.

It is a figure which shows the result of the verification by this inventor. It is sectional drawing which shows the structure of the optical semiconductor element which concerns on 1st Embodiment. It is sectional drawing which shows the structure of the active layer 3 in 1st Embodiment. It is sectional drawing which shows the manufacturing method of the optical semiconductor element which concerns on 1st Embodiment. FIG. 4B is a cross-sectional view illustrating the method for manufacturing the optical semiconductor element, following FIG. 4A. It is sectional drawing which shows the method of forming the active layer 3 in 1st Embodiment. It is sectional drawing which shows the method of forming the active layer 3 following FIG. 5A. It is sectional drawing which shows the manufacturing method of the optical semiconductor element which concerns on 2nd Embodiment. FIG. 6B is a cross-sectional view illustrating a method for manufacturing the optical semiconductor element following FIG. 6A. It is sectional drawing which shows the structure of the active layer 3 in 3rd Embodiment. It is sectional drawing which shows the method of forming the active layer 3 in 3rd Embodiment. FIG. 8B is a cross-sectional view illustrating a method for forming the active layer 3 following FIG. 8A. It is a figure which shows the structure of the optical semiconductor module which concerns on 4th Embodiment.

  The inventor of the present application has intensively studied the cause of the difficulty in reducing the threshold current value in the conventional technique. As a result, the following matters were found.

  When the InGaAsP intermediate layer is used, composition separation occurs during the formation of the InGaAsP intermediate layer, so that the composition of the InGaAsP intermediate layer is not uniform, and is rich in InAs in the region above the InAs quantum dots, and GaP in the other regions. Become rich. The reason why the composition separation occurs is that the quantum dot layer has already been formed, and there is a difference in surface energy due to the local distribution of surface strain and shape. Since InAs has a larger lattice constant than GaP, a portion protruding from the GaP-rich region is generated in the InAs-rich region of the InGaAsP intermediate layer. That is, unevenness occurs on the surface of the InGaAsP intermediate layer. When the inventor of the present application scrutinized the contents described in Non-Patent Document 3, as shown in FIG. 1 (a), the thicker the InGaAsP intermediate layer, the smaller the unevenness, but the thicker the InGaAsP intermediate layer was about 40 nm. It was also revealed that there are irregularities (atomic steps) of 1 ML (mole layer) or less. For this reason, when focusing on the underlayer of the quantum dot layer, the quantum dot layer positioned closest to the substrate is formed on a flat surface, whereas the quantum dot layer positioned farther from the substrate is a InGaAsP intermediate layer. It will be formed on the surface where the unevenness of the layer exists.

  Furthermore, when the inventor of the present application also scrutinized the contents described in Non-Patent Document 4, when the surface of the InGaAsP intermediate layer has irregularities, the size of the InAs quantum dots increases as the distance from the substrate increases. As shown in FIG. 1 (b), it was found that as the number of quantum dot layers increases, the density of InAs quantum dots decreases and the half width of photoluminescence (PL) increases. For example, under the condition where the result shown in FIG. 1B is obtained, when the quantum dot layer is four layers, the quantum dot density is about 40% lower than that of the single layer, and the PL It was revealed that the full width at half maximum was about 12% higher. The tendency shown in FIG. 1B is for the case where the thickness of the InGaAsP intermediate layer is 30 nm.

  Because of this tendency, the threshold current value is high in a semiconductor laser including an active layer including a plurality of quantum dot layers of conventional InAs quantum dots.

  It is possible to reduce the unevenness by increasing the thickness of the InGaAsP intermediate layer. However, the thicker the InGaAsP intermediate layer, the lower the density of quantum dots in the active layer. Become.

  Hereinafter, embodiments conceived based on these findings will be specifically described with reference to the accompanying drawings.

(First embodiment)
First, the first embodiment will be described. FIG. 2 is a cross-sectional view showing the structure of the optical semiconductor device (semiconductor laser) according to the first embodiment. FIG. 2B shows a cross section taken along line I-I in FIG.

In the first embodiment, as shown in FIG. 2, a buffer layer 2, an active layer 3, and a cladding layer 4 are formed on a substrate 1, and these are etched to form a mesa structure 102. As the substrate 1, for example, an n-type InP substrate having a surface orientation of (001) is used. As the buffer layer 2, for example, an n-type InP layer doped with an n-type dopant at a concentration of 5.0 × 10 ¹⁷ cm ⁻³ and having a thickness of 500 nm is used. The active layer 3 will be described later. As the clad layer 4, for example, a p-type InP layer having a thickness of 200 nm and doped with a p-type dopant at a concentration of 5.0 × 10 ¹⁷ cm ⁻³ is used. A buried layer 103 and a block layer 104 are formed around the mesa structure 102. For example, a p-type InP layer is used as the buried layer 103, and an n-type InP layer is used as the block layer 104, for example. Further, a cladding layer 5 in contact with the cladding layer 4 is formed on the block layer 104, and a contact layer 6 is formed on the cladding layer 5. For example, a p-type InP layer doped with a p-type impurity at a concentration of 5.0 × 10 ¹⁷ cm ⁻³ is used as the cladding layer 5, and a p-type impurity is, for example, 1.0 p-type impurity. A p-type InGaAs layer doped at a concentration of × 10 ¹⁹ cm ⁻³ is used. A p-side electrode 7P is formed on the contact layer 6, and an n-side electrode 7N is formed on the back surface of the substrate 1. A low reflection film 8L is formed so as to cover one end face of the mesa structure 102, and a high reflection film 8H is formed so as to cover the other end face.

  Here, the active layer 3 will be described. FIG. 3 is a cross-sectional view showing the structure of the active layer 3 in the first embodiment.

  In the first embodiment, as shown in FIG. 3, the active layer 3 includes an optical confinement (SCH) layer 11 formed on the buffer layer 2. As the optical confinement layer 11, for example, a non-doped InGaAsP layer having a composition wavelength of 1.15 μm, a strain amount of 0%, and a thickness of 30 nm is used.

A quantum dot layer 12 is formed on the light confinement layer 11. The quantum dot layer 12 includes a plurality of self-forming (SK (Stranski-Krastanov) mode) InAs quantum dots 12a. For example, the surface density of the InAs quantum dots 12a is about 4.0 × 10 ¹⁰ cm ⁻² and the PL emission wavelength is 1.55 μm. On the quantum dot layer 12, a lower InGaAsP layer 13, an insertion layer 14, and an upper InGaAsP layer 15 are formed. As the lower InGaAsP layer 13, for example, an InGaAsP layer having a composition wavelength of 1.15 μm, no distortion, and a thickness of 10 nm is used. The lower InGaAsP layer 13 includes an InAs rich region 13a located above the quantum dot 12a and a GaP rich region 13b located above another portion (above the wet layer of the InAs quantum dot 12a). On the surface of the lower InGaAsP layer 13, there are irregularities of about 0.175 nm, for example, due to the difference in lattice constant between the InAs rich region 13a and the GaP rich region 13b. As the insertion layer 14, for example, an InP layer having a thickness of 2 nm is used. The insertion layer 14 does not inherit the unevenness present on the surface of the lower InGaAsP layer 13, and the surface of the insertion layer 14 is flat. As the upper InGaAsP layer 15, for example, an InGaAsP layer having a composition wavelength of 1.15 μm, no distortion, and a thickness of 20 nm is used. Since the surface of the insertion layer 14 is flat, the surface of the upper InGaAsP layer 15 is also flat. The compositions of the lower InGaAsP layer 13 and the upper InGaAsP layer 15 are represented by In _a Ga _1-a As _b P _1-b (0 <a <1, 0 <b <1), and may be common to each other. The composition may be different between the lower InGaAsP layer 13 and the upper InGaAsP layer 15. In the present embodiment, a stacked body of the lower InGaAsP layer 13, the insertion layer 14, and the upper InGaAsP layer 15 is an example of an intermediate layer.

  On the upper InGaAsP layer 15, two stacked bodies of the quantum dot layer 12, the lower InGaAsP layer 13, the insertion layer 14, and the upper InGaAsP layer 15 as described above are formed. Further, a quantum dot layer 12 is formed on the upper InGaAsP layer 15 located at the top, and a light confinement (SCH: separate confinement heterostructure) layer 16 is formed thereon. As the light confinement layer 16, as with the light confinement layer 11, for example, a non-doped InGaAsP layer having a composition wavelength of 1.15 μm, a strain amount of 0%, and a thickness of 30 nm is used. That is, the active layer 3 includes a total of four quantum dot layers 12. In the present embodiment, the quantum dot layer 12 positioned closest to the substrate 1 and the three quantum dot layers 12 positioned higher than the quantum dot layer 12 are all formed on a flat surface.

  For this reason, between the four quantum dot layers 12, the size and surface density of the quantum dots 12a are uniform. Accordingly, in consideration of FIG. 1B showing the characteristics of the optical semiconductor element (reference example) in which the thickness of the InGaAsP intermediate layer is 30 nm and the insertion layer is not used, according to the present embodiment, the insertion layer 14 is used. It can be said that the surface density of the quantum dots can be improved by about 40% and the half-value width of PL can be reduced by about 12%, compared to the case where it is not. Since the optical gain is proportional to the surface density of the quantum dots and inversely proportional to the PL half-value width, the optical gain increases by about 1.6 times compared to the case where the insertion layer 14 is not used, and the threshold current value Can be reduced by about 38%.

  Next, a method for manufacturing the optical semiconductor element (semiconductor laser) according to the first embodiment will be described. 4A to 4B are cross-sectional views illustrating the method of manufacturing the optical semiconductor device according to the first embodiment in the order of steps.

First, an n-type InP substrate 1 having a surface orientation of (001) is installed in a metal organic vapor phase epitaxy (MOVPE) growth reactor, and phosphine (PH) that is a raw material of P (Group V element) is used. ₃ ) Raise the growth temperature (substrate temperature) to 630 ° C. in an atmosphere. Next, trisilane indium (TMIn), which is a raw material of In (III group element), and monosilane (SiH ₄ ), which is a raw material of Si (n-type dopant), are supplied, and as shown in FIG. A buffer layer 2 of type InP is formed.

Thereafter, the active layer 3 is formed on the buffer layer 2. Here, a method of forming the active layer 3 will be described. 5A to 5B are cross-sectional views showing a method of forming the active layer 3 in the first embodiment in the order of steps. After the buffer layer 2 is formed, the supply of TMIn and SiH ₄ is stopped, and the growth temperature is lowered to 480 ° C. in a PH ₃ atmosphere. Next, the atmosphere is switched from a PH ₃ atmosphere to a mixed gas atmosphere of arsine (AsH ₃ ) which is a raw material of PH ₃ and As (group V element). Thereafter, TMIn and triethylgallium (TEGa), which is a raw material of Ga (Group III), are further supplied to form a non-doped InGaAsP optical confinement layer 11 as shown in FIG. 5A.

Subsequently, the supply of TMIn and AsH ₃ is continued, the supply of TEGa and PH ₃ is stopped, and as shown in FIG. 5A (b), the first InAs quantum dot layer 12 is formed. In the formation of the quantum dot layer 12, for example, the growth is performed under the conditions of a growth temperature of 480 ° C., an InAs supply amount of 2.5 ML, a growth rate of 0.1 μm / h, and a V / III ratio of 30. Under such conditions, the quantum dot layer 12 including the SK quantum dots 12a having a surface density of about 4.0 × 10 ¹⁰ cm ⁻² and a PL emission wavelength of 1.55 μm is formed.

  Next, under the same conditions as in the formation of the optical confinement layer 11, a lower InGaAsP layer 13 of InGaAsP is formed on the quantum dot layer 12, as shown in FIG. 5A (c). At this time, with the composition separation, the lower InGaAsP layer 13 includes the InAs rich region 13a and the GaP rich region 13b, and the surface of the lower InGaAsP layer 13 is accompanied by a difference in these lattice constants. For example, unevenness of about 0.175 nm is formed.

Thereafter, while maintaining the growth temperature at 480 ° C., the supply of TMIn and PH ₃ is continued, the supply of TEGa and AsH ₃ is stopped, and an InP insertion layer 14 is formed as shown in FIG. 5A (d). To do. The insertion layer 14 does not inherit the irregularities present on the surface of the lower InGaAsP layer 13, and the surface of the insertion layer 14 is flat.

  Subsequently, an upper InGaAsP layer 15 of InGaAsP is formed on the insertion layer 14 as shown in FIG. 5B (e) under the same conditions as those for forming the lower InGaAsP layer 13. Since the surface of the insertion layer 14 is flat, composition separation does not occur when the upper InGaAsP layer 15 is formed, and the surface of the upper InGaAsP layer 15 is flat.

  Next, under the same conditions as those for forming the first InAs quantum dot layer 12, the second InAs quantum dot layer 12 is placed on the upper InGaAsP layer 15 as shown in FIG. 5B (f). To form. Since the surface of the upper InGaAsP layer 15 is as flat as the surface of the optical confinement layer 11, the surface density of the quantum dots 12a in the second InAs quantum dot layer 12 is the same as that of the first layer. become. Thereafter, the formation of the lower InGaAsP layer 13, the insertion layer 14, the upper InGaAsP layer 15 and the quantum dot layer 12 is repeated twice under the same conditions as described above. Thereafter, an InGaAsP light confinement layer 16 is formed on the fourth quantum dot 12 under the same conditions as those for forming the light confinement layer 11. In this way, the active layer 3 including the four quantum dot layers 12 can be formed.

After the formation of the active layer 3, the growth temperature is raised to 630 ° C. in a PH ₃ atmosphere. Next, diethyl zinc (DEZn), TMIn and PH ₃ which are raw materials of Zn (p-type dopant) are supplied to form a p-type InP cladding layer 4 as shown in FIG. 4A (a). Thereafter, for example, the dielectric mask 101 having a length of 300 μm and a width of 1.5 μm extending in the [110] direction is patterned.

  Subsequently, dry etching is performed using the mask 101 as an etching mask to form a striped mesa structure 102 as shown in FIG. 4A (b).

  Next, as shown in FIG. 4B (c), a p-type InP buried layer 103 and an n-type InP block layer 104 are formed on both sides of the mesa structure 102 by pn buried growth using the mask 101 as a selective growth mask. To do. That is, the waveguide is formed by a current confinement structure of a stripe mesa pn buried type.

  After that, as shown in FIG. 4B (d), the mask 101 is removed by wet etching, and the p-type InP clad layer 5 and the p-type InGaAs contact layer 6 are formed on the block layer 104 and the clad layer 4. .

In the crystal growth by these MOCVD methods, for example, hydrogen (H ₂ ) is used as a carrier gas, and the growth pressure is 50 Torr.

  Then, the p-side electrode 7P is formed on the contact layer 6, the n-side electrode 7N is formed on the back surface of the substrate 1, the low reflection film 8L is formed on one end face (front end face) of the mesa structure 102, and the other The high reflection film 8H is formed on the end face (rear end face).

  In this manner, the optical semiconductor element (semiconductor laser) according to the first embodiment can be manufactured.

(Second Embodiment)
Next, a second embodiment will be described. In the first embodiment, a current confinement structure is formed by pn buried growth, whereas in the second embodiment, a current confinement structure is formed by Fe-doped high resistance (SI) buried growth. The structure of the optical semiconductor device (semiconductor laser) according to the second embodiment will be described together with its manufacturing method. 6A to 6B are cross-sectional views illustrating the method of manufacturing the optical semiconductor device according to the second embodiment in the order of steps.

  First, similarly to the first embodiment, as shown in FIG. 6A (a), processing up to the formation of the cladding layer 4 is performed. Next, the contact layer 6 is formed on the cladding layer 4. Thereafter, a mask 101 is formed on the contact layer 6 in the same manner as in the first embodiment.

  Subsequently, dry etching is performed using the mask 101 as an etching mask to form a striped mesa structure 102 as shown in FIG. 6A (b).

  Next, Fe-doped high-resistance (SI) buried growth using the mask 101 as a selective growth mask is used to form a Fe-doped high-resistance buried layer 105 on both sides of the mesa structure 102 as shown in FIG. 6B (c). To form. That is, the waveguide is formed by the current confinement structure of the stripe mesa SI embedded type.

  Thereafter, similarly to the first embodiment, the p-side electrode 7P, the n-side electrode 7N, the low reflection film 8L, and the high reflection film 8H are formed.

  Thus, the optical semiconductor device (semiconductor laser) according to the second embodiment can be manufactured.

  In the first and second embodiments, the total thickness of the pair of lower InGaAsP layer 13 and upper InGaAsP layer 15 positioned between the quantum dot layers 12 adjacent in the thickness direction is 10 nm or more and 40 nm or less. It is. If the total thickness is less than 10 nm, coupling of wave functions may occur between the quantum dot layers 12 adjacent in the thickness direction. When the total thickness exceeds 40 nm, the number density of the quantum dots 12a in the active layer 3 is low, and a vertical and high-dimensional propagation mode may occur. Further, the thickness of the lower InGaAsP layer 13 is 10 nm or more. That is, the insertion layer 14 is separated from the quantum dot layer 12 located immediately below by 10 nm or more in the thickness direction. If the thickness of the lower InGaAsP layer 13 is less than 10 nm, the degree of spread of the wave function to the insertion layer 14 differs depending on the size distribution of the quantum dot layer 12, so that the PL half-value width increases due to the expansion of the energy level distribution. In addition, the optical gain is reduced.

(Third embodiment)
Next, a third embodiment will be described. In the third embodiment, the configuration of the active layer 3 is different from that of the first embodiment. Other structures are the same as those of the first embodiment. FIG. 7 is a cross-sectional view showing the structure of the active layer 3 in the third embodiment.

In the third embodiment, as shown in FIG. 7, the active layer 3 includes a light confinement layer 21 formed on the buffer layer 2. As the optical confinement layer 21, for example, a non-doped InGaAsP layer having a composition wavelength of 1.2 μm, a strain amount of 0%, and a thickness of 30 nm is used. An insertion layer 24 is formed on the optical confinement layer 21. As the insertion layer 24, for example, an InP layer having a thickness of 2 nm is used. The quantum dot layer 12 is formed on the insertion layer 24. The quantum dot layer 12 includes a plurality of InAs quantum dots 12a. For example, the surface density of the InAs quantum dots 12a is about 3.0 × 10 ¹⁰ cm ⁻² and the PL emission wavelength is 1.55 μm. is there. An InGaAsP layer 23 is formed on the quantum dot layer 12. As the InGaAsP layer 23, for example, a layer having a composition wavelength of 1.2 μm, no distortion, and a thickness of 20 nm is used. The InGaAsP layer 23 includes an InAs rich region 23a located above the quantum dot 12a and a GaP rich region 23b located above another portion (above the wet layer of the InAs quantum dot 12a). On the surface of the InGaAsP layer 23, there are irregularities of, for example, about 0.1 nm due to the difference in lattice constant between the InAs rich region 23a and the GaP rich region 23b. Further, an insertion layer 24 is formed on such an InGaAsP layer 23. The insertion layer 24 does not inherit the unevenness present on the surface of the InGaAsP layer 23, and the surface of the insertion layer 24 is flat. The composition of the InGaAsP layer 23 is represented by In _a Ga _1-a As _b P _1-b (0 <a <1, 0 <b <1). In the present embodiment, the stacked body of the InGaAsP layer 23 and the insertion layer 24 is an example of an intermediate layer.

  Two stacked bodies of the quantum dot layer 12, the InGaAsP layer 23, and the insertion layer 24 as described above are formed on the second insertion layer 24 from the substrate 1 side. Further, the quantum dot layer 12 is formed on the insertion layer 24 positioned at the uppermost portion, and the light confinement layer 26 is formed thereon. As the light confinement layer 26, as with the light confinement layer 21, for example, a non-doped InGaAsP layer having a composition wavelength of 1.2 μm, a strain amount of 0%, and a thickness of 30 nm is used. That is, the active layer 3 includes a total of four quantum dot layers 12. Also in this embodiment, the quantum dot layer 12 positioned closest to the substrate 1 and the three quantum dot layers 12 positioned higher than the quantum dot layer 12 are all formed on a flat surface.

  For this reason, between the four quantum dot layers 12, the size and surface density of the quantum dots 12a are uniform. Therefore, as in the first embodiment, the threshold current value can be reduced while obtaining a high optical gain.

  Next, a method for manufacturing an optical semiconductor element (semiconductor laser) according to the third embodiment will be described. However, since the third embodiment is different from the first embodiment in the structure of the active layer 3, a method for forming the active layer 3 in the third embodiment will be described here. 8A to 8B are cross-sectional views showing a method of forming the active layer 3 in the third embodiment in the order of steps.

In the third embodiment, after the buffer layer 2 is formed, the supply of TMIn and SiH ₄ is stopped, and the growth temperature is lowered to 480 ° C. in a PH ₃ atmosphere. Next, the atmosphere is switched from a PH ₃ atmosphere to a mixed gas atmosphere of PH ₃ and AsH ₃ . Thereafter, TMIn and TEGa are further supplied to form the light confinement layer 21 of non-doped InGaAsP as shown in FIG. 8A (a). Subsequently, while maintaining the growth temperature at 480 ° C., the supply of TMIn and PH ₃ is continued, the supply of TEGa and AsH ₃ is stopped, and the InP insertion layer 24 is formed. Since the surface of the optical confinement layer 21 is flat, the surface of the insertion layer 24 is flat.

Next, TMIn and AsH ₃ are supplied to form the first InAs quantum dot layer 12 as shown in FIG. 8A (b). In the formation of the quantum dot layer 12, for example, the growth is performed under the conditions of a growth temperature of 480 ° C., an InAs supply amount of 2.5 ML, a growth rate of 0.1 μm / h, and a V / III ratio of 30. Under such conditions, the quantum dot layer 12 including the SK quantum dots 12a having a surface density of about 3.0 × 10 ¹⁰ cm ⁻² and a PL emission wavelength of 1.55 μm is formed.

  Next, an InGaAsP layer 23 of InGaAsP is formed on the quantum dot layer 12 as shown in FIG. 8A (c) under the same conditions as those for forming the optical confinement layer 21. At this time, the InGaAsP layer 23 includes the InAs rich region 23a and the GaP rich region 23b due to the composition separation, and the surface of the InGaAsP layer 23 has a difference of these lattice constants, for example, 0.1 nm. A degree of unevenness is formed.

Thereafter, the supply of TMIn and PH ₃ is continued, the supply of TEGa and AsH ₃ is stopped, and the second InP insertion layer 24 is formed from the substrate 1 side in FIG. 8B (d). The insertion layer 24 does not inherit the unevenness present on the surface of the InGaAsP layer 23, and the surface of the insertion layer 24 is flat.

  Subsequently, under the same conditions as in the formation of the first InAs quantum dot layer 12, the second InAs quantum dot layer 12 is replaced with the second InAs quantum dot layer 12 as shown in FIG. 5B (d). Formed on the insertion layer 24. Since the surface of the insertion layer 24 is as flat as the surface of the light confinement layer 21, the surface density of the quantum dots 12a in the second InAs quantum dot layer 12 is the same as that of the first layer. become. Thereafter, the formation of the InGaAsP layer 23, the insertion layer 24, and the quantum dot layer 12 under the same conditions as described above is repeated twice. Thereafter, an InGaAsP light confinement layer 26 is formed on the fourth-layer quantum dots 12 under the same conditions as in the formation of the light confinement layer 21. In this way, the active layer 3 including the four quantum dot layers 12 can be formed.

  In this manner, the optical semiconductor element (semiconductor laser) according to the third embodiment can be manufactured.

  In the third embodiment, the thickness of the InGaAsP layer 23 positioned between the quantum dot layers 12 adjacent in the thickness direction is 10 nm or more and 40 nm or less. If this thickness is less than 10 nm, coupling of wave functions may occur between the quantum dot layers 12 adjacent in the thickness direction. If this thickness exceeds 40 nm, the number density of the quantum dots 12a in the active layer 3 is low, and a longitudinal and high-dimensional propagation mode may occur.

  In the third embodiment, a current confinement structure is formed by pn buried growth as in the first embodiment. However, as in the second embodiment, Fe-doped high resistance (SI) buried growth is performed. Thus, a current confinement structure may be formed.

  Further, the insertion layer 24 located closest to the substrate 1 may not be provided. That is, the quantum dot layer 12 positioned closest to the substrate 1 may be formed directly on the light confinement layer 21. This is because the surface of the light confinement layer 21 is flat.

  In the first to fourth embodiments, the thickness of the insertion layers 14 and 24 above the quantum dot layer 12 located closest to the substrate 1 is not less than 0.3 nm and not more than 2 nm. If the thickness of the insertion layers 14 and 24 is less than 0.3 nm (1 ML), the influence of the unevenness existing on the surface of the lower InGaAsP layer 13 or InGaAsP layer 23 below the surface of the insertion layers 14 and 24 Also, irregularities appear on the surfaces of the insertion layers 14 and 24. On the other hand, if the thickness of the insertion layers 14 and 24 exceeds 2 nm, the element resistance becomes too high and the light emission efficiency is insufficient.

  Actually, when the inventor of the present application conducted the following experiment on the active layer 3 similar to that of the first embodiment, it was confirmed that the element resistance increased when the thickness of the insertion layer exceeded 2 nm. It was. In this experiment, the thicknesses of the lower InGaAsP layer / InP insertion layer / upper InGaAsP layer were 10 nm / 0 nm / 20 nm, 10 nm / 1 nm / 19 nm, 10 nm / 2 nm / 18 nm, 10 nm / 3 nm / 17 nm, respectively. An active layer in which four InAs quantum dot layers were grown was formed for each combination by employing a combination of thicknesses. Then, four types of semiconductor lasers using these active layers were produced. In each semiconductor laser, the stripe mesa width was 1.5 μm and the resonator length was 300 μm. As a result of measuring the element resistance of such a semiconductor laser, the resistance value of the three types of semiconductor lasers using the active layers of 10 nm / 0 nm / 20 nm, 10 nm / 1 nm / 19 nm, 10 nm / 2 nm / 18 nm was about 6Ω. In contrast, the resistance value of the semiconductor laser using the active layer of 10 nm / 3 nm / 17 nm was as high as 10Ω.

  It is considered that the increase in the element resistance accompanying the increase in the thickness of the insertion layer is due to the inhibition of carrier injection by applying the InP layer having a high band gap. Therefore, the thickness of the insertion layers 14 and 24 is set to 2 nm or less which does not inhibit carrier injection.

In the first to fourth embodiments, the structural parameters, constituent materials, and device structures are not limited to those described above. For example, the supply amount of InAs quantum dots and the composition wavelength, thickness, and strain amount of the InGaAsP barrier layer are not limited to the above values. Moreover, you may use things other than InAs as a material of a quantum dot. For example, it is possible to use InSb, InGaAs, etc. InGaAsSb, those whose composition is expressed by _{In x Ga 1-x As y} Sb 1-y (0 <x ≦ 1,0 <y ≦ 1). However, InAs is preferable from the viewpoint that the in-plane symmetry of the quantum dots is small. Further, as the substrate 1, a p-doped InP (001) substrate, a high resistance (SI) InP (001) substrate, or the like may be used. In these cases, it is preferable to appropriately change the embedded structure.

(Fourth embodiment)
Next, a fourth embodiment will be described. The fourth embodiment relates to an optical semiconductor module including the optical semiconductor element (semiconductor laser) of any one of the first to third embodiments. FIG. 9 is a diagram illustrating a configuration of an optical semiconductor module according to the fourth embodiment.

  In the optical semiconductor module according to this embodiment, as shown in FIG. 9, the semiconductor laser 31 of any of the first to third embodiments includes a coaxial package 33 having a pair of lead pins 36 and a pair of lead pins 37. It is mounted on. Further, a light receiving element 32 for back monitoring is installed on the rear end face side of the semiconductor laser 31. The pair of lead pins 36 is connected to the semiconductor laser 31, and the pair of lead pins 37 is connected to the light receiving element 32. The lead pin (terminal) 36 is connected to an electric signal source that drives the semiconductor laser 31. On the other hand, the lead pin 37 is connected to a monitor device that monitors the output of the semiconductor laser 31. In addition, a lens 35 that collects the laser beam 31L emitted from the front end surface of the semiconductor laser 31 and makes it incident on the optical fiber is provided on the cap 34. Here, the lens 35 functions as a light output port for outputting the signal light emitted from the semiconductor laser 31.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Appendix 1)
A substrate,
A plurality of quantum dot layers formed above the substrate;
An intermediate layer located between the plurality of quantum dot layers;
Have
The composition of the quantum dots contained in the quantum dot layer is represented by In _x Ga _1-x As _y Sb _1-y (0 <x ≦ 1, 0 <y ≦ 1),
The intermediate layer is
An InGaAsP layer having _a composition represented by In _a Ga _1-a As _b P _1-b (0 <a <1, 0 <b <1) and a thickness of 10 nm to 40 nm;
An InP layer located at a height of 10 nm to less than 40 nm from the bottom surface of the InGaAsP layer and having a thickness of 0.3 nm to 2 nm;
An optical semiconductor element comprising:

(Appendix 2)
A substrate,
A plurality of quantum dot layers formed above the substrate;
An intermediate layer located between the plurality of quantum dot layers;
Have
The composition of the quantum dots contained in the quantum dot layer is represented by In _x Ga _1-x As _y Sb _1-y (0 <x ≦ 1, 0 <y ≦ 1),
The intermediate layer is
An InGaAsP layer having _a composition represented by In _a Ga _1-a As _b P _1-b (0 <a <1, 0 <b <1) and a thickness of 10 nm to 40 nm;
An InP layer formed on the InGaAsP layer and having a thickness of 0.3 nm to 2 nm;
An optical semiconductor element comprising:

(Appendix 3)
The optical semiconductor element according to appendix 1 or 2, wherein the composition of the quantum dots is represented by InAs.

(Appendix 4)
A striped mesa structure including the plurality of quantum dot layers is formed,
4. The optical semiconductor element according to any one of appendices 1 to 3, wherein a waveguide is formed by providing a pn buried type current confinement structure around the mesa structure.

(Appendix 5)
A striped mesa structure including the plurality of quantum dot layers is formed,
4. The optical semiconductor device according to any one of appendices 1 to 3, wherein a waveguide is formed by providing a high-resistance buried type current confinement structure around the mesa structure.

(Appendix 6)
6. The optical semiconductor element according to any one of appendices 1 to 5, wherein the substrate is an InP substrate.

(Appendix 7)
The optical semiconductor element according to any one of appendices 1 to 6, wherein the intermediate layer includes the InGaAsP layer and the InP layer.

(Appendix 8)
An optical semiconductor module comprising the optical semiconductor element according to any one of appendices 1 to 7.

(Appendix 9)
Forming a plurality of quantum dot layers and an intermediate layer positioned between the plurality of quantum dot layers above the substrate;
The composition of the quantum dots contained in the quantum dot layer is represented by In _x Ga _1-x As _y Sb _1-y (0 <x ≦ 1, 0 <y ≦ 1),
The step of forming the intermediate layer is an InGaAsP having _a composition represented by In _a Ga _{1 -a} As _b P _{1 -b} (0 <a <1, 0 <b <1) and a thickness of 10 nm to 40 nm. And a step of forming an InP layer having a thickness of 0.3 nm or more and 2 nm or less located at a height of 10 nm or more and less than 40 nm from the bottom surface of the InGaAsP layer. .

(Appendix 10)
Forming a plurality of quantum dot layers and an intermediate layer positioned between the plurality of quantum dot layers above the substrate;
The composition of the quantum dots contained in the quantum dot layer is represented by In _x Ga _1-x As _y Sb _1-y (0 <x ≦ 1, 0 <y ≦ 1),
The step of forming the intermediate layer includes
Forming an InGaAsP layer having _a composition represented by In _a Ga _1-a As _b P _1-b (0 <a <1, 0 <b <1) and a thickness of 10 nm to 40 nm;
Forming an InP layer having a thickness of 0.3 nm to 2 nm on the InGaAsP layer;
A method for producing an optical semiconductor element, comprising:

(Appendix 11)
The method for producing an optical semiconductor element according to appendix 9 or 10, wherein the composition of the quantum dots is represented by InAs.

(Appendix 12)
Forming a striped mesa structure including the plurality of quantum dot layers;
Providing a pn buried type current confinement structure around the mesa structure to form a waveguide;
The method for manufacturing an optical semiconductor element according to any one of appendices 9 to 11, wherein:

(Appendix 13)
Forming a striped mesa structure including the plurality of quantum dot layers;
Forming a waveguide by providing a high-resistance buried type current confinement structure around the mesa structure; and
The method for manufacturing an optical semiconductor element according to any one of appendices 9 to 11, wherein:

(Appendix 14)
14. The method for manufacturing an optical semiconductor element according to any one of appendices 9 to 13, wherein the substrate is an InP substrate.

(Appendix 15)
15. The method of manufacturing an optical semiconductor element according to any one of appendices 9 to 14, wherein the intermediate layer includes the InGaAsP layer and the InP layer.

1: Substrate 3: Active layer 11: Optical confinement layer 12: Quantum dot layer 12a: Quantum dot 13: Lower InGaAsP layer 14: Insertion layer 15: Upper InGaAsP layer 16: Optical confinement layer 21: Optical confinement layer 23: InGaAsP layer 24: Insertion layer 26: Optical confinement layer 31: Optical semiconductor element

Claims (10)

A substrate,
A plurality of quantum dot layers formed above the substrate;
An intermediate layer located between the plurality of quantum dot layers;
Have
The composition of the quantum dots contained in the quantum dot layer is represented by In _x Ga _1-x As _y Sb _1-y (0 <x ≦ 1, 0 <y ≦ 1),
The intermediate layer is
An InGaAsP layer having _a composition represented by In _a Ga _1-a As _b P _1-b (0 <a <1, 0 <b <1) and a thickness of 10 nm to 40 nm;
An InP layer located at a height of 10 nm to less than 40 nm from the bottom surface of the InGaAsP layer and having a thickness of 0.3 nm to 2 nm;
An optical semiconductor element comprising: A substrate,
A plurality of quantum dot layers formed above the substrate;
An intermediate layer located between the plurality of quantum dot layers;
Have
The composition of the quantum dots contained in the quantum dot layer is represented by In _x Ga _1-x As _y Sb _1-y (0 <x ≦ 1, 0 <y ≦ 1),
The intermediate layer is
An InGaAsP layer having _a composition represented by In _a Ga _1-a As _b P _1-b (0 <a <1, 0 <b <1) and a thickness of 10 nm to 40 nm;
An InP layer formed on the InGaAsP layer and having a thickness of 0.3 nm to 2 nm;
An optical semiconductor element comprising:   The optical semiconductor element according to claim 1, wherein the composition of the quantum dots is represented by InAs. A striped mesa structure including the plurality of quantum dot layers is formed,
4. The optical semiconductor device according to claim 1, wherein a waveguide is formed by providing a pn buried type current confinement structure around the mesa structure. 5. A striped mesa structure including the plurality of quantum dot layers is formed,
4. The optical semiconductor device according to claim 1, wherein a waveguide is formed by providing a high-resistance buried type current confinement structure around the mesa structure. 5.   The optical semiconductor device according to claim 1, wherein the substrate is an InP substrate.   An optical semiconductor module comprising the optical semiconductor element according to claim 1. Forming a plurality of quantum dot layers and an intermediate layer positioned between the plurality of quantum dot layers above the substrate;
The composition of the quantum dots contained in the quantum dot layer is represented by In _x Ga _1-x As _y Sb _1-y (0 <x ≦ 1, 0 <y ≦ 1),
The step of forming the intermediate layer is an InGaAsP having _a composition represented by In _a Ga _{1 -a} As _b P _{1 -b} (0 <a <1, 0 <b <1) and a thickness of 10 nm to 40 nm. And a step of forming an InP layer having a thickness of 0.3 nm or more and 2 nm or less located at a height of 10 nm or more and less than 40 nm from the bottom surface of the InGaAsP layer. . Forming a plurality of quantum dot layers and an intermediate layer positioned between the plurality of quantum dot layers above the substrate;
The composition of the quantum dots contained in the quantum dot layer is represented by In _x Ga _1-x As _y Sb _1-y (0 <x ≦ 1, 0 <y ≦ 1),
The step of forming the intermediate layer includes
Forming an InGaAsP layer having _a composition represented by In _a Ga _1-a As _b P _1-b (0 <a <1, 0 <b <1) and a thickness of 10 nm to 40 nm;
Forming an InP layer having a thickness of 0.3 nm to 2 nm on the InGaAsP layer;
A method for producing an optical semiconductor element, comprising:   The method of manufacturing an optical semiconductor element according to claim 8, wherein the composition of the quantum dots is represented by InAs.

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