JP2013098886A - Communication device and operation method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique capable of reducing the number of components in a communication device, while adding to the communication device an equivalent function to an interleave function after repetition.SOLUTION: A communication device 10 includes: a memory for storing a transmission data; an output controller 131 for controlling the output of the transmission data stored in the memory; and transmission means for modulating and transmitting the data output from the memory. The output controller 131 changes an output order of each bit data included in the transmission data stored in the memory, to output for a predetermined number of times per data bit.

Description

  The present invention relates to communication technology.

  Generally, in a communication device that performs communication via a wired or wireless transmission path, various devices have been made in order to reliably transmit transmission data to the receiving side.

  As a method for reliably transmitting transmission data to the reception side, for example, in a transmission device, encoding for adding error correction information to the transmission data is performed, and the encoded transmission data is transmitted. There is a method. The receiving device that has received the encoded transmission data can acquire the original transmission data by decoding the reception data.

  As another method, for example, there is a method of performing repetition (Repetition) in which transmission data is repeatedly copied in a transmission device (for example, Patent Document 1). According to this method, since the data after repetition is transmitted over several symbols, the redundancy can be increased and the robustness of the transmission data against interference can be improved.

JP 2011-176598 A

  However, since the data after repetition generated by repeating the transmission data is vulnerable to burst errors that occur continuously, there is a possibility that data redundancy will not be sufficiently exhibited. As a result, the bit error rate of the demodulated data may deteriorate on the receiving side.

  As a method for dealing with continuous burst errors, it is conceivable to perform interleaving for rearranging bit strings of data after repetition. However, in order to implement interleaving after repetition, a communication unit having a function of performing interleaving after repetition, such as a storage unit for storing data after repetition that has been repeatedly copied, is required to realize the function. This increases the number of parts.

  Therefore, an object of the present invention is to provide a technique capable of reducing the number of parts of a communication device while giving the communication device a function equivalent to a function of performing interleaving after repetition.

  A first aspect of the communication device according to the present invention is a storage unit that stores transmission data, output control means that controls output of the transmission data stored in the storage unit, and data output from the storage unit Transmitting means for modulating and transmitting the data, and the output control means outputs each bit data included in the transmission data a predetermined number of times for each bit data by changing the output order.

  Also, a second aspect of the communication apparatus according to the present invention is the first aspect, wherein the output control means stores an address indicating a storage destination of output target bit data in the storage unit as an output start address. The storage unit outputs the bit data stored in the output start address according to the input of the output start address, and sequentially outputs other bit data included in the transmission data. The output control means outputs the output start address to the storage unit a predetermined number of times while changing the output start address.

  Moreover, the 3rd aspect of the communication apparatus which concerns on this invention is the said 1st aspect, Comprising: The said output control means WHEREIN: Each address which shows the storage place of each bit data contained in the said transmission data is said memory | storage part And the storage unit outputs bit data stored in each address according to the input of each address, and the output control means changes the output order of the addresses while changing the output order. The predetermined number of times is output for each address.

  Moreover, the 4th aspect of the communication apparatus which concerns on this invention is the said 1st aspect, Comprising: The said output control means is the shift number at the time of carrying out bit shift of the bit sequence regarding the said transmission data memorize | stored in the said memory | storage part. To the storage unit, the storage unit performs a cyclic shift process of shifting the bit string in a certain direction in accordance with the input of the shift number, and filling the bit string overflowed by the shift into an empty part, The storage unit sequentially outputs the bit string after the cyclic shift processing from one end, and the output control unit outputs the shift number to the storage unit the predetermined number of times while changing the shift number.

  A communication device according to a fifth aspect of the present invention is the communication device according to any one of the first to fourth embodiments, wherein the input data is subjected to error correction encoding, and the code Interleaving means for performing an interleaving process on the data output from the converting means, and the transmission data stored in the storage unit is the data after the interleaving process.

  The operation method of the communication apparatus according to the present invention includes: a) a step of outputting each bit data included in the transmission data stored in the storage unit a predetermined number of times for each bit data by changing the output order; b) the storage And modulating and transmitting data output from the unit.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to implement | achieve size reduction of a communication apparatus, providing the function equivalent to the function to perform interleaving after repetition to a communication apparatus.

It is a block diagram of the communication system which concerns on this embodiment. It is a figure which shows the structure of the transmitter which concerns on this embodiment. It is a figure which shows an example of the process performed to transmission data before primary modulation. It is a figure for demonstrating the output operation of the data from an interleave part.

  Hereinafter, embodiments will be described with reference to the drawings.

<Embodiment>
[1. Configuration of communication system]
FIG. 1 is a configuration diagram of a communication system 1 according to the present embodiment.

  As illustrated in FIG. 1, the communication system 1 includes a first communication device 10 and a second communication device 20. The first communication device 10 and the second communication device 20 in the communication system 1 are configured to be able to communicate with each other by wired communication. The transmission line 30 that electrically connects the first communication device 10 and the second communication device 20 may be a normal communication line or a power line. When a power line is used as a transmission path, the first communication device 10 and the second communication device 20 perform communication by power line communication (PLC).

  The wired communication between the communication devices 10 and 20 is performed using an OFDM (Orthogonal Frequency Division Multiplexing) signal obtained by combining a plurality of subcarriers orthogonal to each other on the frequency axis. Then, the OFDM signal is transmitted in packet units divided by a certain time unit.

  Below, the structure of the communication apparatus 10 (20) which functions as a transmission apparatus is explained in full detail.

[2. Configuration of transmitter]
FIG. 2 is a diagram illustrating a configuration of the transmission device 10 according to the present embodiment.

  As illustrated in FIG. 2, the transmission device 10 includes a scrambler 111, an encoding unit 112, an interleave unit (interleaver) 113, an output control unit 131, a primary modulation unit 114, an input signal configuration unit 115, an IFFT (inverse high speed). A Fourier transform unit 116, a parallel / serial conversion unit (parallel / serial conversion unit) 117, a GI addition unit 118, a preamble generation unit 119, a packet configuration unit 120, and a transmission unit 121 are provided.

  Specifically, the scrambler 111 performs scramble processing that agitates and rearranges the input transmission data. The transmission data that has been scrambled by the scrambler 111 is input to the encoding unit 112.

  The encoding unit 112 performs redundant encoding for error correction on the transmission data subjected to the scramble process. For example, a convolutional code having a constraint length k = 7 and a coding rate of 1/2 is used for the redundant coding. A bit string of transmission data output from the encoding unit 112 is input to the interleaving unit 113.

  Interleaving section 113 performs bit interleaving for rearranging the bit string of the transmission data so that errors in the transmission data output from encoding section 112 are not biased.

  The output control unit 131 has a function of controlling the output of the interleave unit 113. Details of the output control by the output control unit 131 will be described later. Transmission data output from the interleaving unit 113 is input to the primary modulation unit 114.

  In primary modulation section 114, transmission data is mapped (correlated) to subcarriers for each symbol according to a predetermined modulation scheme (for example, QPSK, 16QAM).

  Note that the symbol (Symbol) here is a unit of transmission data, which is determined by each modulation scheme and is carried on a carrier wave (subcarrier). In order to avoid confusion with an OFDM symbol described later, a data symbol or a complex symbol is used. Also called a symbol. For example, in QPSK, transmission data that can be transmitted in one symbol (one data symbol) is 2 bits.

  Input signal configuration section 115 is configured by a buffer or the like, and converts data symbols input from primary modulation section 114 into a predetermined number of parallel data in order to disperse data signals including transmission data on subcarriers. have.

  The IFFT unit 116 performs inverse fast Fourier transform on the parallel data input from the input signal configuration unit 115 to convert the frequency domain data into time domain data. The frequency domain data input from the input signal configuration unit 115 is amplitude and phase data for each subcarrier, and the IFFT unit 116 calculates time data for one OFDM symbol from the amplitude phase data for each subcarrier. Will be generated.

  The parallel-serial conversion unit 117 has a function of converting parallel data input from the IFFT unit 116 into serial data. The serial data output from the parallel-serial conversion unit 117 is input to the GI adding unit 118 as a baseband (baseband) OFDM signal (baseband OFDM signal).

  The GI addition unit 118 performs a guard interval (GI) addition process on the baseband OFDM signal input from the parallel-serial conversion unit 117 and outputs the baseband OFDM signal to which the GI has been added to the packet configuration unit 120. .

  The preamble generation unit 119 has a function of generating and outputting a preamble signal for use in various synchronization processes such as frame synchronization and frequency synchronization performed on the reception side.

  The packet composing unit 120 adds a preamble signal to the OFDM signal output from the GI adding unit 118 to generate a signal in units of packets (also referred to as “packet signal”).

  The transmission unit 121 performs DA conversion processing that converts the digital packet signal generated by the packet configuration unit 120 into an analog packet signal, and outputs the packet signal after the DA conversion processing as a communication signal. The communication signal output from the transmission unit 121 is transmitted to the reception device 20 via the transmission path 30.

  In this way, the transmission device 10 generates a packet signal and transmits the packet signal as a communication signal.

  In addition, the primary modulation unit 114, the input signal configuration unit 115, the IFFT unit 116, the parallel-serial conversion unit 117, the GI addition unit 118, the preamble generation unit 119, the packet configuration unit 120, and the transmission unit 121 included in the transmission device 10 described above. Can also be expressed as transmission means for modulating and transmitting data output from the interleave unit 113.

[3. Transmission data before primary modulation]
Here, transmission data before being input to primary modulation section 114 will be described. FIG. 3 is a diagram illustrating an example of processing performed on transmission data before primary modulation.

  As shown in FIG. 2, transmission data before being input to primary modulation section 114 is subjected to encoding for error correction in encoding section 112 (see FIG. 2). In order to reliably transmit data to the receiving side, it is preferable to improve the robustness of transmission data against interference.

  As a technique for improving the robustness, for example, there is a technique of performing repetition (copying) of transmission data one or more times and transmitting the data after repetition.

  For example, as shown in FIG. 3, when transmission data D1 having a data length of 8 bits is output from the encoding unit 112, the interleaving unit 113 performs interleaving on the transmission data D1. , Transmission data D2 is generated. If the transmission data D1 includes an error part ER, the bias of the error part ER is corrected by the interleaving.

  Then, when repetition is performed on the transmission data D2 after interleaving three times, 32-bit transmission data D3 is generated. Note that the repetition in which the transmission data D2 is repeated three times is also referred to as a repetition in which the transmission data D2 is quadrupled.

  Transmission data D3 after repetition includes four transmission data D1. By transmitting such transmission data D3, the redundancy can be increased compared to the case where transmission data D1 before repetition is transmitted, and therefore there is a possibility that the transmission data D1 can be demodulated on the receiving side. Get higher.

  However, if the transmission data D3 after repetition is used as it is to generate an OFDM signal in the time domain, the ratio of maximum power to average power (PAPR: Peak to Average Power Ratio) in the OFDM signal may be increased. Generally, a transmission apparatus that transmits an OFDM signal is designed so that the signal is not distorted by widening the dynamic range (maximum and minimum ranges of signal amplitude) of an amplifier that amplifies the transmission signal. For this reason, when the PAPR of the transmission signal increases, it becomes difficult to design an amplifier.

  In addition, since the transmission data D3 after repetition is vulnerable to continuously occurring burst errors, there is a possibility that data redundancy is not sufficiently exhibited. For this reason, when the transmission data D3 after repetition is used as it is to generate an OFDM signal in the time domain and the OFDM signal is transmitted, the bit error rate (BER: Bit Error Rate) of the demodulated data on the receiving side Becomes worse than the theoretical value.

  These phenomena are considered to have occurred because the transmission data D3 after repetition is data having periodicity generated by simply copying the transmission data D1 a plurality of times.

  Therefore, as shown in FIG. 3, the transmission data D3 after repetition is further interleaved to generate transmission data D4 having no periodicity, and an OFDM signal is transmitted using the transmission data D4. Is preferably generated.

  However, when interleaving is performed on the transmission data D3 after repetition by the conventional method, a storage unit for interleaving is required. Further, when the transmission data after repetition increases, the time required for interleaving increases.

  Therefore, the transmission apparatus 10 of this embodiment controls the output of the interleaving unit 113 to perform primary modulation on data having the same properties as the transmission data D4 obtained by repetition and interleaving on the transmission data D2. Input to the unit 114.

[4. Data output operation from interleave unit 113]
Next, the data output operation from the interleaving unit 113 executed according to the control of the output control unit 131 will be described in detail. FIG. 4 is a diagram for explaining the data output operation from the interleave unit 113. In FIG. 4, for the sake of simplicity, it is assumed that transmission data D1 having a data length of 8 bits is output from the encoding unit 112, but the transmission data D1 has other data lengths. You may do it.

  As shown in FIG. 4, the interleave unit 113 performs interleaving on the 8-bit transmission data D <b> 1 output from the encoding unit 112. The transmission data D2 generated by the interleaving is temporarily stored in the storage unit 132 in the interleaving unit 113.

  The output control unit 131 outputs the bit unit data (also referred to as “bit data”) included in the transmission data D2 in the storage unit 132 so that the output order is changed a predetermined number of times (for example, four times) for each bit data. Control the output.

  Specifically, the output control unit 131 generates an address indicating a storage destination of data to be output, and outputs the address to the storage unit 132 as an output start address (also referred to as “read start address”). In response to the input of the output start address, the storage unit 132 outputs the bit data stored at the output start address, and sequentially outputs the bit data stored at other addresses according to a predetermined output rule. .

For example, when the address AD0 is input as the output start address, the storage unit 132 outputs the bit data stored in the output start address AD0 and increments the address (output target address) by one. The bit data stored at each address is sequentially output. That is, when the output start address AD0 is input, the storage unit 132 executes the output operation PE1, and the bit data b ₀ , bit data b ₁ , bit data b ₂ , bit data b ₃ , bit data b ₄ , bit Data b ₅ , bit data b ₆ , and bit data b ₇ are sequentially output in this order.

  Next, the output control unit 131 generates an output start address different from the previously output output start address AD0 and outputs it to the storage unit 132.

For example, the output control unit 131 outputs an output start address AD6 different from the output start address AD0 to the storage unit 132. In this case, the storage unit 132 outputs the bit data b ₆ stored in the output start address AD6, increments the output target address by 1, and outputs the bit data b ₇ . When the output target address reaches the final address, the storage unit 132 resets the output target address and moves the output target address to the top address. Further, the output of the bit data is restarted from the head address, and the output target address is incremented by 1 until the output of all the bit data included in the transmission data D2 is completed, and stored in each incremented output target address. The bit data is output sequentially. That is, when the output start address AD6 is input, the storage unit 132 executes the output operation PE2, and the bit data b ₆ , bit data b ₇ , bit data b ₀ , bit data b ₁ , bit data b ₂ , bit Data b ₃ , bit data b ₄ , and bit data b ₅ are sequentially output in this order.

  Further, the output control unit 131 generates an output start address that is different from the output start address AD6 output previously, and outputs the output start address to the storage unit 132.

For example, the output control unit 131 outputs an output start address AD5 different from the output start address AD6 to the storage unit 132. In this case, the storage unit 132 outputs the bit data b ₅ stored in the output start address AD5, increments the output target address by 1, and outputs bit data b ₆ and b ₇ respectively. When the output target address reaches the final address, the storage unit 132 resets the output target address and moves the output target address to the top address. Further, the output of the bit data is restarted from the head address, and the output target address is incremented by 1 until the output of all the bit data included in the transmission data D2 is completed, and stored in each incremented output target address. The bit data is output sequentially. That is, when the output start address AD5 is input, the storage unit 132 executes the output operation PE3, and the bit data b ₅ , bit data b ₆ , bit data b ₇ , bit data b ₀ , bit data b ₁ , bit Data b ₂ , bit data b ₃ , and bit data b ₄ are sequentially output in this order.

  Furthermore, the output control unit 131 generates an output start address different from the previously output output start address AD5 and outputs it to the storage unit 132.

For example, the output control unit 131 outputs an output start address AD2 different from the output start address AD5 to the storage unit 132. In this case, the storage unit 132 outputs the bit data b ₂ stored in the output start address AD2, increments the output target address by 1, sequentially bit data stored in the incremented each address Output to. When the output target address reaches the final address, the storage unit 132 resets the output target address and moves the output target address to the top address. Further, the output of the bit data is restarted from the head address, and the output target address is incremented by 1 until the output of all the bit data included in the transmission data D2 is completed, and stored in each incremented output target address. The bit data is output sequentially. That is, when the output start address AD2 is input, the storage unit 132 executes the output operation PE4, and the bit data b ₂ , bit data b ₃ , bit data b ₄ , bit data b ₅ , bit data b ₆ , bit Data b ₇ , bit data b ₀ , and bit data b ₁ are sequentially output in this order.

  In this way, each time the output start address is input from the output control unit 131 to the storage unit 132, the storage unit 132 executes the output operation and outputs all the bit data included in the transmission data D2. Therefore, when output start addresses are sequentially input from the output control unit 131 to the storage unit 132 a predetermined number of times, each bit data included in the transmission data D2 is output from the storage unit 132 a predetermined number of times. Become.

  For example, as illustrated above, when the output start addresses AD0, AD6, AD5, and AD2 are input to the storage unit 132 four times from the output control unit 131, all the bit data included in the transmission data D2 is received from the storage unit 132. Will be output four times. That is, the storage unit 132 outputs substantially four transmission data D2, and the output data D11 output from the storage unit 132 (in other words, from the interleave unit 113) is four times the transmission data D2. Corresponds to the data obtained (repeated three times).

  Since the output control unit 131 changes the output start address for output, the output order of the bit data output by each of the output operations PE1, PE2, PE3, and PE4 is different. As a result, the bit data in the output data D11 are arranged in a disordered manner as if they were interleaved.

  In this way, the output control unit 131 controls the output of the interleaving unit 113 to thereby convert the data D11 having the same properties as data obtained by subjecting the transmission data D2 to repetition and interleaving to the primary modulation unit 114. To input.

  In the above description, the case where the output control unit 131 outputs the output start address four times and the transmission data D2 is repeated three times (repetition number) is exemplified. However, the transmission data D2 is repeated only once. The output start address can be freely set by changing the number of outputs. For example, when the repeat count of the transmission data D2 is set to 1, the output count of the output start address by the output control unit 131 is set to 2 times. That is, the output count of the output start address by the output control unit 131 (corresponding to “predetermined number” in this specification) is set according to the number of repetitions of the transmission data D2.

  As described above, the transmission device 10 according to the present embodiment includes the storage unit 132 that stores the transmission data D2, the output control unit 131 that controls the output of the transmission data D2 stored in the storage unit 132, and the storage unit 132. Transmitting means for modulating and transmitting the data output from. Then, the output control unit 131 outputs each bit data included in the transmission data D2 stored in the storage unit 132 a predetermined number of times for each bit data by changing the output order.

  According to such a transmission apparatus 10, the data D11 having the same properties as the transmission data D4 obtained by subjecting the transmission data D2 to repetition and interleaving can be input to the primary modulation unit 114. Therefore, the number of parts of the transmission apparatus 10 can be reduced as compared with a case where a function for actually performing repetition on the transmission data D2 and a function for actually interleaving data after repetition are newly provided. It becomes possible. In particular, in the transmission device 10 of the present embodiment, it is not necessary to provide a buffer for performing interleaving after repetition.

  Also, when the data after repetition becomes large, the processing time required for interleaving increases in interleaving after repetition. However, in the transmission device 10 of the present embodiment, normal interleaving is not actually performed, so that the processing time required for interleaving can be shortened.

  Note that the receiving device 20 has information about the output order of each bit data controlled by the output control unit 131 as known information in advance. For this reason, the receiving device 20 can acquire the transmission data by decoding the reception data.

<Modification>
Although the embodiment has been described above, the present invention is not limited to the content described above.

  For example, in the above embodiment, the output control unit 131 inputs the output start address to the storage unit 132, but the present invention is not limited to this.

Specifically, the output control unit 131 sequentially inputs one address at a time indicating the storage destination of the bit data to be output to the storage unit 132, and the storage unit 132 receives the bit according to the input address. It is good also as an aspect which outputs data. In this case, for example, in the first output operation PE1, the output control unit 131 sequentially outputs the addresses AD0 to AD7 to the storage unit 132, and the storage unit 132 responds to the input of the addresses AD0 to AD7. thereby outputting bit data b ₀ ~b ₇ sequentially. In the next output operation PE2, the output control unit 131 sequentially outputs to the addresses AD6, AD7, AD0 to AD5 storage unit 132, and the storage unit 132 responds to the inputs of the addresses AD6, AD7, AD0 to AD5. Te, thereby outputting the bit data _{b 6, b 7, b 0} ~b 5 sequentially.

  In this aspect, the output control unit 131 outputs each address indicating the storage destination of each bit data included in the transmission data a predetermined number of times for each address while changing the output order.

  Further, the data output operation from the interleave unit 113 may be a mode in which the bit data is output while shifting the bit string of the transmission data D2 and performing a cyclic shift to fill the vacant bit string in the vacant part. Good.

Specifically, the output control unit 131 outputs the shift number when the bit string of the transmission data D2 is bit-shifted to the storage unit 132. For example, in the first output operation PE1, the output control unit 131 outputs, to the storage unit 132, the shift number “0” when performing the first output for each bit data included in the transmission data D2. When the input shift number is “0”, the storage unit 132 outputs bit data in order from the left end of the data stored in the storage unit 132 (in this case, bit data b ₀ ) without performing a shift. To do.

In the next output operation PE <b> 2, the output control unit 131 outputs the shift number “2” when performing the second output for each bit data to the storage unit 132. The storage unit 132 shifts the bit string of the data stored in the storage unit 132 to the left by 2 bits according to the input shift number “2”, and the bit string overflowed by the shift (bit data b ₆ , b ₇ ) Perform a cyclic shift process to fill the empty part, and store the data after the cyclic shift process in the storage unit 132. Then, the storage unit 132, the left end of the stored data (in this case, bit data b ₆₎ outputs the bit data in order from.

In the next output operation PE <b> 3, the output control unit 131 outputs the shift number “1” when performing the third output for each bit data to the storage unit 132. The storage unit 132 shifts the bit string of the data stored in the storage unit 132 to the left by 1 bit in accordance with the input shift number “1”, and the bit string (bit data b ₅ ) overflowed by the shift is stored. Performs a cyclic shift process to fill in empty areas. Then, the storage unit 132, the left end of the data after cyclic shift processing (in this case, bit data b ₅₎ outputs the bit data in order from.

In the next output operation PE4, the output control unit 131 outputs to the storage unit 132 the shift number “3” when performing the fourth output for each bit data. The storage unit 132 shifts the bit string of the data stored in the storage unit 132 to the left by 3 bits according to the input shift number “3”, and the bit string overflowed by the shift (bit data b ₂ , b ₃ and b ₄ ) are cyclically shifted to fill the empty part. Then, the storage unit 132, the left end of the data after cyclic shift processing (in this case, bit data b ₂₎ and outputs the bit data in order from.

  As described above, when the bit data is output while performing the cyclic shift, the output control unit 131 outputs the shift number to the storage unit 132 a predetermined number of times while changing the shift number.

  Moreover, although the transmission apparatus 10 and the receiving apparatus 20 in the communication system 1 illustrated the aspect comprised so that communication was possible by wired communication in the said embodiment, it is not limited to this. Specifically, the transmission device 10 and the reception device 20 may be configured to be communicable by wireless communication.

  Moreover, in the said embodiment, although the memory | storage part 132 was set as the aspect which exists in the interleave part 113, it is not limited to this, It is good also as an aspect provided inside the transmitter 10 and outside the interleave part 113. . In this case, the output control unit 131 performs data output control on the storage unit 132.

1 Communication System 10 Communication Device (Transmitter)
20 Communication device (receiving device)
30 transmission path 112 encoding unit 113 interleaving unit 114 primary modulation unit 131 output control unit 132 storage unit

Claims (6)

A storage unit for storing transmission data;
Output control means for controlling the output of the transmission data stored in the storage unit;
Transmitting means for modulating and transmitting data output from the storage unit;
With
The output control means is a communication device for outputting each bit data included in the transmission data a predetermined number of times for each bit data by changing an output order. The output control means outputs an address indicating a storage destination of output target bit data to the storage unit as an output start address,
The storage unit outputs the bit data stored in the output start address according to the input of the output start address, and sequentially outputs other bit data included in the transmission data,
The communication apparatus according to claim 1, wherein the output control unit outputs the output start address to the storage unit the predetermined times while changing the output start address. The output control means outputs each address indicating a storage location of each bit data included in the transmission data to the storage unit,
In response to the input of each address, the storage unit outputs bit data stored in each address,
The communication apparatus according to claim 1, wherein the output control means outputs the addresses a predetermined number of times for each address while changing an output order. The output control means outputs, to the storage unit, a shift number when bit-shifting a bit string related to the transmission data stored in the storage unit,
The storage unit performs a cyclic shift process in which the bit string is shifted in a certain direction in accordance with the input of the shift number, and the bit string overflowed by the shift is filled in an empty part,
The storage unit sequentially outputs the bit string after the cyclic shift processing from one end,
The communication apparatus according to claim 1, wherein the output control unit outputs the shift number to the storage unit the predetermined number of times while changing the shift number. Encoding means for error-correcting the input data;
Interleaving means for performing an interleaving process on the data output from the encoding means;
Further comprising
The communication apparatus according to claim 1, wherein the transmission data stored in the storage unit is data after the interleaving process. a) outputting each bit data included in the transmission data stored in the storage unit a predetermined number of times for each bit data by changing the output order;
b) modulating and transmitting data output from the storage unit;
A method of operating a communication device comprising:

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