KR20100105222A - Apparatus and method for interleaving in communication system - Google Patents

Abstract

PURPOSE: An interleaving device in a communication system and a method thereof are provided to perform interleaving to make reliable input bits of decoders, thereby increasing system performance. CONSTITUTION: An interleaver performs each uniform interleaving for A, B, Y1, Y2, W1 and W2 sub blocks(700). According to reliability of bits of A sub block, the interleaver performs the first permutation for bits of B sub block(702). The interleaver performs the second permutation for bits of W1 sub block based on reliability of bits of Y1 sub block(704). The interleaver groups bits for each sub block(706).

Description

Apparatus and method for interleaving in a communication system {APPARATUS AND METHOD FOR INTERLEAVING IN COMMUNICATION SYSTEM}

The present invention relates to interleaving, and more particularly, to an interleaving apparatus and method for ensuring that input bits of a decoder have a uniform reliability in a communication system.

In recent years, digital communication systems have tended to apply a high-order modulation scheme for high-speed data transmission within a limited frequency band. For example, terrestrial digital TV systems and Institute of Electrical and Electronics Engineers (IEEE) 802.16 systems can be used to transfer data using limited bandwidth, such as Quadrature Phase Shift Keying (QPSK), Quadrature Amplitude Modulation (16QAM), and 64QAM. High order modulation is used.

In a wireless communication system, channel coding such as a convolution code, a turbo code, and a convolution turbo code (CTC) is used to prevent distortion of information transmitted by multipath fading or noise. The CTC is used for channel coding of the IEEE 802.16 standard. In the turbo code, the encoder receives and processes one bit every clock, whereas the CTC receives and processes two bits every clock. Therefore, the processing speed in the CTC decoder is about 2 times higher than that of the binary turbo code.

On the other hand, in the current wireless communication system, errors occurring on the communication channel due to fading interference and noise have a coherency, and the maximum likelihood ratio, which is the output of the decoder, has a correlation with each other. If this correlated information is used as the input of the next iteration decoder, satisfactory performance will not be obtained. Therefore, in order to effectively convert the correlated information so as to reduce the correlation and change the burst error to a random error, the transmitter performs interleaver. That is, interleaving converts the concatenation error into a random error by distributing and outputting code bits. The interleaved code bits are mapped to the constellation point and modulated according to the modulation scheme.

1 shows a 16QAM constellation according to the prior art.

Referring to FIG. 1, in the 16QAM modulation scheme, 4 bits are mapped to one modulation symbol among 16 modulation symbols. Here, when the bits mapped to the 16QAM modulation symbols are b3, b2, b1, and b0, interleaved code bits are input to the modulator in the order of b0, b1, b2, b3 according to a predefined interleaving scheme. In the 16QAM modulation scheme, mapping bits b3 and b1 have higher reliability than mapping bits b2 and b0. In the following description, the reliability of b3 and b1 is represented as H (100), and the reliability of b2 and b0 is represented as L (102).

That is, b3 and b1 indicate constellation points (0000, 0001, 0100, 0101) in one quadrant, constellation points (1101, 1001, 1100, 1000) in two quadrants, and constellation points (1110, 1010, 1111, 1011) in three quadrants. In quadrant 4, one quadrant of constellation points (0010, 0110, 0011, 0111) is determined (110), and b2 and b0 determine one of the four constellations in that quadrant (112). .

Since the I / Q distance by b3 and b1 is larger than the I / Q distance by b2 and b0, signal detection is easy and b3 and b1 are more reliable than b2 and b0. On the other hand, since the I / Q distance by b2 and b0 is smaller than the I / Q distance by b3 and b1, it can be said that the reliability is low (that is, signal detection is not easy).

Figure 2 shows a 64QAM constellation according to the prior art.

Referring to FIG. 2, in the 64QAM modulation scheme, 6 bits are mapped to one modulation symbol among 64 modulation symbols. Here, when bits mapped to 64QAM modulation symbols are b5, b4, b3, b2, b1, and b0, interleaved code bits are input to the modulator in the order of b0, b1, b2, b3, b4, and b5. In 64QAM, b5 and b2 have the highest reliability, b4 and b1 have lower reliability than mapping bits b5 and b2, and b3 and b0 have the lowest reliability.

In the following description, for convenience, the reliability of b5 and b2 is represented by H (200), the reliability of b4 and b1 is represented by M (202), and the reliability of b3 and b0 is represented by L (204). In other words, b5 and b2 determine 16 modulation symbols of the 64 modulation symbols (210), b4 and b1 determine 4 modulation symbols of the 16 modulation symbols determined by b5 and b2 (212), b3 And b0 determine one of the four modulation symbols determined in b4 and b1 (214).

Here, when considering a higher order modulation scheme such as 16QAM or 64QAM, a significant performance gap may be caused depending on which reliability bits of information bits and parity bits that enter an input of a decoder of a receiver are mapped to modulation bits. For example, when the code bits are 16QAM modulated with a corresponding reliability (eg, H or L) at a transmitter and transmitted to a receiver, when the receiver decodes 4-bit modulated code bits transmitted at the corresponding reliability, the 4 The more uniform the reliability of the encoded bit, such as HLHL or LHLH, the better the system performance. In the case of 64QAM, the higher the reliability of 4-bit coded bits such as HLHL (or LHLH), HLMM, and MMMM, the better the performance.

However, the communication system does not consider the equal reliability of the code bits input from the transmitter to the decoder of the receiver. In other words, the reliability of the code bits input to the decoder of the receiver is HHHH or LLLL for 16QAM, and HHMM, MMHH and LLLL for 64QAM.

Therefore, there is a need for an interleaving apparatus and method for ensuring that input bits of a decoder have uniform reliability in a communication system.

An object of the present invention is to provide an interleaving apparatus and method for mapping code bits to modulation symbols so that input bits of a decoder have uniform reliability in a communication system.

Another object of the present invention is to provide an interleaving apparatus and method for reducing performance degradation when using a high-order modulation method in a communication system based on CTC (Convolutional Turbo Code).

According to a first aspect of the present invention for achieving the above objects, a method for interleaving in a communication system, comprising: interleaving bits in a first subblock to a sixth subblock, respectively; Dividing the bits in the second subblock into predetermined bit units and performing first permutation of the predetermined bits in reverse order, respectively;

And performing bit grouping on the first to sixth subblocks.

According to a second aspect of the present invention for achieving the above objects, an interleaving apparatus in a communication system, comprising: a plurality of subblock interleavers for interleaving bits in first to sixth subblocks, respectively; A first permutator for dividing the bits in the interleaved second subblock into predetermined bit units and firstly permutating the predetermined bits in reverse order, respectively, for the first to sixth subblocks; And a bit grouping device for performing bit grouping.

According to a third aspect of the present invention for achieving the above objects, there is provided a method for deinterleaving in a communication system, the method comprising: receiving bits in bit grouped first to sixth subblocks; Dividing the bits in the two subblocks into predetermined bit units and performing first permutation of the predetermined bits in reverse order, respectively, and deinterleaving the bits in the first to sixth subblocks, respectively. Characterized in that it comprises a process.

According to a fourth aspect of the present invention for achieving the above objects, in a deinterleaving apparatus in a communication system, a first subblock to a sixth to receive bits in bit grouped first to sixth subblocks; A first permutator for dividing the sub-blocks and the bits in the second sub-block into predetermined bit units and firstly permutating the predetermined bits in reverse order; the first to sixth subblocks; And a plurality of subblock interleavers for performing deinterleaving on the bits in the channel.

As described above, by performing interleaving so that the input bits of the decoder have uniform reliability in the communication system, system performance can be improved.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, detailed descriptions of related well-known functions or configurations will be omitted if it is determined that the detailed description of the present invention may unnecessarily obscure the subject matter of the present invention. The following terms are defined in consideration of the functions of the present invention, and may be changed according to the intentions or customs of the user, the operator, and the like. Therefore, the definition should be made based on the contents throughout the specification.

Hereinafter, the present invention will be described with respect to an apparatus and method for interleaving code bits so that input bits of a decoder have a uniform reliability in a communication system. In particular, it will be described based on a convolutional turbo code (hereinafter referred to as "CTC") in the Institute of Electrical and Electronics Engineers (IEEE) 802.16 communication system.

3 illustrates a transmitter in a communication system according to an embodiment of the present invention.

Referring to FIG. 3, the transmitter includes a channel coding unit 300, an interleaver 310, a puncturing unit 320, and a modulator 330.

The channel coder 300 is a 1/3 CTC channel encoder that generates a parity bit when an information bit is input and outputs the parity bit to the interleaver 310 together with the information bit. Hereinafter, the information bits and the parity bits are collectively referred to as code bits.

The channel coding unit 300 receives two bits of information bits from an upper layer and buffers one bit in the A subblock and the other one bit in the B subblock, and passes through an inner interleaver (not shown). 2 bits of the parity bits generated from the CTC encoder by inputting the 2 bits of the information bits are buffered one by one into the Y1 subblock and the W1 subblock, respectively. The parity bits generated from the CTC encoder with bit 2 bit as input are buffered one by one into the Y2 subblock and the W2 subblock.

Here, four bits input to the CTC decoder of the receiver are composed of 1 bit in the A subblock, 1 bit in the B subblock, 1 bit in the Y1 subblock, and 1 bit in the W1 subblock.

The interleaver 310 performs interleaving so that 4-bit reliability is as uniform as possible when four bits composed of one bit of the A, B, Y1, and W1 subblocks are input to the decoder of the receiver. Operation of the detailed interleaver 310 will be described with reference to FIG. 4.

The puncturing unit 320 punctures the parity bits (bits buffered in the Y1 block, the W1 block, and the Y2 block W2 block) according to the code rate of the code bits interleaved by the interleaver 310 to modulate the modulator. Output to (330).

The modulator 330 maps the interleaved code bits to modulation symbols according to a corresponding modulation scheme. For example, the modulator 330 maps one modulation symbol every four bits in the case of 16QAM modulation and one modulation symbol every six bits in the case of 64QAM modulation.

4 shows a detailed functional block diagram of an interleaver 310 in accordance with an embodiment of the present invention.

Referring to FIG. 4, the interleaver 310 includes an A subblock 400, a B subblock 401, and Y1. Subblock 402, Y2 Subblock 403, W1 subblock 404, W2 Subblock 405, first subblock interleaver 410, second subblock interleaver 411, third subblock interleaver 412, fourth subblock interleaver 413, fifth subblock interleaver 414 , The sixth subblock interleaver 415, the first permutator 420, the second permutator 420, the first bit grouping 430, the second bit grouping 431, and the third bit grouping 432. ), And a fourth bitgrouping 433.

The information bits from the channel coding unit 300 are buffered by 1 bit in the A subblock and the B subblock, respectively, and the parity bits generated by inputting the 2 bits of the information without passing through the internal interleaver are the Y1 subblock and the W1 subblock. A parity bit generated by inputting 2 bits of information interleaved as a result after the 2 bits of information have been passed through the internal interleaver is buffered by 1 bit in the Y2 block and the W2 block, respectively.

In this case, the first subblock interleaver 410 rearranges the bits buffered in the A subblock 400 according to the corresponding interleaving technique in order to change a burst error into a random error. Similarly, the second subblock interleaver 411 rearranges the bits buffered in the B subblock 401 according to the corresponding interleaving technique, and the third subblock interleaver 412 replaces the Y1 subblock 402. Reorder the bits buffered in the corresponding interleaving scheme, and the fourth subblock interleaver 413 rearranges the bits buffered in the Y2 subblock 403 according to the corresponding interleaving scheme. The interleaver 414 rearranges the bits buffered in the W1 subblock 404 according to the interleaving technique, and the sixth subblock interleaver 415 interleaves the bits buffered in the W2 subblock 405. Rearrange according to the technique.

Subsequently, when 4 bits each consisting of 1 bit of the A, B, Y1, and W1 subblocks 400, 401, 402, and 404 are input to the decoder of the receiver, the first bit is to be as uniform as possible. The permutator 420 performs permutation on the bits interleaved by the second subblock interleaver 411 by Equation 1 below. Similarly, the second permutator 421 also performs permutation on the bits interleaved by the fifth subblock interleaver 414 by Equation 1 below.

Here, floor (x) is a function for outputting a maximum integer smaller than x, mod (·) means a modular operation, and N is the size of one subblock.

That is, the bits of the A subblock 400, the B subblock 401, the Y1 subblock 402, and the W1 subblock 404 are interleaved according to the same interleaving scheme, respectively, and mapped to corresponding modulation symbols. Will be mapped with the same reliability (see FIGS. 1 and 2 above). For example, after the bits of the A subblock 400 are interleaved by the first subblock interleaver 410, four bits are mapped to one modulation symbol in case of 16QAM and one bit is used in case of 64QAM. Mapped to modulation symbol. In this case, the reliability of 4 bits mapped to one modulation symbol is HLHL (or LHLH), and the reliability of 6 bits mapped to one modulation symbol is HMLHML (or LMHLMH). Similarly, after the bits of the B subblock 401 are interleaved by the second subblock interleaver 411, four modulation bits are mapped to one modulation symbol for 16QAM and one modulation symbol for 6 bits for 64QAM. Mapped to The reliability of 4 bits mapped to one modulation symbol is HLHL (or LHLH), and the reliability of 6 bits mapped to one modulation symbol is HMLHML (or LMHLMH).

If the first permutator 420 does not perform permutation on the bits of the second subblock interleaver 411, the bits of the A subblock 400 and the B subblock 401. ) Bits are HLHLHLHL... It has a reliability of HMLHMLHMLHML…. You will have a confidence of.

Accordingly, when 1 bit is output from the A subblock 400, the B subblock 401, the Y1 subblock 402, and the W1 subblock 404, respectively, 4 bits are input to the receiver's CTC decoder, In the case of 4-bit reliability is HHHH or LLLL, and in 64QAM, 4-bit reliability is HHHH, MMMM, or LLLL. As a result, the 4-bit reliability input to the CTC decoder of the receiver is not uniform.

In the present invention, the bits of the B subblock 401 interleaved using the first permutator 420 are permuted in order to make the 4-bit reliability input to the CTC decoder of the receiver uniform.

When multiplexing the bits of the Y1 subblock 402 and the Y2 subblock 403 and the multiplexing of the bits of the W1 subblock 404 and the W2 subblock 405, Bit grouping may be performed to have uniform reliability for the bits of the Y1 subblock 402 and the Y2 subblock 403. That is, in case of 16QAM, the bits of the W1 subblock 404 separately interleaved using the second permutator 421 may not be permutated. However, in the case of 64QAM, three reliability (HML) factors need to be considered, and thus, multiplexing on bits of the Y1 subblock 402 and the Y2 subblock 403 and the W1 subblock 404 and the W2 sub There is a limit to having uniform reliability only by multiplexing the bits of block 405. Accordingly, in the case of 64AQM, permutation is performed on bits of the W1 subblock 404 interleaved using the second permutator 421 like the first permutator 420.

An example of the expansion by the first permutator 420 and the second permutator 421 will be described with reference to FIGS. 5 and 6 below.

Thereafter, the bits output from the first subblock interleaver 410 are bit grouped as they are (called the first bit grouping 430), and the bits output from the first permutator 420 are bit grouped as they are. (Called second bitgrouping 431). The bits of the third subblock interleaver 412 and the bits of the fourth subblock interleaver 413 are multiplexed to be bit grouped (called third bit grouping 432), and the second permutator ( The bits of 421 and the sixth subblock interleaver 415 bits are multiplexed and bit grouped (called fourth bit grouping 432).

Here, the fourth bitgrouping 433 has a mapping opposite to that of the third bitgrouping 432 (that is, the third bitgrouping 432 alternately causes the third subblock interleaver 412). Is followed by a bit of the fourth subblock interleaver 413. Wherein the fourth bitgrouping 433 is alternately followed by a bit of the sixth subblock interleaver 415 followed by the permuted Comes the fifth subblock interleaver 414 bits.) It may contribute to the reliability averaging in 16QAM.

 Thereafter, the first bit grouping 430, the second bit grouping 431, the third bit grouping 432, and the fourth bit grouping 432 have one predetermined bit according to a corresponding modulation scheme. It is mapped to the modulation symbol of and transmitted.

5 shows an example of permutation performed by the first permutator 420 and the second permutator 421 according to an embodiment of the present invention.

Referring to FIG. 5, when N bits are respectively output from the second subblock interleaver 411 or the fifth subblock interleaver 414, the first permutator 420 and the second permutation are output. According to Equation 1, the group 421 divides N bits into 6 bit units and permutates them in descending order. For example, 0, 1, 2, 3, 4, 5 bits are separated and replaced with 5, 4, 3, 2, 1, 0.

Therefore, when the A subblock 400 and the B subblock 401, the Y1 subblock 402 and the W1 subblock 404 are output by 1 bit and 4 bits are input to the CTC decoder of the receiver, When 1 bit of reliability H is output in block 400, when 1 bit of reliability L is output in B subblock 401, and 1 bit of reliability H is output in Y1 subblock 402. In the W1 subblock 404, one bit of reliability L is output. Therefore, the 4-bit reliability input to the CTC decoder of the receiver becomes uniform.

In some implementations, the first permutator 420 is performed after the first subblock interleaver 410, or the second permutator 421 is performed after the third subblock interleaver 412. Even if the bit reliability is achieved.

In addition, the bit reliability may be uniformed to some extent only by performing the first permutation. That is, the second permutation may not be performed.

6 illustrates an example of permutation performed by the first permutator 420 and the second permutator 421 according to another embodiment of the present invention.

Referring to FIG. 6, when N bits are respectively output from the second subblock interleaver 411 or the fifth subblock interleaver 414, the first permutator 420 and the second permutator According to Equation 2, 421 divides N bits into 12 bit units and permutates them in descending order. For example, the 0, 1, 2, 3, 4, 5, 6, ... 11th bits are replaced with 11, 10, ..., 3, 2, 1, 0.

Here, floor (x) is a function for outputting a maximum integer smaller than x, mod (·) means a modular operation, and N is the size of one subblock.

5 and 6, if the number of bits in the subblock is not a multiple of 6, the remaining bits are bit grouped without performing the first permutation or the second permutation.

Meanwhile, Equation 1. and Equation 2 may be generalized and arranged as in Equation 3 below.

Here, floor (x) is a function for outputting a maximum integer smaller than x, mod (·) means a modular operation, N is the size of one subblock, i = 0, ..., PW * floor (N / PW), PW is a multiple of any 6 less than or equal to N.

7 illustrates a flowchart for interleaving in a communication system according to an embodiment of the present invention.

Referring to FIG. 7, the interleaver 310 performs the same interleaving on the A, B, Y1, Y2, W1, and W2 subblocks, in order to change the concatenation error into a random error in step 700.

In step 702, the interleaver 310 performs first permutation on the bits of the B subblock according to the reliability of the bits of the A subblock. The first permutation follows Equation 1 or Equation 2.

In step 704, the interleaver 310 performs a second permutation on the bits of the W1 subblock according to the reliability of the bits of the Y1 subblock. The second permutation follows Equation 1 or Equation 2.

By performing a first permutation on the bits of the B subblock and performing a second permutation on the bits of the W1 subblock, four bits of the input bit of the CTC decoder of the receiver have uniform reliability and are decoded. do.

Thereafter, the interleaver 310 performs bit grouping on each subblock in order to make the bits of the subblock uniformly punctured when puncturing the bits in step 706. In other words, the first bit grouping groups the bits output from the interleaved bits of the A subblock, and the second bit grouping outputs the interleaved bits of the B subblock, and the interleaved bits are first permutated and output. Group the bits that become The third bit grouping multiplexes and groups the bits output from the interleaved bits of the Y1 subblock and the bits output from the interleaved bits of the Y2 subblock. The fourth bit grouping multiplexes and groups the bits outputted by interleaving the bits of the W1 subblock and the interleaved bits and the bits outputted by interleaving and outputting the bits of the W2 subblock.

The procedure of the present invention is then terminated.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the scope of the following claims, but also by the equivalents of the claims.

1 is a 16QAM constellation according to the prior art,

2 is a 64QAM constellation according to the prior art,

3 is a block diagram for a transmitter in a communication system according to an embodiment of the present invention;

4 is a detailed functional block diagram of an interleaver according to an embodiment of the present invention;

5 illustrates an example of permutation performed by the first permutator 420 and the second permutator 421 according to an embodiment of the present invention.

6 is a diagram illustrating a permutation performed by the first permutator 420 and the second permutator 421 according to another embodiment of the present invention;

7 is a flowchart for interleaving in a communication system according to an embodiment of the present invention.

Claims (18)

In the method for interleaving in a communication system, Performing interleaving on the bits in the first to sixth subblocks, respectively;  Dividing the bits in the interleaved second subblock into predetermined bit units and respectively performing first permutation of the predetermined bits; And performing bit grouping on the first to sixth subblocks. The method of claim 1, The method of dividing the predetermined bits in the reverse order by dividing the predetermined bit units may be determined by Equation 4 below.

Here, floor (x) is a function for outputting a maximum integer smaller than x, mod (·) means a modular operation, N is the size of one subblock, i = 0, ..., PW * floor (N / PW), PW is any multiple of less than or equal to N. The method of claim 1, And dividing the bits in the interleaved fifth subblock into predetermined bit units and performing second permutation of the predetermined bits in reverse order, respectively. The method of claim 1, The bits in the first subblock and the second subblock are information bits, and the bits in the third subblock and the fifth subblock are generated from the information bits that do not pass through an inner interleaver. Parity bits, wherein the bits in the fourth and sixth subblocks are parity bits generated from the information bits passing through an internal interleaver. The method of claim 1, The process of performing the bit grouping, The bits of the first subblock are interleaved to group the output bits, the bits of the second subblock are interleaved, the interleaved bits are first grouped and output bits are grouped, and the third subblock is grouped. And multiplexing the bits of the interleaved bits and the bits of the fourth subblock by interleaving and outputting the bits of the fourth subblock. And multiplexing and grouping bits in which the bits of the fifth subblock are interleaved and the interleaved bits are second permutated and output, and the bits of the sixth subblock are interleaved and output. An interleaving apparatus in a communication system, A plurality of subblock interleavers for interleaving the bits in the first to sixth subblocks, respectively;  A first permutator for dividing the bits in the interleaved second subblock into predetermined bit units and respectively performing first predetermined permutation of the predetermined bits; And a bit grouping device for performing bit grouping on the first to sixth subblocks. The method of claim 6, The rule of dividing the predetermined bit in reverse order by dividing the predetermined bit unit is determined by Equation 5 below.

Here, floor (x) is a function for outputting a maximum integer smaller than x, mod (·) means a modular operation, N is the size of one subblock, i = 0, ..., PW * floor (N / PW), PW is any multiple of less than or equal to N. The method of claim 6, And a second permutator for dividing the bits in the interleaved fifth subblock into predetermined bit units and respectively performing a second permutation of the predetermined bits in reverse order. The method of claim 6, The bits in the first subblock and the second subblock are information bits, and the bits in the third subblock and the fifth subblock are generated from the information bits that do not pass through an inner interleaver. Parity bits, wherein the bits in the fourth and sixth subblocks are parity bits generated from the information bits passing through an internal interleaver. The method of claim 6, The bit grouping machine The bits of the first subblock are interleaved to group the output bits, the bits of the second subblock are interleaved, the interleaved bits are first grouped and output bits are grouped, and the third subblock is grouped. And multiplexing the bits of the interleaved bits and the bits of the fourth subblock by interleaving the bits of the fourth subblock. And multiplexing and grouping the bits output from the interleaved bits and the interleaved bits are second permutated and output, and the bits output from the interleaved bits of the sixth subblock. In the method for deinterleaving in a communication system, Receiving bits in the bitgrouped first to sixth subblocks; Dividing the bits in the second subblock into predetermined bit units and performing first permutation of the predetermined bits in reverse order, respectively; Performing deinterleaving of the bits in the first to sixth subblocks, respectively. The method of claim 11, The method of dividing the predetermined bits in the reverse order by dividing the predetermined bit units may be determined by Equation 6 below.

Here, floor (x) is a function for outputting a maximum integer smaller than x, mod (·) means a modular operation, N is the size of one subblock, i = 0, ..., PW * floor (N / PW), PW is any multiple of less than or equal to N. The method of claim 11, And dividing the bits in the fifth subblock into predetermined bit units and performing second permutation of the predetermined bits in reverse order, respectively. The method of claim 1, The bits in the first subblock and the second subblock are information bits, and the bits in the third subblock and the fifth subblock are generated from the information bits that do not pass through an inner interleaver. Parity bits, wherein the bits in the fourth and sixth subblocks are parity bits generated from the information bits passing through an internal interleaver. A deinterleaving apparatus in a communication system, First to sixth subblocks that receive bits in the bitgrouped first to sixth subblocks; A first permutator for dividing the bits in the second subblock into predetermined bit units and respectively performing first predetermined permutation of the predetermined bits; And a plurality of subblock interleavers for deinterleaving the bits in the first to sixth subblocks, respectively. The method of claim 15, And a rule for substituting the predetermined bit in reverse order by dividing the predetermined bit unit is determined by the following Equation (7).

Here, floor (x) is a function for outputting a maximum integer smaller than x, mod (·) means a modular operation, N is the size of one subblock, i = 0, ..., PW * floor (N / PW), PW is any multiple of less than or equal to N. The method of claim 15, And a second permutator for dividing the bits in the fifth subblock into predetermined bit units and respectively performing a second permutation of the predetermined bits in reverse order. The method of claim 15, The bits in the first subblock and the second subblock are information bits, and the bits in the third subblock and the fifth subblock are generated from the information bits that do not pass through an inner interleaver. Parity bits, wherein the bits in the fourth and sixth subblocks are parity bits generated from the information bits passing through an internal interleaver.

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