JPH11298338A - Transmitter and transmission method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a circuit scale by holding and outputting conversion data in the current frame that is read in a prescribed bit number unit and finishing storage processing of conversion data for all bits of the next frame within a prescribed time. SOLUTION: A controlling part 50 switches a write signal SW1 to a read signal SR1 and outputs it to an interleaved memory 22A in the case of reading transmission symbol series data D16 written in the memory 22A for one cycle. The memory 22A reads the data D16 for six bits as conversion data D5 at one time based on read address information RA1 that is synchronized with a clock CLK1 and transmits it to a transmitter 8. The part 50 holds the conversion data with a latch circuit 22B based on a clock CLK2 and continues to hold the data D5 for the same six bits until the next clock CLK2 is supplied to the circuit 22B.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Table of Contents] The present invention will be described in the following order.

BACKGROUND OF THE INVENTION Problems to be Solved by the Invention (FIG. 13) Means for Solving the Problems Embodiments of the Invention (FIGS. 1 to 12) Effects of the Invention

[0003]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmitting apparatus and a transmitting method, and is suitably applied to a wireless communication system such as a mobile phone system.

[0004]

2. Description of the Related Art Conventionally, in a radio communication system of this type, an area for providing a communication service is divided into cells of a desired size, and base stations as fixed radio stations are installed in the cells, respectively. A mobile phone as a wireless station is configured to wirelessly communicate with a base station in a cell in which the mobile phone is located, and constructs a so-called cellular system.

At this time, various communication systems have been proposed between the portable telephone and the base station, but CDMA (Code Division Multiple Access) has recently been receiving attention.
There is a code division multiple access system called a system. This CD
The MA system assigns a unique PN (Pseude random Noise sequence) code composed of a pseudo random number sequence code to each communication line on the transmission side, and multiplies the PN code by a primary modulation signal of the same carrier frequency. The secondary modulation signal is spread over a band wider than the original frequency band (hereinafter, referred to as spread spectrum), and subjected to the spread spectrum processing.

In a mobile station of such a CDMA cellular system, a convolutional coding process is performed after adding a CRC (Cyclic Redundancy Check) code to voice data to be actually transmitted (hereinafter, the process up to this point). Is stored in an internal memory of an interleave processing circuit (hereinafter referred to as an interleaver) in a predetermined writing order, and is read out in a reading order different from the writing order. , The order of each symbol is randomly rearranged, that is, an interleaving process is performed, and the interleaved transmission symbol sequence is modulated by a predetermined method and then transmitted as an analog transmission signal.

Here, the transmission symbol sequence subjected to the convolutional coding processing has a random (average) error in the transmission path.
And tends to occur in bursts (locally). When such a burst error occurs,
If the error in that part exceeds the error correction capability, an error that cannot be corrected remains. In order to prevent this from occurring, an interleave process is performed on the transmission symbol sequence so that errors occurring on the transmission path can be dispersed so that an error correction process can be efficiently performed on the reception side. I have.

[0008]

When the above-described interleaving process is performed, as shown in FIG.
First, the transmission symbol sequence of the frame “0” encoded first is stored in the memory 4 of the interleaver 3 via the switch 2 in a predetermined writing order, and sequentially read out in a reading order different from the stored order. Interleave processing is performed, and the read data is transmitted to the transmitter 6
After the modulation, the signal is transmitted via the antenna 7 as an analog transmission signal. At this time, the controller 1 stores the transmission symbol sequence of the next frame “1” in the memory 5 by switching the output destination of the switch 2 while reading data from the memory 4.

When reading of all data from the memory 4 is completed, the controller 1 starts reading data from the memory 5 in a reading order different from that in which the data was stored, thereby performing an interleaving process and switching the switch 2. , The transmission symbol sequence of the next frame “2” is stored in the memory 4.

[0010] However, the controller 1
When the interleaving process is executed while alternately using the memories 5, a plurality of memories 4 and 5 must be provided without fail, which increases the capacity of the memory used as a whole and increases the circuit scale. There was a problem.

On the other hand, when the interleave process is executed by using only the memory 4 provided in the interleaver 3 alone, the controller 1 first reads the frame “ The data "0" is transmitted to the transmitter 6 one bit at a time. Then, the controller 1 reads the last 1-bit data in the frame “0” from the memory 4 and outputs the data to the transmitter 6, and then continuously reads the first 1-bit data in the next frame “1” from the memory 4 without interruption. The data is read out and output to the transmitter 6.

However, the controller 1 reads the last one-bit data in the frame "0" from the memory 4 and outputs it to the transmitter 6, and then stores the first one-bit data in the next frame "1" in the memory 4. In a short time until the data is read out, the transmission symbol sequence generated by adding the CRC code to the audio data corresponding to the next frame “1” and performing the convolutional encoding process is all stored in the memory 4 of the interleaver 3. In some cases, the encoding process to be stored could not keep up.

Therefore, in order to make the encoding process in a short time as described above, a higher-speed clock must be used, which results in an increase in power consumption or in a short time. A separate memory for the encoding process must be provided separately, resulting in a problem that the circuit scale becomes large.

The present invention has been made in view of the above points, and has as its object to propose a transmission apparatus and a transmission method capable of reducing the memory capacity required for interleaving processing.

[0015]

According to the present invention, in order to solve this problem, the order of each symbol of a transmission symbol sequence generated by encoding original data is randomly rearranged for each frame, and the rearrangement is performed. When transmitting a transmission signal generated by subjecting the converted data to a predetermined modulation process, a transmission symbol sequence is stored for each frame in a predetermined writing order, and a predetermined bit is stored in a reading order different from the writing order. The conversion data of a predetermined number of bits, which is read out for each number and sequentially read in the reading order, is temporarily held by the holding means, and the conversion data of the last predetermined number of bits in the current frame is held by the holding means. Is held, the transmission symbol sequence in the next frame is stored in the storage means.

The conversion data of the current frame read from the storage means is held and output in units of a predetermined number of bits by the holding means, so that the converted data for the last predetermined number of bits of the current frame is output. By the time the converted data for the first predetermined number of bits in the next frame is output, the storage processing of all the converted data for all bits in the next frame can be completed, and as a result a plurality of storage means are provided. There is no need.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

In FIG. 1, reference numeral 1 denotes a communication terminal as a transmitting apparatus as a whole according to the present invention. During a call, a voice signal S1 picked up by a microphone 2 is interface-converted via a handset 3 for voice communication. It is sent to codec 4. The audio codec 4 increases the transmission processing speed of the audio signal S1 to 9600 based on the detection result obtained by detecting the line quality, the quality of the audio signal S1, and the amount of information thereof.
One of four types, [bps], 4800 [bps], 2400 [bps], and 1200 [bps] is selected.

The audio codec 4 digitizes the audio signal S1 having the selected transmission processing speed to generate audio data D1, and sends it to the channel encoder 6 of the channel codec 5. In addition, the voice codec 4 generates speed information data D2 representing the selected transmission processing speed every time the transmission processing speed is selected, and sends it to the controller 7.

The controller 7 generates control data D 3 corresponding to the transmission processing speed indicated by the speed information data D 2 and sends it to the channel encoder 6. The channel encoder 6 executes transmission processing according to the transmission processing speed based on the control data D3, and adds communication control data D4 supplied from an internal memory (not shown) of the controller 7 to the audio data D1. After the convolutional encoding, the conversion data D5 obtained by converting the data into a predetermined data format is transmitted to the transmitter 8.

The transmitter 8 is supplied with a frequency control signal S2 for controlling the transmission frequency from the synthesizer 9, modulates the converted data D5 in a predetermined format based on the frequency control signal S2, and obtains the transmission data D6 obtained as a result. Is transmitted to a base station (not shown) at a predetermined wireless transmission rate via the duplexer 10 and the antenna 11.

Also at the base station, transmission processing is performed at a transmission processing speed of 9600 [bps], 4800 [bps], 2400 [bps], or 1200 [bps], similarly to the transmission data D6 described above. The communication terminal 1 receives data transmitted from the base station via the antenna 11 and supplies the received data as reception data D7 to the receiver 12 via the duplexer 10.

The receiver 12 is supplied with a frequency control signal S3 for controlling a reception frequency from the synthesizer 9,
The demodulated data D8 is generated by demodulating the received data D7 in a predetermined format based on the frequency control signal S3, and is transmitted to the channel decoder 13.

The channel decoder 13 is connected to the controller 7
9600 [bps], 4800 [bps], 2400 which are the same as the transmission processing speed when used in the base station on the transmission side.
The reception processing of the demodulated data D8 is executed at a reception processing speed of either [bps] or 1200 [bps]. In this case, the channel decoder 13 converts the demodulated data D8 into a predetermined format corresponding to the reception processing speed, performs error correction by the Viterbi decoding method, and then decodes the data to generate decoded data.

In addition, the channel decoder 13 sends to the voice codec 4 voice data D10 corresponding to the voice of the other party in the decoded data obtained by decoding the demodulated data D8. The communication control data D11 of the data is sent to the controller 7.

The voice codec 4 converts the voice data D10 into an analog voice signal S5 based on the control signal S4 inputted from the controller 7, converts the data into an analog voice signal S5 via the handset 3, and then sends it to the speaker 14. I do. Thus, in the communication terminal 1, a voice call with the other party can be realized by generating a voice from the speaker 14.

The controller 7 generates communication control data D4 to be added to the voice data D1 and decodes the communication control data D11 input from the channel decoder 13 to set, cancel, and maintain a call. Key/
The I / O (In / Out) control of the outing chair play 15 is executed.
In addition, the controller 7 controls a synthesizer 9 that generates a transmission frequency and a reception frequency.

Here, as shown in FIGS. 2 and 3 in which the same reference numerals are given to the parts corresponding to those in FIG. 1, first, at the time of data transmission, the channel encoder 6 outputs the audio codecs 4 to 96.
The audio data D1 having a transmission processing speed of any of 00 [bps], 4800 [bps], 2400 [bps] or 1200 [bps] is CRC.
It is input to the generator 20.

When voice data D1 having a transmission processing speed of 9600 [bps] is input, the CRC generator 20 adds a total of 172 bits by adding communication control data D4 supplied from the controller 7 to the voice data D1. And the following formula based on the generated raw data:

[0030]

(Equation 1)

Using the generator polynomial G1 (X)
A 184-bit data is generated by generating a 12-bit CRC code and adding this to the original data. Thereafter, the CRC generator 20 adds 8-bit tail bits to the 184-bit data to generate 192-bit code-added data D15, and sends this to the convolutional encoder 21.

The CRC generator 20 is 4800 [bp]
s], the communication control data D4 supplied from the controller 7 is added to the audio data D1 to add a total of 80 audio data D1.
In addition to generating the original data of the bit, based on the generated original data,

[0033]

(Equation 2)

An 8-bit CRC code is generated using the generator polynomial G2 (X) expressed by the following formula, and is added to the original data to generate 88-bit data. After this C
The RC generator 20 adds an 8-bit tail bit to the 88-bit data to generate a 96-bit code-added data D.
15 is sent to the convolutional encoder 21.

Further, the CRC generator 20 has a capacity of 2400 [b
ps], the communication control data D4 supplied from the controller 7 is added to the audio data D1 to add a total of 40 audio data D1.
The original bit data is generated, and an 8-bit tail bit of "0" is added to the generated original data.
The 48-bit code additional data D15 is generated and sent to the convolutional encoder 21.

Further, the CRC generator 20 has a capacity of 1200 b
ps], the communication control data D4 supplied from the controller 7 is added to the audio data D1 so that a total of 16
The original bit data is generated, and an 8-bit tail bit of "0" is added to the generated original data.
The 24-bit code additional data D15 is generated and sent to the convolutional encoder 21.

The convolutional encoder 21 converts the code addition data D15 generated by the CRC generator 20 for each transmission processing speed into a preset constraint length k (set to "9" in this embodiment) and The convolutional coding is performed based on the coding rate R (set to “１ ／” in this embodiment), and the resulting transmission symbol sequence data D16 is sent to the interleaver 22.

By the way, the convolutional encoder 21 operates at 9600 [bps].
192 bits of code-added data D consisting of a transmission processing speed of
When 15 is input, 576-bit transmission symbol sequence data D16 is generated based on the 192-bit code addition data D15, and 96-bit code addition data D15 having a transmission processing speed of 4800 [bps]. Is input, the 288-bit transmission symbol sequence data D16 is generated based on the 96-bit code addition data D15.

The convolutional encoder 21 has a 48-bit code addition data D15 having a transmission processing speed of 2400 [bps].
Is input, 144-bit transmission symbol sequence data D16 is generated based on the 48-bit code addition data D15, and 24-bit code addition data D15 having a transmission processing speed of 1200 [bps] is generated. When it is input, it generates 72-bit transmission symbol sequence data D16 based on the 24-bit code addition data D15.

In the interleaver 22, the number of data repetitions is set in advance for each transmission processing speed.
When the transmission symbol sequence data D16 of 576 bits generated according to the transmission processing speed of [bps] is input,
The interleave process is performed by sequentially writing data to an internally provided interleave memory (not shown) in accordance with predetermined write address information as it is without repeating data, and then reading the data sequentially according to predetermined read address information. The conversion data D5 of 576 bits obtained as a result is transmitted to the transmitter 8 at a line transmission speed of 28,800 [bps] (576 bits / 20 [msec]).

When 288 bits of transmission symbol sequence data D16 generated according to a transmission processing speed of 4800 [bps] are input, the interleaver 22 repeats the data one bit at a time and uses it once. (Ie, the same data continues two by two) to generate 576-bit repetition data, and to sequentially write the 576-bit repetition data into an internal interleave memory according to predetermined write address information, The interleaving process is performed by sequentially reading out according to the read address information, and the resulting 576-bit converted data D5 is transmitted to the transmitter 8 at a line transmission speed of 28,800 [bps] (576 bits / 20 [msec]). I do.

When the transmission symbol sequence data D16 of 144 bits generated according to the transmission processing speed of 2400 [bps] is input, the interleaver 22 sequentially uses the data three times, one bit at a time. (I.e., the same data continues four by four) to generate 576-bit repetition data, and sequentially write the 576-bit repetition data into an internal interleave memory according to predetermined write address information. The interleaving process is performed by sequentially reading out according to the read address information, and the resulting 576-bit converted data D5 is transmitted to the transmitter 8 at a line transmission speed of 28,800 [bps] (576 bits / 20 [msec]). I do.

Further, the interleaver 22 operates at 1200 [bps].
When the 72-bit transmission symbol sequence data D16 generated according to the transmission processing speed is input, the data must be sequentially repeated 7 times, one bit at a time (ie, the same data continues eight by two). 576-bit repetition data is generated, and the 576-bit repetition data is sequentially written into an internal interleave memory according to predetermined write address information, and then sequentially read according to predetermined read address information, thereby performing an interleave process. And the resulting 576-bit converted data D5 is transmitted to the transmitter 8 at a line transmission speed of 28,800 [bps] (576 bits / 20 [msec]).

As shown in FIG. 4, the interleaver 22 generates three types of data (288) according to the transmission processing speeds of 4800 [bps], 2400 [bps] and 1200 [bps].
By performing the above-described data repetition processing and interleave processing on transmission symbol sequence data D16 composed of 144 bits and 72 bits, 96 bits are obtained.
The transmission symbol sequence data D16 generated according to the transmission processing speed of 00 [bps] generates converted data D5 having the same bit length (576 bits) as that obtained when the interleaving process is performed, and converts the converted data to a 28800 [bps] line. The data is transmitted to the transmitter 8 at the transmission speed.

On the other hand, in FIG. 2 and FIG. 5 in which the same reference numerals are given to the parts corresponding to FIG. 1, at the time of data reception, the channel decoder 13 converts the demodulated data D8 supplied from the receiver 12 into a deinterleaver 25. To enter.

The deinterleaver 25 sequentially stores the demodulated data D8 in an internal deinterleave memory (not shown) by a length of 576 bits (one cycle at the time of transmission).
The demodulated data D8 from the deinterleave memory is 576
Read out for each bit length. Here, when reading out the demodulated data D8 from the deinterleave memory, 9600 [bps] or 4800 [b] according to the transmission processing speed used on the transmission side.
ps], 2400 [bps], or 1200 [bps].

In addition, the deinterleaver 25
The order of the 76-bit demodulated data D8 is rearranged in a procedure completely opposite to that when rearranged on the transmission side according to the respective reception processing speeds, thereby returning the original arrangement order (hereinafter referred to as deinterleaving). ), Resulting in
The soft decision data D28 having a length of 576 bits (hereinafter referred to as first soft decision data) D28 is sent to the data addition processor 26.

The data addition processor 26 generates soft decision data (hereinafter, referred to as soft decision data) consisting of a predetermined number of bits before one bit of data is repeated a predetermined number of times for each reception processing speed based on the first soft decision data D28. D29) (referred to as second soft decision data). Accordingly, when the first soft decision data D28 is input at the reception processing speed of 9600 [bps], the data addition processor 26 performs the first processing.
Is not subjected to data processing because repetition processing has not been performed, and the second soft decision data D
29 and transmitted to the Viterbi decoder 27.

The data addition processor 26 has 4800 [bps].
When the first soft decision data D28 is input at the reception processing speed of, the second soft decision data D29 of 288 bits is generated by performing data addition processing based on the first soft decision data D28. To the Viterbi decoder 27. When the first soft decision data D28 is input at a reception processing speed of 2400 [bps], the data addition processor 26
By performing data addition processing based on the first soft decision data D28, the second soft decision data D2 of 144 bits is obtained.
9 and sends it to the Viterbi decoder 27.

Further, the data addition processor 26 outputs 1200 [bp]
s], the second soft decision data D29 of 72 bits is generated by performing data addition processing based on the first soft decision data D28. Are sent to the Viterbi decoder 27.

The Viterbi decoder 27 applies a Viterbi algorithm to the second soft-decision data D29 input at each reception processing speed, and uses a Viterbi algorithm to set the constraint length k to "9" and the coding rate R to "9". By performing the maximum likelihood decoding process set to "1/3", decoded data D30 (tail bits of 8 bits are removed) is generated and sent to the error detector 29.

Here, when the second soft decision data D29 is input at a reception processing speed of 9600 [bps], the Viterbi decoder 27 generates 184-bit decoded data D30 and outputs 4800 bits.
When the second soft decision data D29 is input at the reception processing speed of [bps], 88-bit decoded data D30 is generated, and the second soft decision data D is received at the reception processing speed of 2400 [bps].
When 29 is input, 40-bit decoded data D30
Is generated, and when the second soft decision data D29 is input at a reception processing speed of 1200 [bps], 16-bit decoded data D30 is generated.

When the decoded data D30 corresponding to the reception processing speed of 9600 [bps] is input, the error detector 29 converts the decoded data D30 into the generator polynomial G1 shown in the equation (1).
After detecting an error using (X), the 12-bit data of the portion to which the CRC code is estimated to be added is removed from the decoded data D30, and the resulting 172-bit audio data D10 is output to the audio codec 4. Send out.

When the decoded data D30 corresponding to the reception processing speed of 4800 [bps] is input, the error detector 29 converts the decoded data D30 using the generator polynomial G2 (X) shown in the equation (2). After detecting an error, the decoded data D30
Of the portion estimated to have a CRC code added from
The bit data is removed, and the resulting 80-bit audio data D10 is sent to the audio codec 4.

When the decoded data D30 corresponding to the reception processing speed of 2400 [bps] is input, the error detector 29 does not process the data because the CRC data is not added to the decoded data D30. The bit decoded data D30 is transmitted to the audio codec 4 as audio data D10. Further, when the decoded data D30 corresponding to the reception processing speed of 1200 [bps] is input, the error detector 29 does not perform the data processing because the decoded data D30 is not added with the CRC code. The data is transmitted to the audio codec 4 as data D10.

Next, the channel encoder 6 on the transmitting side
The interleave processing method in the interleaver 22 will be described. As shown in FIG. 6, the control unit 50 of the controller 7 controls the operation speed of the interleave memory 22A and the latch circuit 22B, and the clock CL of 9.8 [MHz] is supplied to the interleave memory 22A.
A write and read process is executed for each K1 and a clock CL of 4.8 [KHz] is applied to the latch circuit 22B.
The conversion data D5 latched for each K2 is output.

First, when writing the transmission symbol sequence data D16 supplied from the convolutional encoder 21 to the interleave memory 22A of the interleaver 22, the control unit 50 of the controller 7 firstly converts the request signal RQ1 sent from the transmitter 8 Based on the input timing, a write signal SW1 and a write enable signal WE1 indicating a writable state are output to the interleave memory 22A, and the write address information WA1 generated by the write address generator 52 is output via the selector 51. Output to the interleave memory 22A.

The control unit 50 transmits the transmission symbol series data D from the convolutional encoder 21 based on the clock CLK1.
At the same time, the readout of the read symbol 16 is started, and the transmission symbol sequence data D16 for one cycle (576 bits / 20 [msec]) is transmitted one bit at a time based on the write address information WA1 synchronized with the clock CLK1 of 9.8 [MHz].
The data is sequentially written at a predetermined position of 2A.

Next, when reading out the transmission symbol sequence data D16 for one cycle written in the interleave memory 22A, the control unit 50 first determines the timing based on the input timing of the request signal RQ1 sent from the transmitter 8. The write signal SW1 is switched to the read signal SR1 and output to the interleave memory 22A, and a read enable signal RE1 indicating a readable state is output to the interleave memory 22A. The information RA1 is output to the interleave memory 22A via the selector 51.

The interleave memory 22A stores read address information RA1 synchronized with the clock CLK1 of 9.8 [MHz].
The transmission symbol sequence data D16 for 6 bits based on
Is read out at once as conversion data D5 and sent to the transmitter 8. The control unit 50 holds the conversion data D5 for 6 bits read from the interleave memory 22A in the latch circuit 22B based on the clock CLK2 of 4.8 [KHz], and keeps the same until the next clock CLK2 is supplied to the latch circuit 22B. The conversion data D5 for 6 bits is continuously held.

As described above, the interleaver 22 includes the control unit 5
0, the processing speed (9.8 [MHz]) at the time of writing and reading of the interleave memory 22A is set high, and the processing speed (4.8 [4.8 [MHz]) at which the latch circuit 22B outputs the conversion data D5 for 6 bits. KHz]) is set to be slow, and the conversion data D5 for 6 bits output at a time from the latch circuit 22B is sequentially output to the transmitter 8.

The transmitter 8 calculates the following equation based on the 6-bit conversion data D5 supplied from the latch circuit 22B.

[0063]

(Equation 3)

The symbol index SI represented by

The transmitter 8 converts the conversion data D5 for 6 bits into a Walsh code consisting of a 64-bit orthogonal code corresponding to the symbol index SI based on the conversion table shown in FIG. Is performed for a total of 96 times, each of 6 bits, for 576 bits of encoded data D16 for one cycle (20 [msec]) stored in the interleave memory 22A, and then modulated by a predetermined method to perform a predetermined wireless transmission. Transmit in bursts (continuously) at speed. By the way, the transmitter 8 transmits the supplied conversion data D for 6 bits.
5 every time the conversion processing is performed based on the request signal RQ
1 to the control unit 50.

Next, an interleave processing method using the interleave memory 22A of the interleaver 22 will be specifically described for each transmission processing speed. As shown in FIG. 8, the convolutional encoder 2 has a transmission processing speed of 9600 [bps].
1 is the write symbol information WA1 supplied from the controller 7.
According to, "1", "2",
Data of each bit is sequentially written in the order of "3",... "32", and then "33", "34",.
And finally in the 18th column on the far right end ... "576"
Are written in order.

Next, the transmission symbol sequence data D16 written in this way is read by the controller 7 at the time of reading.
From the leftmost numbers "1" to "33", "6" in the top row of the first row in accordance with the read address information RA1 supplied from
5 "," 97 "," 129 ", and" 169 "in that order.
All data is read while B holds the conversion data D5.

As shown in FIG. 9, the transmission symbol sequence data D16 output from the convolutional encoder 21 at a transmission processing speed of 4800 [bps] is updated in accordance with the write address information WA1 supplied from the controller 7. From the first column on the left end, data of each bit is sequentially written in the order of "1", "2", "3",... "16", and then "17" and "18" on the second column. ,..., And finally, the 18th column at the rightmost end,. In this case, the data amount of the transmission symbol sequence data D16 at the time of writing is reduced to half that of 9600 [bps], so that the capacity of the interleave memory 22A is reduced accordingly.

Next, the transmission symbol series data D16 written in this way is read by the controller 7 at the time of reading.
From the leftmost numbers "1" to "17", "3"
3 ”,“ 49 ”,“ 65 ”, and“ 81 ”in this order, and after the data of the first row is read again,
Sixth row: Read out twice for all rows up to “288”.

Further, as shown in FIG. 10, transmission symbol sequence data D16 output from convolutional encoder 21 at a transmission processing speed of 2400 [bps] is updated in accordance with write address information WA1 supplied from controller 7. Leftmost 1
"1", "2", "3", ... "8" in the vertical direction from the column
The data of each bit is sequentially written in the order of
.., "..." in the 18th column at the rightmost end,... "144". In this case, the data amount of the transmission symbol sequence data D16 at the time of writing is 1/4 of 9600 [bps], so that the capacity of the interleave memory 22A is further reduced accordingly.

Next, the transmission symbol series data D16 written in this way is read by the controller 7 at the time of reading.
In accordance with the read address information RA1 supplied from the first row, the leftmost numbers “1” to “9”, “1”
7 ”,“ 25 ”,“ 33 ”, and“ 41 ”are read in order, and the data in the first row is read again three times, and finally all data up to the eighth row... Is read four times in the row.

Further, as shown in FIG. 11, transmission symbol sequence data D16 output from convolutional encoder 21 at a transmission processing speed of 1200 [bps] is updated in accordance with write address information WA1 supplied from controller 7. Leftmost 1
The data of each bit is sequentially written in the vertical direction from the column in the order of “1”, “2”,..., “4”, and then moves to “5”, “6”,. And finally the rightmost 18
Columns are written in order up to “72”. In this case, the data amount of the transmission symbol sequence data D16 at the time of writing is 1/8 of 9600 [bps],
The capacity of the interleave memory 22A is further reduced accordingly.

Next, the transmission symbol series data D16 written in this way is read by the controller 7 at the time of reading.
From the leftmost numbers "1" to "5", "9",
"13", "17", and "21" are read in this order, and the data in the first row is read again seven times, and finally in all rows up to the fourth row ... "72". Read eight times.

Next, the timing of the writing process and the reading process of the transmission symbol sequence data D16 in the interleave memory 22A of the interleaver 22 will be described with reference to FIG. The interleave memory 22A stores conversion data D5 for the last 6 bits in frame "0" (read addresses: 570, 571, 572, 573, 574, 575).
Is read out based on the clock CLK1 of 9.8 [MHz] and output to the latch circuit 22B.

Once the latch circuit 22B holds the last six bits of conversion data D5 in the frame "0", the clock CL of 4.8 [KHz] supplied from the control unit 50.
The conversion data D5 for the last 6 bits based on K2
Is output to the transmitter 8 at the timing of the time t1, and the same conversion data D5 is continuously output until the timing of the time t2 when the next clock CLK2 is supplied.

In this case, since the interleave memory 22A has read all the transmission symbol sequence data D16 for one cycle in the frame "0", the interleave memory 22A stores the 576-bit transmission symbol sequence data D16 in the next frame "1". It can be stored. At this time, the control unit 50 immediately changes the read signal SR1 to the write signal SW1.
And a write enable signal WE1 indicating a readable state is output to the interleave memory 22A, and at the same time, the write address information WA1 of the transmission processing speed corresponding to the next frame "1" is clocked at 9.8 [MHz].
The data is output to the interleave memory 22A via the selector 51 based on K1.

At this time, the control unit 50 generates the original data by reading the communication control data D4 from the internal memory (not shown) of the controller 7 and adding it to the audio data D1, and generates a CRC code and Alternatively, code addition data D15 is generated by adding a tail bit, and transmission symbol sequence data D16 is generated by performing convolutional coding processing on the code addition data D15, thereby generating one cycle (576 bits / 20). [msec]) is transmitted as write address information WA.
1 at a predetermined position in the interleave memory 22A.
Write one bit at a time at the operating speed of [MHz].

Here, the last 6 in the frame “0”
The processing from the point in time t1 when the converted data D5 for the bit is output from the latch circuit 22B of the interleaver 22 to the transmitter 8 to the point in time t2 when the converted data D5 for the first six bits in the next frame "1" is output is as follows. Since the processing is performed based on the clock CLK2 of 4.8 [KHz], the processing time is 0.208 [msec] (20 [msec] / 96).

In the processing time of 0.208 [msec], when the transmission symbol sequence data D16 for one cycle is written into the interleave memory 22A at the operation speed of 9.8 [MHz], 2038
(9.8 × 10 ⁶ × 0.208 × 10 ^-3 ) The processing for the clock can be executed. Therefore, when the transmission processing speed is 9600 [bps], when writing the transmission symbol sequence data D16 of 576 bits in one cycle to the interleave memory 22A, 5
It requires 76 times of write address information WA1, but 0.20
Since the write address information WA1 can be output 2038 times within the processing time of 8 [msec], the transmission symbol sequence data D of 576 bits per cycle can be output within a sufficient time margin.
All 16 can be written.

As described above, the control unit 50 of the controller 7
Is from when the latch circuit 22B starts outputting the conversion data D5 for the last 6 bits in the frame "0" to when the conversion data D5 for the first 6 bits in the next frame "1" starts to be output. 0.208 [msec] (20 [m
[sec] / 96), it is possible to complete the writing process of the transmission symbol sequence data D16 of one period of 576 bits, so that the converted data D5 in the next frame can be continuously transmitted without causing a time delay. Can be output to

In the above configuration, the control unit 50 of the controller 7 holds the converted data D5 in the frame "0" read out from the interleave memory 22A at the operation speed of 9.8 [MHz] by the latch circuit 22B in units of 6 bits.
The conversion data D5 for the 6 bits is output from the latch circuit 22B at an operation speed of 4.8 [KHz], and the conversion data D5 for the last 6 bits in the frame “0” is output from the latch circuit 22B.
From time t1 output from B, the conversion data D5 for the first 6 bits in the next frame "1" is
By writing the convolutionally encoded transmission symbol sequence data D16 into the interleave memory 22A at an operation speed of 9.8 [MHz] between the time t2 and the output time t2, the latch circuit 22B converts 6 bits. In the processing interval for outputting the data D5, the writing process of the transmission symbol sequence data D16 for one cycle can all be completed.

As a result, the control unit 50 sets the frame "0"
Since the conversion data D5 for 6 bits can be output to the transmitter 8 without interruption at the moment when the frame and the frame "1" are switched, the write processing can be executed without increasing the memory capacity of the interleave memory 22. The scale can be reduced.

The control unit 50 of the controller 7 holds the converted data D5 by 6 bits at a time by the latch circuit 22B and outputs it at an operation speed of 4.8 [KHz]. Compared with the case where the read converted data D5 is held and output one bit at a time, the clock for writing the transmission symbol series data D16 does not need to be speeded up to 9.8 [MHz] or more, thereby increasing power consumption. Can be prevented.

According to the above configuration, the control unit 50 of the controller 7 sets the predetermined write address information W for each frame.
The conversion data D5 read out from the transmission symbol sequence data D16 written in A1 based on the predetermined read address information RA1 is held in the latch circuit 22B in 6-bit units, and the conversion data D5 for 6 bits is stored in 4.8 [KHz]. At the operation speed, the conversion data D5 for the first 6 bits in the next frame "1" is converted from the latch circuit 22 at time t1 when the conversion data D5 for the last 6 bits in the frame "0" is output from the latch circuit 22B. 22B, the transmission symbol sequence data D16 is
By writing the data into the interleave memory 22A at the operation speed of 9.8 [MHz], the latch circuit 22B outputs one cycle of the next frame "1" in the processing interval in which the conversion data D5 for 6 bits is sequentially output. All of the transmission symbol sequence data D16 can be written into the interleave memory 22A, and thus the plurality of interleave memories 22A can be written.
A need not be provided, and the circuit scale can be reduced.

In the above embodiment, the conversion data D for 6 bits is transmitted by the transmitter 8 as the modulating means.
5 is converted to a 64-bit Walsh code. However, the present invention is not limited to this. Depending on the modulation method of the transmitter 8, the conversion data D5 output to the transmitter 8 may be used. May be changed to various other numbers of bits other than 6 bits. For example, when the number of bits of the conversion data D5 is increased to 8 bits by another modulation method, the conversion data D5 for the 8 bits is used.
Is longer than 0.208 [msec], the transmission symbol sequence data D16 for one cycle can be written with more time, and the frequency of the clock CLK to be used can be reduced. ,
Power consumption can be reduced accordingly.

In the above-described embodiment, the control unit 50 as the control means operates the latch circuit 22B as the holding means with the clock CLK2 of 4.8 [KHz], and the interleave memory 22A as the storage means. 9.
The case where the operation is performed by the clock CLK1 of 8 [MHz] has been described. However, the present invention is not limited to this, and after outputting the conversion data D5 for the last 6 bits in the previous frame, the next operation is performed. If the operating speed of the clock CLK1 is made faster than the clock CLK2 so that the transmission symbol series data D16 for one cycle can be written and processed before the conversion data D5 for the first 6 bits in the frame is output, various other operations are performed. Speed clocks CLK1 and CLK2
May be used.

Further, in the above-described embodiment, when the transmission processing speed is 4800 [bps], 2400 [bps] and 1200 [bps], the encoded data D16 is written once into the interleave memory 22A of the interleaver 22, and 2 when reading
By reading repeatedly 4 times, 4 times, and 8 times, 9600 [b
ps], the conversion data D of 576 bits in length
5, the present invention is not limited to this, and the transmission processing speed is 4800 [bps], 2400 [bp]
s] and 1200 [bps], the data may be repeatedly written twice, four times, and eight times, and all data may be sequentially read only once at the time of reading.

[0088]

As described above, according to the present invention, the conversion data in the current frame read from the storage means is held and output in the unit of a predetermined number of bits by the holding means. After outputting the converted data for the predetermined number of bits and before outputting the converted data for the first predetermined number of bits in the next frame, the storage processing of the converted data for all the bits in the next frame is completed. As a result, it is not necessary to provide a plurality of storage means, and the circuit scale can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration of a communication terminal according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a circuit configuration of a channel code.

FIG. 3 is a block diagram for explaining a flow of a transmission process in a channel code;

FIG. 4 is a schematic diagram for explaining conditions of transmission processing in a channel codec.

FIG. 5 is a block diagram for explaining a flow of a receiving process in a channel code;

FIG. 6 is a block diagram showing a configuration of a controller and an interleaver.

FIG. 7 is a schematic diagram illustrating a conversion table.

FIG. 8 is a schematic diagram for explaining memory write and read processing at 9600 bps.

FIG. 9 is a schematic diagram used to explain memory write and read processing at 4800 bps.

FIG. 10 is a schematic diagram used to explain memory write and read processing at 2400 bps.

FIG. 11 is a schematic diagram used to explain memory write and read processing at 1200 bps.

FIG. 12 is a schematic diagram used for describing a processing sequence in a control unit.

FIG. 13 is a schematic diagram for explaining a conventional interleave processing method using a plurality of memories.

[Explanation of symbols]

1 ... communication terminal, 5 ... channel code, 6 ... channel encoder, 7 ... controller, 8 ... transmitter, 20 ... CRC generator, 21 ... convolutional encoder, 22 ... interleaver, 22A ... ... interleave memory, 22B ... latch circuit, 50 ... control unit.

Claims (4)

[Claims] 1. The method according to claim 1, wherein the order of each symbol of the transmission symbol sequence generated by encoding the original data is randomly rearranged for each frame, and a predetermined modulation process is performed on the rearranged converted data. A transmitting device for transmitting the generated transmission signal, a storage unit for storing the transmission symbol sequence in a predetermined writing order for each of the frames, and reading out the reading symbol sequence for each predetermined number of bits in a reading order different from the writing order; Holding means for temporarily holding the conversion data of the predetermined number of bits sequentially read out at the following; and modulation means for performing the predetermined modulation processing based on the conversion data of the predetermined number of bits output from the holding means; While holding the converted data of the last predetermined number of bits in the current frame by the holding means, A control unit for storing the transmission symbol sequence in the storage unit. 2. The storage means writes, for each frame, the transmission symbol sequence generated based on the original data when the original data has a speed other than the fastest transmission rate among a plurality of types. 2. The transmitting apparatus according to claim 1, wherein reading is repeatedly performed a plurality of times for each predetermined number of bits in a reading order. 3. The method according to claim 1, wherein the order of each symbol of the transmission symbol sequence generated by encoding the original data is randomly rearranged for each frame, and a predetermined modulation process is performed on the rearranged converted data. In the transmission method for transmitting the generated transmission signal, the transmission symbol sequence is stored in a predetermined writing order for each frame, read out for a predetermined number of bits in a reading order different from the writing order, and sequentially read in the reading order. The conversion data of the given predetermined number of bits is temporarily held by the holding unit, and while the conversion data of the last predetermined number of bits in the current frame is held by the holding unit, the next frame is stored. The transmission method according to claim 1, wherein the transmission symbol sequence is stored in the storage means. 4. When the original data has a transmission rate other than the fastest among a plurality of types, the transmission symbol sequence generated based on the original data is written into the storage means for each frame, and the read is performed. 4. The method according to claim 3, wherein the data is read out a plurality of times in a predetermined number of bits.
Transmission method described in.