JP2013098507A - High frequency electronic component - Google Patents

High frequency electronic component Download PDF

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Publication number
JP2013098507A
JP2013098507A JP2011243027A JP2011243027A JP2013098507A JP 2013098507 A JP2013098507 A JP 2013098507A JP 2011243027 A JP2011243027 A JP 2011243027A JP 2011243027 A JP2011243027 A JP 2011243027A JP 2013098507 A JP2013098507 A JP 2013098507A
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electrode
substrate
terminal
electronic component
frequency electronic
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JP5862210B2 (en
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Koji Miyamoto
幸治 宮本
Hiroki Watanabe
寛樹 渡辺
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a high frequency electronic component in which release of an electrode terminal can be suppressed and deterioration of isolation characteristics can be suppressed.SOLUTION: A high frequency electronic component comprises a substrate 200, a surface acoustic wave element 100 which is mounted on the substrate 200, an electrode layer 330 including a plurality of electrode terminals which are formed while being separated from each other on a rear side of the substrate 200 and of which at least one is connected electrically with the surface acoustic wave element 100, and a protecting layer 400 which is formed on a terminal face. The protecting layer 400 is formed in an edge area on the rear side of the substrate 200 so as to expose a central area on the rear side of the substrate 200 and to cover an edge of the plurality of electrode terminals in the electrode layer 330.

Description

本発明は、高周波電子部品に関し、特に、基板の端子面上に保護層を設けた高周波電子部品に関する。   The present invention relates to a high frequency electronic component, and more particularly to a high frequency electronic component in which a protective layer is provided on a terminal surface of a substrate.

特開２００６−１００４６０号公報（特許文献１）には、プリント基板（１）のランド部（２）の周辺を覆うようにソルダーレジスト層（３）を形成することが示されている。   Japanese Patent Laying-Open No. 2006-100460 (Patent Document 1) shows that the solder resist layer (3) is formed so as to cover the periphery of the land portion (2) of the printed circuit board (1).

特開２００６−１００４６０号公報JP 2006-100460 A

特許文献１に記載のソルダーレジスト層（３）は、ランド部（２）を保護する保護層として機能する。   The solder resist layer (3) described in Patent Document 1 functions as a protective layer that protects the land portion (2).

しかしながら、所定の配置および所定の形状の規格を満足する電極端子を有する高周波電子部品において、特許文献１に記載のソルダーレジスト層（３）と同様の構成を保護層として用いようとした場合、保護層で電極端子を覆うために、電極端子を上記所定の形状よりも大きく形成する必要がある。これにより、電極端子間の隙間が小さくなって、電極端子間の橋絡容量が増加し、隣接する電極端子のアイソレーション特性が悪化するという問題があった。   However, in a high-frequency electronic component having an electrode terminal satisfying a standard of a predetermined arrangement and a predetermined shape, when a configuration similar to the solder resist layer (3) described in Patent Document 1 is used as a protective layer, In order to cover the electrode terminal with the layer, it is necessary to form the electrode terminal larger than the predetermined shape. As a result, there is a problem that the gap between the electrode terminals is reduced, the bridging capacity between the electrode terminals is increased, and the isolation characteristics of the adjacent electrode terminals are deteriorated.

本発明は、上記のような問題に鑑みてなされたものであり、本発明の目的は、電極端子の剥離を抑制するとともに、アイソレーション特性の悪化を抑制することが可能な高周波電子部品を提供することにある。   The present invention has been made in view of the above problems, and an object of the present invention is to provide a high-frequency electronic component capable of suppressing peeling of electrode terminals and deterioration of isolation characteristics. There is to do.

本発明に係る高周波電子部品は、互いに対向する搭載面と端子面とを有する基板と、搭載面に搭載される高周波回路素子と、端子面上に互いに離間して形成され、少なくとも１つが高周波回路素子と電気的に接続される複数の電極端子と、端子面上に形成された保護層とを備える。保護層は、端子面の中央領域を露出させ、かつ、複数の電極端子の周縁部を覆うように端子面の周縁領域に形成される。   A high-frequency electronic component according to the present invention is formed on a substrate having a mounting surface and a terminal surface facing each other, a high-frequency circuit element mounted on the mounting surface, and spaced apart from each other on the terminal surface, at least one of which is a high-frequency circuit A plurality of electrode terminals electrically connected to the element and a protective layer formed on the terminal surface. The protective layer is formed in the peripheral region of the terminal surface so as to expose the central region of the terminal surface and cover the peripheral portions of the plurality of electrode terminals.

１つの実施態様では、上記高周波電子部品において、基板は矩形形状を有し、保護層は、少なくとも、端子面の角領域に形成される。   In one embodiment, in the high-frequency electronic component, the substrate has a rectangular shape, and the protective layer is formed at least in a corner region of the terminal surface.

１つの実施態様では、上記高周波電子部品において、保護層は、端子面の角領域のみに形成される。   In one embodiment, in the high frequency electronic component, the protective layer is formed only in the corner region of the terminal surface.

１つの実施態様では、上記高周波電子部品において、複数の電極は、グランド接続可能に形成された少なくとも２つの接地電極を含み、少なくとも２つの接地電極は、電気的に互いに接続され、かつ、保護層から露出している。   In one embodiment, in the above high-frequency electronic component, the plurality of electrodes include at least two ground electrodes formed so as to be capable of ground connection, and the at least two ground electrodes are electrically connected to each other and have a protective layer Is exposed from.

本発明によれば、高周波電子部品において、電極端子の剥離を抑制するとともに、アイソレーション特性の悪化を抑制することができる。   ADVANTAGE OF THE INVENTION According to this invention, in a high frequency electronic component, while suppressing peeling of an electrode terminal, the deterioration of an isolation characteristic can be suppressed.

本発明の実施の形態１に係る弾性表面波デュプレクサ（高周波電子部品）における各電極層を示す図である。It is a figure which shows each electrode layer in the surface acoustic wave duplexer (high frequency electronic component) which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る弾性表面波デュプレクサ（高周波電子部品）の模式的断面図である。1 is a schematic cross-sectional view of a surface acoustic wave duplexer (high-frequency electronic component) according to Embodiment 1 of the present invention. 本発明の実施の形態１に係る弾性表面波デュプレクサ（高周波電子部品）の回路構成を模式的に示す図である。It is a figure which shows typically the circuit structure of the surface acoustic wave duplexer (high frequency electronic component) which concerns on Embodiment 1 of this invention. 比較例１に係る弾性表面波デュプレクサ（高周波電子部品）における各電極層を示す図である。It is a figure which shows each electrode layer in the surface acoustic wave duplexer (high frequency electronic component) which concerns on the comparative example 1. FIG. 比較例２に係る弾性表面波デュプレクサ（高周波電子部品）における各電極層を示す図である。It is a figure which shows each electrode layer in the surface acoustic wave duplexer (high frequency electronic component) which concerns on the comparative example 2. FIG. 本発明の実施の形態１と比較例２との電気的特性を比較して示した図である。It is the figure which compared and showed the electrical property of Embodiment 1 of this invention and the comparative example 2. FIG. 本発明の実施の形態２に係る弾性表面波デュプレクサ（高周波電子部品）における裏面電極層を示す図である。It is a figure which shows the back surface electrode layer in the surface acoustic wave duplexer (high frequency electronic component) which concerns on Embodiment 2 of this invention. 本発明の実施の形態３に係る弾性表面波デュプレクサ（高周波電子部品）における裏面電極層を示す図である。It is a figure which shows the back surface electrode layer in the surface acoustic wave duplexer (high frequency electronic component) which concerns on Embodiment 3 of this invention.

以下に、本発明の実施の形態について説明する。なお、同一または相当する部分に同一の参照符号を付し、その説明を繰返さない場合がある。   Embodiments of the present invention will be described below. Note that the same or corresponding portions are denoted by the same reference numerals, and the description thereof may not be repeated.

なお、以下に説明する実施の形態において、個数、量などに言及する場合、特に記載がある場合を除き、本発明の範囲は必ずしもその個数、量などに限定されない。また、以下の実施の形態において、各々の構成要素は、特に記載がある場合を除き、本発明にとって必ずしも必須のものではない。   Note that in the embodiments described below, when referring to the number, amount, and the like, the scope of the present invention is not necessarily limited to the number, amount, and the like unless otherwise specified. In the following embodiments, each component is not necessarily essential for the present invention unless otherwise specified.

（実施の形態１）
図１は、実施の形態１に係る弾性表面波デュプレクサ（高周波電子部品）における各電極層を示す図である。 (Embodiment 1)
FIG. 1 is a diagram showing each electrode layer in the surface acoustic wave duplexer (high-frequency electronic component) according to the first embodiment.

図１を参照して、後述する基板２００（図２参照）の実装面に形成された電極層３１０は、アンテナ端子電極部３１１と、送信端子電極部３１２と、受信端子電極部３１３と、グランド端子電極部３１４とを含む。より具体的には、電極層３１０は、３つのシグナル端子（アンテナ端子１１、送信端子１２、および受信端子１３）を各々構成する各１つのアンテナ端子電極部３１１、送信端子電極部３１２、および受信端子電極部３１３と、６つのグランド端子電極部３１４とを含む。   Referring to FIG. 1, an electrode layer 310 formed on a mounting surface of a substrate 200 (see FIG. 2) described later includes an antenna terminal electrode portion 311, a transmission terminal electrode portion 312, a reception terminal electrode portion 313, and a ground. Terminal electrode portion 314. More specifically, the electrode layer 310 includes three signal terminals (the antenna terminal 11, the transmission terminal 12, and the reception terminal 13), each one of the antenna terminal electrode part 311, the transmission terminal electrode part 312, and the reception. A terminal electrode portion 313 and six ground terminal electrode portions 314 are included.

基板２００（図２参照）の内部に形成された電極層３２０は、アンテナ端子電極部３２１と、送信端子電極部３２２と、受信端子電極部３２３と、グランド端子電極部３２４とを含む。アンテナ端子電極部３２１、送信端子電極部３２２、受信端子電極部３２３、およびグランド端子電極部３２４は、各々、電極層３１０におけるアンテナ端子電極部３１１、送信端子電極部３１２、受信端子電極部３１３、およびグランド端子電極部３１４と電気的に接続される。   The electrode layer 320 formed inside the substrate 200 (see FIG. 2) includes an antenna terminal electrode part 321, a transmission terminal electrode part 322, a reception terminal electrode part 323, and a ground terminal electrode part 324. The antenna terminal electrode part 321, the transmission terminal electrode part 322, the reception terminal electrode part 323, and the ground terminal electrode part 324 are respectively the antenna terminal electrode part 311, the transmission terminal electrode part 312, the reception terminal electrode part 313 in the electrode layer 310, And electrically connected to the ground terminal electrode portion 314.

基板２００（図２参照）の裏面に形成された電極層３３０は、アンテナ端子電極部３３１と、送信端子電極部３３２と、受信端子電極部３３３と、グランド端子電極部３３４とを含む。アンテナ端子電極部３３１、送信端子電極部３３２、受信端子電極部３３３、およびグランド端子電極部３３４は、各々、電極層３２０におけるアンテナ端子電極部３２１、送信端子電極部３２２、受信端子電極部３２３、およびグランド端子電極部３２４と電気的に接続される。   The electrode layer 330 formed on the back surface of the substrate 200 (see FIG. 2) includes an antenna terminal electrode portion 331, a transmission terminal electrode portion 332, a reception terminal electrode portion 333, and a ground terminal electrode portion 334. The antenna terminal electrode part 331, the transmission terminal electrode part 332, the reception terminal electrode part 333, and the ground terminal electrode part 334 are respectively an antenna terminal electrode part 321, a transmission terminal electrode part 322, a reception terminal electrode part 323 in the electrode layer 320, And electrically connected to the ground terminal electrode portion 324.

本実施の形態に係るデュプレクサ１０は、保護層４００の形状にその特徴を有するものである。すなわち、本実施の形態に係るデュプレクサ１０において、保護層４００は、図１（ｃ）に示すように、矩形形状の基板２００の裏面の中央領域を露出させ、かつ、前記基板２００の４辺と隣接して対向する複数の矩形形状の電極部３３１〜３３４の１辺を含む周縁部の一部を覆うように基板２００の裏面の４辺を含む周縁領域に形成されている。   The duplexer 10 according to the present embodiment is characterized by the shape of the protective layer 400. That is, in the duplexer 10 according to the present embodiment, as shown in FIG. 1C, the protective layer 400 exposes the central region of the back surface of the rectangular substrate 200, and the four sides of the substrate 200 A plurality of rectangular electrode portions 331 to 334 adjacent to each other are formed in a peripheral region including four sides of the back surface of the substrate 200 so as to cover a part of the peripheral portion including one side.

図２は、本実施の形態に係るデュプレクサの模式的断面図である。図２に示すように、本実施の形態に係るデュプレクサは、弾性表面波素子（電気素子）１００と、互いに対向する実装面と裏面とを有する基板２００と、基板２００に形成された電極層３００と、基板２００の裏面側に形成された保護層４００とを有する。   FIG. 2 is a schematic cross-sectional view of the duplexer according to the present embodiment. As shown in FIG. 2, the duplexer according to the present embodiment includes a surface acoustic wave element (electric element) 100, a substrate 200 having a mounting surface and a back surface facing each other, and an electrode layer 300 formed on the substrate 200. And a protective layer 400 formed on the back side of the substrate 200.

弾性表面波素子１００はタンタル酸リチウム、ニオブ酸リチウム、水晶などの圧電基板からなり、圧電基板の一方主面にはＩＤＴ、配線、パッド電極などの図示しない電極が形成されている。弾性表面波素子１００は、パッド電極上に設けられたバンプ５００により、基板２００の実装面にフリップチップ実装されている。そして、弾性表面波素子１００は、封止樹脂６００によって封止されている。すなわち、デュプレクサ１０は、ＣＳＰ（Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）型の弾性表面波デュプレクサである。   The surface acoustic wave element 100 is made of a piezoelectric substrate such as lithium tantalate, lithium niobate, or quartz. An electrode (not shown) such as an IDT, wiring, or pad electrode is formed on one main surface of the piezoelectric substrate. The surface acoustic wave element 100 is flip-chip mounted on the mounting surface of the substrate 200 with bumps 500 provided on the pad electrode. The surface acoustic wave element 100 is sealed with a sealing resin 600. That is, the duplexer 10 is a CSP (Chip Size Package) type surface acoustic wave duplexer.

基板２００は、第１誘電体層２１０および第２誘電体層２２０とからなる。電極層３００は、第１電極層３１０と、第２電極層３２０と、第３電極層３３０とからなる。第１電極層３１０は基板２００の実装面に形成されており、弾性表面波素子１００のパッド電極にバンプを介して電気的に接続されている複数のランド電極と、ランド電極に接続されている引き回し配線とを含む。第２電極層３２０は基板２００の内部に形成されており、複数の内部配線を含む。第３電極層３３０は基板２００の裏面に形成されており、弾性表面波デュプレクサの外部端子である複数の裏面電極を含む。   The substrate 200 includes a first dielectric layer 210 and a second dielectric layer 220. The electrode layer 300 includes a first electrode layer 310, a second electrode layer 320, and a third electrode layer 330. The first electrode layer 310 is formed on the mounting surface of the substrate 200, and is connected to a plurality of land electrodes electrically connected to the pad electrodes of the surface acoustic wave element 100 via bumps, and to the land electrodes. Including routing wiring. The second electrode layer 320 is formed inside the substrate 200 and includes a plurality of internal wirings. The third electrode layer 330 is formed on the back surface of the substrate 200 and includes a plurality of back surface electrodes that are external terminals of the surface acoustic wave duplexer.

誘電体層２１０，２２０と、電極層３１０，３２０，３３０とは、交互に積層されている。そして、第１電極層３１０、第２電極層３２０、および第３電極層３３０は、実装基板の内部で図示しないビアホールを介して電気的に接続されている。誘電体層２１０，２２０は、典型的には、セラミックにより構成することができる。   Dielectric layers 210, 220 and electrode layers 310, 320, 330 are alternately stacked. The first electrode layer 310, the second electrode layer 320, and the third electrode layer 330 are electrically connected to each other through a via hole (not shown) inside the mounting substrate. The dielectric layers 210 and 220 can typically be made of ceramic.

図３は、本実施の形態に係る高周波電子部品としてのデュプレクサ１０の回路構成を模式的に示す図である。図３に示すデュプレクサ１０は、たとえば、携帯電話機などのＲＦ回路に搭載されるものである。デュプレクサ１０は、たとえば、ＵＭＴＳ−ＢＡＮＤ４に対応するデュプレクサである。   FIG. 3 is a diagram schematically showing a circuit configuration of the duplexer 10 as the high-frequency electronic component according to the present embodiment. The duplexer 10 shown in FIG. 3 is mounted on an RF circuit such as a mobile phone, for example. The duplexer 10 is, for example, a duplexer corresponding to UMTS-BAND4.

図３に示すように、デュプレクサ１０は、アンテナに接続されるアンテナ端子１１と、送信端子１２と、受信端子１３とを有する。   As illustrated in FIG. 3, the duplexer 10 includes an antenna terminal 11 connected to the antenna, a transmission terminal 12, and a reception terminal 13.

図３に示すように、アンテナ端子１１と送信端子１２との間に、送信フィルタ２０が接続されている。また、アンテナ端子１１と受信端子１３との間に、受信フィルタ３０が接続される。アンテナ端子１１と送信フィルタ２０および受信フィルタ３０との間に、インダクタＬ１からなる整合回路が接続されている。インダクタＬ１の一端がアンテナ端子１１に接続されており、他端がグラウンドに接続されている。   As shown in FIG. 3, a transmission filter 20 is connected between the antenna terminal 11 and the transmission terminal 12. A reception filter 30 is connected between the antenna terminal 11 and the reception terminal 13. A matching circuit including an inductor L1 is connected between the antenna terminal 11 and the transmission filter 20 and the reception filter 30. One end of the inductor L1 is connected to the antenna terminal 11, and the other end is connected to the ground.

送信フィルタ２０は、ラダ−型弾性表面波フィルタにより構成されている。送信フィルタ２０は、出力端子２１と、入力端子２２とを有する。出力端子２１はアンテナ端子１１と接続されており、入力端子２２は送信端子１２と接続されている。   The transmission filter 20 is a ladder-type surface acoustic wave filter. The transmission filter 20 has an output terminal 21 and an input terminal 22. The output terminal 21 is connected to the antenna terminal 11, and the input terminal 22 is connected to the transmission terminal 12.

送信フィルタ２０は、出力端子２１と入力端子２２との間を接続している直列腕２３を有する。直列腕２３において、直列腕共振子Ｓ１〜Ｓ４が直列に接続されている。送信フィルタ２０は、直列腕２３とグラウンドとの間に接続されている並列腕２４〜２６を有する。並列腕２４〜２６には、並列腕共振子Ｐ１〜Ｐ３が設けられている。直列腕共振子Ｓ１〜Ｓ４および並列腕共振子Ｐ１〜Ｐ３は、それぞれ、弾性表面波共振子により構成されている。   The transmission filter 20 includes a series arm 23 that connects between the output terminal 21 and the input terminal 22. In the series arm 23, the series arm resonators S1 to S4 are connected in series. The transmission filter 20 has parallel arms 24-26 connected between the series arm 23 and the ground. The parallel arms 24-26 are provided with parallel arm resonators P1-P3. The series arm resonators S1 to S4 and the parallel arm resonators P1 to P3 are each constituted by a surface acoustic wave resonator.

また、並列腕共振子Ｐ１とグラウンドとの間には、インダクタＬ２が接続されている。並列腕共振子Ｐ２，Ｐ３とグラウンドとの間には、インダクタＬ３が接続され、並列腕共振子Ｐ２，Ｐ３と並列に接続した接続点がインダクタＬ３を介してグランドに接続されている。   An inductor L2 is connected between the parallel arm resonator P1 and the ground. An inductor L3 is connected between the parallel arm resonators P2 and P3 and the ground, and a connection point connected in parallel with the parallel arm resonators P2 and P3 is connected to the ground via the inductor L3.

受信フィルタ３０は、縦結合共振子型弾性表面波フィルタにより構成されている。受信フィルタ３０は、不平衡入力−不平衡出力型のフィルタである。そのため、受信フィルタ３０は、不平衡入力端子３１と、不平衡出力端子３２とを有する。不平衡入力端子３１はアンテナ端子１１と接続されており、不平衡出力端子３２は受信端子１３と接続されている。受信フィルタ３０は、不平衡入力端子３１と不平衡出力端子３２との間に接続されている、弾性表面波共振子３３と、第１および第２の縦結合共振子型弾性表面波フィルタ部３４，３５とを有する。   The reception filter 30 is composed of a longitudinally coupled resonator type surface acoustic wave filter. The reception filter 30 is an unbalanced input-unbalanced output type filter. Therefore, the reception filter 30 has an unbalanced input terminal 31 and an unbalanced output terminal 32. The unbalanced input terminal 31 is connected to the antenna terminal 11, and the unbalanced output terminal 32 is connected to the receiving terminal 13. The reception filter 30 includes a surface acoustic wave resonator 33 and first and second longitudinally coupled resonator type surface acoustic wave filter units 34 connected between an unbalanced input terminal 31 and an unbalanced output terminal 32. , 35.

本実施の形態および後述する実施の形態２，３において、弾性表面波素子１００は、上記送信フィルタ２０のインダクタＬ２，Ｌ３，Ｌ４を除いた部分と、受信フィルタ３０とが一体に形成されたものである。ただし、本発明においては、送信フィルタ２０のインダクタＬ２，Ｌ３，Ｌ４を除いた部分が設けられた送信側弾性表面波素子と、受信フィルタ３０が設けられた受信側弾性表面波素子とが、それぞれ別体に設けられていてもよい。   In this embodiment and Embodiments 2 and 3 to be described later, the surface acoustic wave element 100 is formed by integrally forming a portion of the transmission filter 20 excluding the inductors L2, L3, and L4 and the reception filter 30. It is. However, in the present invention, the transmission-side surface acoustic wave element provided with a portion excluding the inductors L2, L3, and L4 of the transmission filter 20 and the reception-side surface acoustic wave element provided with the reception filter 30 are respectively provided. It may be provided separately.

上述のとおり、本実施の形態に係る電子部品は、保護層４００の形状にその特徴を有するものである。本実施の形態に係る保護層４００の作用効果について、図４、図５に示す比較例１，２と対比しながら説明する。   As described above, the electronic component according to the present embodiment is characterized by the shape of the protective layer 400. The effects of the protective layer 400 according to the present embodiment will be described in comparison with Comparative Examples 1 and 2 shown in FIGS.

なお、図４に示す比較例１は、基板２００の裏面のすべての辺においてクリアランスレジスト構造（電極部３３１〜３３４の端部から間隙を設けてソルダーレジスト層を形成する構造）を採用したものである。   In addition, the comparative example 1 shown in FIG. 4 employs a clearance resist structure (a structure in which a solder resist layer is formed by providing a gap from the ends of the electrode portions 331 to 334) on all sides of the back surface of the substrate 200. is there.

また、図５に示す比較例２は、基板２００の裏面に形成された電極部３３１〜３３４の全ての辺に対してオーバーレジスト構造（電極部３３１〜３３４の周縁部にソルダーレジスト層を重ねて形成する構造）を採用したものである。   Further, in Comparative Example 2 shown in FIG. 5, an over resist structure is formed on all sides of the electrode portions 331 to 334 formed on the back surface of the substrate 200 (a solder resist layer is overlapped on the peripheral portions of the electrode portions 331 to 334). The structure to be formed) is adopted.

本実施の形態（図１）と比較例１（図４）とを対比すると、本実施の形態に係るデュプレクサ１０では、基板２００の周縁領域に位置し、基板の端辺に隣接する複数の電極部３３１〜３３４（裏面端子）の周縁部を覆うように保護層４００を形成するオーバーレジスト構造とされているため、実装熱衝撃試験や実装たわみ試験などで応力が加わっても、電極部３３１〜３３４のはがれが発生しにくい。これに対し、比較例１では、電極部３３１〜３３４にオーバーレジスト構造が無い状態であるため、はがれ強度が相対的に低い。   When this embodiment (FIG. 1) is compared with comparative example 1 (FIG. 4), in duplexer 10 according to this embodiment, a plurality of electrodes located in the peripheral region of substrate 200 and adjacent to the edge of the substrate Since the protective layer 400 is formed so as to cover the peripheral portion of the parts 331 to 334 (back surface terminals), the electrode parts 331 to 331 are applied even when stress is applied in a mounting thermal shock test or a mounting deflection test. Peeling of 334 hardly occurs. On the other hand, in Comparative Example 1, since the electrode portions 331 to 334 have no over resist structure, the peel strength is relatively low.

次に、本実施の形態（図１）と比較例２（図５）とを対比すると、本実施の形態に係るデュプレクサ１０では、基板２００の裏面の周縁領域のみに保護層４００が形成されているのに対し、比較例２では、基板２００の裏面に形成された各電極部３３１〜３３４の全周縁に対してオーバーレジスト構造が採用されているため、本実施の形態（図１）と比較して、特に、基板２００の裏面の中央領域において、電極部を比較的大きく形成する必要がある（図５（ｃ）参照）。   Next, when this embodiment (FIG. 1) is compared with comparative example 2 (FIG. 5), in duplexer 10 according to this embodiment, protective layer 400 is formed only in the peripheral region on the back surface of substrate 200. On the other hand, in Comparative Example 2, since the over resist structure is adopted for the entire periphery of each of the electrode portions 331 to 334 formed on the back surface of the substrate 200, it is compared with the present embodiment (FIG. 1). In particular, it is necessary to form a relatively large electrode portion in the central region on the back surface of the substrate 200 (see FIG. 5C).

比較例２（図５）においては、上述のとおり、各電極部３３１〜３３４の全周縁に対してオーバーレジスト構造が採用されるため、基板２００の裏面上の各電極部を比較的大きく形成する必要がある。そのため、電極部３３１〜３３４間の隙間が小さくなる。この隙間が減少すれば電極部３３１〜３３４間の橋絡容量が増加するため、基板上に隣接して配置される電極部３３１〜３３４間の橋絡容量を介して通過する信号が増加する。これにより隣接する電極部３３１〜３３４間のアイソレーション特性が悪化することが懸念される。   In Comparative Example 2 (FIG. 5), as described above, the over resist structure is adopted for the entire periphery of each of the electrode portions 331 to 334, so that each electrode portion on the back surface of the substrate 200 is formed relatively large. There is a need. Therefore, the gap between the electrode portions 331 to 334 is reduced. If this gap decreases, the bridging capacity between the electrode parts 331 to 334 increases, so that the signal passing through the bridging capacity between the electrode parts 331 to 334 arranged adjacent to each other on the substrate increases. As a result, there is a concern that the isolation characteristics between the adjacent electrode portions 331 to 334 deteriorate.

これに対し、本実施の形態に係るデュプレクサ１０においては、上述のとおり、基板２００の裏面の周縁領域のみにオーバーレジスト構造の保護層４００を形成するため、言い換えれば基板２００の端辺と対向する電極部３３１〜３３４の周縁部に対してオーバーレジスト構造が採用されるため、比較例２と比べて電極部３３１〜３３４が相対的に小さくなる。その結果、オーバーレジスト構造を用いても隣接する電極部３３１〜３３４間の隙間が大きくならず、隣接する電極部３３１〜３３４間のアイソレーション特性の悪化を抑制することが可能である。   On the other hand, in the duplexer 10 according to the present embodiment, as described above, the over-resist structure protective layer 400 is formed only in the peripheral region on the back surface of the substrate 200, in other words, opposite to the edge of the substrate 200. Since the over resist structure is adopted for the peripheral portions of the electrode portions 331 to 334, the electrode portions 331 to 334 are relatively small as compared with the second comparative example. As a result, even when the over resist structure is used, the gap between the adjacent electrode portions 331 to 334 is not increased, and deterioration of the isolation characteristics between the adjacent electrode portions 331 to 334 can be suppressed.

図６に示すように、デュプレクサの送信周波数帯域（Ｔｘ帯域）に対して、本実施の形態に係るデュプレクサ１０と比較例２に係るデュプレクサとでアイソレーション特性を比較する。図６の比較結果から、本実施の形態に係るデュプレクサ１０のアイソレーション特性が、比較例２に係るデュプレクサに対して改善（本実施の形態：６１．８ｄＢ、比較例２：６１．１ｄＢ）することが確認できる。   As illustrated in FIG. 6, the isolation characteristics of the duplexer 10 according to the present embodiment and the duplexer according to the comparative example 2 are compared with respect to the transmission frequency band (Tx band) of the duplexer. From the comparison result of FIG. 6, the isolation characteristic of the duplexer 10 according to the present embodiment is improved compared to the duplexer according to the comparative example 2 (the present embodiment: 61.8 dB, the comparative example 2: 61.1 dB). I can confirm that.

上述のとおり、電極部３３１〜３３４が形成される基板２００は、典型的には、セラミックにより構成される。一般的に、セラミック基板は、樹脂製のプリント基板よりも熱膨張係数が小さく、比誘電率が高い。したがって、基板２００が含まれる高周波電子部品をプリント基板上に実装する際、セラミック基板およびプリント基板に対して熱を加えることで、両基板はともに変形するが、セラミック基板の熱膨張係数がプリント基板に対して相対的に小さいため、両基板の変形量に差が出る。この結果、基板２００の裏面に形成された電極部３３１〜３３４に発生する応力は、コーナ部（角領域）で特に大きくなる。したがって、コーナ部に位置する電極部３３１〜３３４は、その他の電極部３３１〜３３４に比べ、熱膨張係数の差に起因する上記応力の影響を受けやすい。これに対し、本実施の形態に係るデュプレクサ１０では、応力の影響を特に受けやすい電極部３３１〜３３４に対して保護層４００を設けているため、「はがれ防止」の効果が大きい。さらに本実施の形態に係るデュプレクサ１０を相対的に比誘電率が高いセラミック基板に適用する場合では、基板上に隣接して配置される電極部間の橋絡容量によるアイソレーション特性の悪化を抑える効果が大きい。   As described above, the substrate 200 on which the electrode portions 331 to 334 are formed is typically made of ceramic. In general, a ceramic substrate has a smaller thermal expansion coefficient and a higher dielectric constant than a printed circuit board made of resin. Therefore, when a high frequency electronic component including the substrate 200 is mounted on a printed board, both the substrates are deformed by applying heat to the ceramic substrate and the printed board, but the thermal expansion coefficient of the ceramic substrate is However, there is a difference in the amount of deformation between the two substrates. As a result, the stress generated in the electrode portions 331 to 334 formed on the back surface of the substrate 200 is particularly large in the corner portion (corner region). Therefore, the electrode parts 331 to 334 located in the corner part are more susceptible to the stress due to the difference in thermal expansion coefficient than the other electrode parts 331 to 334. On the other hand, in the duplexer 10 according to the present embodiment, since the protective layer 400 is provided for the electrode portions 331 to 334 that are particularly susceptible to stress, the effect of “preventing peeling” is great. Further, when the duplexer 10 according to the present embodiment is applied to a ceramic substrate having a relatively high relative dielectric constant, deterioration of isolation characteristics due to bridging capacitance between electrode portions arranged adjacent to each other on the substrate is suppressed. Great effect.

このように、本実施の形態に係るデュプレクサ１０によれば、基板２００の裏面に形成された電極部３３１〜３３４の剥離を抑制するとともに、アイソレーション特性の悪化を抑制することができる。   Thus, according to the duplexer 10 according to the present embodiment, it is possible to suppress peeling of the electrode portions 331 to 334 formed on the back surface of the substrate 200 and to suppress deterioration of isolation characteristics.

（実施の形態２）
図７は、実施の形態２に係る弾性表面波デュプレクサ（高周波電子部品）における電極層３３０を示す図である。 (Embodiment 2)
FIG. 7 is a diagram showing an electrode layer 330 in the surface acoustic wave duplexer (high-frequency electronic component) according to the second embodiment.

図７を参照して、本実施の形態に係るデュプレクサは、実施の形態１に係るデュプレクサの変形例であって、基板２００の裏面のコーナ部（角領域）にのみ保護層４００を形成することを特徴とする。なお、保護層４００は、コーナ部（角領域）に形成された電極部３３２〜３３４の角領域側の一部を覆うように形成されている。   Referring to FIG. 7, the duplexer according to the present embodiment is a modification of the duplexer according to the first embodiment, and the protective layer 400 is formed only at the corner portion (corner region) on the back surface of the substrate 200. It is characterized by. The protective layer 400 is formed so as to cover a part on the corner region side of the electrode portions 332 to 334 formed in the corner portion (corner region).

本実施の形態においても、上述した熱膨張係数の差に起因する応力の影響を特に受けやすい角領域の電極部に対して保護層４００を設けているため、実施の形態１と同様に、基板２００の裏面に形成された電極部の剥離を抑制するとともに、アイソレーション特性の悪化を抑制することができる。   Also in the present embodiment, since the protective layer 400 is provided for the electrode portion in the corner region that is particularly susceptible to the stress caused by the difference in thermal expansion coefficient described above, the substrate is the same as in the first embodiment. While suppressing peeling of the electrode part formed in the back surface of 200, the deterioration of an isolation characteristic can be suppressed.

（実施の形態３）
図８は、実施の形態３に係る弾性表面波デュプレクサ（高周波電子部品）における電極層３３０を示す図である。 (Embodiment 3)
FIG. 8 is a diagram showing an electrode layer 330 in the surface acoustic wave duplexer (high frequency electronic component) according to the third embodiment.

図８を参照して、本実施の形態に係るデュプレクサは、実施の形態１に係るデュプレクサの変形例であって、３つのシグナル端子に対応する電極部３３１〜３３４の外周部にのみ保護層４００を設けたことを特徴とする。   Referring to FIG. 8, the duplexer according to the present embodiment is a modification of the duplexer according to the first embodiment, and includes a protective layer 400 only on the outer periphery of electrode portions 331 to 334 corresponding to three signal terminals. Is provided.

すなわち、本実施の形態においては、電気的特性上重要であるシグナル端子に対してのみ保護層４００を設ける構造としている。その理由を以下に述べる。   That is, in this embodiment mode, the protective layer 400 is provided only for signal terminals that are important in terms of electrical characteristics. The reason is described below.

図１（ｂ）に示すように、中間の電極層３２０において、複数のグランド端子は共通化されている（電極部３２４）。したがって、裏面の電極層３３０において、グランド端子に対応する１つの電極部３３４のはがれが生じたとしても、中間の電極層３２０における電極部３２４を介して、グランド信号は別の電極部３３４とつながり、グランド接続が確保された状態となり、電気的特性は劣化しない。   As shown in FIG. 1B, a plurality of ground terminals are shared in the intermediate electrode layer 320 (electrode portion 324). Therefore, even if peeling of one electrode portion 334 corresponding to the ground terminal occurs in the electrode layer 330 on the back surface, the ground signal is connected to another electrode portion 334 via the electrode portion 324 in the intermediate electrode layer 320. The ground connection is ensured and the electrical characteristics are not deteriorated.

本実施の形態においても、実施の形態１，２と同様に、基板２００の裏面に形成された電極部の剥離を抑制するとともに、アイソレーション特性の悪化を抑制することができる。また、電気的特性上重要であるシグナル端子を重点的に保護することも可能である。   Also in the present embodiment, as in the first and second embodiments, it is possible to suppress peeling of the electrode portion formed on the back surface of the substrate 200 and to suppress deterioration of isolation characteristics. It is also possible to focus on signal terminals that are important in terms of electrical characteristics.

以上、本発明の実施の形態について説明したが、今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は特許請求の範囲によって示され、特許請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。   Although the embodiments of the present invention have been described above, the embodiments disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

１０ デュプレクサ、１１ アンテナ端子、１２ 送信端子、１３ 受信端子、２０ 送信フィルタ、２１ 出力端子、２２ 入力端子、２３ 直列腕、２４〜２６ 並列腕、３０ 受信フィルタ、３１ 不平衡入力端子、３２ 不平衡出力端子、３３ 弾性表面波共振子、３４，３５ 弾性表面波フィルタ部、１００ 弾性表面波素子、２００ 基板、２１０ 第１誘電体層、２２０ 第２誘電体層、３００ 電極層、３１０ 第１電極層、３１１，３２１，３３１ アンテナ端子電極部、３１２，３２２，３３２ 送信端子電極部、３１３，３２３，３３３ 受信端子電極部、３１４，３２４，３３４ グランド端子電極部、３２０ 第２電極層、３３０ 第３電極層、４００ 保護層、５００ バンプ、６００ 封止樹脂。   10 duplexer, 11 antenna terminal, 12 transmission terminal, 13 reception terminal, 20 transmission filter, 21 output terminal, 22 input terminal, 23 serial arm, 24-26 parallel arm, 30 reception filter, 31 unbalanced input terminal, 32 unbalanced Output terminal, 33 Surface acoustic wave resonator, 34, 35 Surface acoustic wave filter, 100 Surface acoustic wave element, 200 Substrate, 210 First dielectric layer, 220 Second dielectric layer, 300 Electrode layer, 310 First electrode Layer, 311, 321, 331 antenna terminal electrode part, 312, 322, 332 transmission terminal electrode part, 313, 323, 333 reception terminal electrode part, 314, 324, 334 ground terminal electrode part, 320 second electrode layer, 330 3 electrode layers, 400 protective layers, 500 bumps, 600 sealing resin.

Claims (4)

互いに対向する搭載面と端子面とを有する基板と、
前記搭載面に搭載される高周波回路素子と、
前記端子面上に互いに離間して形成され、少なくとも１つが前記高周波回路素子と電気的に接続される複数の電極端子と、
前記端子面上に形成された保護層とを備え、
前記保護層は、前記端子面の中央領域を露出させ、かつ、前記複数の電極端子の周縁部を覆うように前記端子面の周縁領域に形成された、高周波電子部品。 A substrate having a mounting surface and a terminal surface facing each other;
A high-frequency circuit element mounted on the mounting surface;
A plurality of electrode terminals formed on the terminal surface and spaced apart from each other, at least one of which is electrically connected to the high-frequency circuit element;
A protective layer formed on the terminal surface,
The high-frequency electronic component, wherein the protective layer is formed in a peripheral region of the terminal surface so as to expose a central region of the terminal surface and cover peripheral portions of the plurality of electrode terminals. 前記基板は矩形形状を有し、
前記保護層は、少なくとも、前記端子面の角領域に形成される、請求項１に記載の高周波電子部品。 The substrate has a rectangular shape;
The high-frequency electronic component according to claim 1, wherein the protective layer is formed at least in a corner region of the terminal surface. 前記保護層は、前記端子面の角領域のみに形成される、請求項２に記載の高周波電子部品。   The high-frequency electronic component according to claim 2, wherein the protective layer is formed only in a corner region of the terminal surface. 前記複数の電極は、グランド接続可能に形成された少なくとも２つの接地電極を含み、
前記少なくとも２つの接地電極は、電気的に互いに接続され、かつ、保護層から露出している、請求項１から請求項３のいずれかに記載の高周波電子部品。 The plurality of electrodes include at least two ground electrodes formed so as to be groundable,
The high-frequency electronic component according to claim 1, wherein the at least two ground electrodes are electrically connected to each other and exposed from the protective layer.
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JP2005340562A (en) * 2004-05-28 2005-12-08 Kyocera Corp Multiple patterning substrate
JP2007088179A (en) * 2005-09-21 2007-04-05 Murata Mfg Co Ltd High frequency device

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JP2005340562A (en) * 2004-05-28 2005-12-08 Kyocera Corp Multiple patterning substrate
JP2007088179A (en) * 2005-09-21 2007-04-05 Murata Mfg Co Ltd High frequency device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10388603B2 (en) 2015-10-30 2019-08-20 Murata Manufacturing Co., Ltd. Thin film element and method for manufacturing the same

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