JP2013098308A - Semiconductor wafer, semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the occurrence of a crack on a substrate by stress concentration on an alignment mark end portion.SOLUTION: On a first principal plane of the substrate, an annular first groove and a second groove having a shape of no end portion are formed, when viewed opposite to the first principal plane. After an insulating film is formed in a manner to embed the first and second grooves, a photoresist film is formed on the first principal plane of the substrate. A first pattern aligned by setting as a reference the position of the second groove, having the embedded insulating film, on the substrate is transferred to the photoresist film. A through electrode penetrating through the substrate to the thickness direction is formed on the substrate positioned inside the annular first groove having the embedded insulating film.

Description

  The present invention relates to a semiconductor wafer, a semiconductor device, and a manufacturing method thereof.

  In a semiconductor device in which a plurality of semiconductor chips are stacked to realize a high function, upper and lower semiconductors are formed by through electrodes (Through Silicon Via, hereinafter referred to as TSV) provided so as to penetrate the semiconductor chips. A structure for electrically connecting the chips is used. In such a semiconductor chip, an insulating ring structure in which the periphery of the TSV is surrounded by an insulator may be used for the purpose of insulating and separating the TSV and the element region and reducing the capacity between neighboring TSVs. .

  Patent Document 1 (Japanese Unexamined Patent Application Publication No. 2009-1111061) discloses a method for manufacturing a semiconductor device having a through electrode provided with an insulating ring. This discloses a process in which an insulating ring is first formed (via first), element formation to wiring formation, and finally TSV is formed (via last). More specifically, first, a ring-shaped trench is dug in the depth direction from the element forming surface side of the silicon substrate, and the trench is filled with an insulating film to form an insulating ring. Thereafter, after the element formation on the substrate surface, the wiring layer formation, the surface electrode formation step, and the like, the silicon substrate is ground from the back side to be thinned. At this time, by grinding the back surface until the bottom of the insulating ring is exposed from the back surface of the substrate, the insulating ring penetrates the silicon substrate from the front surface to the back surface. And TSV is formed by forming a back surface electrode from the back surface side so that a silicon substrate may be penetrated inside an insulating ring.

JP 2009-1111061 A

  Unlike the above method, if the step of forming the element isolation region (field) is the first step performed on the substrate without forming the insulating ring or the like by via first, the position of the element isolation region on the substrate is determined. There is no need to adjust. That is, since no other member is formed on the substrate when the element isolation region is formed, it is not necessary to align the element isolation region with respect to these members.

  On the other hand, as described above, when forming an element isolation region on a substrate on which an insulating ring has already been formed by via first, the element isolation region is formed by adjusting (positioning) the position on the substrate. There is a need. That is, after the formation of the insulating ring, it is necessary to form an alignment mark used for photolithography before patterning the element isolation region on the substrate.

  However, in the conventional method, since the alignment mark trench is deep and the width thereof is narrow, when an insulating film is embedded in the trench, a seam or a void may occur inside. Since the trench for the alignment mark is formed in a line-and-space shape, stress concentrates on an embedding defect portion such as a seam or a void, and a crack may occur in the substrate starting from this portion. This crack sometimes reaches the element region, and in this case, the manufacturing yield is reduced.

One embodiment is:
Forming an annular first groove and a second groove having a terminal portion on the first main surface of the substrate when facing the first main surface; and
Forming an insulating film so as to fill the first and second grooves;
After the step of forming the insulating film, forming a photoresist film on the first main surface of the substrate;
Transferring the first pattern, which is aligned on the basis of the position of the second groove embedded in the insulating film on the substrate, to the photoresist film;
Forming a through electrode penetrating through the substrate in a thickness direction on the substrate located inside the annular first groove embedded in the insulating film;
The present invention relates to a method for manufacturing a semiconductor device.

Other embodiments are:
A substrate,
An insulating ring that penetrates the substrate in the thickness direction and has an annular shape when viewed from the first main surface of the substrate;
An alignment mark that penetrates the substrate in the thickness direction and has a shape that does not have a terminal portion when viewed from the first main surface of the substrate.
In the substrate located inside the annular insulating ring, a through electrode provided to penetrate the substrate in the thickness direction;
The present invention relates to a semiconductor wafer.

Other embodiments are:
A substrate,
An insulating ring that penetrates the chip region of the substrate in the thickness direction and has an annular shape when viewed from the first main surface of the substrate;
An alignment mark that penetrates the chip region of the substrate in the thickness direction and has a shape that does not have a terminal portion when viewed from the first main surface of the substrate.
In the chip region located inside the annular insulating ring, a through electrode provided to penetrate the substrate in the thickness direction;
The present invention relates to a semiconductor device.

  An alignment mark having a shape that does not include the end portion is formed. Thereby, it is possible to reduce the occurrence of cracks in the substrate due to the stress concentration at the alignment mark end portion.

It is a figure showing the method which this inventor examined. It is a figure showing the method which this inventor examined. It is a figure showing the method which this inventor examined. It is a figure showing the semiconductor device of 1st Example. 3 is a flowchart illustrating a method for manufacturing the semiconductor device according to the first embodiment. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the 1st modification of 1st Example. It is a figure showing the 2nd modification of 1st Example. It is a figure showing the 3rd modification of 1st Example.

  Japanese Patent Laid-Open No. 2005-217071 discloses a method of simultaneously forming an alignment mark that serves as an alignment reference during chip stacking by a process of forming a TSV body. More specifically, when a plurality of chips cut out from a wafer are stacked on each other, a conductive material penetrating through the same substrate as TSV is used as an alignment mark for causing the bonding apparatus to recognize the position of the chip so as not to cause misalignment. This is a technology that uses materials to form simultaneously with the TSV forming process.

  Therefore, as an application example of the above technique, the present inventor provides an alignment mark that serves as a reference for alignment in the step of transferring the STI (field) pattern (photolithographic step), which is the first step of the element forming step. The method of forming simultaneously with the insulating ring was examined in advance. Normally, when an STI is first formed on a wafer on which no component of the semiconductor device is formed, there is no need to align with any element, and therefore no alignment mark is necessary in the STI formation process. Further, in the step after the STI formation step, alignment may be performed with reference to the alignment mark formed simultaneously in the STI formation step.

  On the other hand, the structure which is the subject of the present application enters an element formation step after first forming an insulating ring surrounding the TSV (via first). Therefore, an alignment mark (field alignment mark) for aligning the STI with respect to the insulating ring is required, and the above-described technique has been studied as a method for forming the alignment mark. The field alignment mark investigated by the present inventor has a shape in which insulating grooves are arranged in a line and space (L / S) shape so that it can be recognized in the lithography process.

  In the following, a semiconductor device and a manufacturing method thereof studied by the present inventors will be described with reference to FIGS. In each drawing, some structures are omitted as appropriate, and only important structures are shown. As shown in FIG. 1A, this semiconductor device has a chip region 3 surrounded by a scribe region 2 on a semiconductor substrate 17. The chip region 3 is provided with an element region 4 and a through electrode 5, and the scribe region 2 is provided with an alignment mark 1. 1B is a cross-sectional view in the A′-A ′ direction near the through electrode 5 in FIG. 1A, and FIG. 1C is a cross-sectional view in the B′-B ′ direction of a part of the alignment mark 1 in FIG. 1A. As shown in FIG. 1B, the through electrode 5 includes a front surface electrode 33, a wiring layer 14 and a back surface electrode 34. A part of the wiring layer 14 and the back electrode 34 penetrates the interlayer insulating film 16. In the chip region 3, an annular insulating ring 6 is provided so as to surround the through electrode 5, and the through electrode 5 is insulated and separated from other elements 8 such as transistors. The element 8 is connected to the wiring 8a through the contact plug 8b. As shown in FIG. 1C, an alignment mark 1 is provided in the scribe region 2. A wiring layer 15 is provided in the interlayer insulating film 16 above the alignment mark 1. The lengths of the insulating ring 6 and the alignment mark 1 in the substrate thickness direction 38 are the same. The chip region 3 and the scribe region 2 are provided with an element isolation region (STI) 7.

  2 and 3 show the steps of forming the insulating ring 6 and the alignment mark 1 of the semiconductor device of FIG. 1, and other parts are not shown for the sake of simplicity. 2 and 3, A is a process for forming the insulating ring 6 in FIG. 1B, B is a process for forming the alignment mark 1 in FIG. 1C, and C is an enlarged view of a portion P surrounded by a dotted line in FIG. , D shows an enlarged view of a portion Q surrounded by a dotted line in FIG. FIG. 3E shows a top view of the entire alignment mark 1 on the first main surface 17a.

  As shown in FIG. 2, after forming a photoresist film 20 on the surface of the silicon semiconductor substrate 17, a pattern is formed in the photoresist film 20 by lithography. Subsequently, dry etching of the semiconductor substrate 17 is performed using the photoresist film 20 as a mask. Thus, an annular trench (insulating ring trench) 32 and an alignment mark trench 25 are formed simultaneously. The trench 25 for the alignment mark is a line and space (L / S) in which a plurality of trenches 25 are arranged at a constant pitch in the width direction 25b of the trench 25 when viewed from the first main surface 17a. It is formed into a shape.

As shown in FIG. 3, after removing the photoresist film 20, both the trenches 25 and 32 are simultaneously filled with the insulating film 26. Here, as the insulating film 26, an NSG (None-Doped Silicate Glass) film formed by a CVD method (chemical vapor deposition method) using TEOS (Tetra Ethoxy Silane; Si (OC ₂ H ₅ ) ₄ ) as a raw material is used. Use. Thereby, the insulating ring 6 and the alignment mark 1 are formed.

  Here, since the alignment mark trench 25 formed in the same manner as the insulating ring trench 32 is deep (˜40 μm) and wide (˜2 μm), the embedding property is low, and a seam or void is formed in the insulating film 26. 56. In particular, in the alignment mark 1 in which a plurality of trenches 25 are arranged in an L / S shape, the seam or the like 56 is formed in the vicinity of the center in the width direction 25b of the trench 25 and extends in the extension direction 50 of the trench. Ends at the terminal end 25a. For this reason, it has been proved by the inventor that stress concentrates in the trench termination portion 25a corresponding to the end of the seam or the like 56, and the crack 57 is generated in the semiconductor substrate 17 from the termination portion 25a. Such cracks 57 may reach the element region 4 and cause a decrease in manufacturing yield. Thus, it was found that there is room for improvement in the manufacturing method of this study example.

  Therefore, the present inventor examined a method for preventing the occurrence of the crack 57. As a result, it has been found that if the alignment mark trench 25 is formed so that the end portion of the trench does not exist, the generation of the crack 57 can be prevented. That is, in the present invention, the trench 25 for the alignment mark having a closed shape surrounding a part of the semiconductor substrate 17 is formed so that the terminal portion does not exist in a plan view. For this reason, even when a poor embedment such as a seam or a void 56 occurs in the insulating film 26 in which the trench 25 is embedded, stress concentrates on the terminal portion of the trench 25 and a crack 57 occurs in the semiconductor substrate 17. Can be reduced. As a result, the manufacturing yield can be improved.

  The present invention will be described below with reference to the drawings. In addition, these Examples are specific examples shown for a deeper understanding of the present invention, and the present invention is not limited to these specific examples.

(First embodiment)
4 and 5 are views showing a semiconductor device manufactured by the manufacturing method of the first embodiment. As shown in FIG. 4A, this semiconductor device has a chip region 3 surrounded by a scribe region (cutting region) 2 on a semiconductor substrate 17. The chip region 3 is provided with an element region 4 and a through electrode 5. As will be described later, a plurality of semiconductor chips can be electrically connected through the through electrode 5. An alignment mark 1 is provided in the scribe region 2.

  4B is a cross-sectional view in the A′-A ′ direction near the through electrode 5 in FIG. 4A, FIG. 4C is a cross-sectional view in the B′-B ′ direction in the vicinity of the alignment mark 1 in FIG. 4A, and FIG. 4D is C ′ in FIG. FIG. 4E shows a horizontal sectional view in the D′-D ′ direction of FIG. 4C.

  As shown in FIGS. 4B and 4D, the through electrode 5 includes a front surface electrode 33, a wiring layer 14, and a back surface electrode 34. A part of the wiring layer 14 and the back electrode 34 penetrates the interlayer insulating film 16. The tip region 3 is provided with an annular insulating ring 6 when viewed from the first main surface 17a. The insulating ring 6 extends from the first main surface 17a in the thickness direction 38 of the semiconductor substrate 17 and extends through the semiconductor substrate 17 to the second main surface 17b. The insulating ring 6 is provided so as to surround the through electrode 5 and insulates the through electrode 5 from other elements 8. As shown in FIGS. 4C and 4E, the scribe region 2 is provided with an alignment mark 1 having an annular shape as viewed from the first main surface 17a. The alignment mark 1 has the same depth as the insulating ring 6 in the thickness direction 38 of the semiconductor substrate 17. A wiring layer 15 is provided in the interlayer insulating film 16 above the alignment mark 1. An element isolation region (STI) 7 is provided in the element region 4 and the scribe region 2.

  5 to 15 are views for explaining a method of manufacturing the semiconductor device of this embodiment. Hereinafter, the manufacturing method of the present embodiment will be described with reference to these drawings. FIG. 5 is a flowchart showing the manufacturing method of this embodiment. 6 to 14, A is a cross-sectional view corresponding to FIG. 4B, B is a cross-sectional view corresponding to FIG. 4C, and C is a top view when B is viewed from a direction facing the first main surface 17 a. Represent. In FIG. 7C, the trench 25 is shown as a perspective view so that the positional relationship is clear. 15A is a cross-sectional view showing a state in which a plurality of semiconductor chips are stacked, and FIG. 15B is an enlarged view of a portion 51 surrounded by a dotted line in FIG. 15A.

  As shown in FIG. 6, a photoresist film 20 is formed on the surface of the silicon semiconductor substrate 17. Patterns for insulating rings and alignment marks are formed in the photoresist film 20 by lithography. The semiconductor substrate 17 is dry etched using the pattern of the photoresist film 20. Thereby, a trench (first groove) 32 for an insulating ring and a trench (second groove) 25 for an alignment mark are formed (S11 in FIG. 5). In the present embodiment, the insulating ring trench (first groove) 32 is annular when viewed from the first main surface 17a, and has a depth of 40 μm, a width of 2 μm, and a ring diameter of 20 μm. Although the dimension of the trench 32 for insulation rings is not specifically limited, For example, it can be set as 30-50 micrometers in depth, 1-3 micrometers in width, and 15-30 micrometers in ring diameter.

  In addition, the alignment mark trench 25 (second groove) has an annular shape when viewed from the first main surface 17a. Since the alignment mark trench 25 is formed in the same process as the insulating ring trench 32, the depth of both is the same (in the above example, 40 μm). The width and pattern diameter of the alignment mark trench 25 are determined by the detectable size of the mark sensor that detects the alignment mark. Here, in order to minimize the area that the alignment mark occupies on the wafer, dimensions (width, pattern diameter) close to the lower limit of the detectable dimension of the mark sensor are desirable. Accordingly, the dimension of the alignment mark pattern is set to be approximately the same as or smaller than the dimension of the insulating ring pattern. When the groove width of the alignment mark trench 25 is small, stress concentration due to poor embedding tends to occur.

  Further, as described with reference to FIG. 3E, when the alignment mark 1 is composed of an L / S repetitive pattern, it is understood that stress concentration is likely to occur even if the groove width is approximately the same as that of the insulating ring 6. ing. For example, in the alignment mark 1 having the shape described with reference to FIG. 3E, the L / S width (the length in the width direction 25b) is about 2 μm (the pitch is about 4 μm), and the line length (the length in the extending direction 50). It is known that cracks 57 due to stress concentration occur in the process after embedding the insulating film 26 when the thickness is about 35 to 45 μm and the number of lines is 18 (the depth of the trench 25 is the same as that of the insulating ring 6). About 40 μm).

As shown in FIG. 7, the photoresist film 20 is removed. An NSG (None-Doped Silicate Glass) film 26 is formed on the semiconductor substrate 17 by a CVD method using TEOS (Tetra EthOxy Silane; Si (OC ₂ H ₅ ) ₄ ) as a raw material (hereinafter, this film 26 is referred to as TEOS). -Called NSG film). The film thickness of the TEOS-NSG film 26 formed by such a deposition method (film thickness on the semiconductor substrate 17) is at least 1/2 of the width of the trenches 25 and 32 from the viewpoint of completely embedding the trenches 25 and 32. Is the film thickness. Further, the TEOS-NSG film 26 is used because it can be formed conformally with good coverage in order to avoid generation of voids as much as possible when embedding the high aspect ratio trenches 25 and 32. is there. In the case where the same effect is obtained, another material may be used for the insulating film 26.

  As shown in FIG. 8, in order to reduce the CMP load when removing the TEOS-NSG film 26 on the semiconductor substrate 17 in a subsequent polishing step, the film thickness of the TEOS-NSG film 26 is reduced by wet etching. At this time, a seam may occur in the TEOS-NSG film 26 formed in the trench 25 for alignment marks. In this case, if the TEOS-NSG film 26 is wet-etched as it is, the seam in the TEOS-NSG film 26 is deepened. Therefore, wet etching is performed in a state where the TEOS-NSG film 26 on the alignment mark trench 25 is protected by a protective film such as the photoresist film 20.

  As discussed with reference to FIGS. 2 and 3, when the insulating film 26 is embedded in the alignment mark trench 25, seams and voids 56 may be generated inside the insulating film 26. In particular, when the alignment mark trench 25 in which a plurality of trenches are arranged in a line-and-space manner is formed, the seam or void 56 is formed near the center in the width direction 25b of the trench, and the extension of the trench when seen in plan view. It extends in the same direction as direction 50. Since the seam or the like 56 ends at the end portion 25a in the extending direction 50 of the trench, stress is easily concentrated on the trench end portion 25a. As a result, in the structure studied above, the crack 57 is generated in the semiconductor substrate 17 starting from the terminal portion 25a when the TEOS-NSG film 26 shown in FIG. 7 is formed or during the wet etching shown in FIG. When such a crack 57 reaches the element region 4, it causes a decrease in manufacturing yield.

  On the other hand, in this embodiment, the alignment mark trench 25 is formed in a closed shape surrounding a part of the semiconductor substrate 17 so that the terminal portion does not exist in a plan view. Even when a seam or void is poorly embedded in the TEOS-NSG film 26 embedded in the alignment mark trench 25, the seam or the like is formed near the center in the width direction 25b of the trench. For this reason, when viewed in plan, the seam or the like is formed so as to have a closed shape with no terminal portion. Therefore, as in the case where the line and space trench is formed and the TEOS-NSG film 26 shown in FIG. 7 is formed or the wet etching shown in FIG. 8 is performed, the trench end portion 25a which is the end portion of the seam or the like is formed. Concentration of stress can be prevented. As a result, the generation of cracks 57 starting from the trench termination portion 25a can be reduced, and the manufacturing yield can be improved.

  As shown in FIG. 9, after removing the photoresist film 20, heat treatment is performed at 950 ° C. for 60 minutes to degas the TEOS-NSG film 26. Next, the TEOS-NSG film 26 on the first main surface 17a of the semiconductor substrate 17 is removed by a chemical mechanical polishing method (CMP method), thereby completing the insulating ring 6 and the alignment mark 1 (FIG. 5). S12).

  As shown in FIG. 10, a photoresist film 20 is formed on the semiconductor substrate 17. The first pattern 29 is formed by transferring the field pattern for STI onto the photoresist film 20 by lithography. At this time, in this embodiment, the alignment mark 1 formed as described above can be used as an alignment mark for the field pattern for STI. That is, by transferring the field pattern aligned with the position of the alignment mark 1 on the semiconductor substrate 17 as a reference to the photoresist film 20, misalignment of photolithography can be reduced.

  The semiconductor substrate 17 is etched using the first pattern 29 of the photoresist film 20. Thus, as shown in FIG. 11, an STI trench 7a is formed (S21 in FIG. 5). Thereafter, the photoresist film 20 is removed. After an insulating film such as a silicon oxide film or a silicon nitride film is embedded on the semiconductor substrate 17, a CMP process is performed on the insulating film. Thereby, an STI (element isolation region) 7 is formed (S22 in FIG. 5).

  As shown in FIG. 12, an element 8 such as a transistor is formed in the active region 30 of the semiconductor substrate 17 (S23 in FIG. 5). An interlayer insulating film 16 is formed on the semiconductor substrate 17 in several stages. In the process of forming the interlayer insulating film 16, the wiring layer 14 and the alignment mark above the region in the semiconductor substrate 17 surrounded by the contact plug 8 b, the wiring 8 a, and the insulating ring 6 that reach the impurity diffusion layer of the transistor 8. A wiring layer 15 is formed in the vicinity of 1. The wiring layer 14 functions as a pad for connecting to the front surface electrode 33 and the back surface electrode 34 to be formed in a later step. The wiring layer 14 includes a plurality of wirings 14a to 14d made of aluminum (Al), copper (Cu), or the like, and a plurality of contact plugs 14e to 14g made of a metal film such as tungsten for connecting the plurality of wirings. The wiring layer 15 includes a plurality of wirings 15a to 15d and a plurality of contact plugs 15e to 15g that connect the plurality of wirings.

  As shown in FIG. 13, a protective film 36 made of a silicon oxynitride film (SiON) 36 a and a polyimide film (passivation film) 36 b is formed on the interlayer insulating film 16 so as to cover the wiring layer 14. Next, a first opening 33a is formed in the protective film 36 so that the upper surface of the wiring layer 14 is exposed. The seed film 11 is formed on the protective film 36 including the first opening 33a by sputtering. After forming a photoresist film (not shown) on the protective film 36, patterning is performed to expose the seed film 11 provided in the first opening 33a. A copper bump 13 and a solder film 12 are sequentially formed on the exposed seed film 11 by electroplating. After removing the photoresist film on the protective film 36, the exposed seed film 11 is removed. The seed film 11, the copper bump 13, and the solder film 12 constitute a surface electrode 33 (S3 in FIG. 5).

  As shown in FIG. 14, a support substrate (not shown) is provided on the side of the semiconductor substrate 17 on which the surface electrode 33 is provided via an adhesive layer (not shown). Thereafter, the second main surface 17b facing the first main surface 17a of the semiconductor substrate 17 in the thickness direction is thinned to a thickness of, for example, 775 μm to 40 to 50 μm (S4 in FIG. 5). By this grinding process, the insulating ring 6 and the bottom of the alignment mark 1 formed in advance are exposed on the second main surface 17 b side of the semiconductor substrate 17. Anisotropic dry etching is performed on the semiconductor substrate 17 located inside the annular insulating ring 6 so that the wiring layer 14 is exposed from the second main surface 17b side of the semiconductor substrate 17. At this time, a second opening 34 a that penetrates the semiconductor substrate 17 and extends in a part of the interlayer insulating film 16 is formed. Next, a seed film 10 is formed by laminating a titanium (Ti) film and a copper (Cu) film on the entire surface of the second main surface 17b of the semiconductor substrate 17 by sputtering. A photoresist pattern (not shown) having a third opening at the same position as the second opening 34 a is formed on the second main surface 17 b of the semiconductor substrate 17. A copper bump 19 and a solder film 9 such as a SnAg film are sequentially formed in the third opening by electroplating. A back electrode 34 is formed by the seed film 10, the copper bump 19, and the solder film 9. Next, after removing the photoresist pattern, the exposed portion of the seed film 10 is removed (S5 in FIG. 5).

  Thereafter, the surface of the solder film 9 is made convex by reflow. The adhesive layer and the support substrate are removed. As described above, the semiconductor device shown in FIG. 4 is obtained. In this semiconductor device, a through electrode 5 is provided in each chip region 3 partitioned by the scribe region 2 so as to penetrate the semiconductor substrate 17. The through electrode 5 has bumps (surface electrode 33 and back electrode 34) for connection at the upper and lower ends, and is arranged vertically via the through electrode 5 when a plurality of semiconductor chips are stacked as will be described later. The connected semiconductor chips are electrically connected. The through electrode 5 includes a through plug (surface electrode 33, back electrode 34) that penetrates the semiconductor substrate 17 and a wiring layer 14 that penetrates the plurality of interlayer insulating films 16 on the semiconductor substrate 17. A portion of the through electrode 5 that penetrates the semiconductor substrate 17 is surrounded by an annular insulating ring 6 and is insulated and separated from other elements 8 and the like.

  Next, the semiconductor substrate 17 is scribed along the scribe region (cutting region) 2 (S6 in FIG. 5). Thereby, the semiconductor substrate 17 is separated into individual pieces to form a semiconductor chip.

  As shown in FIG. 15, a plurality of semiconductor chips 40 are mounted such that the front surface electrode 33 and the back surface electrode 34 of different semiconductor chips 40 are in contact with each other. The solder films 9 and 12 of the front surface electrode 33 and the back surface electrode 34 of each semiconductor chip 40 are joined by reflow. After filling the underfill 41 between the semiconductor chips 40, the plurality of semiconductor chips 40 are mounted on the package substrate 42. Thereafter, by molding with the mold resin 43, the semiconductor device of this example is completed (S7 in FIG. 5).

  Examples of the semiconductor device of this embodiment include storage devices such as DRAM, SRAM, and flash memory, and arithmetic processing devices such as MPU and DSP.

  As described above, in this embodiment, seams and voids may be generated in the TEOS-NSG film 26 embedded in the alignment mark trench 25 in the step of FIG. However, even in such a case, the alignment mark trench 25 is formed in an annular shape surrounding a part of the semiconductor substrate 17 when viewed from the first main surface 17a of the semiconductor substrate 17, There is no termination. Since the seam and void are formed near the center in the width direction 25b of the trench, similar to the shape of the trench 25, the seam and void are also closed so as to surround a partial region of the semiconductor substrate 17 when viewed in plan. It is formed in a shape, and there is no terminal part. Generally, since stress concentrates on the end portion of a seam or the like, stress concentration on the end portion such as a seam can be prevented by eliminating the end portion such as the seam as described above. As a result, when the TEOS-NSG film 26 shown in FIG. 7 is formed or when the wet etching shown in FIG. 8 is performed, the generation of cracks in the semiconductor substrate 17 starting from the end portion of the seam or the like is reduced to improve the manufacturing yield. Can be made.

  In this embodiment, the annular alignment mark trench 25 is formed, but the alignment mark trench 25 is not limited to the annular shape. That is, the alignment mark trench (second groove) 25 is a closed portion that surrounds a part of the semiconductor substrate 17 when viewed from a direction facing the first main surface 17a of the semiconductor substrate 17 (in plan view). The shape is not particularly limited as long as it has a different shape. In such a shape, since there is no termination in the alignment mark trench (second groove), it is possible to reduce the occurrence of cracks starting from the termination in the semiconductor substrate 17 as described above. it can. In addition, the shape of the alignment mark trench (second groove) 25 is not particularly limited as long as it does not have a terminal portion and is practically usable as a field alignment mark when aligning the STI 7. The shape can be a straight line or a curved line. In the present embodiment, one alignment mark 1 is formed at one place on the scribe region 2, but the position and number of the alignment marks 1 can be changed as appropriate.

  In this embodiment, the alignment mark 1 is used as a field alignment mark during the STI 7 alignment. The alignment mark 1 can be used as a field alignment mark for alignment of other structures in addition to the alignment of the STI 7. For example, in the step of FIG. 14, it can be used as a field alignment mark for alignment when forming the second opening 34a.

  In this embodiment, the TEOS-NSG film 26 is exemplified as the insulating film for burying the insulating ring trench 32 and the alignment mark trench 25. However, the material for burying the trenches 25 and 32 is not limited thereto. . When a deep and wide trench 25 is buried with an insulating film like the alignment mark 1, seams and voids are likely to occur due to poor filling even if it is not a TEOS-NSG film. Therefore, the present invention is not limited to the TEOS-NSG film 26, but is equally effective when applied to a process of filling the trench 25 with another insulating film. On the other hand, when the TEOS-NSG film 26 is used, heat treatment for baking (Degas) is required. The TEOS-NSG film 26 may be contracted by this heat treatment, and the seam may be expanded. Therefore, it can be said that the present invention is more effective for the process of filling the trench 25 with the TEOS-NSG film 26.

(First modification)
In the first embodiment, one alignment mark 1 having a perfect circle shape is formed at one place on the scribe region 2 in plan view. However, in this modification, the shape in plan view is different from a perfect circle at one place. The difference is that a plurality of circular alignment marks 1 are provided. FIG. 16 is a view showing the alignment mark 1 formed in this modification, and FIGS. 16A and 16B are cross-sectional views corresponding to FIGS. 4C and 4E of the first embodiment, respectively. As shown in FIG. 16, in this modification, a plurality of circular alignment marks 1 are provided in plan view. Thus, even if the alignment mark 1 has a circular shape as shown in FIG. 16B in a plan view, since there is no terminal portion of the alignment mark 1, cracks starting from the terminal portion are formed as in the first embodiment. Occurrence can be prevented.

  The alignment mark 1 of this modification is the same as the alignment mark 1 of the first embodiment except for the shape and number in plan view. For this reason, in the process of FIG. 6 of the first embodiment, the process is the same as that of the first embodiment, except that the alignment mark trenches 25 are formed so as to have the number and shape of the alignment marks 1 of the present modification. Thus, a semiconductor device can be formed.

  Further, the shape of the alignment mark 1 is not limited to the shape shown in the first embodiment and the first modification as long as the alignment mark 1 is a closed shape having no terminal portion when viewed in plan. The shape of the alignment mark 1 can be a closed shape such as a shape including a rectangle, a square, a straight line, and a curve in a plan view.

(Second modification)
In the first embodiment, the alignment mark 1 consisting of one layer of the TEOS-NSG film 26 is formed. In this modification, the alignment mark 1 consisting of two layers of the silicon nitride film 26a and the TEOS-NSG film 26b and the insulating ring are used. 6 is different. Hereinafter, the manufacturing process of the present modification will be described focusing on processes different from the first embodiment.

  First, the process of FIG. 6 of the first embodiment is performed. Instead of the process of FIG. 7 of the first embodiment, a thin silicon nitride film 26a and a TEOS-NSG film 26b are formed on the entire surface of the semiconductor substrate 17 so as to fill the trench 32 for the insulating ring and the trench 25 for the alignment mark. Form.

  Next, as in the step of FIG. 8 of the first embodiment, a photoresist film 20 is formed on the insulating ring trench 32 and the alignment mark trench 25, and then nitrided using the photoresist film 20 as a mask. The silicon film 26a and the TEOS-NSG film 26b are wet etched.

  As shown in FIG. 17, a CMP process is performed on the TEOS-NSG film 26b using the silicon nitride film 26a on the semiconductor substrate 17 as a stopper. 17A, 17B, and 17C represent cross sections corresponding to FIGS. 9A, 9B, and 9C of the first embodiment, respectively.

  Thereafter, the steps of FIGS. 10 to 15 of the first embodiment are performed. In the steps after FIG. 10, if necessary, part or all of the silicon nitride film 26 a on the first major surface 17 a of the semiconductor substrate 17 may be removed.

(Third Modification)
In the first embodiment, the alignment mark 1 is formed in the scribe region 2 of the semiconductor substrate 17, but this modification is different in that the alignment mark 1 is formed in a region other than the scribe region 2 of the semiconductor substrate 17.

  FIG. 18A is a plan view illustrating an example in which the alignment mark 1 is provided in the ineffective shot region 45 of the semiconductor substrate 17. The semiconductor substrate 17 includes a plurality of effective shot regions (regions indicated by hatching in FIG. 18A) 46 formed of semiconductor chips on which the semiconductor device is formed by performing lithography exposure in a later process, and the semiconductor device. There is a non-effective shot region (a white region in FIG. 18A) 45 that is not formed. The non-effective shot region 45 refers to a region where a semiconductor chip where a normal semiconductor device pattern cannot be formed is located. That is, since the semiconductor substrate 17 is formed in a circular shape and the semiconductor chip is formed in a rectangular shape, a part of the semiconductor chip applied to the terminal portion of the semiconductor substrate 17 protrudes from the semiconductor substrate 17 and cannot be patterned. Become. Since the size of the semiconductor chip is determined when the design of the semiconductor device is completed, the position of the ineffective shot region 45 on the semiconductor substrate 17 can be grasped in advance. If pattern formation is repeated at the terminal portion of the semiconductor substrate 17, foreign matter is generated, and thus no pattern is formed in the ineffective shot region 45. Therefore, the ineffective shot region 45 is a useless region that does not contribute to the manufacture of the semiconductor device. In this modification, the alignment mark 1 is formed by using the non-effective shot area 45 which becomes the useless area, so that it is not necessary to secure an area for the alignment mark 1 in the effective shot area 46, and the fine mark is fine. It can be set as the semiconductor device corresponding to conversion. Note that the number and positions of the non-effective shot regions 45 for forming the alignment mark 1 are not limited to the example of FIG. 18A, and the alignment marks 1 can be appropriately formed in the desired number and positions of the non-effective shot regions 45. .

  18B is a view showing another example, showing an example in which the alignment mark 1 is formed in the chip region 3 of the semiconductor substrate 17, and corresponding to FIG. 4A of the first embodiment. As shown in FIG. 18B, the alignment mark 1 may be formed in the chip region 3. Further, the formation position and the number of alignment marks 1 in the chip region 3 are not limited to the example of FIG. 18B, and a desired number of alignment marks 1 are formed in a desired position in the chip region 3. Can do.

DESCRIPTION OF SYMBOLS 1 Alignment mark 2 Scribe area 3 Chip area 4 Element area 5 Through electrode 6 Insulating ring 7 Element isolation area (STI)
7a Trench for element isolation region 8 Element 8a Wiring layer 8b Contact plug 9, 12 Solder film 10, 11 Seed film 13, 19 Copper bump 14, 15 Wiring layers 14a-14d, 15a-15d Wiring 14e-14g, 15e-15g Contact plug 16 Interlayer insulating film 17 Semiconductor substrate 17a First main surface 17b Second main surface 20 Photoresist film 25 Alignment mark trench 25a Trench termination portion 25b Alignment mark trench width direction 26 Insulating film 26a Nitride Silicon film 26b TEOS-NSG film 29 First pattern 30 Active region 32 Trench 33 for insulating ring Surface electrode 33a First opening 34 Back electrode 34a Second opening 36 Protective film 36a Silicon oxynitride film (SiON)
36b Polyimide film (passivation film)
38 Semiconductor substrate thickness direction 40 Semiconductor chip 41 Underfill 42 Package substrate 43 Mold resin 45 Ineffective shot region 46 Effective shot region 50 Trench extension direction 56 Seam, void 57 Crack

Claims (17)

Forming an annular first groove and a second groove having a terminal portion on the first main surface of the substrate when facing the first main surface; and
Forming an insulating film so as to fill the first and second grooves;
After the step of forming the insulating film, forming a photoresist film on the first main surface of the substrate;
Transferring the first pattern, which is aligned on the basis of the position of the second groove embedded in the insulating film on the substrate, to the photoresist film;
Forming a through electrode penetrating through the substrate in a thickness direction on the substrate located inside the annular first groove embedded in the insulating film;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein the second groove has an annular shape, a rectangular shape, or a square shape as viewed from the first main surface. After the step of forming the insulating film and before the step of forming the through electrode,
The substrate is ground from the second main surface side facing the first main surface of the substrate in the thickness direction until the bottoms of the first and second grooves embedded in the insulating film are exposed. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of reducing the thickness of the substrate.   The step of forming the insulating film is characterized in that the insulating film is formed so as to fill the first groove and the second groove by a chemical vapor deposition method using TEOS as a raw material. Item 4. The method for manufacturing a semiconductor device according to any one of Items 1 to 3. The step of forming the insulating film includes
Forming a silicon nitride film on the inner wall surfaces of the first groove and the second groove;
Forming an insulating film so as to embed the first groove and the second groove by chemical vapor deposition using TEOS as a raw material;
The method for manufacturing a semiconductor device according to claim 1, wherein: After the step of forming the insulating film,
Forming a mask pattern so that a mask is positioned on the insulating film on the first groove and the second groove;
Removing a part of the insulating film by etching using the mask pattern so that the first main surface of the substrate is not exposed;
Flattening the insulating film after removing the mask pattern;
The method of manufacturing a semiconductor device according to claim 1, further comprising:   7. The method according to claim 1, further comprising a step of forming an element isolation region on the first main surface of the substrate using the first pattern transferred to the photoresist film. The manufacturing method of the semiconductor device as described in 2. Cutting the substrate along the cutting region to further singulate the substrate;
The semiconductor device according to claim 1, wherein in the step of forming the first and second grooves, the second groove is formed in the cutting region of the substrate. Production method. A substrate,
An insulating ring that penetrates the substrate in the thickness direction and has an annular shape when viewed from the first main surface of the substrate;
An alignment mark that penetrates the substrate in the thickness direction and has a shape that does not have a terminal portion when viewed from the first main surface of the substrate.
In the substrate located inside the annular insulating ring, a through electrode provided to penetrate the substrate in the thickness direction;
A semiconductor wafer comprising:   The semiconductor wafer according to claim 9, wherein the alignment mark has an annular shape, a rectangular shape, or a square shape when viewed from the first main surface.   The semiconductor wafer according to claim 9, wherein the insulating ring and the alignment mark are made of a material including an NSG film (None-doped Silicate Glass).   The semiconductor wafer according to claim 9, further comprising an element isolation region on the first main surface of the substrate.   The semiconductor wafer according to claim 9, wherein the alignment mark is formed in a cutting area, a chip area, or an ineffective shot area of the substrate. A substrate,
An insulating ring that penetrates the chip region of the substrate in the thickness direction and has an annular shape when viewed from the first main surface of the substrate;
An alignment mark that penetrates the chip region of the substrate in the thickness direction and has a shape that does not have a terminal portion when viewed from the first main surface of the substrate.
In the chip region located inside the annular insulating ring, a through electrode provided to penetrate the substrate in the thickness direction;
A semiconductor device comprising:   The semiconductor device according to claim 14, wherein the alignment mark has an annular shape, a rectangular shape, or a square shape as viewed from the first main surface.   The semiconductor device according to claim 14, wherein the insulating ring and the alignment mark are made of a material including an NSG film (None-doped Silicate Glass).   The semiconductor device according to claim 14, further comprising an element isolation region on the first main surface of the substrate.