JP2013110255A - Semiconductor wafer, semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce directional dependence of a stress concentrated on an alignment mark to minimize occurrence of cracks.SOLUTION: A semiconductor device manufacturing method comprises: forming an annular first groove and a dot-shaped second grove on a first principal surface of a substrate; forming an insulation film so as to fill the first and second grooves; forming a photoresist film on the first principal surface of the substrate; transferring a first pattern aligned with reference to a position of the second groove filled with the insulation film on the substrate to the photoresist film; and forming a through electrode penetrating the substrate in a thickness direction, in the substrate at a position inside the annular first groove filled with the insulation film.

Description

  The present invention relates to a semiconductor wafer, a semiconductor device, and a manufacturing method thereof.

  In a semiconductor device in which a plurality of semiconductor chips are stacked to realize a high function, upper and lower semiconductors are formed by through electrodes (Through Silicon Via, hereinafter referred to as TSV) provided so as to penetrate the semiconductor chips. A structure for electrically connecting the chips is used. In such a semiconductor chip, an insulating ring structure in which the periphery of the TSV is surrounded by an insulator may be used for the purpose of insulating and separating the TSV and the element region and reducing the capacity between neighboring TSVs. .

  Patent Document 1 (Japanese Unexamined Patent Application Publication No. 2009-1111061) discloses a method for manufacturing a semiconductor device having a through electrode provided with an insulating ring. This discloses a process in which an insulating ring is first formed (via first), element formation to wiring formation, and finally TSV is formed (via last). More specifically, first, a ring-shaped trench is dug in the depth direction from the element forming surface side of the silicon substrate, and the trench is filled with an insulating film to form an insulating ring. Thereafter, after the element formation on the substrate surface, the wiring layer formation, the surface electrode formation step, and the like, the silicon substrate is ground from the back side to be thinned. At this time, by grinding the back surface until the bottom of the insulating ring is exposed from the back surface of the substrate, the insulating ring penetrates the silicon substrate from the front surface to the back surface. And TSV is formed by forming a back surface electrode from the back surface side so that a silicon substrate may be penetrated inside an insulating ring.

JP 2009-1111061 A

  Unlike the above method, if the step of forming the element isolation region (field) is the first step performed on the substrate without forming the insulating ring or the like by via first, the position of the element isolation region on the substrate is determined. There is no need to adjust. That is, since no other member is formed on the substrate when the element isolation region is formed, it is not necessary to align the element isolation region with respect to these members.

  On the other hand, as described above, when forming an element isolation region on a substrate on which an insulating ring has already been formed by via first, the element isolation region is formed by adjusting (positioning) the position on the substrate. There is a need. That is, after the formation of the insulating ring, it is necessary to form an alignment mark used for photolithography before patterning the element isolation region on the substrate.

  However, in the conventional method, since the alignment mark trench is deep and the width thereof is narrow, when an insulating film is embedded in the trench, a seam or a void may occur inside. Since the trench for the alignment mark is formed in a line and space shape, the area of the inner wall side surface in the long side direction and the inner wall side surface in the short side direction of the trench are greatly different in plan view. For this reason, stress having a direction dependency in which the stress in a specific direction is increased is concentrated at a defective embedding portion such as a seam or a void. Therefore, cracks may occur in the substrate starting from seams and voids. This crack sometimes reaches the element region, and in this case, the manufacturing yield is reduced.

One embodiment is:
A step of forming an annular first groove and a dot-shaped second groove on the first main surface of the substrate when viewed opposite to the first main surface;
Forming an insulating film so as to fill the first and second grooves;
After the step of forming the insulating film, forming a photoresist film on the first main surface of the substrate;
Transferring the first pattern, which is aligned on the basis of the position of the second groove embedded in the insulating film on the substrate, to the photoresist film;
Forming a through electrode penetrating through the substrate in a thickness direction on the substrate located inside the annular first groove embedded in the insulating film;
The present invention relates to a method for manufacturing a semiconductor device.

Other embodiments are:
A substrate,
An insulating ring that penetrates the substrate in the thickness direction and is annular when viewed opposite the first main surface of the substrate;
An alignment mark that penetrates the substrate in the thickness direction and has a dot shape when viewed facing the first main surface of the substrate;
In the substrate located inside the annular insulating ring, a through electrode provided to penetrate the substrate in the thickness direction;
The present invention relates to a semiconductor wafer.

Other embodiments are:
A substrate,
An insulating ring that penetrates the chip region of the substrate in the thickness direction and is annular when viewed opposite the first main surface of the substrate;
An alignment mark that penetrates the chip region of the substrate in the thickness direction and has a dot shape when viewed to face the first main surface of the substrate;
In the substrate located inside the annular insulating ring, a through electrode provided to penetrate the substrate in the thickness direction;
The present invention relates to a semiconductor device.

  By forming the dot-shaped alignment mark, the direction dependency of the stress concentrated on the alignment mark can be reduced. As a result, cracks are less likely to occur.

It is a figure showing the method which this inventor examined. It is a figure showing the method which this inventor examined. It is a figure showing the method which this inventor examined. It is a figure showing the method which this inventor examined. It is a figure showing the semiconductor device of 1st Example. 3 is a flowchart illustrating a method for manufacturing the semiconductor device according to the first embodiment. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the 1st modification of 1st Example.

  Japanese Patent Laid-Open No. 2005-217071 discloses a method of simultaneously forming an alignment mark that serves as an alignment reference during chip stacking by a process of forming a TSV body. More specifically, when a plurality of chips cut out from a wafer are stacked on each other, a conductive material penetrating through the same substrate as TSV is used as an alignment mark for causing the bonding apparatus to recognize the position of the chip so as not to cause misalignment. This is a technology that uses materials to form simultaneously with the TSV forming process.

  Therefore, as an application example of the above technique, the present inventor provides an alignment mark that serves as a reference for alignment in the step of transferring the STI (field) pattern (photolithographic step), which is the first step of the element forming step. The method of forming simultaneously with the insulating ring was examined in advance. Normally, when an STI is first formed on a wafer on which no component of the semiconductor device is formed, there is no need to align with any element, and therefore no alignment mark is necessary in the STI formation process. Further, in the step after the STI formation step, alignment may be performed with reference to the alignment mark formed simultaneously in the STI formation step.

  On the other hand, the structure which is the subject of the present application enters an element formation step after first forming an insulating ring surrounding the TSV (via first). Therefore, an alignment mark (field alignment mark) for aligning the STI with respect to the insulating ring is required, and the above-described technique has been studied as a method for forming the alignment mark. The field alignment mark investigated by the present inventor has a shape in which insulating grooves are arranged in a line and space (L / S) shape so that it can be recognized in the lithography process.

  Hereinafter, a semiconductor device and a manufacturing method thereof studied by the present inventors will be described with reference to FIGS. As shown in FIG. 1A, this semiconductor device has a chip region 3 surrounded by a scribe region 2 on a semiconductor substrate 17. The chip region 3 is provided with an element region 4 and a through electrode 5, and the scribe region 2 is provided with an alignment mark 1. 1B is a cross-sectional view in the A′-A ′ direction near the through electrode 5 in FIG. 1A, and FIG. 1C is a cross-sectional view in the B′-B ′ direction of a part of the alignment mark 1 in FIG. 1A. 1D and 1E respectively show a top view and a cross-sectional view of a part of the alignment mark 1 when viewed from the first main surface 17a of the semiconductor substrate 17. FIG.

  As shown in FIG. 1B, the through electrode 5 includes a front electrode 33, a wiring layer 14, and a back electrode 34. A part of the wiring layer 14 and the back electrode 34 penetrates the interlayer insulating film 16. In the element region 4, an annular insulating ring 6 is provided so as to surround the through electrode 5, and the through electrode 5 is insulated and separated from other elements 8 such as a transistor. The element 8 is connected to the wiring 8a through the contact plug 8b. As shown in FIG. 1C, the scribe region 2 is provided with an alignment mark 1 and a wiring layer 15. The lengths of the insulating ring 6 and the alignment mark 1 in the thickness direction 38 of the semiconductor substrate 17 are the same. The element region 4 and the scribe region 2 are provided with an element isolation region (STI) 7. A protective film 36 made of a silicon oxynitride film 36 a and a polyimide film 36 b is formed on the interlayer insulating film 16 in the element region 4 and the scribe region 2.

  2 to 4 show the steps of forming the insulating ring 6 and the alignment mark 1 of the semiconductor device of FIG. 1, and other parts are not shown for the sake of simplicity. 2 and 3, A is a process for forming the insulating ring 6 in FIG. 1B, B is a process for forming the alignment mark 1 in FIG. 1C, and C is an enlarged view of a portion P surrounded by a dotted line in FIG. , D shows an enlarged view of a portion Q surrounded by a dotted line in FIG. FIG. 3E is a top view of the entire alignment mark 1 on the first main surface 17a, and FIGS. 2E and 3F are views of the alignment mark trench 25 or a part of the alignment mark 1 from the direction facing the first main surface 17a. A top view is shown. 2F and 3G represent enlarged cross-sectional views of portions of FIGS. 2B and 3B, respectively. FIG. 4 is a schematic perspective view showing a state in which stress concentrates on the seam 56a and the crack 56b in FIG. 3, and only a part of the structure is shown.

  As shown in FIG. 2, after a photoresist film 20 is formed on the first main surface 17a of the silicon semiconductor substrate 17, a pattern is formed on the photoresist film 20 by a lithography technique. Subsequently, dry etching of the semiconductor substrate 17 is performed using the photoresist film 20 as a mask. Thus, an annular trench (insulating ring trench) 32 and an alignment mark trench 25 are formed simultaneously. The trench 25 for the alignment mark is a line and space (L / S) in which a plurality of trenches 25 are arranged at a constant pitch in the width direction 25b of the trench 25 when viewed from the first main surface 17a. It is formed into a shape.

As shown in FIG. 3, after removing the photoresist film 20, both the trenches 25 and 32 are simultaneously filled with the insulating film 26. Here, as the insulating film 26, an NSG (None-Doped Silicate Glass) film formed by a CVD method (chemical vapor deposition method) using TEOS (Tetra Ethoxy Silane; Si (OC ₂ H ₅ ) ₄ ) as a raw material is used. Use. Thereby, the insulating ring 6 and the alignment mark 1 are formed.

  Here, since the alignment mark trench 25 formed in the same manner as the insulating ring trench 32 is deep (˜40 μm) and wide (˜2 μm), the embedding property is low, and the seam 56 a Void 56b may be generated. In particular, in the alignment mark 1 in which the plurality of trenches 25 are arranged in an L / S shape, when viewed from the direction facing the first main surface 17a, the inner wall surface of the trench 25 is parallel to the trench extending direction 25a. The area of the inner wall side surface 25c is much larger than the area of the inner wall side surface 25d parallel to the width direction 25b of the trench. For this reason, the source gas supplied at the time of forming the insulating film 26 is consumed in a larger amount in the vicinity of the inner wall side surface 25c than in the vicinity of the inner wall side surface 25d, and the source gas is relatively short in the vicinity of the inner wall side surface 25c. Therefore, as shown in FIGS. 3F and 3G, a seam 56a and a void 56b having large steps are formed near the center in the width direction 25b of the trench 25, and the seam 56a and the void 56b are formed in the extending direction 25a of the trench. Extend to. As shown in FIGS. 1D and 1E, the seam 56a and the void 56b remain even after the insulating film 26 on the first main surface 17a is removed.

  When such a seam 56a and void 56b are formed, stress is concentrated on the alignment mark 1 toward the seam 56a and void 56b, as shown in FIGS. The length of the inner wall side surface 25c in the trench extending direction 25a is different from the length of the inner wall side surface 25d in the trench width direction 25b. Further, as shown in FIG. 4, a stress difference is generated between the thin film portion 26a and the thick film portion 26b of the insulating film. For this reason, this stress has the direction dependence which becomes large in a specific direction. As a result, it has been proved by the inventor that the crack 57 is generated in the semiconductor substrate 17 due to the direction dependency of the stress concentrated on the seam 56a and the void 56b. Such cracks 57 may reach the element region 4 and cause a decrease in manufacturing yield. Thus, it was found that there is room for improvement in the manufacturing method of this study example.

  Therefore, the present inventor examined a method for preventing the occurrence of the crack 57. As a result, if a dot-shaped trench is formed as the alignment mark trench 25, the direction dependency of stress concentrated in the seam 56a and void 56b generated in the alignment mark is reduced, and the crack 57 is less likely to occur. I discovered that. That is, in the present invention, as illustrated in FIG. 5, when viewed from the direction facing the first main surface 17a of the semiconductor substrate 17 (in plan view), the dot-shaped alignment mark 1 is formed. Unlike the line-and-space shape, the alignment mark 1 has a shape in which the length of each side of the trench 25 when viewed in plan is approximately the same, and the trench 25 does not extend in a specific direction. For this reason, when the insulating film 26 is formed in the trench 25, the source gas is consumed to the same extent in the vicinity of the side surfaces of the inner walls of the trench 25. Even when the seam 56a is generated, the step shape is reduced. Can be small. In addition, the direction dependency of stress concentrated on the seam 56a and the void 56b can be reduced. As a result, the generation of cracks can be reduced and the manufacturing yield can be improved.

  The present invention will be described below with reference to the drawings. In addition, these Examples are specific examples shown for a deeper understanding of the present invention, and the present invention is not limited to these specific examples.

(First embodiment)
FIG. 5 is a diagram illustrating a semiconductor device manufactured by the manufacturing method of the first embodiment. As shown in FIG. 5A, this semiconductor device has a chip region 3 surrounded by a scribe region (cutting region) 2 on a semiconductor substrate 17. The chip region 3 is provided with an element region 4 and a through electrode 5. As will be described later, a plurality of semiconductor chips can be electrically connected through the through electrode 5. An alignment mark 1 is provided in the scribe region 2.

  5B is a sectional view in the A′-A ′ direction in the vicinity of the through electrode 5 in FIG. 5A, FIG. 5C is a sectional view in the B′-B ′ direction of a part of the alignment mark 1 in FIG. 5A, and FIG. FIG. 5E is a schematic sectional view of a part of the alignment mark 1 in FIG. 5C. In FIG. 5, the seam 56a and the void 56b are shown only in FIG. 5E, and are omitted in other drawings. Similarly, in FIGS. 8E and 10E and subsequent drawings, the seam 56a and the void 56b are omitted.

  As shown in FIG. 5B, the through electrode 5 includes a front surface electrode 33, a wiring layer 14, and a back surface electrode 34. A part of the wiring layer 14 and the back electrode 34 penetrates the interlayer insulating film 16. The tip region 3 is provided with an annular insulating ring 6 when viewed from the first main surface 17a. The insulating ring 6 extends from the first main surface 17a in the thickness direction 38 of the semiconductor substrate 17 and extends through the semiconductor substrate 17 to the second main surface 17b. The insulating ring 6 is provided so as to surround the through electrode 5 and insulates the through electrode 5 from other elements 8. The element 8 is connected to the wiring 8a through the contact plug 8b.

  As shown in FIGS. 5C and 5D, the scribe region 2 is provided with an alignment mark 1 and a wiring layer 15. The alignment mark 1 is formed in a dot shape when viewed facing the first main surface 17a. That is, each trench 25 constituting the alignment mark 1 has a substantially square shape in a plan view, and the plurality of trenches 25 are arranged at a constant pitch in the first direction 50a and the second direction 50b perpendicular to each other. It is formed in an array. The alignment mark 1 has the same depth as the insulating ring 6 in the thickness direction 38 of the semiconductor substrate 17. The element region 4 and the scribe region 2 are provided with an element isolation region (STI) 7. A protective film 36 made of a silicon oxynitride film 36 a and a polyimide film 36 b is formed on the interlayer insulating film 16 in the element region 4 and the scribe region 2.

  6 to 16 are views for explaining a method of manufacturing the semiconductor device according to this embodiment. Hereinafter, the manufacturing method of the present embodiment will be described with reference to these drawings. FIG. 6 is a flowchart showing the manufacturing method of this embodiment. 7 to 15, A is a cross-sectional view corresponding to FIG. 5B, B is a cross-sectional view corresponding to FIG. 5C, and C is the entire alignment mark 1 or a structure corresponding thereto facing the first main surface 17 a. The top view seen from the direction to do is represented. 8D and 10D are schematic top views in which parts of FIGS. 8C and 10C are enlarged, and FIGS. 8E and 10E are schematic cross-sectional views in which parts of FIGS. 8B and 10B are enlarged. 8C and 8D, the trench 25 is shown as a perspective view in order to clarify the positional relationship. 16A is a cross-sectional view showing a state in which a plurality of semiconductor chips 40 are stacked, and FIG. 16B is an enlarged view of a portion 51 surrounded by a dotted line in FIG. 16A.

  As shown in FIG. 7, a photoresist film 20 is formed on the first main surface 17 a of the silicon semiconductor substrate 17. Patterns for insulating rings and alignment marks are formed in the photoresist film 20 by lithography. The semiconductor substrate 17 is dry etched using the pattern of the photoresist film 20. Thereby, a trench (first groove) 32 for an insulating ring and a trench (second groove) 25 for an alignment mark are formed (S11 in FIG. 6). When the alignment mark trench 25 is viewed from the direction facing the first main surface 17a, a plurality of substantially square trenches are spaced apart in a first direction 50a and a second direction 50b perpendicular to each other. It becomes the dot shape arranged by. The lengths of the trenches 25 in the first direction 50a and the second direction 50b are substantially the same, and are substantially square in plan view. The length of each trench 25 in the first direction 50a and the second direction 50b is preferably 0.35 to 2.0 μm.

  In the present embodiment, the insulating ring trench (first groove) 32 is annular when viewed from the first main surface 17a, and has a depth of 40 μm, a width of 2 μm, and a ring diameter of 20 μm. Although the dimension of the trench 32 for insulation rings is not specifically limited, For example, it can be set as 30-50 micrometers in depth, 1-3 micrometers in width, and 15-30 micrometers in ring diameter.

As shown in FIG. 8, the photoresist film 20 is removed. An NSG (None-Doped Silicate Glass) film 26 is formed on the semiconductor substrate 17 by a CVD method using TEOS (Tetra EthOxy Silane; Si (OC ₂ H ₅ ) ₄ ) as a raw material (hereinafter, this film 26 is referred to as TEOS). -Called NSG film). The film thickness of the TEOS-NSG film 26 formed by such a deposition method (film thickness on the semiconductor substrate 17) is at least 1/2 of the width of the trenches 25 and 32 from the viewpoint of completely embedding the trenches 25 and 32. Is the film thickness. Further, the TEOS-NSG film 26 is used because it can be formed conformally with good coverage in order to avoid generation of voids as much as possible when embedding the high aspect ratio trenches 25 and 32. is there. In the case where the same effect is obtained, another material may be used for the insulating film 26. For example, as the insulating film 26, (a) a silicon nitride film and a TEOS-NSG film, (b) a silicon oxide film and a TEOS-NSG film, or (c) a silicon oxide film, a silicon nitride film, and a TEOS-NSG film are used. can do. In these cases, in the trenches 25 and 32, when shown in order from the film on the inner wall surface side of the trenches 25 and 32, the SiN film / TEOS-NSG film, the SiO ₂ film / TEOS-NSG film, or the SiO ₂ film, respectively. / SiN film / TEOS-NSG film.

  As shown in FIG. 9, the film thickness of the TEOS-NSG film 26 is reduced by wet etching in order to reduce the CMP load when removing the TEOS-NSG film 26 on the semiconductor substrate 17 in a subsequent polishing step. At this time, a seam may occur in the TEOS-NSG film 26 formed in the trench 25 for alignment marks. In this case, if the TEOS-NSG film 26 is wet-etched as it is, the seam in the TEOS-NSG film 26 is deepened. Therefore, wet etching is performed in a state where the TEOS-NSG film 26 on the alignment mark trench 25 is protected by a protective film (mask pattern) such as the photoresist film 20.

  As shown in FIG. 10, after removing the photoresist film 20, heat treatment is performed at 950 ° C. for 60 minutes, so that the TEOS-NSG film 26 is degassed. Next, the TEOS-NSG film 26 on the first main surface 17a of the semiconductor substrate 17 is removed by a chemical mechanical polishing method (CMP method), thereby completing the insulating ring 6 and the alignment mark 1 (FIG. 6). S12).

  As discussed with reference to FIGS. 2 to 4, when the insulating film 26 is embedded in the alignment mark trench 25, a seam 56 a and a void 56 b can be generated therein. In particular, when the alignment mark trench 25 in which a plurality of trenches are arranged in a line-and-space manner is formed, a seam 56a is formed near the center in the trench width direction 25b. Since the areas of the inner wall side surfaces 25c and 25d of the trench 25 are greatly different, the source gas on the inner wall side surface 25c is relatively reduced to form a seam 56a having a large step, and the seam 56a and the void 56b have a specific direction. Stress with direction dependence that increases the stress of is concentrated. As a result, when the formation of the TEOS-NSG film 26 in FIG. 8, the wet etching in FIG. 9, the CMP method in FIG. 10 or the like is applied to the above-examined structure, a crack 57 is generated in the semiconductor substrate 17. When such a crack 57 reaches the element region 4, it causes a decrease in manufacturing yield.

  On the other hand, in the present embodiment, the dot-shaped alignment mark trench 25 is formed in a plan view. For this reason, the length and area of the inner wall side surface of each trench 25 when viewed in plan are the same, and even when the seam 56a is generated, the seam 56a has a small step as shown in FIGS. 8E and 10E. Can do. Further, the direction dependency of stress concentrated on the seam 56a and the void 56b shown in FIGS. 8E and 10E can be reduced. For this reason, when the TEOS-NSG film 26 shown in FIG. 8, the wet etching shown in FIG. 9, the CMP method shown in FIG. As a result, the manufacturing yield can be improved.

  As shown in FIG. 11, a photoresist film 20 is formed on the semiconductor substrate 17. The first pattern 29 is formed by transferring the field pattern for STI onto the photoresist film 20 by lithography. At this time, in this embodiment, the alignment mark 1 formed as described above can be used as an alignment mark for the field pattern for STI. That is, by transferring the field pattern aligned with the position of the alignment mark 1 on the semiconductor substrate 17 as a reference to the photoresist film 20, misalignment of photolithography can be reduced.

  The semiconductor substrate 17 is etched using the first pattern 29 of the photoresist film 20. As a result, as shown in FIG. 12, a trench 7a for STI is formed (S21 in FIG. 6). Thereafter, the photoresist film 20 is removed. After an insulating film such as a silicon oxide film or a silicon nitride film is embedded on the semiconductor substrate 17, a CMP process is performed on the insulating film. As a result, an STI (element isolation region) 7 is formed (S22 in FIG. 6).

  As shown in FIG. 13, the element 8 such as a transistor is formed in the active region 30 of the semiconductor substrate 17 (S23 in FIG. 6). An interlayer insulating film 16 is formed on the semiconductor substrate 17 in several stages. In the process of forming the interlayer insulating film 16, the wiring layer 14 and the alignment mark above the region in the semiconductor substrate 17 surrounded by the contact plug 8 b, the wiring 8 a, and the insulating ring 6 that reach the impurity diffusion layer of the transistor 8. A wiring layer 15 is formed above 1. The wiring layer 14 functions as a pad for connecting to the front surface electrode 33 and the back surface electrode 34 to be formed in a later step. The wiring layer 14 includes a plurality of wirings 14a to 14d made of aluminum (Al), copper (Cu), or the like, and a plurality of contact plugs 14e to 14g made of a metal film such as tungsten for connecting the plurality of wirings. The wiring layer 15 includes a plurality of wirings 15a to 15d and a plurality of contact plugs 15e to 15g that connect the plurality of wirings.

  As shown in FIG. 14, a protective film 36 made of a silicon oxynitride film (SiON) 36 a and a polyimide film (passivation film) 36 b is formed on the interlayer insulating film 16 so as to cover the wiring layer 14. Next, a first opening 33a is formed in the protective film 36 so that the upper surface of the wiring layer 14 is exposed. The seed film 11 is formed on the protective film 36 including the first opening 33a by sputtering. After forming a photoresist film (not shown) on the protective film 36, patterning is performed to expose the seed film 11 provided in the first opening 33a. A copper bump 13 and a solder film 12 are sequentially formed on the exposed seed film 11 by electroplating. After removing the photoresist film on the protective film 36, the exposed seed film 11 is removed. A surface electrode 33 is composed of the seed film 11, the copper bump 13, and the solder film 12 (S3 in FIG. 6).

  As shown in FIG. 15, a support substrate (not shown) is provided on the side of the semiconductor substrate 17 on which the surface electrode 33 is provided via an adhesive layer (not shown). Thereafter, the second main surface 17b facing the first main surface 17a of the semiconductor substrate 17 in the thickness direction is thinned to a thickness of, for example, 775 μm to 40 to 50 μm (S4 in FIG. 6). By this grinding process, the insulating ring 6 and the bottom of the alignment mark 1 formed in advance are exposed on the second main surface 17 b side of the semiconductor substrate 17. Anisotropic dry etching is performed on the semiconductor substrate 17 located inside the annular insulating ring 6 so that the wiring layer 14 is exposed from the second main surface 17b side of the semiconductor substrate 17. At this time, a second opening 34 a that penetrates the semiconductor substrate 17 and extends in a part of the interlayer insulating film 16 is formed. Next, a seed film 10 is formed by laminating a titanium (Ti) film and a copper (Cu) film on the entire surface of the second main surface 17b of the semiconductor substrate 17 by sputtering. A photoresist pattern (not shown) having a third opening at the same position as the second opening 34 a is formed on the second main surface 17 b of the semiconductor substrate 17. A copper bump 19 and a solder film 9 such as a SnAg film are sequentially formed in the third opening by electroplating. A back electrode 34 is formed by the seed film 10, the copper bump 19, and the solder film 9. Next, after removing the photoresist pattern, the exposed portion of the seed film 10 is removed (S5 in FIG. 6).

  Thereafter, the surface of the solder film 9 is made convex by reflow. The adhesive layer and the support substrate are removed. As described above, the semiconductor device shown in FIG. 5 is obtained. In this semiconductor device, a through electrode 5 is provided in each chip region 3 partitioned by the scribe region 2 so as to penetrate the semiconductor substrate 17. The through electrode 5 has bumps (surface electrode 33 and back electrode 34) for connection at the upper and lower ends, and is arranged vertically via the through electrode 5 when a plurality of semiconductor chips are stacked as will be described later. The connected semiconductor chips are electrically connected. The through electrode 5 includes a through plug (surface electrode 33, back electrode 34) that penetrates the semiconductor substrate 17 and a wiring layer 14 that penetrates the interlayer insulating film 16 on the semiconductor substrate 17. A portion of the through electrode 5 that penetrates the semiconductor substrate 17 is surrounded by an annular insulating ring 6 and is insulated and separated from other elements 8 and the like.

  Next, the semiconductor substrate 17 is scribed along the scribe region (cutting region) 2 (S6 in FIG. 6). Thereby, the semiconductor substrate 17 is separated into individual pieces to form a semiconductor chip.

  As shown in FIG. 16, the plurality of semiconductor chips 40 are mounted such that the front surface electrode 33 and the back surface electrode 34 of different semiconductor chips 40 are in contact with each other. The solder films 9 and 12 of the front surface electrode 33 and the back surface electrode 34 of each semiconductor chip 40 are joined by reflow. After filling the underfill 41 between the semiconductor chips 40, the plurality of semiconductor chips 40 are mounted on the package substrate 42. Thereafter, by molding with the mold resin 43, the semiconductor device of this example is completed (S7 in FIG. 6).

  Examples of the semiconductor device of this embodiment include storage devices such as DRAM, SRAM, and flash memory, and arithmetic processing devices such as MPU and DSP.

  As described above, in this embodiment, the seam 56a and the void 56b may be generated in the TEOS-NSG film 26 embedded in the alignment mark trench 25 in the step of FIG. At this time, as discussed in FIGS. 2 to 4, when the conventional line-and-space alignment mark 1 is formed, the areas of the inner wall side surfaces 25c and 25d of the alignment mark trench 25 are greatly different. For this reason, the step of the seam 56a becomes large, and the stress concentrated on the seam 56a and the void 56b has a direction dependency in which the stress in a specific direction becomes strong. As a result, when the TEOS-NSG film 26 shown in FIG. 8, the wet etching shown in FIG. 9, the CMP method shown in FIG. 10, or the like is performed, cracks 57 may occur in the semiconductor substrate 17 starting from the void 56b. .

  On the other hand, in the present embodiment, the dot-shaped alignment mark 1 is formed, and the trench 25 constituting each dot has an inner wall surface having substantially the same area in plan view. For this reason, when the TEOS-NSG film 26 is formed, the amount of the source gas consumed on the side surfaces of the inner walls constituting the trench 25 becomes substantially the same, and the step of the seam 56a can be reduced as shown in FIG. 5E and the like. it can. In addition, the direction dependency of stress concentrated on the seam 56a and the void 56b can be reduced. As a result, cracks are less likely to occur and the manufacturing yield can be improved.

  In this embodiment, the alignment mark 1 has a dot shape in which a plurality of dots are arranged in the first direction 50a and the second direction 50b perpendicular to each other. However, the first direction 50a and the second direction 50b may not be perpendicular to each other. The first direction 50a and the second direction 50b can be set to desired directions as long as they are not the same direction but can arrange a plurality of dots in an array. Further, the number of dots arranged in the first direction 50a and the second direction 50b is not limited to the example of the present embodiment, and can be appropriately set to a desired number.

  In the present embodiment, each dot constituting the alignment mark 1 is substantially square in plan view. However, the shape of each dot in plan view is not limited to a substantially square shape. Are different circles), polygons (for example, rectangles, regular n-gons where n is an even number), and shapes including curves. Moreover, when the planar view shape of each dot is a polygon, although the length of each side which comprises a polygon may differ, it is preferable that the length of each side is the same regular polygon. For example, when the plan view shape is a square, the length of each side is preferably 0.35 to 2.0 μm.

  In this embodiment, the alignment mark 1 is used as a field alignment mark during the STI 7 alignment. The alignment mark 1 can be used as a field alignment mark for alignment of other structures in addition to the alignment of the STI 7. For example, in the step of FIG. 15, it can be used as a field alignment mark for alignment when forming the second opening 34a.

  In this embodiment, the TEOS-NSG film 26 is exemplified as the insulating film for burying the insulating ring trench 32 and the alignment mark trench 25. However, the material for burying the trenches 25 and 32 is not limited thereto. . When a deep and narrow groove like the alignment mark 1 is embedded with an insulating film, the seam 56a and the void 56b are likely to be generated due to a poor embedding even if the trench is not a TEOS-NSG film. Therefore, the present invention is not limited to the TEOS-NSG film 26, but is equally effective when applied to a process of filling the trenches 25 and 32 with other insulating films. On the other hand, when the TEOS-NSG film 26 is used, heat treatment for baking (Degas) is required. The TEOS-NSG film 26 may be contracted by this heat treatment, and the seam 56a may be enlarged. Therefore, it can be said that the present invention is more effective for the step of filling the trench 25 with the TEOS-NSG film 26.

(First modification)
In the first embodiment, the alignment mark 1 is formed in the scribe region 2 of the semiconductor substrate 17, but this modification is different in that the alignment mark 1 is formed in a region other than the scribe region 2 of the semiconductor substrate 17.

  FIG. 17A is a plan view illustrating an example in which the alignment mark 1 is provided in the ineffective shot region 45 of the semiconductor substrate 17. The semiconductor substrate 17 includes a plurality of effective shot regions (regions indicated by hatching in FIG. 17A) 46 formed of semiconductor chips on which a semiconductor device is formed by performing lithography exposure or the like in a later step, and the semiconductor device. There is a non-effective shot area (a white area in FIG. 17A) 45 that is not formed. The non-effective shot region 45 refers to a region where a semiconductor chip where a normal semiconductor device pattern cannot be formed is located. That is, since the semiconductor substrate 17 is formed in a circular shape and the semiconductor chip is formed in a rectangular shape, a part of the semiconductor chip applied to the terminal portion of the semiconductor substrate 17 protrudes from the semiconductor substrate 17 and cannot be patterned. Become. Since the size of the semiconductor chip is determined when the design of the semiconductor device is completed, the position of the ineffective shot region 45 on the semiconductor substrate 17 can be grasped in advance. If pattern formation is repeated at the terminal portion of the semiconductor substrate 17, foreign matter is generated, and thus no pattern is formed in the ineffective shot region 45. Therefore, the ineffective shot region 45 is a useless region that does not contribute to the manufacture of the semiconductor device. In this modification, the alignment mark 1 is formed by using the non-effective shot area 45 which becomes the useless area, so that it is not necessary to secure an area for the alignment mark 1 in the effective shot area 46, and the fine mark is fine. It can be set as the semiconductor device corresponding to conversion. Note that the number and positions of the non-effective shot regions 45 forming the alignment mark 1 are not limited to the example of FIG. 17A, and the alignment marks 1 can be appropriately formed in the desired number and positions of the non-effective shot regions 45. .

  FIG. 17B is a view showing another example, showing an example in which the alignment mark 1 is formed in the chip region 3 of the semiconductor substrate 17, and corresponding to FIG. 5A of the first embodiment. As shown in FIG. 17B, the alignment mark 1 may be formed in the chip region 3. Further, the formation position and number of alignment marks 1 in the chip region 3 are not limited to the example of FIG. 17B, and a desired number of alignment marks 1 are formed in desired positions in the chip region 3. Can do.

DESCRIPTION OF SYMBOLS 1 Alignment mark 2 Scribe area 3 Chip area 4 Element area 5 Through electrode 6 Insulating ring 7 Element isolation area (STI)
7a Trench for element isolation region 8 Element 8a Wiring layer 8b Contact plug 9, 12 Solder film 10, 11 Seed film 13, 19 Copper bump 14, 15 Wiring layer 14a, 14b, 14c, 14d, 15a, 15b, 15c, 15d Wiring 14e, 14f, 14g, 15e, 15f, 15g Contact plug 16 Interlayer insulating film 17 Semiconductor substrate 17a First main surface 17b Second main surface 20 Photoresist film 25 Alignment mark trench 25a Trench extension direction 25b Trench width direction 25c, 25d Inner wall side surface 26 Insulating film 26a Insulating film thin film portion 26b Insulating film thick film portion 29 First pattern 30 Active region 32 Insulating ring trench 33 Surface electrode 33a First opening 34 Back electrode 34a Second opening 36 Protective film 36a Silicon oxynitride film (SiON)
36b Polyimide film (passivation film)
38 Semiconductor substrate thickness direction 40 Semiconductor chip 41 Underfill 42 Package substrate 43 Mold resin 45 Ineffective shot region 46 Effective shot region 50a First direction 50b Second direction 56a Seam 56b Void 57 Crack

Claims (16)

A step of forming an annular first groove and a dot-shaped second groove on the first main surface of the substrate when viewed opposite to the first main surface;
Forming an insulating film so as to fill the first and second grooves;
After the step of forming the insulating film, forming a photoresist film on the first main surface of the substrate;
Transferring the first pattern, which is aligned on the basis of the position of the second groove embedded in the insulating film on the substrate, to the photoresist film;
Forming a through electrode penetrating through the substrate in a thickness direction on the substrate located inside the annular first groove embedded in the insulating film;
A method for manufacturing a semiconductor device, comprising:   2. The semiconductor device according to claim 1, wherein each dot constituting the second groove having the dot shape is circular or polygonal when viewed opposite to the first main surface. 3. Production method. After the step of forming the insulating film and before the step of forming the through electrode,
The substrate is ground from the second main surface side facing the first main surface of the substrate in the thickness direction until the bottoms of the first and second grooves embedded in the insulating film are exposed. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of reducing the thickness of the substrate.   The step of forming the insulating film is characterized in that the insulating film is formed so as to fill the first groove and the second groove by a chemical vapor deposition method using TEOS as a raw material. Item 4. The method for manufacturing a semiconductor device according to any one of Items 1 to 3. After the step of forming the insulating film,
Forming a mask pattern so that a mask is positioned on the insulating film on the first and second grooves;
Removing a part of the insulating film by etching using the mask pattern so that the first main surface of the substrate is not exposed;
Flattening the insulating film after removing the mask pattern;
The method of manufacturing a semiconductor device according to claim 1, further comprising:   6. The method according to claim 1, further comprising a step of forming an element isolation region on the first main surface of the substrate using the first pattern transferred to the photoresist film. The manufacturing method of the semiconductor device as described in any one of. Cutting the substrate along the cutting region to further singulate the substrate;
The semiconductor device according to claim 1, wherein in the step of forming the first and second grooves, the second groove is formed in the cutting region of the substrate. Production method. A substrate,
An insulating ring that penetrates the substrate in the thickness direction and is annular when viewed opposite the first main surface of the substrate;
An alignment mark that penetrates the substrate in the thickness direction and has a dot shape when viewed facing the first main surface of the substrate;
In the substrate located inside the annular insulating ring, a through electrode provided to penetrate the substrate in the thickness direction;
A semiconductor wafer comprising:   The semiconductor wafer according to claim 8, wherein each dot constituting the dot-shaped alignment mark is circular or polygonal when viewed opposite to the first main surface.   The semiconductor wafer according to claim 8 or 9, wherein the insulating ring and the alignment mark are made of a material including an NSG film (None-doped Silicate Glass).   The semiconductor wafer according to claim 8, further comprising an element isolation region on the first main surface of the substrate.   The semiconductor wafer according to claim 8, wherein the alignment mark is formed in a cutting region of the substrate. A substrate,
An insulating ring that penetrates the chip region of the substrate in the thickness direction and is annular when viewed opposite the first main surface of the substrate;
An alignment mark that penetrates the chip region of the substrate in the thickness direction and has a dot shape when viewed to face the first main surface of the substrate;
In the substrate located inside the annular insulating ring, a through electrode provided to penetrate the substrate in the thickness direction;
A semiconductor device comprising:   14. The semiconductor device according to claim 13, wherein each dot constituting the dot-shaped alignment mark is circular or polygonal when viewed opposite to the first main surface.   15. The semiconductor device according to claim 13, wherein the insulating ring and the alignment mark are made of a material including an NSG film (None-doped Silicate Glass).   The semiconductor device according to claim 13, further comprising an element isolation region on the first main surface of the substrate.

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