JP2013118258A - Semiconductor wafer, semiconductor device, and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress generation of cracks by dispersing a stress generated in an insulating film on a second groove.SOLUTION: The method includes steps of: forming first and second annular grooves on a fist main surface of a substrate; then forming an insulating film on the substrate so as to fill the first and second grooves; forming a mask pattern so that a mask is positioned on the insulating film on the first groove and a plurality of divided masks are positioned on the insulating film on the second groove; removing the insulating film by etching using the mask pattern so that the first main surface of the substrate is not exposed; removing the insulating film on the first main surface and then forming a photoresist film on the first main surface of the substrate; transferring a first pattern which has been aligned with a position on the substrate of the second groove filled with the insulating film as a reference, onto the photoresist film; and forming a through electrode on the substrate positioned inside of the first annular groove filled with the insulating film.

Description

  The present invention relates to a semiconductor wafer, a semiconductor device, and a manufacturing method thereof.

  In a semiconductor device in which a plurality of semiconductor chips are stacked to realize a high function, upper and lower semiconductors are formed by through electrodes (Through Silicon Via, hereinafter referred to as TSV) provided so as to penetrate the semiconductor chips. A structure for electrically connecting the chips is used. In such a semiconductor chip, an insulating ring structure in which the periphery of the TSV is surrounded by an insulator may be used for the purpose of insulating and separating the TSV and the element region and reducing the capacity between neighboring TSVs. .

  Patent Document 1 (Japanese Unexamined Patent Application Publication No. 2009-1111061) discloses a method for manufacturing a semiconductor device having a through electrode provided with an insulating ring. This discloses a process in which an insulating ring is first formed (via first), element formation to wiring formation, and finally TSV is formed (via last). More specifically, first, a ring-shaped trench is dug in the depth direction from the element forming surface side of the silicon substrate, and the trench is filled with an insulating film to form an insulating ring. Thereafter, after the element formation on the substrate surface, the wiring layer formation, the surface electrode formation step, and the like, the silicon substrate is ground from the back side to be thinned. At this time, by grinding the back surface until the bottom of the insulating ring is exposed from the back surface of the substrate, the insulating ring penetrates the silicon substrate from the front surface to the back surface. And TSV is formed by forming a back surface electrode from the back surface side so that a silicon substrate may be penetrated inside an insulating ring.

JP 2009-1111061 A

  Unlike the above method, if the step of forming the element isolation region (field) is the first step performed on the substrate without forming the insulating ring or the like by via first, the position of the element isolation region on the substrate is determined. There is no need to adjust. That is, since no other member is formed on the substrate when the element isolation region is formed, it is not necessary to align the element isolation region with respect to these members.

  On the other hand, as described above, when forming an element isolation region on a substrate on which an insulating ring has already been formed by via first, the element isolation region is formed by adjusting (positioning) the position on the substrate. There is a need. That is, after the formation of the insulating ring, it is necessary to form an alignment mark used for photolithography before patterning the element isolation region on the substrate.

  However, in the conventional method, since the alignment mark trench is deep and the width thereof is narrow, when an insulating film is embedded in the trench, a seam or a void may occur inside. Since the trench for the alignment mark is formed in a line-and-space shape, stress concentrates on an embedding defect portion such as a seam or a void, and a crack may occur in the substrate starting from this portion. This crack sometimes reaches the element region, and in this case, the manufacturing yield is reduced.

One embodiment is:
Forming an annular first groove and a second groove on the first main surface of the substrate when facing the first main surface;
Forming an insulating film on the first main surface of the substrate so as to fill the first and second grooves;
Forming a mask pattern so that a mask is positioned on the insulating film on the first groove and a plurality of divided masks are positioned on the insulating film on the second groove;
Removing a part of the insulating film by etching using the mask pattern so that the first main surface of the substrate is not exposed;
Removing the insulating film on the first main surface after removing the mask pattern;
After the step of removing the insulating film, forming a photoresist film on the first main surface of the substrate;
Transferring the first pattern, which is aligned on the basis of the position of the second groove embedded in the insulating film on the substrate, to the photoresist film;
Forming a through electrode penetrating through the substrate in a thickness direction on the substrate located inside the annular first groove embedded in the insulating film;
The present invention relates to a method for manufacturing a semiconductor device.

Other embodiments are:
A substrate,
An insulating ring that is provided on the first main surface of the substrate and is annular when viewed opposite to the first main surface;
An alignment mark provided on the first main surface of the substrate;
An insulating film provided on the first main surface of the substrate, wherein an upper surface of the insulating film on the alignment mark is positioned at a first height and a second height;
The present invention relates to a semiconductor wafer.

Other embodiments are:
A substrate,
An insulating ring that is provided on the first main surface of the chip region of the substrate and is annular when viewed opposite to the first main surface;
An alignment mark provided on the first main surface of the chip region of the substrate;
An insulating film provided on a first main surface of a chip region of the substrate, wherein an upper surface of the insulating film on the alignment mark is positioned at a first height and a second height;
The present invention relates to a semiconductor device.

  A mask pattern having a mask divided into a plurality of portions is formed on the insulating film located on the second trench. By using this mask pattern to remove the insulating film on the first main surface, the stress generated in the insulating film on the second groove can be dispersed and the occurrence of cracks can be suppressed.

It is a figure showing the method which this inventor examined. It is a figure showing the method which this inventor examined. It is a figure showing the method which this inventor examined. It is a figure showing the semiconductor device of 1st Example. 3 is a flowchart illustrating a method for manufacturing the semiconductor device according to the first embodiment. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the 1st modification of 1st Example.

  Japanese Patent Laid-Open No. 2005-217071 discloses a method of simultaneously forming an alignment mark that serves as an alignment reference during chip stacking by a process of forming a TSV body. More specifically, when a plurality of chips cut out from a wafer are stacked on each other, a conductive material penetrating through the same substrate as TSV is used as an alignment mark for causing the bonding apparatus to recognize the position of the chip so as not to cause misalignment. This is a technology that uses materials to form simultaneously with the TSV forming process.

  Therefore, as an application example of the above technique, the present inventor provides an alignment mark that serves as a reference for alignment in the step of transferring the STI (field) pattern (photolithographic step), which is the first step of the element forming step. The method of forming simultaneously with the insulating ring was examined in advance. Normally, when an STI is first formed on a wafer on which no component of the semiconductor device is formed, there is no need to align with any element, and therefore no alignment mark is necessary in the STI formation process. Further, in the step after the STI formation step, alignment may be performed with reference to the alignment mark formed simultaneously in the STI formation step.

  On the other hand, the structure which is the subject of the present application enters an element formation step after first forming an insulating ring surrounding the TSV (via first). Therefore, an alignment mark (field alignment mark) for aligning the STI with respect to the insulating ring is required, and the above-described technique has been studied as a method for forming the alignment mark. The field alignment mark investigated by the present inventor has a shape in which insulating grooves are arranged in a line and space (L / S) shape so that it can be recognized in the lithography process.

  In the following, a semiconductor device and a manufacturing method thereof studied by the present inventors will be described with reference to FIGS. As shown in FIG. 1A, this semiconductor device has a chip region 3 surrounded by a scribe region 2 on a semiconductor substrate 17. The chip region 3 is provided with an element region 4 and a through electrode 5, and the scribe region 2 is provided with an alignment mark 1. 1B is a cross-sectional view in the A′-A ′ direction near the through electrode 5 in FIG. 1A, and FIG. 1C is a cross-sectional view in the B′-B ′ direction of a part of the alignment mark 1 in FIG. 1A. As shown in FIG. 1B, the through electrode 5 includes a front electrode 33, a wiring layer 14, and a back electrode 34. A part of the wiring layer 14 and the back electrode 34 penetrates the interlayer insulating film 16. In the element region 4, an annular insulating ring 6 is provided so as to surround the through electrode 5, and the through electrode 5 is insulated and separated from other elements 8 such as a transistor. The element 8 is connected to the wiring 8a through the contact plug 8b. As shown in FIG. 1C, the scribe region 2 is provided with an alignment mark 1 and a wiring layer 15. The lengths of the insulating ring 6 and the alignment mark 1 in the substrate thickness direction 38 are the same. The element region 4 and the scribe region 2 are provided with an element isolation region (STI) 7. A protective film 36 made of a silicon oxynitride film 36 a and a polyimide film 36 b is formed on the interlayer insulating film 16 in the element region 4 and the scribe region 2.

  2 and 3 show the steps of forming the insulating ring 6 and the alignment mark 1 of the semiconductor device of FIG. 1, and other parts are not shown for the sake of simplicity. 2 and 3, A is a process for forming the insulating ring 6 in FIG. 1B, B is a process for forming the alignment mark 1 in FIG. 1C, and C is an enlarged view of a portion P surrounded by a dotted line in FIG. , D shows an enlarged view of a portion Q surrounded by a dotted line in FIG. FIG. 3E is a top view of the entire alignment mark 1 on the first main surface 17a. FIG. 3F is a schematic cross-sectional view showing a state of stress generated in the insulating film 26 located on the alignment mark 1 in the step of FIG. 3, and a part of the structure is omitted.

  As shown in FIG. 2, after a photoresist film 20 is formed on the first main surface 17a of the silicon semiconductor substrate 17, a pattern is formed on the photoresist film 20 by a lithography technique. Subsequently, dry etching of the semiconductor substrate 17 is performed using the photoresist film 20 as a mask. Thus, an annular trench (insulating ring trench) 32 and an alignment mark trench 25 are formed simultaneously. The trench 25 for the alignment mark is a line and space (L / S) in which a plurality of trenches 25 are arranged at a constant pitch in the width direction 25b of the trench 25 when viewed from the first main surface 17a. It is formed into a shape. The pitch represents the distance in the width direction 25b of the semiconductor substrate 17 located between the adjacent trenches 25.

As shown in FIG. 3, after removing the photoresist film 20, both the trenches 25 and 32 in the semiconductor substrate 17 are simultaneously filled with the insulating film 26. Here, as the insulating film 26, an NSG (None-Doped Silicate Glass) film formed by a CVD method (chemical vapor deposition method) using TEOS (Tetra Ethoxy Silane; Si (OC ₂ H ₅ ) ₄ ) as a raw material is used. Use. Thereby, the insulating ring 6 and the alignment mark 1 are formed. The TEOS-NSG film 26 on the insulating ring trench 32 and the alignment mark trench 25 is wet-etched in a state protected by the photoresist film 20 to reduce the thickness of the TEOS-NSG film 26.

  After the wet etching, stress is generated in the insulating film 26 on the first main surface 17a of the semiconductor substrate 17. This stress is generated in the width direction 25b of the trench and the like, and as shown in FIG. 3F, this stress is large at the thick part of the insulating film 26 and small at the thin part. For this reason, the area of the portion having a particularly large film thickness becomes larger in the insulating film 26 on the alignment mark 1. As a result, the stress balance of the entire semiconductor substrate 17 positioned under the insulating film 26 is lost, and stress is concentrated on the alignment mark 1 having a line-and-space shape. Here, since the alignment mark trench 25 formed in the same manner as the insulating ring trench 32 is deep (˜40 μm) and narrower than the depth (˜2 μm), the embedding property is low, and the insulating film Seams and voids 56 may be created within 26. In particular, in the alignment mark 1 in which a plurality of trenches 25 are arranged in an L / S shape, the seam or the like 56 is formed near the center in the width direction 25 b of the trench 25. For this reason, the stress generated in the insulating film 26 is concentrated on the seam etc. 56 in the alignment mark 1, and the semiconductor substrate 17 starts from the seam etc. 56 to the trench 25 from the end portion 25 a of the trench 25. It has been found by the inventor's verification that the crack 57 extending in the extending direction 25c is generated. Such cracks 57 may reach the element region 4 and cause a decrease in manufacturing yield. Thus, it was found that there is room for improvement in the manufacturing method of this study example.

  Therefore, the present inventor examined a method for preventing the occurrence of the crack 57. As a result, it has been discovered that a mask pattern having a plurality of divided masks may be used on the alignment mark trench 25 as a mask pattern for wet etching of the insulating film 26. When the insulating film 26 is wet-etched using such a mask pattern, the portion of the insulating film 26 on which the mask is not provided is removed. For this reason, in plan view, similarly to the shape of the mask pattern, the upper portion of the insulating film 26 on the alignment mark trench 25 is also divided into a plurality of parts. At this time, the upper surface of the portion of the insulating film 26 that has not been etched on the alignment mark trench 25 remains unchanged at the first height. On the other hand, the upper surface of the etched portion of the insulating film 26 is lowered to the second height, and the first height> the second height. As described above, after the etching, the insulating film 26 has an upper surface having two levels of the first height and the second height on the alignment mark trench 25.

  As described above, when the upper portion of the insulating film 26 on the alignment mark trench 25 is divided into a plurality of portions by etching, the area of each of the divided insulating films 26 is reduced in plan view, so that the insulating film 26 is generated in the insulating film 26. The stress can be dispersed and reduced. Accordingly, the stress concentrated on the alignment mark 1 located under the insulating film 26 can be reduced. As a result, the generation of cracks in the semiconductor substrate 17 can be prevented and the manufacturing yield can be improved.

  Embodiments of the present invention will be described below with reference to the drawings. In addition, these Examples are specific examples shown for a deeper understanding of the present invention, and the present invention is not limited to these specific examples.

(First embodiment)
4 and 5 are views showing a semiconductor device manufactured by the manufacturing method of the first embodiment. As shown in FIG. 4A, this semiconductor device has a chip region 3 surrounded by a scribe region (cutting region) 2 on a semiconductor substrate 17. The chip region 3 is provided with an element region 4 and a through electrode 5. As will be described later, a plurality of semiconductor chips can be electrically connected through the through electrode 5. An alignment mark 1 is provided in the scribe region 2.

  4B is a cross-sectional view in the A′-A ′ direction near the through electrode 5 in FIG. 4A, FIG. 4C is a cross-sectional view in the B′-B ′ direction of a part of the alignment mark 1 in FIG. 4A, and FIG. The top view of the alignment mark 1 whole in the main surface 17a is represented.

  As shown in FIG. 4B, the through electrode 5 includes a front electrode 33, a wiring layer 14, and a back electrode 34. A part of the wiring layer 14 and the back electrode 34 penetrates the interlayer insulating film 16. The tip region 3 is provided with an annular insulating ring 6 when viewed from the first main surface 17a. The insulating ring 6 extends from the first main surface 17a in the thickness direction 38 of the semiconductor substrate 17 and extends through the semiconductor substrate 17 to the second main surface 17b. The insulating ring 6 is provided so as to surround the through electrode 5 and insulates the through electrode 5 from other elements 8. The element 8 is connected to the wiring 8a through the contact plug 8b.

  As shown in FIGS. 4C and 4D, the scribe region 2 is provided with an alignment mark 1 and a wiring layer 15. The alignment mark 1 is formed in a line and space shape in which a plurality of marks are arranged at a constant pitch in the width direction 25b. Each mark constituting the alignment mark 1 extends in the direction 25c when viewed facing the first main surface 17a. The alignment mark 1 has the same depth as the insulating ring 6 in the thickness direction 38 of the semiconductor substrate 17. The element region 4 and the scribe region 2 are provided with an element isolation region (STI) 7. A protective film 36 made of a silicon oxynitride film 36 a and a polyimide film 36 b is formed on the interlayer insulating film 16 in the element region 4 and the scribe region 2.

  5 to 15 are views for explaining a method of manufacturing the semiconductor device of this embodiment. Hereinafter, the manufacturing method of the present embodiment will be described with reference to these drawings. FIG. 5 is a flowchart showing the manufacturing method of this embodiment. 6 to 14, A is a cross-sectional view corresponding to FIG. 4B, B is a cross-sectional view corresponding to FIG. 4C, and C is the entire alignment mark 1 or a structure corresponding thereto facing the first main surface 17 a. The top view seen from the direction to do is represented. In FIG. 7C, the alignment mark trench 25 is shown as a perspective view in order to clarify the positional relationship. FIG. 8D is a schematic cross-sectional view showing the state of stress generated in the insulating film 26 on the alignment mark trench 25 in the step of FIG. 8, and a part of the structure is omitted. 15A is a sectional view showing a state in which a plurality of semiconductor chips 40 are stacked, and FIG. 15B is an enlarged view of a portion 50 surrounded by a dotted line in FIG. 15A.

  As shown in FIG. 6, a photoresist film 20 is formed on the first main surface 17 a of the silicon semiconductor substrate 17. Patterns for insulating rings and alignment marks are formed in the photoresist film 20 by lithography. The semiconductor substrate 17 is dry etched using the pattern of the photoresist film 20. As a result, a trench (first groove) 32 for an insulating ring and a trench 25 for an alignment mark are formed (S11 in FIG. 5).

  In the present embodiment, the insulating ring trench (first groove) 32 is annular when viewed from the first main surface 17a, and has a depth of 40 μm, a width of 2 μm, and a ring diameter of 20 μm. Although the dimension of the trench 32 for insulation rings is not specifically limited, For example, it can be set as 30-50 micrometers in depth, 1-3 micrometers in width, and 15-30 micrometers in ring diameter. The alignment mark trench (second groove) 25 is a line-and-space shape as opposed to the first main surface 17a, and has a depth of 40 μm, a length of 2 μm in the width direction 25b, and a pitch (adjacent to each other). The distance in the width direction 25b of the semiconductor substrate 17 located between the trenches 25) is 4 μm, and the length in the trench extending direction 25c is 42 μm. Since the alignment mark trench 25 is formed in the same process as the insulating ring trench 32, the depth of both is the same (in the above example, 40 μm). The dimension of the alignment mark trench 25 is determined by the detectable dimension of the mark sensor that detects the alignment mark. Here, in order to minimize the area occupied by the alignment mark on the wafer, a dimension close to the lower limit of the detectable dimension of the mark sensor is desirable. The alignment mark trench (second groove) 25 has, for example, a plurality of second grooves each having a length in the width direction 25b of 1 to 3 μm and a length in the trench extending direction 25c of 30 to 30 mm. It can be formed to be 50 μm, and the line and space pitch can be 2 to 6 μm.

As shown in FIG. 7, the photoresist film 20 is removed. An NSG (None-Doped Silicate Glass) film 26 is formed on the semiconductor substrate 17 by a CVD method using TEOS (Tetra EthOxy Silane; Si (OC ₂ H ₅ ) ₄ ) as a raw material (hereinafter, this film 26 is referred to as TEOS). -Called NSG film). The film thickness of the TEOS-NSG film 26 formed by such a deposition method (film thickness on the semiconductor substrate 17) is at least 1/2 of the width of the trenches 25 and 32 from the viewpoint of completely embedding the trenches 25 and 32. Is the film thickness. Further, the TEOS-NSG film 26 is used because it can be formed conformally with good coverage in order to avoid generation of voids as much as possible when embedding the high aspect ratio trenches 25 and 32. is there. In the case where the same effect is obtained, another material may be used for the insulating film 26. For example, as the insulating film 26, a thin silicon nitride film and a TEOS-NSG film can be used.

  As shown in FIG. 8, in order to reduce the CMP load when removing the TEOS-NSG film 26 on the semiconductor substrate 17 in a subsequent polishing step, the film thickness of the TEOS-NSG film 26 is reduced by wet etching. At this time, a seam may occur in the TEOS-NSG film 26 formed in the trench 25 for alignment marks. In this case, if the TEOS-NSG film 26 is wet-etched as it is, the seam in the TEOS-NSG film 26 is deepened. Therefore, wet etching is performed in a state where the TEOS-NSG film 26 on the alignment mark trench 25 is protected by a protective film (mask pattern) such as the photoresist film 20.

  At this time, the photoresist film (mask pattern) 20 on the alignment mark trench 25 is formed to have two divided masks 20a and 20b. By wet etching using the photoresist film 20, the upper portion of the insulating film 26 on the alignment mark trench 25 is divided into portions 26a and 26b. Portions 26a and 26b have an upper surface 26c located at a first height. The portions 26a and 26b are divided by the trench 26e, and the upper surface 26d located at the bottom of the trench 26e has a second height. The upper surface 26c is positioned at a first height that is the same as the height of the insulating film 26 before etching (after the step of FIG. 7). The upper surface 26d is formed at the bottom of the trench 26e formed by etching, extends in the extending direction 25c of the trench 25, and is positioned at a second height lower than the first height. The upper portion of the insulating film 26 on the semiconductor substrate 17 is divided into two portions 26a and 26b by wet etching, and the lower portion is integrated.

  Stress is generated in the insulating film 26 on the first major surface 17 a of the semiconductor substrate 17. As described above with reference to FIG. 3F, this stress is large in the thick portion of the insulating film 26 and small in the thin portion. In particular, the area of the thick part becomes large in the insulating film 26 on the trench 25. However, in this embodiment, as described above, since the insulating film 26 on the trench 25 is etched using the mask pattern 20 having the divided mask, the upper portion of the insulating film 26 on the trench 25 is also divided into a plurality. Therefore, as shown in FIG. 8D, since the area of each divided insulating film 26 is reduced in plan view, the stress generated in the insulating film 26 can be dispersed and reduced. For this reason, even if a seam or a trench occurs in the insulating film 26 embedded in the trench 25, the stress concentrated on the seam or the like can be reduced. As a result, the generation of cracks in the semiconductor substrate 17 can be prevented and the manufacturing yield can be improved.

  As shown in FIG. 9, after removing the photoresist film 20, heat treatment is performed at 950 ° C. for 60 minutes to degas the TEOS-NSG film 26. Next, the TEOS-NSG film 26 on the first main surface 17a of the semiconductor substrate 17 is removed by a chemical mechanical polishing method (CMP method), thereby completing the insulating ring 6 and the alignment mark 1 (FIG. 5). S12).

  As shown in FIG. 10, a photoresist film 20 is formed on the semiconductor substrate 17. The first pattern 29 is formed by transferring the field pattern for STI onto the photoresist film 20 by lithography. At this time, in this embodiment, the alignment mark 1 formed as described above can be used as an alignment mark for the field pattern for STI. That is, by transferring the field pattern aligned with the position of the alignment mark 1 on the semiconductor substrate 17 as a reference to the photoresist film 20, misalignment of photolithography can be reduced.

  The semiconductor substrate 17 is etched using the first pattern 29 of the photoresist film 20. Thus, as shown in FIG. 11, an STI trench 7a is formed (S21 in FIG. 5). Thereafter, the photoresist film 20 is removed. After an insulating film such as a silicon oxide film or a silicon nitride film is embedded on the semiconductor substrate 17, a CMP process is performed on the insulating film. Thereby, an STI (element isolation region) 7 is formed (S22 in FIG. 5).

  As shown in FIG. 12, an element 8 such as a transistor is formed in the active region 30 of the semiconductor substrate 17 (S23 in FIG. 5). An interlayer insulating film 16 is formed on the semiconductor substrate 17 in several stages. In the process of forming the interlayer insulating film 16, the wiring layer 14 and the alignment mark above the region in the semiconductor substrate 17 surrounded by the contact plug 8 b, the wiring 8 a, and the insulating ring 6 that reach the impurity diffusion layer of the transistor 8. A wiring layer 15 is formed above 1. The wiring layer 14 functions as a pad for connecting to the front surface electrode 33 and the back surface electrode 34 to be formed in a later step. The wiring layer 14 includes a plurality of wirings 14a to 14d made of aluminum (Al), copper (Cu), or the like, and a plurality of contact plugs 14e to 14g made of a metal film such as tungsten for connecting the plurality of wirings. The wiring layer 15 includes a plurality of wirings 15a to 15d and a plurality of contact plugs 15e to 15g that connect the plurality of wirings.

  As shown in FIG. 13, a protective film 36 made of a silicon oxynitride film (SiON) 36 a and a polyimide film (passivation film) 36 b is formed on the interlayer insulating film 16 so as to cover the wiring layer 14. Next, a first opening 33a is formed in the protective film 36 so that the upper surface of the wiring layer 14 is exposed. The seed film 11 is formed on the protective film 36 including the first opening 33a by sputtering. After forming a photoresist film (not shown) on the protective film 36, patterning is performed to expose the seed film 11 provided in the first opening 33a. A copper bump 13 and a solder film 12 are sequentially formed on the exposed seed film 11 by electroplating. After removing the photoresist film on the protective film 36, the exposed seed film 11 is removed. The seed film 11, the copper bump 13, and the solder film 12 constitute a surface electrode 33 (S3 in FIG. 5).

  As shown in FIG. 14, a support substrate (not shown) is provided on the side of the semiconductor substrate 17 on which the surface electrode 33 is provided via an adhesive layer (not shown). Thereafter, the second main surface 17b facing the first main surface 17a of the semiconductor substrate 17 in the thickness direction is thinned to a thickness of, for example, 775 μm to 40 to 50 μm (S4 in FIG. 5). By this grinding process, the insulating ring 6 and the bottom of the alignment mark 1 formed in advance are exposed on the second main surface 17 b side of the semiconductor substrate 17. Anisotropic dry etching is performed on the semiconductor substrate 17 located inside the annular insulating ring 6 so that the wiring layer 14 is exposed from the second main surface 17b side of the semiconductor substrate 17. At this time, a second opening 34 a that penetrates the semiconductor substrate 17 and extends in a part of the interlayer insulating film 16 is formed. Next, a seed film 10 is formed by laminating a titanium (Ti) film and a copper (Cu) film on the entire surface of the second main surface 17b of the semiconductor substrate 17 by sputtering. A photoresist pattern (not shown) having a third opening at the same position as the second opening 34 a is formed on the second main surface 17 b of the semiconductor substrate 17. A copper bump 19 and a solder film 9 such as a SnAg film are sequentially formed in the third opening by electroplating. A back electrode 34 is formed by the seed film 10, the copper bump 19, and the solder film 9. Next, after removing the photoresist pattern, the exposed portion of the seed film 10 is removed (S5 in FIG. 5).

  Thereafter, the surface of the solder film 9 is made convex by reflow. The adhesive layer and the support substrate are removed. As described above, the semiconductor device shown in FIG. 4 is obtained. In this semiconductor device, a through electrode 5 is provided in each chip region 3 partitioned by the scribe region 2 so as to penetrate the semiconductor substrate 17. The through electrode 5 includes bumps for connection (surface electrode 33 and back electrode 34) at the upper end and the lower end. As will be described later, when a plurality of semiconductor chips 40 are stacked, the through electrode 5 is vertically moved through the through electrode 5. The arranged semiconductor chips 40 are electrically connected. The through electrode 5 includes a through plug (surface electrode 33, back electrode 34) that penetrates the semiconductor substrate 17 and a wiring layer 14 that penetrates the interlayer insulating film 16 on the semiconductor substrate 17. A portion of the through electrode 5 that penetrates the semiconductor substrate 17 is surrounded by an annular insulating ring 6 and is insulated and separated from other elements 8 and the like.

  Next, the semiconductor substrate 17 is scribed along the scribe region (cutting region) 2 (S6 in FIG. 5). Thereby, the semiconductor substrate 17 is separated into individual pieces to form a semiconductor chip.

  As shown in FIG. 15, a plurality of semiconductor chips 40 are mounted such that the front surface electrode 33 and the back surface electrode 34 of different semiconductor chips 40 are in contact with each other. The solder films 9 and 12 of the front surface electrode 33 and the back surface electrode 34 of each semiconductor chip 40 are joined by reflow. After filling the underfill 41 between the semiconductor chips 40, the plurality of semiconductor chips 40 are mounted on the package substrate 42. Thereafter, by molding with the mold resin 43, the semiconductor device of this example is completed (S7 in FIG. 5).

  Examples of the semiconductor device of this embodiment include storage devices such as DRAM, SRAM, and flash memory, and arithmetic processing devices such as MPU and DSP.

  As described above, in this embodiment, the photoresist film (mask pattern) 20 having the masks 20a and 20b divided into two is formed on the trench 25 for alignment marks. By performing wet etching of the insulating film 26 using the photoresist film 20, the upper portion of the insulating film 26 located on the trench 25 is also divided into a plurality of parts. Accordingly, the area of each divided insulating film 26 in a plan view is reduced, and the stress generated in the insulating film 26 on the trench 25 can be dispersed and reduced. Thereby, even when a seam or a void is generated in the alignment mark 1 located under the insulating film 26, the stress concentrated on the seam or the like can be reduced. As a result, the generation of cracks in the semiconductor substrate 17 can be prevented and the manufacturing yield can be improved.

  In this embodiment, the line and space-shaped trench 25 is formed as the alignment mark trench 25 in plan view. However, the trench 25 is not limited to the line-and-space shape, and even in other shapes, the upper portion of the insulating film 26 formed on the trench 25 is divided into a plurality of parts, so that the stress in the insulating film 26 is dispersed. The stress concentrated on the lower alignment mark 1 can be reduced, and the effects of the present invention can be achieved. On the other hand, in the case of the line-and-space-shaped trench 25, the stress in the insulating film 26 can be effectively dispersed by dividing the upper portion of the insulating film 26 along the extending direction 25c of the trench. . Therefore, the stress concentrated on the alignment mark 1 located under the insulating film 26 can be reduced, and the present invention is more effective for the process of forming the line-and-space-shaped trench 25. It can be said that there is.

  In the present embodiment, the upper portion of the insulating film 26 is divided into a plurality along the trench extending direction 25c. However, if the upper portion of the insulating film 26 is divided into a plurality of directions, the direction is not limited to the extending direction 25c of the trench, and the stress in the insulating film 26 is dispersed even in other directions. The effect of can be produced. On the other hand, in the case of the trench 25 extending in a certain direction like a line-and-space shape, the stress in the insulating film 26 is divided by dividing the upper portion of the insulating film 26 along the extending direction 25c of the trench. Can be effectively dispersed. Accordingly, the stress concentrated on the alignment mark 1 located under the insulating film 26 can be effectively reduced, and the process of dividing the upper portion of the insulating film 26 into a plurality along the extending direction 25c of the trench. Can be said to be more effective by applying the present invention.

  On the trench 25, the number of the upper portions of the insulating film 26 after the division is not particularly limited, and may be two as in this embodiment, or may be three or more. In general, the more the insulating film 26 is divided, the more effectively the stress is dispersed and cracks are less likely to occur. However, in the lithography process at the time of dividing the insulating film 26 and the CMP process after etching. In consideration of the workability of the above, the number of the upper portions of the insulating film 26 after the division can be appropriately set to a suitable number.

  In this embodiment, the alignment mark 1 is used as a field alignment mark during the STI 7 alignment. The alignment mark 1 can be used as a field alignment mark for alignment of other structures in addition to the alignment of the STI 7. For example, in the step of FIG. 14, it can be used as a field alignment mark for alignment when forming the second opening 34a.

  In this embodiment, the TEOS-NSG film 26 is exemplified as the insulating film for burying the insulating ring trench 32 and the alignment mark trench 25. However, the material for burying the trenches 25 and 32 is not limited thereto. . When the trench 25 as deep as the alignment mark 1 and narrow with respect to the depth is buried with an insulating film, seams and voids are likely to occur due to poor filling even if it is not a TEOS-NSG film. Therefore, the present invention is not limited to the TEOS-NSG film 26, but is equally effective when applied to a process of filling the trenches 25 and 32 with other insulating films. On the other hand, when the TEOS-NSG film 26 is used, heat treatment for baking (Degas) is required. The TEOS-NSG film 26 may be contracted by this heat treatment, and the seam may be expanded. Therefore, it can be said that the present invention is more effective for the step of filling the trench 25 with the TEOS-NSG film 26.

(First modification)
In the first embodiment, the alignment mark 1 is formed in the scribe region 2 of the semiconductor substrate 17, but this modification is different in that the alignment mark 1 is formed in a region other than the scribe region 2 of the semiconductor substrate 17.

  FIG. 16A is a plan view illustrating an example in which the alignment mark 1 is provided in the non-effective shot region 45 of the semiconductor substrate 17. The semiconductor substrate 17 includes a plurality of effective shot regions (regions indicated by hatching in FIG. 16A) 46 formed of semiconductor chips on which a semiconductor device is formed by performing lithography exposure or the like in a later process, and the semiconductor device There is a non-effective shot area (white area in FIG. 16A) 45 that is not formed. The non-effective shot region 45 refers to a region where a semiconductor chip where a normal semiconductor device pattern cannot be formed is located. That is, since the semiconductor substrate 17 is formed in a circular shape and the semiconductor chip is formed in a rectangular shape, a part of the semiconductor chip applied to the terminal portion of the semiconductor substrate 17 protrudes from the semiconductor substrate 17 and cannot be patterned. Become. Since the size of the semiconductor chip is determined when the design of the semiconductor device is completed, the position of the ineffective shot region 45 on the semiconductor substrate 17 can be grasped in advance. If pattern formation is repeated at the terminal portion of the semiconductor substrate 17, foreign matter is generated, and thus no pattern is formed in the ineffective shot region 45. Therefore, the ineffective shot region 45 is a useless region that does not contribute to the manufacture of the semiconductor device. In this modification, the alignment mark 1 is formed by using the non-effective shot area 45 which becomes the useless area, so that it is not necessary to secure an area for the alignment mark 1 in the effective shot area 46, and the fine mark is fine. It can be set as the semiconductor device corresponding to conversion. Note that the number and positions of the non-effective shot regions 45 forming the alignment mark 1 are not limited to the example of FIG. 16A, and the alignment marks 1 can be appropriately formed in the non-effective shot regions 45 having a desired number and position. .

  FIG. 16B is a view showing another example, showing an example in which the alignment mark 1 is formed in the chip region 3 of the semiconductor substrate 17, and corresponding to FIG. 4A of the first embodiment. As shown in FIG. 16B, the alignment mark 1 may be formed in the chip region 3. Further, the formation position and the number of alignment marks 1 in the chip region 3 are not limited to the example of FIG. 16B, and a desired number of alignment marks 1 are formed in a desired position in the chip region 3. Can do.

DESCRIPTION OF SYMBOLS 1 Alignment mark 2 Scribe area 3 Chip area 4 Element area 5 Through electrode 6 Insulating ring 7 Element isolation area (STI)
7a Trench for element isolation region 8 Element 8a Wiring layer 8b Contact plug 9, 12 Solder film 10, 11 Seed film 13, 19 Copper bump 14, 15 Wiring layer 14a, 14b, 14c, 14d, 15a, 15b, 15c, 15d Wirings 14e, 14f, 14g, 15e, 15f, 15g Contact plug 16 Interlayer insulating film 17 Semiconductor substrate 17a First main surface 17b Second main surface 20, 20a, 20b Photoresist film 25 Alignment mark trench 25a End portion 25b Trench width direction 25c Trench extension direction 26 Insulating films 26a, 26b Upper portions 26c, 26d of the divided insulating films Upper surfaces 26e of the insulating films Trench 29 First pattern 30 Active region 32 Trench 33 for insulating ring Front electrode 33a First opening 34 Back electrode 34a Second Mouth 36 protective layer 36a silicon oxynitride film (SiON)
36b Polyimide film (passivation film)
38 Semiconductor substrate thickness direction 40 Semiconductor chip 41 Underfill 42 Package substrate 43 Mold resin 45 Ineffective shot area 46 Effective shot area 56 Seam, void 57 Crack

Claims (17)

Forming an annular first groove and a second groove on the first main surface of the substrate when facing the first main surface;
Forming an insulating film on the first main surface of the substrate so as to fill the first and second grooves;
Forming a mask pattern so that a mask is positioned on the insulating film on the first groove and a plurality of divided masks are positioned on the insulating film on the second groove;
Removing a part of the insulating film by etching using the mask pattern so that the first main surface of the substrate is not exposed;
Removing the insulating film on the first main surface after removing the mask pattern;
After the step of removing the insulating film, forming a photoresist film on the first main surface of the substrate;
Transferring the first pattern, which is aligned on the basis of the position of the second groove embedded in the insulating film on the substrate, to the photoresist film;
Forming a through electrode penetrating through the substrate in a thickness direction on the substrate located inside the annular first groove embedded in the insulating film;
A method for manufacturing a semiconductor device, comprising: In the step of forming the first and second grooves,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the plurality of second grooves are formed so that a shape viewed from the first main surface is a line-and-space shape. 3. In the step of forming the mask pattern,
3. The semiconductor device according to claim 2, wherein a mask divided into a plurality of portions along an extending direction of the second groove is formed as a mask positioned on the insulating film on the second groove. Production method. In the step of forming the first and second grooves,
Each of the plurality of second grooves is formed to have a width of 1 to 3 μm and a length in the extending direction of the second grooves of 30 to 50 μm, and the line and space pitch is 2 to 2 mm. The method of manufacturing a semiconductor device according to claim 2, wherein the second groove is formed so as to be 6 μm. In the step of removing a part of the insulating film,
The method for manufacturing a semiconductor device according to claim 1, wherein a part of the insulating film is removed by wet etching. After the step of transferring the first pattern to the photoresist film, before the step of forming the through electrode,
The substrate is ground from the second main surface side facing the first main surface of the substrate in the thickness direction until the bottoms of the first and second grooves embedded in the insulating film are exposed. 6. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of reducing the thickness of the substrate. In the step of forming the insulating film,
The method for manufacturing a semiconductor device according to claim 1, wherein the insulating film is formed by a chemical vapor deposition method using TEOS as a raw material.   8. The method according to claim 1, further comprising a step of forming an element isolation region on the first main surface of the substrate using the first pattern transferred to the photoresist film. The manufacturing method of the semiconductor device as described in any one of Claims 1-3. Cutting the substrate along the cutting region to further singulate the substrate;
In the step of forming the first and second grooves,
The method for manufacturing a semiconductor device according to claim 1, wherein the second groove is formed in the cutting region of the substrate. A substrate,
An insulating ring that is provided on the first main surface of the substrate and is annular when viewed opposite to the first main surface;
An alignment mark provided on the first main surface of the substrate;
An insulating film provided on the first main surface of the substrate, wherein an upper surface of the insulating film on the alignment mark is positioned at a first height and a second height;
A semiconductor wafer comprising:   The semiconductor wafer according to claim 10, wherein the alignment mark has a line-and-space shape when viewed from the first main surface.   In the insulating film on the alignment mark, the first height is higher than the second height, and an upper surface located at the second height extends in an extending direction of the alignment mark. The semiconductor wafer according to claim 11.   Each of the plurality of marks constituting the alignment mark is formed to have a width of 1 to 3 μm and a length in the extending direction of the alignment mark of 30 to 50 μm, and the line and space pitch is 2 to 2 μm. The semiconductor wafer according to claim 11, wherein the semiconductor wafer is 6 μm. A substrate,
An insulating ring that is provided on the first main surface of the chip region of the substrate and is annular when viewed opposite to the first main surface;
An alignment mark provided on the first main surface of the chip region of the substrate;
An insulating film provided on a first main surface of a chip region of the substrate, wherein an upper surface of the insulating film on the alignment mark is positioned at a first height and a second height;
A semiconductor device comprising:   The semiconductor device according to claim 14, wherein the alignment mark has a line-and-space shape when viewed from the first main surface.   In the insulating film on the alignment mark, the first height is higher than the second height, and an upper surface located at the second height extends in an extending direction of the alignment mark. The semiconductor device according to claim 15.   Each of the plurality of marks constituting the alignment mark is formed to have a width of 1 to 3 μm and a length in the extending direction of the alignment mark of 30 to 50 μm, and the line and space pitch is 2 to 2 μm. The semiconductor device according to claim 15, wherein the semiconductor device is 6 μm.