KR20110078103A - Method for manufacturing pad metal of semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor multilayer wire is provided to shorten deposition time by forming a penetration electrode with a slit. CONSTITUTION: A first bottom conductive layer(100) is formed on a semiconductor substrate(10). A first interlayer dielectric layer(102) is formed on the semiconductor substrate with the first bottom conductive layer. A first penetration electrode(106) passes through the semiconductor substrate and the first interlayer dielectric layer. A second interlayer dielectric layer(112'') is formed on the semiconductor substrate with a second bottom conductive layer(108) and a top metal layer(110). A second penetration electrode(116) passes through the first penetration electrode and the second interlayer dielectric layer.

Description

METHOD FOR MANUFACTURING PAD METAL OF SEMICONDUCTOR DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for manufacturing semiconductor multilayer wirings, and more particularly, to a method for manufacturing semiconductor multilayer wirings suitable for solving the problems and problems resulting from the formation of through electrodes.

As the degree of integration of semiconductor chips increases, a semiconductor chip or semiconductor package structure using a through electrode penetrating a semiconductor substrate is disclosed. Typically, the through electrode may be formed to penetrate the conductive pad and the multilayer wiring pattern and the semiconductor substrate directly below the pad.

1 illustrates a semiconductor multilayer wiring structure in which such a penetrating electrode is formed.

As illustrated in FIG. 1, a penetrating electrode 1 penetrating a conductive pad and a semiconductor substrate is shown, and through the penetrating electrode 1 penetrating the semiconductor substrate, a semiconductor chip having different conductive pads in a semiconductor multilayer wiring structure or It can be connected to the substrate.

For example, a through electrode 1 (Thru Silicon Via, TSV) may be applied to the through electrode 1, and the through electrode 1 may be formed by using a copper (Cu) electrochemical plating (ECP) process. Is formed.

However, when the through electrode is formed using the copper ECP process, a crack may occur due to a difference in coefficient of thermal expansion (CTE) with a substrate.

In addition, in a conventional semiconductor multilayer wiring manufacturing process having a through electrode, a void problem, a problem of etching a deep via (for example, a 70 μm or more via), a problem of lengthening a process time, and the like may occur.

Therefore, in the present invention, by applying a chemical vapor deposition (CVD) process instead of the ECP (Electrochemical Plating) process, and proceeds by separating the through-electrode forming process at least two times, the aspect ratio generated when etching the deep via (deep via) (spect ratio) This paper proposes a semiconductor multilayer wiring fabrication technique that can solve the gap-fill problem.

In addition, the present invention is to propose a semiconductor multilayer wiring manufacturing technology that can reduce the deposition time by forming a through electrode in a slit (slit) form.

According to the method for manufacturing a semiconductor multilayer wiring for solving the problems of the present invention, forming a first through electrode passing through the semiconductor substrate and the first interlayer insulating film, forming a second interlayer insulating film, and the first through And forming a second through electrode passing through an electrode and the second interlayer insulating layer.

The first through electrode and the second through electrode may be formed by a chemical vapor deposition technique.

In addition, any one of tungsten (W), polysilicon (Si), or copper (Cu) may be applied to the first through electrode and the second through electrode.

In addition, the first through electrode and the second through electrode may be in the form of a slit.

In addition, the width of the slit may be 500 kPa to 2 μm.

In addition, the second through electrode may be aligned with the first through electrode.

In addition, the second through electrode may be aligned with the first through electrode (IR).

The method for manufacturing a semiconductor multilayer wiring may include forming a first lower conductive layer on an upper surface of the semiconductor substrate, and forming the first interlayer insulating layer on an upper surface of the semiconductor substrate on which the first lower conductive layer is formed. Forming a first via on which the first through electrode is to be formed by etching the first interlayer insulating layer using the first photoresist pattern as a mask after forming the first photoresist pattern; Embedding the first through electrode in the first via, removing the first photoresist pattern, and subsequently forming a second lower conductive layer and an upper metal layer, and forming the second lower conductive layer and the second lower conductive layer. Forming a second interlayer insulating film on an upper surface of the semiconductor substrate on which the upper metal layer is formed; and forming a second photoresist pattern, and then forming the second photoresist. Forming a second via to form the second through electrode by etching the second interlayer insulating layer using the mask pattern as a mask, and embedding the second through electrode in the second via. can do.

According to the present invention, in a semiconductor multilayer wiring manufacturing process, a chemical vapor deposition (CVD) process is applied instead of an electrochemical plating (ECP) process, and the through electrode forming process is performed by dividing at least two times into deep vias. It can solve the aspect ratio gap-fill problem that occurs when etching. In addition, the through electrode is formed in a slit form to reduce the overall deposition time.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, and only the embodiments make the disclosure of the present invention complete, and the general knowledge in the art to which the present invention belongs. It is provided to fully inform the person having the scope of the invention, which is defined only by the scope of the claims. Like numbers refer to like elements throughout.

In describing the embodiments of the present invention, if it is determined that a detailed description of a known function or configuration may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. In addition, terms to be described below are terms defined in consideration of functions in the embodiments of the present invention, which may vary according to intentions or customs of users and operators. Therefore, the definition should be based on the contents throughout this specification.

In describing the embodiments of the present invention, it should be noted that in some alternative embodiments the functions mentioned in the blocks or steps may occur out of order. For example, the two blocks or steps shown in succession may in fact be executed substantially concurrently or the blocks or steps may sometimes be performed in the reverse order, depending on the functionality involved.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2 to 6 are cross-sectional views illustrating a method of manufacturing a semiconductor multilayer wiring in accordance with an embodiment of the present invention.

First, as illustrated in FIG. 2, the first lower conductive layer 100 is formed on the upper surface of the semiconductor substrate 10, for example, a Si substrate, and the first lower conductive layer 100 is formed. The first interlayer insulating layer 102 may be formed on the formed semiconductor substrate 10.

Thereafter, after the photoresist (not shown) is applied, the first photoresist pattern 104 may be formed through an exposure process. The first photoresist pattern 104 may be used to etch vias in which a first through electrode to be described later is formed.

By etching the first interlayer insulating layer 102 using the first photoresist pattern 104 as a mask, vias (not shown) in which the first through electrode is to be formed may be formed.

After the vias are formed, the first through electrode 106 according to the present exemplary embodiment may be embedded in the vias. The first through electrode 106 may be provided to pass through the semiconductor substrate 10 and the first interlayer insulating layer 102, for example, as a through silicon via (TSV).

In this case, the first through electrode 106 is formed by a chemical vapor deposition (CVD) technique according to the present embodiment, for example, tungsten (W) or doped polysilicon (poly) All materials to which CVD techniques such as Si) or copper (Cu) can be applied may be selectively formed.

In addition, the first through electrode 106 is characterized in that it is manufactured in the form of a slit (slit) according to this embodiment. Since the first through electrode 106 is manufactured in the form of a slit, it is possible to reduce the overall deposition time. Here, the width of the slit structure of the first through electrode 106 may be limited to, for example, 500 μm to 2 μm.

In FIG. 3, after removing the first photoresist pattern 106, the second lower conductive layer 108 and the upper metal layer 110 are sequentially formed, and the second lower conductive layer 108 and the upper metal layer 110 are sequentially formed. ) May be formed on the semiconductor substrate 10 on which the second interlayer insulating film 112 is formed.

Thereafter, after applying the photoresist (not shown), the second photoresist pattern 114 may be formed through an exposure process. The second photoresist pattern 114 may be used to etch vias in which a second through electrode to be described later is formed.

In FIG. 4, a via (not shown) in which the second through electrode is to be formed may be formed by etching the second interlayer insulating layer 112 using the above-described second photoresist pattern 114 as a mask.

After the via is formed, the second through electrode 116 according to the present exemplary embodiment may be buried in the via. The second through electrode 116 is, for example, a silicon through electrode (TSV), and may be provided to pass through the second interlayer insulating layer 112 through the first through electrode 106. In order to be aligned with the electrode 106, for example, an infrared (IR) alignment technique or the like may be applied. In FIG. 4, reference numeral 112 ′ denotes a second interlayer insulating film after embedding the first through electrode 106 and the second through electrode 116 thus aligned.

In this case, the second through electrode 116 is formed by the CVD technique according to the present embodiment, and for example, all materials to which the CVD technique such as doped polysilicon or copper (Cu) can be selectively formed are formed. Can be.

In addition, the second through electrode 116 is manufactured in the form of a slit according to the present embodiment, similarly to the first through electrode 106 described above. Since the second through electrode 116 is manufactured in the form of a slit, the overall deposition time can be reduced. Here, the width of the slit structure of the second through electrode 116 may be limited to, for example, 500 μm to 2 μm.

Subsequently, in FIG. 5, an etching process is performed to partially remove the second interlayer insulating layer 112 ′ to open the upper metal layer 110. The etching process may include, for example, a dry etching process or a reactive ion etching process. Reactive Ion Etching (RIE) or the like may be applied, and reference numeral 112 ″ in FIG. 5 denotes a second interlayer insulating film after the etching process.

6, TiSN 118 as a diffusion barrier film, Al 120 as a metal film, and TEOS as an insulating film for the etched second interlayer insulating film 112 " and the open upper metal layer 110 upper surface. By sequentially stacking Tetra Ethyl Ortho Silicate (122), SiN (124), and the like, a process for manufacturing a semiconductor multilayer wiring in which a pad metal is formed may be completed.

As described above, in the present embodiment, in the semiconductor multilayer wiring manufacturing process, the CVD process is applied instead of the ECP (Electrochemical Plating) process, the through electrode forming process is divided into at least two times, and the through electrode is formed in the slit form. It is implemented.

Meanwhile, the embodiments of the present invention have been described in detail, but the present invention is not limited to these embodiments, and various modifications may be made by those skilled in the art within the spirit and scope of the present invention described in the claims below. to be.

1 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor multilayer wiring;

2 to 6 are cross-sectional views illustrating a method for manufacturing a semiconductor multilayer wiring in accordance with an embodiment of the present invention.

Claims (8)

Forming a first through electrode passing through the semiconductor substrate and the first interlayer insulating film; Forming a second interlayer insulating film, Forming a second through electrode passing through the first through electrode and the second interlayer insulating layer Semiconductor multilayer wiring manufacturing method comprising a. The method of claim 1, The first through electrode and the second through electrode are formed by a chemical vapor deposition technique. Method for manufacturing semiconductor multilayer wiring. The method according to claim 1 or 2, The first through electrode and the second through electrode, the material of any one of tungsten (W), polysilicon (Si) or copper (Cu) is applied Method for manufacturing semiconductor multilayer wiring. The method of claim 1, The first through electrode and the second through electrode is in the form of a slit Method for manufacturing semiconductor multilayer wiring. The method of claim 4, wherein The width of the slit is 500 kPa to 2 μm Method for manufacturing semiconductor multilayer wiring. The method of claim 1, The second through electrode is aligned with the first through electrode. Method for manufacturing semiconductor multilayer wiring. The method of claim 6, The second through electrode is infrared (IR) aligned with the first through electrode. Method for manufacturing semiconductor multilayer wiring. The method of claim 1, The semiconductor multilayer wiring manufacturing method, Forming a first lower conductive layer on an upper surface of the semiconductor substrate; Forming the first interlayer insulating film on an upper surface of the semiconductor substrate on which the first lower conductive layer is formed; Forming a first via on which the first through electrode is to be formed by etching the first interlayer insulating layer after forming the first photoresist pattern using the first photoresist pattern as a mask; Embedding the first through electrode in the first via; Removing the first photoresist pattern and sequentially forming a second lower conductive layer and an upper metal layer; Forming a second insulating interlayer on an upper surface of the semiconductor substrate on which the second lower conductive layer and the upper metal layer are formed; Forming a second via on which the second through electrode is to be formed by etching the second interlayer insulating layer using the second photoresist pattern as a mask after forming the second photoresist pattern; Embedding the second through electrode in the second via Semiconductor multilayer wiring manufacturing method comprising a.

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