JP2013096727A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of detecting timing violation of a plurality of portions with a small-scale circuit configuration.SOLUTION: A semiconductor device includes: a first selector for selecting any one of a plurality of signals based on a selecting signal; a second selector for selecting any one of a plurality of latched signals based on the selecting signal; a delay circuit for delaying a clock signal CLK for a predetermined time; a flip-flop circuit for detecting timing violation for latching the output of the first selector in synchronization with the clock signal delayed by the delay circuit; and a comparator circuit for comparing the output of the flip-flop circuit for detecting timing violation with the output of the second selector. The semiconductor device can be configured by a single circuit for detecting timing violation without providing circuits respectively for a plurality of signals.

Description

  The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device having a timing violation detection function.

  In recent years, with the increase in scale and speed of LSI (Large Scale Integration), there are many critical paths with severe timing conditions in the LSI chip. When such an LSI is mounted on an actual machine and an operation test is performed, timing violations may occur in the critical path, particularly under high load conditions (high temperature, low voltage, high load operation), and various problems may occur. For example, in the case of an LSI for an image display device, there may occur a problem that noise is mixed in a display image. In such a case, the designer predicts which part of the circuit has a failure based on the correlation between the actual machine evaluation result and the design data, and proceeds with the analysis of the cause of the failure. However, since the timing violation is caused by noise, IR drop, or the like in the actual operation state, there is a problem that it is very difficult to specify the location where the malfunction occurs at the circuit level.

  As a method for efficiently performing the failure analysis due to the timing violation described above, for example, Patent Document 1 discloses that a timing failure caused by power supply noise, crosstalk noise, or the like is detected and generated in an actual operation state in which an LSI is mounted. A method for identifying a location is disclosed.

JP 2000-356667 A

  The following analysis is given by the present invention.

  FIG. 5 is a circuit diagram showing a main part (flip-flop circuit part) of the semiconductor device described in Patent Document 1. As shown in FIG. 5, a flip-flop circuit FF2 that operates for detecting a timing failure, a comparison circuit E-OR1, a delay element, and the like are added to a flip-flop circuit FF1 that operates normally, and a normal clock signal CK and this clock By observing data at two timings with the delayed clock signal obtained by delaying the signal, a mismatch between the two data is detected to detect a timing failure in the LSI operation state (actual operation state).

  However, in the semiconductor device described in Patent Document 1, the circuit shown in FIG. 5 is required for a 1-bit signal, and when an attempt is made to increase the number of detection target signals, it is not necessary to insert the corresponding detection circuit. Therefore, there is a problem that the circuit scale increases. Further, in order to automatically avoid the timing violation, the circuit scale further increases.

  As described above, in a semiconductor device having many critical paths, it is desired to realize a semiconductor device that detects timing violations at a plurality of locations with a small circuit configuration.

  According to a first aspect of the present invention, there is provided a semiconductor device in which a plurality of signals are latched by a plurality of different flip-flop circuits in synchronization with a clock signal, and one of the plurality of signals is selected based on a selection signal. A first selector for selecting one; a second selector for selecting one of the plurality of latched signals based on the selection signal; and a delay circuit for delaying the clock signal for a predetermined time The timing violation detection flip-flop circuit that latches the output of the first selector in synchronization with the clock signal delayed by the delay circuit, the output of the timing violation detection flip-flop circuit, and the second selector And a comparison circuit for comparing the output.

  According to the semiconductor device of the present invention, it is possible to provide a semiconductor device capable of detecting timing violations at a plurality of locations with a small circuit configuration.

It is a block diagram which shows the detail of the semiconductor device which concerns on Embodiment 1 of this invention. 3 is a timing chart illustrating an operation of the semiconductor device according to the first embodiment of the present invention. 1 is a block diagram illustrating an entire semiconductor device according to a first embodiment of the present invention. It is a block diagram which shows the detail of the semiconductor device which concerns on Embodiment 2 of this invention. FIG. 10 is a circuit diagram showing a main part (flip-flop circuit part) of a semiconductor device described in Patent Document 1.

  First, the outline | summary of this invention is demonstrated with reference to drawings as needed. In the description of the outline, the drawings and the reference numerals in the drawings are shown as examples of the embodiments to help understanding, and do not limit the variations of the embodiments according to the present invention.

As shown in FIG. 1, the semiconductor device according to the embodiment of the present invention synchronizes a plurality of signals (S0 to S _N−1 ) with a clock signal CLK, and a plurality of different flip-flop circuits (8, 11, 14), the first selector 41 that selects one of the plurality of signals (S0 to S _N-1 ) based on the selection signal ADDR, and the selection signal ADDR, A second selector 42 that selects one of the latched signals (LS0 to LS _N-1 ), a delay circuit 44 that delays the clock signal CLK for a predetermined time, and a clock signal that is delayed by the delay circuit 44 A timing violation detection flip-flop circuit 45 that latches the output S_SEL of the first selector 41 in synchronization with CLKd, and a timing violation detection flip-flop And a comparing circuit 46 for comparing the output of the flop circuit 45 and the output LS_SEL of the second selector 42 comprises.

With such a configuration, the first and second selectors (41, 42), the delay circuit 44, and the timing violation detection are not provided for the plurality of signals (S0 to S _N-1 ) individually. The timing violation can be detected by one circuit (timing violation detection circuit 48) constituted by the flip-flop circuit 45 and the comparison circuit 46.

  Here, it is preferable that the second selector 42 selects a signal obtained by latching the signal selected by the first selector 41. That is, in FIG. 1, when the signal Si (where i = 0,..., N−1) is selected by the first selector 41, the signal from which the signal Si is latched is selected by the second selector 42. Select LSi.

Further, as shown in FIG. 4, the semiconductor device may further include a counter 24 that outputs the selection signal ADDR by a count operation. With such a configuration, a plurality of signals (S0 to S _N-1 ) and a plurality of latched signals (LS0 to LS _N-1 ) are automatically switched by the first and second selectors (41, 42). This makes it possible to detect timing violations.

  Further, as shown in FIGS. 1 and 3, the semiconductor device may further include a control unit 32 that takes in the comparison result (timing violation detection signal ERR) of the comparison circuit 46 in association with the selection signal ADDR. Good. With such a configuration, the control unit 32 can associate the selection signal ADDR with the timing violation detection signal ERR.

The plurality of signals (S0 to S _N-1 ) may be output signals of a plurality of logic circuits (1, 3, 5, etc.) that operate in synchronization with the clock signal CLK, respectively. As a result, the plurality of signals (S0 to S _N-1 ) can be output signals from the logic circuit (1, 3, 5, etc.) to be detected as a timing violation.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[Embodiment 1]
(Configuration of Embodiment 1)
FIG. 3 is a block diagram showing the entire semiconductor device 50 according to the first embodiment of the present invention. As illustrated in FIG. 3, the semiconductor device 50 includes N critical paths (20, 21, 22, etc.), a timing violation detection circuit 48, a control unit 32, and a register 30. Here, the critical path refers to a path that takes time for signal propagation and has a severe timing condition for receiving correct data in the receiving flip-flop circuit.

FIG. 1 is a block diagram showing in more detail the critical paths 20, 21, and 22 and the timing violation detection circuit 48 of FIG. As shown in FIG. 1, addresses 0 to N-1 are allocated to the N critical paths. As shown in FIG. 1, the logic circuits 1 and 2 are sandwiched between flip-flop circuits 7, 8 and 9 and are connected in series. The logic circuits 3 and 4 are sandwiched between the flip-flop circuits 10, 11, and 12 and are connected in series with each other. The logic circuits 5 and 6 are sandwiched between the flip-flop circuits 13, 14, and 15 and are connected in series with each other. Here, these flip-flop circuits (7 to 15) all perform a latch operation in synchronization with the clock signal CLK. Specifically, the transmission-side flip-flop circuit 7 outputs the transmission signal TS0 and inputs it to the logic circuit 1. The logic circuit 1 outputs a signal S0. Then, the flip-flop circuit 8 on the receiving side latches the signal S0 and outputs the latched signal LS0. Similarly, the transmission-side flip-flop circuit 10 outputs the transmission signal TS 1 and inputs it to the logic circuit 3. The logic circuit 3 outputs a signal S1. Then, the flip-flop circuit 11 on the receiving side latches the signal S1 and outputs the latched signal LS1. Similarly, the transmission-side flip-flop circuit 13 outputs the transmission signal TS _N−1 and inputs it to the logic circuit 5. The logic circuit 5 outputs a signal _SN-1 . Then, the flip-flop circuit of the receiving side 14 latches the signal _{S N-1,} and outputs the signal _{LS N-1} latched.

The semiconductor device 50 includes a plurality of circuits in which such logic circuits and flip-flop circuits are connected in series. Among these, a path having a strict timing known at the design stage is selected in advance as a critical path. In FIG. 1, N critical paths are selected. Specifically, the critical paths 20, 21, 22 and the like indicated by broken line frames, respectively. In the critical path 20, the timing at which the signal S0 is latched by the flip-flop circuit 8 on the receiving side is severe, and when a timing violation occurs, a correct signal is not output as the latched signal LS0. Similarly, in the critical path 21, the timing at which the signal S1 is latched by the receiving flip-flop circuit 11 is strict, and when a timing violation occurs, a correct signal is not output as the latched signal LS1. Similarly, in the critical path 22, the timing at which the signal S _N-1 is latched by the flip-flop circuit 14 on the receiving side is strict, and when a timing violation occurs, the latched signal LS _N-1 has a correct signal. Not output.

  On the other hand, the path between the logic circuit 2 and the flip-flop circuit 9, the path between the logic circuit 4 and the flip-flop circuit 12, and the path between the logic circuit 6 and the flip-flop circuit 15 are not selected as critical paths because there is a margin in operation timing. .

  Next, a detailed configuration of the timing violation detection circuit 48 in FIG. 1 will be described. The timing violation detection circuit 48 includes a first selector (MUX0 in FIG. 1) 41, a second selector (MUX1 in FIG. 1) 42, a delay circuit 44, a timing violation detection flip-flop circuit (FFd) 45, The comparator circuit 46 is configured.

Signals S0 to _SN-1 in each critical path are supplied to the _N input terminals of the first selector 41. On the other hand, the N input terminals of the second selector 42 are supplied with signals LS0 to LSN ₋₁ latched in each critical path. Further, the selection signal ADDR is supplied to the first and second selectors (41, 42) to control switching. Specifically, when the selection signal ADDR is i, control is performed such that Si is selected by the first selector 41 and LSi is selected by the second selector 42.

  The delay circuit 44 is a circuit that delays the clock signal CLK by a predetermined time (τ in FIG. 2), and outputs a delayed clock signal CLKd. Here, the predetermined time to be delayed may be a fixed value, or may be set from the control unit 32 (FIG. 3) via the register 30 (FIG. 3).

  The delayed clock signal CLKd is supplied to the clock input terminal of the timing violation detection flip-flop circuit 45. The output S_SEL of the first selector 41 is input to the input terminal of the timing violation detection flip-flop circuit 45. The signal latched by the timing violation detection flip-flop circuit 45 is supplied to one terminal of the comparison circuit 46.

  Further, the output LS_SEL of the second selector is supplied to the other terminal of the comparison circuit 46. In the comparison circuit 46, it is determined whether or not the two input signals match, and if they match, the timing violation detection signal ERR is output to the Low level, and if they do not match (ie, When a timing violation is detected, the timing violation detection signal ERR is output to a high level.

  In FIG. 3, the selection signal ADDR is switched from the control unit 32 via the register 30 and is supplied to the timing violation detection circuit 48. The timing violation detection signal ERR output from the comparison circuit 46 of the timing violation detection circuit 48 is transferred to the control unit 32, and the control unit 32 captures the timing violation detection signal ERR in association with the selection signal ADDR. As described above, by fetching the timing violation detection signal ERR in association with the selection signal ADDR, the control unit 32 can determine which critical path of the plurality of critical paths has the timing violation. . The control unit 32 is connected to an external tester (not shown), and displays the determination result of the control unit 32 on the display screen of the external tester. Thereby, the determination result can be notified to the user who detects the timing violation in the semiconductor device 50.

(Operation of Embodiment 1)
Next, the operation of the semiconductor device 50 according to the first embodiment will be described with reference to FIG. FIG. 2 is a timing chart showing the operation of the semiconductor device 50. In the following description of the operation, in order to simplify the description, a case will be described in which timing violation detection is performed on only two critical paths (20, 21) out of N critical paths. In this case, the selection signal ADDR performs control to switch between 0 and 1.

  2, in order from the top, the CLK signal, the transmission signal TS0 output from the transmission-side flip-flop circuit 7, the transmission signal TS1 output from the transmission-side flip-flop circuit 10, the signal S0 output from the logic circuit 1, the logic The signal S1, which is the output of the circuit 3, the signal S0 is latched by the flip-flop circuit 8 on the receiving side, the signal LS1 is latched by the flip-flop circuit 11 on the receiving side, the first and second selectors The selection signal ADDR for controlling the selection of (41, 42), the output LS_SEL of the second selector 42, the delayed clock signal CLKd, the output S_SEL of the first selector 41, and the output of the timing violation detection flip-flop circuit (FFd) 45 , And a timing violation detection signal ERR, which is a comparison result of the comparison circuit 46.

  As shown in FIG. 2, the transmission-side flip-flop circuit 7 in the critical path 20 sequentially outputs the signal values A → B → C → D in synchronization with the clock signal CLK as the transmission signal TS0, and in the critical path 21 Assume that the transmission-side flip-flop circuit 10 sequentially outputs signal values E → F → G → H in synchronization with the clock signal CLK as the transmission signal TS1. The selection signal ADDR is 0 at timings t1 to t6, and is switched at timing t6, and becomes 1 at timings t7 to t12. That is, the signals from the critical path 20 are selected by the first and second selectors (41, 42) in the first half period t1 to t6, and S_SEL = S0, LS_SEL = LS0, and the first half period t7-t12. And the signal from the critical path 21 is selected by the second selector (41, 42), and S_SEL = S1 and LS_SEL = LS1.

  Next, transmission of the signal values A to D and E to H at each timing will be described with reference to FIG. The output TS0 of the flip-flop circuit 7 on the transmission side of the critical path 20 is input to the logic circuit 1 and output as the signal S0 from the logic circuit 1. However, the delay amount increases due to some cause and the timing condition cannot be satisfied. Will occur. For example, in the signal S0, the signal value A can be received with a delay amount satisfying the timing condition at the timing t2, but the signal value B has an increased delay amount, and the signal value B has not yet been changed from A to B at the timing t4. Cannot receive B Specifically, as shown in FIG. 2, the delay amount is increased by τ1, so that the transition from A to B is not made at the timing t4 when the clock rises. As a result, the signal LS0 latched in synchronization with the clock signal CLK becomes the signal value A in the periods t3 to t6, and the information on the signal value B is missing.

  Similarly, the output TS1 of the flip-flop circuit 10 on the transmission side of the critical path 21 is input to the logic circuit 3 and output as the signal S1 from the logic circuit 3, but the delay amount increases due to some factor, and the timing condition is set. There are cases where it cannot be satisfied. For example, in the signal S1, the signal value G can be received with a delay amount that satisfies the timing condition at the timing t6, but the signal value H increases in the delay amount, and the signal value H has not yet transited from G to H at the timing t8. I cannot receive H. Specifically, as shown in FIG. 2, since the delay amount is increased by τ2, the transition from G to H is not performed at the rising timing t8 of the clock. As a result, the signal LS1 latched in synchronization with the clock signal CLK becomes a signal value G in all the periods t7 to t10, and information on the signal value H is lost.

  Therefore, as shown in FIG. 2, the output LS_SEL of the second selector 42 has the signal value A in the period t3 to t6 in which the selection signal ADDR is 0, and the signal value G in the period t7 to t10 in which the selection signal ADDR is 1. It becomes.

  Next, the output S_SEL of the first selector 41 becomes the signal S0 in the period t1 to t6 in which ADDR is 0, and the signal S1 in the period t7 to t12 in which ADDR is 1. Next, when the signal S_SEL is latched by the delayed clock signal CLKd, the timing conditions are satisfied at timings t3, t5, t7, and t9, respectively, and latched by the timing violation detection flip-flop circuit (FFd) 45, The signal values A, B, G, and H can be output without being lost.

  Next, the output LS_SEL of the second selector 42 is compared with the output of the timing violation detection flip-flop circuit 45 by the comparison circuit 46, and the mismatched portion becomes the high level and is output as the timing violation detection signal ERR. . As a result, the timing violation detection signal ERR becomes High level during the period when the output of the timing violation detection flip-flop circuit 45 is the signal value B and the signal value H. Note that the timing violation detection signal ERR is captured by the control unit 32 in association with the selection signal ADDR. In the control unit 32, a timing violation that cannot receive the signal value B at the timing t4 occurs in the critical path 20, and the timing in the critical path 21 occurs. It is determined that a timing violation that cannot receive the signal value H has occurred at t8. The determination result is notified to an externally connected tester.

  As described above, according to the semiconductor device according to the first embodiment, in a semiconductor device having a plurality of critical paths, a single timing violation detection circuit 48 can provide a plurality of locations without providing a timing violation detection circuit individually. Timing violation detection can be performed. As a result, it is possible to achieve timing violation detection at a plurality of locations with a small circuit.

  In the description of the operation of the first embodiment, the case where the selection signal ADDR is switched to 0 or 1 has been described. However, the selection signal ADDR is incremented in the range of 0 to N−1 so that all N critical paths are tested. In this case, the same operation as shown in FIG. 2 is repeated. Further, the input of the selection signal ADDR can be an arbitrary pattern. In any case, it is a matter of course that the effects shown in the first embodiment can be obtained.

[Embodiment 2]
Next, a semiconductor device according to Embodiment 2 of the present invention will be described. FIG. 4 is a block diagram illustrating details of the semiconductor device according to the second embodiment. The difference between FIG. 4 and FIG. 1 is that the timing violation detection circuit 56 is newly provided with a counter 24. About others, it is the same as Embodiment 1, the same referential mark is attached | subjected and description is abbreviate | omitted.

In the second embodiment, the count value obtained by the counting operation of the counter 24 is used as the selection signal ADDR. The counter 24 operates based on the clock signal CLK, increments the selection signal ADDR in a certain cycle, and returns to 0 again in a certain cycle. Here, it is desirable to set the counter output bit number m in accordance with the number N of critical paths to be detected. Specifically, it may be set to satisfy 2 ^m ≧ N.

  In FIG. 3 showing the entire semiconductor device of the first embodiment, in the second embodiment, the selection signal ADDR is not supplied from the register 30 but is automatically generated by the counter 24 of the timing violation detection circuit 56. Then, the critical path to be tested is switched by the generated selection signal ADDR, and timing violation detection is performed. The timing violation detection signal ERR is transferred to the control unit 32 together with the selection signal ADDR, and the control unit 32 detects the timing violation detection signal. The ERR and the selection signal ADDR are captured in association with each other.

  As described above, according to the semiconductor device of the second embodiment of the present invention, the same effect as that of the first embodiment can be obtained, and a plurality of critical paths can be automatically set by controlling the selection signal ADDR by the counter 24. There is an effect that the timing violation can be detected by switching.

  The present invention can be used to detect a timing violation and specify an occurrence location when an operation test is performed with a circuit having a plurality of paths having strict timing mounted.

  Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Further, various combinations or selections of various disclosed elements (including each element of each claim, each element of each embodiment, each element of each drawing, etc.) are possible within the scope of the claims of the present invention. It is. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

1, 2, 3, 4, 5, 6: logic circuits 7, 8, 9, 10, 11, 12, 13, 14, 15: flip-flop circuits 20, 21, 22: critical path 24: counter 30: register 32 Control unit 41: first selector 42: second selector 44: delay circuit 45: timing violation detection flip-flop circuit 46: comparison circuit 48, 56: timing violation detection circuit 50: semiconductor devices TS0 to TS _N-1 : Transmission signal S0 to S _N-1 : Signal LS0 to LS _N-1 : Latched signal S_SEL: Output of first selector LS_SEL: Output of second selector ADDR: Selection signal ERR: Timing violation detection signal CLK: Clock signal CLKd: delayed clock signal

Claims (5)

In a semiconductor device that latches a plurality of signals by a plurality of different flip-flop circuits in synchronization with a clock signal,
A first selector that selects any one of the plurality of signals based on a selection signal;
A second selector that selects one of the plurality of latched signals based on the selection signal;
A delay circuit for delaying the clock signal for a predetermined time;
A timing violation detection flip-flop circuit that latches the output of the first selector in synchronization with the clock signal delayed by the delay circuit;
A semiconductor device comprising: a comparison circuit that compares an output of the timing violation detection flip-flop circuit with an output of the second selector.   The semiconductor device according to claim 1, wherein the second selector selects a signal obtained by latching the signal selected by the first selector.   3. The semiconductor device according to claim 1, further comprising a counter that outputs the selection signal by a counting operation.   4. The semiconductor device according to claim 1, further comprising a control unit that captures a comparison result of the comparison circuit in association with the selection signal. 5.   5. The semiconductor device according to claim 1, wherein each of the plurality of signals is an output signal of a plurality of logic circuits that operate in synchronization with the clock signal. 6.

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