JP2013090188A - Crystal oscillator circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a crystal oscillator circuit which eliminates the effects of harmonic noise caused by a through current by using a differential circuit, and because the harmonic noise caused by operative other circuits may affect the oscillation output of the crystal oscillator circuit, which also reduces influences attributable to fluctuations in the power supply voltage and thereby restrains a jitter in the oscillation output.SOLUTION: The crystal oscillator circuit comprises: a resonance circuit which includes a crystal resonator; a signal inversion circuit, connected to the resonance circuit, which includes a differential pair; a current source circuit which supplies a bias current to the differential pair; and a low-pass filter circuit, connected between a voltage line supplying power to the signal inversion and the current source circuits and the signal inversion circuit, whose cutoff frequency is lower than the oscillation frequency of the crystal resonator.

Description

  The present invention relates to a crystal oscillation circuit.

  Quartz oscillation circuits are often used in electronic devices such as radio receivers and signal measuring instruments. This is because the crystal oscillation circuit has high frequency stability. Considering the ease of configuration, frequency characteristics, and the like, the crystal oscillation circuit is often configured using a CMOS (Complementary Metal Oxide Semiconductor) inverter.

  When the crystal oscillation circuit is configured using a CMOS inverter, when the input signal to the CMOS inverter is inverted, there is a moment when the P channel type MOS transistor and the N channel type MOS transistor constituting the CMOS inverter are simultaneously turned on. is there. Then, a through current flowing from the power supply voltage to the ground voltage is generated. When the through current is generated, the power supply voltage fluctuates, and harmonic noise is superimposed on the power supply voltage line and the ground voltage line. This harmonic noise affects not only the output of the crystal oscillation circuit but also circuits other than the crystal oscillation circuit.

  Here, Patent Document 1 discloses a crystal oscillation circuit using a differential circuit as a signal inversion circuit. The crystal oscillation circuit disclosed in Patent Document 1 includes a plurality of switches connected to a differential circuit, and by appropriately switching these switches, output amplitude and power consumption are suppressed, and harmonic noise is reduced. ing.

  Further, Patent Document 2 discloses a temperature characteristic compensator that corrects the temperature characteristic of a control circuit or the like to which a temperature sensor is applied to a linear or arbitrary slope and can guarantee an accurate and stable operation.

  Further, Patent Document 3 discloses a technique for realizing a differential amplifier that operates with a low power supply voltage, consumes low power, and has a large amplification degree.

JP 2008-26312 A JP 2003-273654 A JP-A-10-303658

  Each disclosure of the above prior art document is incorporated herein by reference. The following analysis has been made from the viewpoint of the present invention.

  The signal inversion circuit included in the crystal oscillation circuit disclosed in Patent Document 1 is configured by a differential circuit. The crystal oscillation circuit disclosed in Patent Document 1 uses a differential circuit and does not use a CMOS inverter. Since a CMOS inverter is not used, fluctuations in the power supply voltage (or ground voltage) due to the above-described through current do not occur, and harmonic noise is suppressed.

  However, the crystal oscillation circuit also requires power supply, and is often supplied in common with the power supply voltage supplied to other circuits. This power supply voltage may fluctuate due to the operation of other circuits. This is because if a CMOS inverter is used in another circuit, a through current is generated. This fluctuation in the power supply voltage affects the crystal oscillation circuit. Specifically, the fluctuation of the power supply voltage propagates to the inverted signal output of the differential circuit, causing a problem that jitter occurs in the oscillation output of the differential circuit. Therefore, a crystal oscillation circuit that reduces the influence of fluctuations in the power supply voltage and suppresses oscillation output jitter is desired.

  According to a first aspect of the present invention, a resonance circuit including a crystal resonator, a signal inversion circuit including a differential pair connected to the resonance circuit, and a current source circuit for supplying a bias current to the differential pair A low-pass filter circuit connected between a voltage line for supplying power to the signal inverting circuit and the current source circuit and the signal inverting circuit, and having a cutoff frequency lower than a specific oscillation frequency of the crystal resonator, A crystal oscillation circuit is provided.

  According to the first aspect of the present invention, there is provided a crystal oscillation circuit that reduces the influence of fluctuations in the power supply voltage and suppresses the jitter of the oscillation output.

It is a figure for demonstrating the outline | summary of one Embodiment of this invention. It is a figure which shows an example of the internal structure of the crystal oscillation circuit 1 which concerns on the 1st Embodiment of this invention. It is a figure which shows an example of the output frequency analysis waveform at the time of applying power supply noise to a crystal oscillation circuit. FIG. 4 is a diagram showing an example of an output frequency analysis waveform when power supply noise similar to that in FIG. 3 is applied to the crystal oscillation circuit 1 shown in FIG. 2. It is a figure which shows an example of the internal structure of the crystal oscillation circuit 2 which concerns on the 2nd Embodiment of this invention. FIG. 6 is a diagram showing an example of an output frequency analysis waveform when power supply noise similar to that in FIG. 3 is applied to the crystal oscillation circuit 2 shown in FIG. 5. It is a figure which shows an example of the internal structure of the crystal oscillation circuit 3 which concerns on the 3rd Embodiment of this invention.

  First, an outline of an embodiment will be described with reference to FIG. Note that the reference numerals of the drawings attached to this summary are attached to the respective elements for convenience as an example for facilitating understanding, and are not intended to limit the present invention to the illustrated embodiment.

  As described above, by using the differential circuit, it is possible to configure a crystal oscillation circuit that eliminates the influence of harmonic noise caused by the through current. However, harmonic noise generated by the operation of other circuits may affect the oscillation output of the crystal oscillation circuit. Therefore, a crystal oscillation circuit that reduces the influence of fluctuations in the power supply voltage and suppresses oscillation output jitter is desired.

  Therefore, as an example, the crystal oscillation circuit shown in FIG. 1 is provided. The crystal oscillation circuit shown in FIG. 1 includes a resonance circuit 100 including a crystal resonator, a signal inverting circuit 200 connected to the resonance circuit 100 and including a differential pair, and a current source circuit 300 that supplies a bias current to the differential pair. A low-pass filter circuit 400 connected between the voltage line for supplying power to the signal inverting circuit 200 and the current source circuit 300 and the signal inverting circuit 200 and having a cutoff frequency lower than the inherent oscillation frequency of the crystal resonator. I have.

  That is, by using a differential pair for the signal inverting circuit 200, the signal inverting circuit 200 itself is prevented from becoming a noise generation source. Furthermore, the low-pass filter circuit 400 that filters the power supply voltage supplied to the signal inverting circuit 200 is provided, thereby removing the influence of fluctuations in the power supply voltage. Here, the cutoff frequency of the low-pass filter circuit 400 is set to a frequency lower than the inherent oscillation frequency of the crystal resonator. As a result, it is possible to remove high frequency noise having a frequency higher than the oscillation frequency of the crystal resonator. Furthermore, it is sufficient that the cutoff frequency of the low-pass filter circuit 400 is lower than the oscillation frequency of the crystal resonator, and the cutoff frequency of the low-pass filter circuit 400 does not need to be excessively lowered. Therefore, the area occupied by the elements constituting the low-pass filter circuit 400 does not become excessive. With the configuration as described above, the jitter of the oscillation output of the crystal oscillation circuit can be suppressed.

  In the present invention, the following modes are possible.

  [Mode 1] The crystal oscillation circuit according to the first aspect.

  [Mode 2] The resonance circuit includes a first capacitor connected in series with the crystal resonator, and a feedback resistor connected in parallel with the crystal resonator, and is included in the signal inverting circuit. The differential pair includes a first MOS transistor and a second MOS transistor. The first MOS transistor has a gate connected to a bias voltage source and a drain connected to one end of a first resistor. The second MOS transistor has a gate connected to one end of the feedback resistor, a drain connected to the other end of the feedback resistor and one end of the second resistor, and the sources of the first and second MOS transistors are Are connected in common and connected to the current source circuit, the other ends of the first and second resistors are connected to the low-pass filter circuit, and the current source circuit is connected to the third current source circuit. Including a MOS transistor, a fourth MOS transistor, and a constant current source, wherein the gates of the third and fourth MOS transistors are connected to each other, and the sources of the third and fourth MOS transistors are connected to a ground voltage The drain of the third MOS transistor is connected to the gate of the third MOS transistor and to the constant current source, and the drain of the fourth MOS transistor is connected to the first and second MOS transistors. Connected to the source of the MOS transistor, the low-pass filter circuit includes a third resistor and a second capacitor, one end of the third resistor is connected to the voltage line for supplying power, and the other end is The second capacitor and the first and second resistors included in the signal inverting circuit are connected, and the other end of the second capacitor is connected to the ground voltage. Rukoto is preferable.

  [Mode 3] The crystal oscillation circuit includes a fourth resistor having one end connected to the voltage line, a drain connected to the other end of the fourth resistor, and a gate connected to the gate of the third MOS transistor. A reference voltage generating circuit including a fifth MOS transistor connected to the drain and a source connected to the ground voltage, a non-inverting input node connected to the drain of the second MOS transistor, and an inverting input node And a differential circuit connected to the drain of the fifth MOS transistor.

  [Mode 4] The resistance value of the fourth resistor is preferably variable.

  Hereinafter, specific embodiments will be described in more detail with reference to the drawings.

[First Embodiment]
The first embodiment of the present invention will be described in more detail with reference to the drawings.

  FIG. 2 is a diagram illustrating an example of an internal configuration of the crystal oscillation circuit 1 according to the present embodiment.

  The crystal oscillation circuit 1 includes a current source circuit 10, a signal inverting circuit 20, and a resonance circuit 30.

  The current source circuit 10 includes N-channel MOS transistors N01 and N02 and a constant current source CS01.

  The signal inverting circuit 20 includes N-channel MOS transistors N03 and N04, resistors R01 to R03, and a capacitor C01.

  The resonance circuit 30 includes a crystal resonator 31, a resistor R04, and capacitors C02 and C03.

  The gate and drain of the N-channel MOS transistor N01 are connected in common, and are connected to the gate of the N-channel MOS transistor N02. The source of the N-channel MOS transistor N01 is connected to the ground voltage VSS, and the gate and drain are connected to one end of the constant current source CS01. The gate of the N-channel MOS transistor N02 is connected to the gate and drain of the N-channel MOS transistor N01. The source of the N-channel MOS transistor N02 is connected to the ground voltage VSS, and the drain is commonly connected to the sources of the N-channel MOS transistors N03 and N04. The N-channel MOS transistors N01 and N02 included in the current source circuit 10 constitute a current mirror circuit.

  The gate of the N-channel MOS transistor N03 included in the signal inverting circuit 20 is connected to the bias voltage source Vb, and the drain is connected to one end of the resistor R01. The gate of the N-channel MOS transistor N04 is connected to the input terminal Vin of the signal inverting circuit 20. The drain of the N-channel MOS transistor N04 is connected to the output terminal Vout of the signal inverting circuit 20 and to one end of the resistor R02. The other ends of the resistors R01 and R02 are commonly connected to one end of the resistor R03 and one end of the capacitor C01.

  The other end of the resistor R03 is connected to the power supply voltage VDD, and the other end of the capacitor C01 is connected to the ground voltage VSS. That is, the resistor R03 and the capacitor C01 form a low-pass filter (corresponding to the above-described low-pass filter circuit 400), and the resistors R01 and R02 are connected to the power supply voltage VDD via the low-pass filter.

  The bias current of the signal inverting circuit 20 is determined by the N-channel MOS transistor N02. When a predetermined voltage and a power supply voltage VDD are supplied from the bias voltage source Vb connected to the N-channel MOS transistor N03, an oscillation signal proportional to the series resonance frequency of the crystal resonator 31 is output from the output terminal Vout.

  Here, if the current flowing through the N-channel MOS transistor N01 is Ia, the current flowing through the N-channel MOS transistor N02 is also Ia. Further, since the N-channel MOS transistors N03 and N04 form a differential pair, the N-channel MOS transistors N03 and N04 (resistors R01 and R02) have a current having a current value ½ of the current Ia. (Hereinafter referred to as current Ib) may flow. Therefore, if the resistance value of the resistor R03 is extremely small compared to the resistance value of the resistor R02 and the voltage drop is not taken into consideration, the common level of the output voltage of the signal inverting circuit 20 (voltage of the output terminal Vout) is the resistance R02. And the current Ib.

  As described above, since the resistor R03 and the capacitor C01 form a low-pass filter, the noise component superimposed on the power supply voltage VDD is removed. That is, the voltage supplied from the low pass filter acts as the second power supply voltage of the signal inverting circuit 20. By setting the cutoff frequency fc of the low-pass filter to be equal to or lower than the oscillation frequency fosc of the crystal oscillation circuit (fc << fosc), harmonic noise components having a frequency higher than the oscillation frequency can be removed. The cut-off frequency can be expressed as fc = 1 / (2πR03 × C01).

  FIG. 3 is a diagram illustrating an example of an output frequency analysis waveform when power supply noise is applied to a crystal oscillation circuit that does not include the low-pass filter illustrated in FIG.

  FIG. 4 is a diagram illustrating an example of an output frequency analysis waveform when power supply noise similar to that in FIG. 3 is applied to the crystal oscillation circuit 1 according to the present embodiment.

  As shown in FIG. 3, in a crystal oscillation circuit that does not include a low-pass filter, a power supply noise component is superimposed on the oscillation output. However, as shown in FIG. 4, even if the same power supply noise as in FIG. 3 is applied to the crystal oscillation circuit 1 according to the present embodiment, the noise component is removed.

  Here, as an example of the conditions for performing the waveform analysis, consider a case where the oscillation frequency of the crystal oscillation circuit 1 is 8 MHz, the power supply noise is a spike noise having a frequency of 10 MHz, and an amplitude of ± 10 mV. In this case, in a crystal oscillation circuit that does not include a low-pass filter, a noise component of 10 MHz is superimposed on the oscillation output. On the other hand, in the crystal oscillation circuit 1 according to this embodiment, the influence of power supply noise higher than the oscillation frequency of 8 MHz is removed.

  As described above, the low-pass filter including the resistor R03 and the capacitor C01 can remove harmonic noise generated by operating other circuits. Therefore, in the crystal oscillation circuit 1 according to the present embodiment, even if harmonic noise (power supply noise) is applied, low oscillation output jitter can be realized.

[Second Embodiment]
Next, a second embodiment will be described in detail with reference to the drawings.

  FIG. 5 is a diagram illustrating an example of an internal configuration of the crystal oscillation circuit 2 according to the present embodiment. In FIG. 5, the same components as those in FIG. 2 are denoted by the same reference numerals, and the description thereof is omitted. Note that the output terminal Vout of the signal inverting circuit 20 is replaced with the output terminal Vout1.

  The difference between the crystal oscillation circuit 1 and the crystal oscillation circuit 2 is that a reference voltage generation circuit 40 that outputs a reference voltage Vref and a differential circuit 50 are added.

  The reference voltage generation circuit 40 includes an N-channel MOS transistor N05 and resistors R05 and R06. The gate of the N-channel MOS transistor N05 is commonly connected to the gates of the N-channel MOS transistors N01 and N02, the source is connected to the ground voltage VSS, and the drain is connected to one end of the resistor R05. N-channel MOS transistors N01 and N05 constitute a current mirror circuit. The drain of the N-channel MOS transistor N05 is used as the output terminal Vout2, and the reference voltage Vref is output from the output terminal Vout2.

  The resistors R05 and R06 are connected in series, and one end of the resistor R06 is connected to the power supply voltage VDD. The resistance value of the resistor R05 is set to twice the resistance value of the resistors R01 and R02, and the resistance value of the resistor R06 is set equal to the resistance value of the resistor R03.

  With the above configuration, the reference voltage Vref is determined by the current flowing through the resistor R05, the resistor R06, and the N-channel MOS transistor N05. The common level of the reference voltage Vref and the output voltage of the signal inverting circuit 20 (voltage of the output terminal Vout1) is the same voltage. This is because the resistance values of the resistors R03 and R06 are equal, the resistance value of the resistor R05 is equal to the combined resistance value of the resistors R01 and R02, and the current Ia flowing through the N-channel MOS transistors N02 and N05 is also equal.

  The output terminal Vout1 is connected to the non-inverting input of the differential circuit 50 and the resonance circuit 30, and the output terminal Vout2 is connected to the inverting input terminal of the differential circuit 50. Further, the output node of the differential circuit 50 is set as an oscillation output (output terminal Out). By connecting the output terminals Vout1 and Vout2 to the differential circuit 50, it is possible to remove noise components (common mode noise) superimposed on both terminals in common.

  Therefore, even if the harmonic noise as described in the first embodiment is superimposed on the power supply voltage VDD, the noise superimposed on the waveforms output from the output terminals Vout1 and Vout2 can be further reduced. That is, by connecting the output terminals Vout1 and Vout2 to the differential circuit 50, it is possible to remove a noise component lower than the oscillation frequency (contributes to further lowering the jitter of the oscillation output). Note that a noise component higher than the oscillation frequency can be removed by a low-pass filter.

  FIG. 6 is a diagram illustrating an example of an output frequency analysis waveform when power supply noise similar to that in FIG. 3 is applied to the crystal oscillation circuit 2 according to the present embodiment. FIG. 6 shows the difference between waveforms output from the output terminals Vout1 and Vout2 by superimposing the power supply noise on the power supply voltage VDD.

  Comparing FIG. 4 and FIG. 6, it can be seen that the harmonic components other than the crystal resonator 31 are improved. As described above, the differential circuit 50 receives the output voltage of the signal inverting circuit 20 (voltage of the output terminal Vout1) and the reference voltage Vref (voltage of the output terminal Vout2), so that the crystal oscillation having a strong resistance to power supply noise. A circuit can be realized. Even if the crystal oscillation circuit 2 does not include a low-pass filter (resistor R03 and capacitor C01) and only has a differential configuration using the output terminals Vout1 and Vout2, an effect of noise reduction can be obtained.

[Third Embodiment]
Next, a third embodiment will be described in detail with reference to the drawings.

  FIG. 7 is a diagram illustrating an example of an internal configuration of the crystal oscillation circuit 3 according to the present embodiment. In FIG. 7, the same components as those in FIG. 5 are denoted by the same reference numerals, and the description thereof is omitted. In FIG. 7, the description of the resonance circuit 30 and the differential circuit 50 is omitted.

  The difference between the crystal oscillation circuit 2 and the crystal oscillation circuit 3 is that a variable resistor Rv is used in the reference voltage generation circuit 40a.

  By using the variable resistor Rv, the reference voltage Vref output from the output terminal Vout2 can be adjusted.

  As described in the second embodiment, the reference voltage Vref depends on the current determined by the resistor R05, the resistor R06, and the N-channel MOS transistor N05. Therefore, in theory (ideal value), the reference voltage Vref is equal to the common level of the voltage output from the output terminal Vout.

  However, actually, the relative accuracy of the N-channel MOS transistors N02 and N03 is different, and an offset current is generated. Furthermore, since the relative accuracy of the resistors R01 and R02 and the resistor R05 is different, it is difficult to make these resistance values coincide with the design values. Due to a problem caused by the accuracy (variation) of these semiconductor elements, a voltage difference occurs between the common level of the reference voltage Vref and the output voltage of the signal inverting circuit 20 (the voltage of the output terminal Vout1), which may be an obstacle to realizing low jitter. . Therefore, instead of the resistor R05, a variable resistor Rv is used to adjust the common level. As a result, the crystal oscillation circuit 3 with further reduced noise can be realized.

  Each disclosure of the cited patent documents and the like cited above is incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Further, various combinations or selections of various disclosed elements (including each element of each claim, each element of each embodiment, each element of each drawing, etc.) are possible within the scope of the claims of the present invention. It is. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

1-3 Crystal oscillation circuit 10, 300 Current source circuit 20, 200 Signal inversion circuit 30, 100 Resonant circuit 31 Crystal resonator 40, 40a Reference voltage generation circuit 50 Differential circuit 400 Low-pass filter circuit C01-C03 Capacitor CS01 Constant current source N01 to N05 N-channel MOS transistors R01 to R06 Resistor Rv Variable resistor

Claims (4)

A resonant circuit including a crystal unit;
A signal inverting circuit connected to the resonant circuit and including a differential pair;
A current source circuit for supplying a bias current to the differential pair;
A low-pass filter circuit connected between a voltage line for supplying power to the signal inversion circuit and the current source circuit and the signal inversion circuit, and having a cutoff frequency lower than a specific oscillation frequency of the crystal unit;
A crystal oscillation circuit comprising: The resonant circuit includes a first capacitor connected in series with the crystal resonator, and a feedback resistor connected in parallel with the crystal resonator,
The differential pair included in the signal inversion circuit includes a first MOS transistor and a second MOS transistor,
The first MOS transistor has a gate connected to a bias voltage source and a drain connected to one end of a first resistor. The second MOS transistor has a gate connected to one end of the feedback resistor and a drain connected to the feedback resistor. The other end of the resistor and one end of the second resistor are connected to each other, and the sources of the first and second MOS transistors are connected in common and connected to the current source circuit, respectively. The other end of the resistor 2 is connected to the low-pass filter circuit,
The current source circuit includes a third MOS transistor, a fourth MOS transistor, and a constant current source,
The gates of the third and fourth MOS transistors are connected to each other, the sources of the third and fourth MOS transistors are connected to a ground voltage, and the drain of the third MOS transistor is connected to the third MOS transistor. Connected to the gate and to the constant current source, the drain of the fourth MOS transistor is connected to the sources of the first and second MOS transistors,
The low-pass filter circuit includes a third resistor and a second capacitor,
One end of the third resistor is connected to the voltage line for supplying power, and the other end is connected to the first capacitor and the second resistor included in the second capacitor and the signal inverting circuit. 2. The crystal oscillation circuit according to claim 1, wherein the other end of the capacitor of 2 is connected to a ground voltage. A fourth resistor whose one end is connected to the voltage line, a drain is connected to the other end of the fourth resistor, a gate is connected to the gate and drain of the third MOS transistor, and a source is a ground voltage A reference voltage generation circuit including a fifth MOS transistor connected to
A differential circuit having a non-inverting input node connected to the drain of the second MOS transistor and an inverting input node connected to the drain of the fifth MOS transistor;
A crystal oscillation circuit according to claim 2.   4. The crystal oscillation circuit according to claim 3, wherein a resistance value of the fourth resistor is variable.

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