JP2013090049A - Oversampling circuit and communication device having the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce current consumption accompanying delay amount control operation, in an oversampling circuit for sampling multi-phase serial data with multi-phase clocks.SOLUTION: A serial data SDATA is changed to multi-phase serial data sdata0-sdata3 in a data delay unit 102, and oversampled with multi-phase clocks ck0-ck3 in an oversampling unit 103. In regard to the delay time at a data delay element 107 of the data delay unit 102, a phase difference of oversampling outputs of data generated in a calibration data generator unit 101 is detected by an oversampling phase detector unit 105, and a delay amount control digital signal dd_cnt is adjusted in a manner to obtain the phase difference to be a desired value. The delay amount control digital signal dd_cnt is converted into an analog delay amount generation signal d_cnt by a digital-to-analog converter unit 106, and is supplied to the data delay element 107.

Description

  The present invention relates to an oversampling circuit and a communication apparatus including the same.

  Many high-speed interface standards have been put into practical use in order to satisfy large capacity and high-speed data transmission. Many of them employ a serial transmission method. In serial transmission, data is transmitted based on a predetermined frequency. A clock of that frequency is superimposed on the transmitted data, and the data receiving unit extracts this clock from the received data and restores the received data based on the extracted clock signal. A circuit that performs these restoration operations is called a clock data recovery (CDR) circuit.

  In a conventional CDR circuit, a PLL (Phase Locked Loop) circuit is generally used, and an oscillation clock of a VCO (Voltage Controlled Oscillator) in the PLL circuit is controlled to be synchronized with a phase of received data, and is extracted as a reproduction clock. . The received data is accurately restored by latching the received data on the basis of the recovered clock.

  However, since the VCO transmission frequency increases with an increase in the data rate, a CDR circuit incorporating such a VCO increases disadvantages such as an increase in chip size, an increase in current consumption, and an increase in cost. In addition, since the wiring delay cannot be ignored due to the increase in speed, it is necessary to give sufficient consideration to the element arrangement and the wiring layout, and the design becomes more difficult. In addition, since the element arrangement and the wiring delay largely depend on the characteristics of the device to be used, it is necessary to redesign the layout for each process, the circuit reusability is lowered, and the development period is increased.

  As a CDR circuit that copes with such a problem, there is an oversampling CDR circuit (see Patent Document 1). In an oversampling CDR circuit, a multiphase clock having a phase shifted from a reference clock at equal intervals is generated, and input data is sampled at each phase by the multiphase clock to obtain oversampling data. The timing at which the logic is inverted is detected from the bit string of the oversampled data, and the clock and the data are reproduced based on the result. With this configuration, since the circuit other than the multi-phase clock generation unit can be configured with a digital circuit, the implementation is relatively easy.

  However, in the conventional oversampling CDR circuit, since the multiphase clock is generally generated using DLL (Delay Locked Loop), it is realized when the phase difference of the multiphase clock required by the system becomes small. Therefore, it is necessary to increase the operating speed of the delay element of the DLL to make the delay time minute, and there is a problem that current consumption increases. In addition, since the operating speed of the delay element of the DLL is limited, there is a problem that the phase difference of the multiphase clock required by the system may not be realized.

An oversampling circuit described in Patent Document 2 is an oversampling circuit that addresses this problem.
In Patent Document 2, for the purpose of performing oversampling while suppressing current consumption, delay elements that generate a delay amount according to a bias voltage are connected in series to form a delay line, and a plurality of delay lines are provided. Two bias voltages are provided to the delay elements of each delay line. The bias voltages are controlled so that the difference in transit time between the delay lines becomes a desired value, and a reference clock is input to the delay line. An oversampling circuit having a multiphase clock generation unit that generates a multiphase clock having a desired phase difference and an oversampling unit that samples serial data using the multiphase clock generated by the multiphase clock generation unit is disclosed. ing. However, in this oversampling circuit, since the number of delay lines of the multiphase clock generation unit and the number of delay elements constituting each delay line are large, compared to an oversampling circuit using a multiphase clock generated by a conventional DLL. A significant reduction in current consumption cannot be expected.

  In Patent Document 2, for the purpose of performing oversampling while suppressing current consumption, a delay line is configured by connecting delay elements that generate a delay amount according to a bias voltage in series, and a plurality of delay lines are provided. Two bias voltages to be applied to the delay elements of each delay line are provided, and the bias voltage is controlled so that a difference in transit time between the delay lines becomes a desired value, and serial data is input to the delay line. An oversampling circuit including a phase shift unit that generates multiphase serial data having a desired phase difference and an oversampling unit that samples the multiphase serial data generated by the phase shift unit with a reference clock is disclosed. ing. However, even in this oversampling circuit, the number of delay lines in the phase shift unit and the number of delay elements constituting each delay line are large. Therefore, the oversampling circuit consumes significantly more than an oversampling circuit using a multiphase clock generated by a conventional DLL. Current suppression cannot be expected.

  Therefore, the applicant of the present invention generates multi-phase serial data that generates multi-phase serial data that is a plurality of serial data with different phases by delaying serial data for the purpose of oversampling while suppressing current consumption. And an oversampling circuit that oversamples the multiphase serial data with a multiphase clock (Japanese Patent Application No. 2010-238541, filed on Oct. 25, 2010). According to this oversampling circuit, the number of delay elements can be reduced as compared with the oversampling circuit described in Patent Document 2, and accordingly, current consumption is expected to be suppressed.

  However, this oversampling circuit requires a delay amount control unit for both the multiphase serial data generation unit that generates the multiphase serial data and the multiphase clock generation unit that generates the multiphase clock. In general, the delay amount control is performed by a DLL including an analog circuit, and since the operation current is large, the effect of suppressing current consumption is insufficient.

  The present invention has been made to solve such problems, and its purpose is to reduce current consumption associated with delay amount control operations in an oversampling circuit that oversamples multiphase serial data with a multiphase clock. It is to be.

  The oversampling circuit of the present invention is a multiphase serial data generation unit that delays serial data and generates multiphase serial data that is a plurality of serial data having different phases, and the multiphase serial data generation unit generates the multiphase serial data An oversampling unit that samples multiphase serial data with a multiphase clock that is a plurality of clocks having different phases and generates oversampling data; an oversampling phase detection unit that detects a phase difference between the oversampling data; The oversampling circuit includes a delay time adjustment unit that adjusts the delay time of the multiphase serial data generation unit so that the phase difference detected by the oversampling phase detection unit becomes a desired value.

  According to the present invention, in an oversampling circuit that oversamples multiphase serial data with a multiphase clock, it is possible to reduce current consumption associated with a delay amount control operation.

It is a block diagram of the oversampling circuit of the 1st Embodiment of this invention. It is a timing chart which shows operation | movement of the oversampling circuit of the 1st Embodiment of this invention. It is a block diagram of the oversampling circuit of the 2nd Embodiment of this invention. It is a timing chart which shows operation | movement of the oversampling circuit of the 2nd Embodiment of this invention.

Embodiments of the present invention will be described below with reference to the drawings.
[First Embodiment]
<Block diagram of oversampling circuit>
FIG. 1 is a block diagram of an oversampling circuit according to the first embodiment of the present invention.

  The oversampling circuit of this embodiment includes a signal selection unit 100, a calibration data generation unit 101, a data delay unit 102, an oversampling unit 103, a parallelization unit 104, an oversampling phase detection unit 105, and a digital-analog conversion unit (DAC). ) 106.

  The signal selection unit 100 sends serial data SDATA to the data delay unit 102 during normal operation, and sends calibration data generated by the calibration data generation unit 101 to the data delay unit 102 during calibration.

  The data delay unit 102 is configured by connecting a plurality of data delay elements 107 in series, and delays input data by a plurality of different time periods according to the number of data delay elements 107 that pass the input data. Multi-phase serial data (here, four-phase serial data sdata0 to sdata3) that is a plurality of serial data having different phases is generated.

  As will be described in detail later, the data delay element 107 converts the delay amount control digital signal dd_cnt generated by the oversampling phase detection unit 105 into the voltage of the delay amount generation signal d_cnt analogized by the digital / analog conversion unit (DAC) 106. A corresponding transit time can be given. Since the data delay element 107 is well known, a detailed description thereof is omitted.

  The oversampling unit 103 includes a plurality of FFs (flip flops) 108, and the input multiphase serial data (sdata0 to sdata3) is input to the multiphase clock (here, the four-phase clocks ck0 to ck3). Oversample at the timing of. Oversampling data sd [15: 0] that is an output of the oversampling unit 103 has a phase difference of an oversampling clock (multiphase clock).

  The parallelizing unit 104 converts the input serial format oversampling data into a parallel format and outputs the parallel format. At this time, it is possible to adjust only the timing without changing the bus width and output it, or to output after performing serial / parallel conversion to reduce the data rate by widening the bus width immediately before or after the parallelizing unit 104 You can also.

  When this oversampling circuit is used in serial communication, OVSDATA [15: 0] output from the parallel processing unit 104 is input to a symbol data recovery unit (not shown) to recover data.

  When performing the calibration operation, the oversampling phase detection unit 105 generates the delay amount control digital signal dd_cnt based on the phase of the oversampling data generated by the oversampling unit 103. The delay amount control digital signal dd_cnt is converted into an analog delay amount generation signal d_cnt by the digital / analog conversion unit 106 and sent to the data delay unit 102.

<Oversampling circuit operation>
<< Specific examples of data and clock >>
Before describing the operation of the oversampling circuit of this embodiment, specific examples of data and clocks will be described. Here, a case where serial data with a data rate of 5 Gbps and 1 UI (Unit Interval) of 200 ps is oversampled at intervals of 25 ps (oversampling corresponding to 40 GHz) is taken as an example.

  In order to sample 5 Gbps serial data with 1 UI = 200 ps at intervals of 25 ps, 8 phases of 5 GHz oversampling clocks are required (200 ps ÷ 25 ps = 8).

  In this embodiment, the data delay unit 102 generates multiphase serial data (sdata0 to sdata3) corresponding to 5 GHz and 4 phases, and performs oversampling with an oversampling clock (ck0 to ck3) corresponding to 5 GHz and 2 phases. Thus, oversampling equivalent to 40 GHz is realized. Of course, the number of phases of the multiphase serial data and the selection of the oversampling clock are not limited to this, and can be freely selected. In this embodiment, 2.5 GHz and 4 phase clocks are used as oversampling clocks corresponding to 5 GHz and 2 phases, but the selection of this oversampling clock is not limited to this and can be freely selected.

<Operation of data delay unit>
The serial data SDATA is input to the data delay unit 102 and generates a delay of 125 ps by adding an oversampling interval of 25 ps and an oversampling clock phase difference of 100 ps per one data delay element 107. That is, the difference in data delay time between sdata [n] and sdata [n + 1] is 125 ps.

In general, if the oversampling interval is Tovs and the phase difference of the oversampling clock is Tsmp,
sdata [n + 1]-sdata [n] = Tovs + N * Tsmp (where n = 1, 2, 3, N is an integer).
In this embodiment, N = 1 is taken as an example, but N is not limited to this and can be freely selected.

<Adjustment of delay amount of data delay element>
The delay amount of the data delay element 107 is set by a delay amount control digital signal dd_cnt generated by the oversampling phase detector 105. Hereinafter, a calibration operation for determining the delay amount control digital signal dd_cnt will be described.

  As described above, during calibration, the signal selection unit 100 inputs the calibration data generated by the calibration data generation unit 101 to the data delay unit 102. This data pattern is a pattern having a characteristic that data edges (rising edge or falling edge of data) are uniformly generated (that is, random jitter is large).

  The data pattern of the input calibration data is converted into a multi-phase data pattern by the data delay unit 102, input to the oversampling unit 103, and oversampled. Thereby, oversampling data corresponding to the calibration data is generated.

  The oversampling phase detection unit 105 detects the phase difference of oversampling data. This phase difference is the sum of the phase difference of the multiphase serial data and the phase difference of the multiphase clock.

  As described above, since the data generated by the calibration data generation unit 101 is a pattern in which data edges appear uniformly, the phase difference of the oversampling data is detected (estimated) by counting the number of edges of each sampling data. can do. Since this phase difference detection method is a known technique (second embodiment of Japanese Patent Laid-Open No. 2008-66879), detailed description thereof is omitted.

  The oversampling phase detection unit 105 sets the delay amount control digital signal dd_cnt so that the phase difference of the detected oversampling data becomes a desired value. As a result, the difference between the phase difference of the multiphase serial data and the phase difference of the multiphase clock is detected and adjusted with the multiphase serial data. When a desired phase difference is obtained, the calibration operation is completed, and the operations of the circuits (calibration data generation unit 101 and oversampling phase detection unit 105) related to the calibration are stopped, and a standby state is entered.

  Thus, according to the oversampling circuit of the present embodiment, the phase difference of the multiphase serial data and the phase difference of the multiphase clock are detected together and adjusted with the multiphase serial data. Regardless of whether the misalignment occurs in the multiphase serial data generator or the multiphase clock generator, the delay amount can be controlled by both the multiphase serial data generator and the multiphase clock generator. As compared with the oversampling circuit to be performed, it is possible to reduce power consumption associated with the delay amount adjusting operation.

  Further, by reducing the analog delay amount control circuit, the current consumption can be suppressed. That is, in general, a delay amount control circuit is required to control the delay amount of the data delay element. The delay amount control circuit uses a dummy delay generator with the same characteristics to generate a reference phase difference, which is detected by a phase comparator, and the delay amount generation voltage is controlled so that the desired value is obtained. I do. However, this control method requires a plurality of delay lines and a phase comparator, which increases current consumption.

  In contrast, in this embodiment, the analog delay amount generation signal d_cnt is obtained by analogizing the delay amount control digital signal dd_cnt generated by the oversampling phase detection unit 105 by the digital / analog conversion unit 106. As described above, the delay amount generation signal d_cnt is generated by the digital-analog conversion unit, so that the analog delay amount control circuit which has been conventionally required can be reduced and the current consumption can be suppressed.

<Oversampling operation>
FIG. 2 is a timing chart showing the operation of the oversampling circuit of this embodiment. This timing chart is an operation in the case of oversampling serial data with a data rate of 5 Gbps and a UI of 200 ps at intervals of 25 ps.

  The serial data SDATA is input to the data delay unit 102 and passes through one to four data delay elements 107 having a delay time of 125 ps, thereby generating four multiphase serial data sdata [3: 0] at intervals of 125 ps. The The oversampling clocks ck0, 1, 2, and 3 are each 2.5 GHz and the phase difference between the clocks is 100 ps.

  For convenience of explanation, if 1 UI of SDATA is divided equally into 8 and a0 to a7 from the beginning, sd3 sampled with ck3 is sd3 sampled with ck3, sd2 sampled with ck2 was sampled with a1, and sdata1 was sampled with ck1 sd1 is a2, and sd0 obtained by sampling sdata0 with ck0 is a3. Similarly, a4 to a7 can be sampled by a combination of sdata0,1,2,3 and ck0,1,2,3.

[Second Embodiment]
<Block diagram of oversampling circuit>
FIG. 3 is a block diagram of an oversampling circuit according to the second embodiment of the present invention. In this figure, the same reference numerals as those in FIG. 1 are assigned to the same or corresponding parts as those in FIG. 1 (first embodiment).

  In the oversampling circuit of the present embodiment, a data delay unit 109 and a multiphase serial data selection unit 110 are provided instead of the data delay unit 102 in the oversampling circuit of the first embodiment. Further, the oversampling phase detection unit 105 is configured to generate the multiphase serial data selection signal d_sel and control the selection operation of the multiphase serial data selection unit 110.

  The data delay unit 109 is configured by connecting a plurality of data delay lines 111 in parallel, and is a multiphase serial data which is a plurality of serial data having different phases, each of which is a delay of the input serial data SDATA. s_1, s_2, ..., s_N are generated. At this time, the delay amount of each data delay line 111 is set to be slightly different, and the number of data delay lines 111 that can realize a desired delay amount is provided even if the delay characteristic of the data delay element 112 varies.

  The data delay line 111 is formed by connecting data delay elements 112 in a plurality of stages in series. Each of the data delay elements 112 generates a fixed delay amount, and a desired delay amount is realized in the data delay line 111 by combining a plurality of data delay elements 112 having different delay amounts. Since the data delay element 112 is well known, detailed description thereof is omitted.

  In the multi-phase serial data selection unit 110, four multi-phase serial data sdata0 to sdata3 according to the multi-phase serial data selection signal d_sel from the multi-phase serial data s_1, s_2,. Is output to the oversampling unit 103.

  The configuration and operation of oversampling of the oversampling unit 103 and the configuration and operation of the parallelizing unit 104 that processes the output thereof are the same as those of the oversampling unit 103 and parallelizing unit 104 in the first embodiment.

  When performing the calibration operation, the oversampling phase detection unit 105 generates a multiphase serial data selection signal d_sel based on the phase of the oversampling data generated by the oversampling unit 103, and multiphase serial data selection unit 110. Output to.

<Oversampling circuit operation>
A specific example of data and clock will be described as being the same as in the first embodiment.
<Operation of data delay unit and multiphase serial data selection unit>
The serial data SDATA is input to the data delay unit 109, and multiphase serial data s_1, s_2,... S_N having various delay amounts are generated. From the generated multi-phase serial data, the multi-phase serial data selection unit 110 selects multi-phase serial data that has a delay of 125 ps obtained by adding the over-sampling interval of 25 ps and the phase difference of the over-sampling clock of 100 ps. Is done. That is, the multiphase serial data selection unit 110 selects multiphase serial data such that the difference in data delay time between sdata [n] and sdata [n + 1] is 125 ps.

  Generally, if the oversampling interval is Tovs and the phase difference of the oversampling clock is Tsmp, sdata [n + 1]-sdata [n] = Tovs + N * Tsmp (where n = 1,2,3, N is an integer) ) In this embodiment, N = 1 is taken as an example, but N is not limited to this and can be freely selected.

<< Generation of multiphase serial data selection signal d_sel >>
A calibration operation for generating the multiphase serial data selection signal d_sel will be described.

  At the time of calibration, the signal selection unit 100 inputs calibration data generated by the calibration data generation unit 101 to the data delay unit 109. This data pattern is a characteristic pattern in which data edges (data rising or falling edges) occur uniformly.

  The calibration data is input to the data delay unit 109 and becomes N pieces of multiphase serial data s_1, s_2,..., S_N. In the multiphase serial data selection unit 110, preset serial data is selected, input to the oversampling unit 103 and oversampled, and oversampling data corresponding to the calibration data is generated.

  This oversampling data is input to the oversampling phase detector 105, and the phase difference of the oversampling data is detected using the same known technique as in the first embodiment. Then, the oversampling phase detection unit 105 sets the multiphase serial data selection signal d_sel so that the detected phase difference becomes a desired value.

  When a desired phase difference is obtained, the calibration operation is completed, and the operations of the circuits (calibration data generation unit 101 and oversampling phase detection unit 105) related to the calibration are stopped, and a standby state is entered. In addition, among the data delay lines 111 constituting the data delay unit 109, the operation of the delay line that generates the multi-phase serial data not selected by the multi-phase serial data selection unit 110 is stopped and put into a standby state.

  As described above, in the present embodiment, the data delay line 111 is provided in the data delay unit 109 so as to be equal to or larger than the number of multiphase serial data to be sampled by the oversampling unit 103, so that a plurality of polyphases including a desired delay amount are provided. Serial data is generated. Then, by generating a multi-phase serial data selection signal d_sel for selecting multi-phase serial data of an appropriate phase from the plurality of multi-phase serial data by calibration, a desired supply to the oversampling unit 103 is achieved. Multiphase serial data can be obtained. That is, by selecting an appropriate one from a plurality of multiphase serial data, the delay amount control circuit that has been conventionally required can be reduced and the current consumption can be suppressed.

<Oversampling operation>
FIG. 4 is a timing chart showing the operation of the oversampling circuit of this embodiment. This timing chart is an operation in the case of oversampling serial data with a data rate of 5 Gbps and 1 UI of 200 ps at intervals of 25 ps, as in the first embodiment.

  The serial data SDATA is input to the data delay unit 109 and passes through the data delay line 111, thereby generating multiphase serial data s_1 to s_N given various passing delays. The generated multi-phase serial data is selected by the multi-phase serial data selection unit 110 so as to have a desired phase difference of 125 ps, and multi-phase serial data sdata [3: 0] at intervals of 125 ps is generated.

  That is, for example, s_3 closest to sdata0 from multiphase serial data s_1 to s_4 obtained by delaying SDATA is selected and output as sdata0 by the multiphase serial data selection unit 110. Similarly, for sdata1, sdata2, and sdata3, the one closest to the ideal value is selected and output.

  Since the operation timing chart of the oversampling unit 103 is the same as the operation timing chart (FIG. 2) of the oversampling unit of the first embodiment, description thereof is omitted.

  DESCRIPTION OF SYMBOLS 101 ... Calibration data generation part, 102, 109 ... Data delay part, 103 ... Oversampling part, 105 ... Oversampling phase detection part, 106 ... Digital-analog conversion part, 107, 112 ... Data delay element, 110 ... Multiphase serial Data selection unit 111... Data delay line.

JP 2005-192192 A JP 2010-16545 A

Claims (4)

A multiphase serial data generation unit that delays serial data to generate multiphase serial data that is a plurality of serial data having different phases;
An oversampling unit that samples the multiphase serial data generated by the multiphase serial data generation unit with a multiphase clock that is a plurality of clocks having different phases, and generates oversampling data;
An oversampling phase detector for detecting a phase difference of the oversampling data;
A delay time adjusting unit that adjusts the delay time of the multiphase serial data generation unit so that the phase difference detected by the oversampling phase detection unit has a desired value;
An oversampling circuit. The oversampling circuit according to claim 1,
The multi-phase serial data generation unit includes a data delay element that changes a data delay amount with an analog voltage, and the delay time adjustment unit includes a unit that converts the phase difference into an analog voltage. An oversampling circuit for adjusting a delay time of the data delay element; The oversampling circuit according to claim 1,
The multi-phase serial data generation unit is configured to select a multi-phase serial data to be output from the data delay line, and a multi-phase serial data to be output from the data delay line. An oversampling circuit that generates a selection signal that causes the multiphase serial data selection unit to select multiphase serial data having a desired phase.   A communication apparatus comprising the oversampling circuit according to claim 1.

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