JP2010268365A - Oversampling circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an oversampling circuit capable of highly accurately correcting a phase in such a way that mutual phase differences between multi-phase clocks used for an oversampling type CDR circuit become at equal intervals. <P>SOLUTION: The oversampling circuit includes: a multi-phase clock generating section 200 for generating a multi-phase clock; a phase control section 205 for detecting a phase difference between multi-phase clocks and generating a phase control signal based on a result of the detection; and a phase adjusting section 203 which has delay circuits as many as the number of multi-phase clocks and adjusts a pass time of a signal inputted to each delay element based on the phase control signal for multi-phase clocks to adjust the phase difference between multi-phase clocks. Each delay circuit 300 is composed of a plurality of inverters in different sizes connected in series and inverters connected on post-stages of the plurality of inverters, and the pass time is adjusted based on a product of output resistance of one inverter selected from among the plurality of inverters and input capacitance of an inverter connected on the post-stage of the selected inverter. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an oversampling circuit used for a clock data recovery circuit.

Many high-speed interface standards have been put into practical use in order to satisfy large capacity and high-speed data transmission. Many of them employ a serial transmission method. In serial transmission, data is transmitted based on a predetermined frequency. A clock of that frequency is superimposed on the transmitted data, and the data receiving unit extracts this clock from the received data and restores the received data based on the extracted clock signal. A circuit that performs these restoration operations is called a clock data recovery (CDR) circuit.
In a conventional CDR circuit, a PLL (Phase Locked Loop) circuit is generally used, and an oscillation clock of a VCO (Voltage Controlled Oscillator) in the PLL circuit is controlled to be synchronized with a phase of received data, and is extracted as a reproduction clock. . The received data is accurately restored by latching the received data on the basis of the recovered clock.
However, as the data rate increases, the VCO transmission frequency also increases, and a CDR circuit incorporating such a VCO increases disadvantages such as an increase in chip size, an increase in current consumption, and an increase in cost. Further, the wiring delay cannot be ignored due to the higher speed.
Since the element arrangement and the wiring delay largely depend on the characteristics of the device to be used, it is necessary to redesign the layout for each process, the circuit reusability is lowered, and the development period is increased.

As a solution to this problem, an oversampling CDR circuit has been proposed (see Patent Document 1).
The data recovery circuit proposed in Patent Document 1 includes a multiphase clock generation unit, an oversampling unit, and a symbol data restoration unit.
The multiphase clock generation unit shifts a clock having a predetermined frequency generated from the reference clock REFCLK by a predetermined phase, and generates a multiphase clock having substantially equal phase phases.
The oversampling unit takes in the reception data Data using the multiphase clocks CK0 to CK11 supplied from the multiphase clock generation unit, and outputs oversampling data OVSD. The oversampling unit includes an oversampling number of flip-flops and a parallelizing unit that outputs input data in synchronization with one clock (for example, CK0).

The symbol data restoration unit includes a data selection unit, a DES (deserializer), a selection signal generation unit, and a comma detection unit, and restores the symbol data SYM from the oversampling data OVSD to generate a symbol clock SYMCLK.
That is, the selection signal generation unit instructs the capture phase of the oversampling data OVSD, and the data selection unit outputs restored data from the oversampling data OVSD according to the instruction from the selection signal generation unit. The comma detection unit detects a comma code inserted into the transfer data at a predetermined interval and outputs a comma detection signal. Furthermore, the deserializer converts the restored data supplied from the data selection unit into the symbol data SYM in parallel based on the comma detection signal, and also generates the symbol clock SYMCLK.

  However, in the conventional oversampling CDR circuit, the phase differences between the multiphase clocks need to be equally spaced, and if they are not equally spaced, malfunction may occur. However, the device characteristics vary locally even within the chip, and the parasitic capacitance on the wiring varies depending on the peripheral circuits. In recent years, transistor miniaturization has progressed, and as a result, characteristic variations between devices have also increased. For this reason, it is difficult to generate a multiphase clock having equidistant phases only by arranging the same device. Furthermore, as the serial transmission speed increases, the allowable value of the phase error of the multiphase clock is decreasing. Accordingly, there has been a problem that a circuit for correcting the phase in a wide range is required in order to create a multiphase clock having a phase difference of equal intervals used in an oversampling CDR circuit that performs high-speed and large-capacity serial transmission.

In Patent Document 2, for the purpose of generating oversampled data oversampled at equal intervals, a number of clocks having different phases are generated from a single clock, and clocks having an appropriate phase relationship are selected. It is disclosed that it is used as an oversampling clock. However, since the phase difference generated by the delay element varies depending on the manufacturing process and operating conditions, it is necessary to prepare a multiphase clock generated by a huge number of combinations in order to generate a multiphase clock having an appropriate phase relationship. This leads to an increase in circuit scale and design complexity.
Furthermore, Patent Document 2 also discloses that a plurality of clocks having different phases are generated from a single clock, and the phases are adjusted so as to have an appropriate phase relationship for the purpose of generating data oversampled at equally spaced phases. An adjustment method for adjustment and use in an oversampling circuit is disclosed. However, the problem of realizing a highly accurate and wide-range phase adjustment circuit has not been solved.

  In view of the above problems, an object of the present invention is to provide an oversampling circuit capable of correcting the phase with high accuracy so that the phase difference between the multiphase clocks used in the oversampling CDR circuit is equal. .

In order to solve the above problems, the invention of claim 1 is directed to an oversampling circuit for oversampling serial data using a multiphase clock, a multiphase clock generator for generating a multiphase clock, and the multiphase clock A phase control unit that detects a phase difference of the clock and generates a phase control signal based on the detection result; and a delay circuit corresponding to the number of the multi-phase clocks, and the multi-phase clocks are used as respective delay elements. A phase adjustment unit that adjusts a phase difference between the multiphase clocks by adjusting a transit time of the input signal based on the phase control signal, and each delay circuit has a size connected in series A plurality of inverters different from each other and an inverter connected to a subsequent stage of the plurality of inverters, and one inverter selected from the plurality of inverters And force resistance, and wherein the oversampling circuit for adjusting the transit time based on the product of the input capacitance of the inverter connected to the subsequent stage.
According to a second aspect of the present invention, in the oversampling circuit according to the first aspect, the delay circuit selects one inverter and adjusts the passage time by switching a signal path that passes through the plurality of inverters. The oversampling circuit according to claim 1 is characterized.
According to a third aspect of the present invention, in the oversampling circuit according to the first or second aspect, each delay element is connected in series in a plurality of stages, and one of a plurality of inverters is selected in each stage. And an oversampling circuit for adjusting the delay time.

  Since it is configured as described above, according to the present invention, the delay circuit can be selected by selecting a time constant value so that the passing time difference of each phase adjustment element as a delay circuit constituting the phase adjustment unit becomes a desired value. Oversampling circuit that can generate oversampling data sampled with multiphase clocks with equal phase differences, because the transit time of the can be set to a desired time difference and the phase of the multiphase clock can be adjusted at equal intervals Can provide.

1 is a diagram showing an oversampling data recovery circuit including a multiphase clock generation circuit according to a first embodiment. The figure explaining the phase adjustment element of a 1st Example. The figure explaining operation | movement of the phase adjustment element of a 1st Example. The figure explaining the phase adjustment element of a 2nd Example. The figure explaining the phase adjustment element of a 3rd Example. The figure explaining operation | movement of the phase adjustment element of a 3rd Example.

Embodiments of the present invention will be described below in detail with reference to the drawings.
FIG. 1 is a diagram showing an oversampling data recovery circuit including a multi-phase clock generation circuit according to the first embodiment of the present invention.
The data recovery circuit includes a multiphase clock generation unit 200, an oversampling unit 201, a symbol data restoration unit 202, a multiphase clock phase delay circuit 203, a phase adjustment data generation unit 204, and a phase control unit 205.
The phase adjustment unit 203 includes phase adjustment elements (delay elements) 300 corresponding to the number of multiphase clocks, and the phase difference between the multiphase clocks CK [7: 0] generated by the multiphase clock generation unit 200 is equal. A multi-phase clock CK_adj [7: 0] that is adjusted to have an interval and has a phase difference of equal intervals is output. The oversampling unit 201 takes in the received data using the multiphase clock supplied from the phase adjustment unit 203 and outputs oversampling data OVSD.
The symbol data restoration unit 202 generates symbol data SYM and a symbol clock SYMCLK from the oversampling data OVSD.

The oversampling unit 201 includes a sampling FF unit 206 and a parallelizing unit 207.
The sampling FF unit 206 samples the received data at the rising (or falling) timing of the multiphase clock.
The output D [7: 0] of the sampling FF unit 206 has a sampling clock phase difference.
The parallelizing unit 207 outputs oversampling data OVSD as parallel data synchronized with one clock of data D [7: 0] input with a phase difference.
The paralleling unit 207 can adjust and output only the timing without changing the bus width. However, the serializing conversion is performed immediately before or after the parallelizing unit 207 to increase the bus width and reduce the data rate. It can also be output.

The multiphase clock generation unit 200 generates a multiphase clock having a phase difference by a PLL (Phase Locked Loop) or a DLL (Delay Locked Loop).
This technique is well known and will not be described in detail.
The phase adjustment data generation unit 204 outputs a data pattern for the phase control unit 205 to detect the phase difference of the multiphase clock.
This data pattern is a pattern with a characteristic that data edges (rising edge or falling edge of data) are uniformly generated (that is, jitter is large).
The phase control unit 205 receives the oversampling data OVSD obtained by oversampling the data generated by the phase adjustment data generation unit 204 with the oversampling unit 201 using a multiphase clock.
As described above, the data generated by the phase adjustment data generation unit 204 is a pattern in which data edges appear uniformly, so that the phase difference of the multiphase clock can be estimated by counting the number of edges of each sampling data.
This phase difference estimation method is a known technique disclosed in Patent Document 2 described above.

The phase control unit 205 sends the phase adjustment signal PAdj to the phase adjustment unit 203 so that the estimated phase difference becomes an ideal phase difference.
The phase adjustment unit 203 generates a phase difference corresponding to the phase adjustment signal PAdj in each clock, and adjusts the phase difference of the multiphase clock.
The phase adjustment unit 203 receives the multiphase clock from the multiphase clock generation unit 200 and switches the passage time of the phase adjustment element 300 according to the phase control signal PAdj input from the phase control unit 205, thereby changing the phase between the multiphase clocks. The phase difference can be adjusted.
When it is desired to delay only CK1 by X seconds, clocks other than CK1 may be set to pass through the phase adjustment element 300 in T seconds and CK1 may be set to pass through the phase adjustment element 300 in T + X seconds.

FIG. 2 is a diagram illustrating the phase adjusting element in the first embodiment.
As described above, according to the present invention, a multiphase clock is input to the multiphase clock phase delay circuit 203, and the phase adjustment element 300 in the multiphase clock phase delay circuit 203 generates a difference in transit time. The phase relationship of the phase clock is adjusted.
The phase adjustment element 300 has a structure in which two stages of CMOS inverters are connected in series, and the delay amount can be selected according to the phase control signal PAdj from the phase control unit 205.
In order to switch the passage time of the phase adjustment element 300, the CMOS has a size that is an integral multiple of the value of the time constant, which is the product of the output resistance of the first-stage CMOS inverter and the input capacitance of the second-stage CMOS inverter. A plurality of signal paths configured by inverter pairs are provided, and the transit time of the delay element can be switched to a desired value by switching the output signal in accordance with the phase control signal PAdj.

Details will be described below.
The phase adjusting element 300 includes an inverter group (INV0-3) connected in parallel and an inverter (INV4) connected in series therewith. INV0 to INV3 are switched by inverters that operate according to selection signals s [3: 0] and sb [3: 0]. The selection signal sb [3: 0] is an inverted signal of s [3: 0]. For example, when s [3: 0] = 0001, INV0 is selected.
As described in the description of FIG. 1, the phase adjustment element 300 generates a phase difference by switching the passage time from the input in to the output out.
Hereinafter, a method of changing the passage time from input to output in the phase adjustment element 300 will be described.
When only INV0 in FIG. 2 is selected and the input falls, the voltage Vx of X is expressed by Vx = Vdd (1-exp (−t / (Rx0 * Cx))). Here, Vdd is a power supply voltage, Rx0 is an output resistance of INV0, and Cx is an input capacitance of INV4.
The time T1 until Vx reaches the threshold voltage Vth of INV4 is T1 = Rx0 * Cx * ln (1 / (1-Vth / Vdd)), and K = ln (1 / (1-Vth / Vdd)) This can be expressed as T1 = Rx0 * Cx * K.

Similarly, if the output resistances of INV1 to INV3 are Rx1 to Rx3, the time T1 to T3 until Vx becomes Vth when only one of INV1 to INV3 is selected is also Tn = Rxn * Cx * K (n = 1, 2, 3). Rx0 * Cx is called a time constant.
Since the transit time of the phase adjusting element 300 depends on the time until Vx crosses the threshold voltage, the difference Tn−T0 between the transit time of INVn (n = 1, 2, 3) and the transit time of INV0 is Tn−T0. = (Rxn-Rx0) * Cx * K (n = 1, 2, 3).
In order to adjust the phase of the multiphase clock with high accuracy, it is required to change the passage time of the phase adjusting element minutely and linearly.
When the output resistance ratio is determined so that Rx3: Rx2: Rx1: Rx0 = 4: 3: 2: 1 in order to change the passage time difference of the phase adjusting element 300 linearly, T3-T0: T2-T0: T1- T0 = Rx3-Rx0: Rx2-Rx0: Rx1-Rx0 = 3: 2: 1 and the passing time difference of the phase adjusting element 300 can be changed linearly. At this time, the minimum value (1LSB) of the change amount is Rx0 * Cx * ln (1 / (1-Vth / Vdd)). The value of 1LSB can be designed according to the requirement of the phase accuracy of the multiphase clock.
If the size of each inverter is Mn (n = 0, 1, 2, 3), the output resistance is inversely proportional to the size of the inverter.
M3: M2: M1: M0 = 1/4: 1/3: 1/2: 1 = 3: 4: 6: 12.
In general, the ratio of inverter sizes when performing m-stage phase adjustment is Mm−1: Mm−2. . . : M1: M0 = 1 / (m-1): 1 / (m-2):. . . : 1/2: 1.

FIG. 3 is a diagram for explaining the operation of the phase adjusting element of the first embodiment.
FIG. 3A is a diagram showing the passage time of the phase adjusting element.
In order to describe a specific operation of the phase adjustment element 300 of FIG. 2, consider a case where the input voltage Vin decreases.
When Vin crosses the threshold voltage Vth of the first-stage inverter INVn (n = 0, 1, 2, 3) (the time at this time is 0), the voltage Vx of the output X of the first-stage inverter Stand up. Correctly a transitional change, Vx will begin to rise after a certain amount of delay. When Vx crosses the threshold voltage Vth4 of the inverter in the second stage, the output out decreases. The threshold voltages of the first-stage inverter INVn (n = 0, 1, 2, 3) are equal.

When the size ratio of each inverter is M3: M2: M1: M0 = 1/4: 1/3: 1/2: 1 = 3: 4: 6: 12, Vx is the value of the next inverter. The ratio of the time Tn (n = 0, 1, 2, 3) to reach the threshold voltage is T0: T1: T2: T3 = 1: 2: 3: 4.
Since the time difference in which the input voltage Vx of the second-stage inverter reaches the threshold voltage Vth4 of the second-stage inverter is equal to the passing time difference of the phase adjustment element 300, the output of the phase adjustment element when each inverter is selected When the time until the voltage reaches Vth is D0 to D3, the time difference passing through the phase adjustment element 300 is D1-D0 = K * Rx1 * Cx, D2-D0 = 2 * K * Rx1 * Cx, D3-D0 = 3 * K * Rx1 * Cx (where K = ln (1 / (1-Vth / Vdd))).
FIG. 3B is a diagram showing a difference in the passage time of the phase adjustment element 300 with respect to the phase selection signal.
The vertical axis represents the difference from the passage time of the phase adjustment element 300 of INV0, and the horizontal axis represents 4 bits of the delay selection signal.
By switching the inverter to be selected, the passage time of the phase adjusting element 300 can be selected.

FIG. 4 is a diagram for explaining the phase adjusting element of the second embodiment.
The overall configuration of the oversampling CDR circuit of the second embodiment is the same as that of FIG. 1, but the phase adjustment element 300 is different from that of the first embodiment.
The phase adjusting element of the second embodiment will be described. The phase adjustment element 300 includes four inverter pairs including two inverters connected in series, and a selector type inverter that can select an output connected to each subsequent stage of the inverter pair.
One of the outputs of INV0 to INV3 is selected as the output of the phase adjustment element 300 by the phase selection signals s [3: 0] and sb [3: 0] in the selector type inverter.
The selection signal sb [3: 0] is an inverted signal of s [3: 0]. For example, when s [3: 0] = 0001, the output of INV0 is selected as the output of the phase adjustment element.

A method of changing the passage time from input to output in the phase adjustment element 300 of this embodiment will be described.
The principle of changing the passage time from the input to the output of the phase adjustment element is basically the same as that of the phase adjustment element of the first embodiment.
When the output of INV0 in FIG. 4 is selected and the input falls, the voltage Vx0 of X0 is represented by Vx0 = Vdd (1-exp (−t / (Rx * Cx0))). Here, Vdd is a power supply voltage, Rx is an output resistance of INVX, and Cx0 is an input capacitance of INV0.
The time T1 until Vx0 becomes the threshold voltage Vth0 of INV0 is T1 = Rx * Cx0 * ln (1 / (1-Vth0 / Vdd)), and K = ln (1 / (1-Vth0 / Vdd)) This can be expressed as T1 = Rx * Cx0 * K.
Similarly, when the outputs of INV1 to INV3 are selected, if the input capacitances of INV1 to INV3 are Cx1 to Cx3, the times T1 to T3 until Vxn becomes Vthn are also Tn = Rx * Cxn * K (n = 1, 2,3).
Since the passing time of the phase adjusting element 300 depends on the time until Vx0 crosses the threshold voltage, the difference in the passing time of the phase adjusting element is Tn−T0 = (Cxn−Cx0) * Rx * K with respect to T0. (N = 1, 2, 3).

In order to adjust the phase of the multiphase clock with high accuracy, it is required to change the passage time of the phase adjusting element minutely and linearly.
When the ratio of the input capacitance is determined so that Cx3: Cx2: Cx1: Cx0 = 4: 3: 2: 1 in order to change the passage time difference of the phase adjusting element 300 linearly, T3-T0: T2-T0: T1- T0 = Cx3-Cx0: Cx2-Cx0: Cx1-Cx0 = 3: 2: 1 and the passing time difference of the phase adjusting element 300 can be changed linearly. At this time, the minimum value (1LSB) of the change amount is Rx * Cx0 * ln (1 / (1-Vth / Vdd)). The value of 1LSB can be designed according to the requirement of the phase accuracy of the multiphase clock.
If the size of each inverter is Mn (n = 0, 1, 2, 3), the output capacity is proportional to the size of the inverter.
M3: M2: M1: M0 = 4: 3: 2: 1 ratio.
In general, the ratio of inverter sizes when performing m-stage phase adjustment is Mm−1: Mm−2. . . : M1: M0 = m−1: m−2:. . . : 2: 1.

FIG. 5 is a diagram for explaining the phase adjusting element of the third embodiment.
The overall configuration of the oversampling CDR circuit of the third embodiment is the same as that of FIG. 1, but the phase adjustment element is different from that of the first and second embodiments.
The phase adjustment element in FIG. 5 has a configuration in which two phase adjustment elements in the first embodiment are connected in series.
The passage time of the first phase adjustment element is switched by the phase selection signals s [3: 0] and sb [3: 0]. Specifically, one of the outputs of INV0 to INV3 is selected as the output of the first phase adjustment element.
Similarly, the passage time of the subsequent phase adjustment element is switched by the phase selection signals s [7: 4] and sb [7: 4].
The phase selection signals s [7: 0] and sb [7: 0] are inverted signals. When s [7: 0] = 00010001, the output of INV0 is selected in the first stage and the output of INV4 is selected in the subsequent stage. Since the method for changing the passage time from the input to the output in the two phase adjusting elements 1 and 2 has been described in the first embodiment, a description thereof will be omitted.

FIG. 6 is a diagram for explaining the operation of the phase adjusting element of the third embodiment.
In this embodiment, the phase adjusting elements are connected in two stages in series.
FIG. 6A is a diagram illustrating the passage time of the phase adjusting element of the present embodiment.
The size of each inverter INV0-7 is represented by M0-7.
When M7: M6: M5: M4 = M3: M2: M1: M0 = 3: 4: 6: 12, the time difference passing through the phase adjusting elements 1 and 2 is the passing time D0 and INV4 when INV0 is selected. Based on the passage time F0 when selected, D3-D0: D2-D0: D1-D0 = F3-F0: F2-F0: F1-F0 = 3: 2: 1.
Further, if M7 = 4 * M3, M6 = 4 * M2, M5 = 4 * M1, and M4 = 4 * M0, the difference in the passing time of the phase adjusting element 1 and the passing time of the phase adjusting element 2 is quadrupled. As shown in FIG. 6, a 16-step transit time difference can be created.
FIG. 6B is a diagram showing a passing time difference of the phase adjustment element 1, the phase adjustment element 2, and the entire phase adjustment element with respect to the phase selection signal.
Compared with the passing time of the phase adjusting element 1, the passing time of the phase adjusting element 2 becomes a quarter, and the phase adjusting element as a whole can produce a 16-step passing time difference.

DESCRIPTION OF SYMBOLS 1 ... Phase adjustment element, 2 ... Phase adjustment element, 200 ... Multiphase clock generation part, 201 ... Oversampling part, 202 ... Symbol data restoration part, 203 ... Phase adjustment part, 203 ... Multiphase clock phase delay circuit, 204 ... Phase adjustment data generation unit, 205 ... Phase control unit, 206 ... Sampling FF unit, 207 ... Parallelization unit, 300 ... Phase adjustment element

JP 2005-192192 A JP 2008-66879 A

Claims (3)

In an oversampling circuit that oversamples serial data using a multiphase clock,
A multiphase clock generator for generating a multiphase clock;
A phase control unit that detects a phase difference of the multi-phase clock and generates a phase control signal based on the detection result;
There are delay circuits for the number of the multiphase clocks, and the multiphase clocks are adjusted between the multiphase clocks by adjusting the transit time of the signals input to the delay elements based on the phase control signals. A phase adjustment unit for adjusting the phase difference,
Each delay circuit includes a plurality of inverters of different sizes connected in series and an inverter connected to a subsequent stage of the plurality of inverters, and an output resistance of one inverter selected from the plurality of inverters, An oversampling circuit that adjusts a transit time based on a product of an input capacity of an inverter connected to a subsequent stage. The oversampling circuit according to claim 1,
2. The oversampling circuit according to claim 1, wherein the delay circuit selects one inverter by switching a signal path passing through the plurality of inverters and adjusts the passage time.   3. The oversampling circuit according to claim 1, wherein each delay element is connected in series in a plurality of stages, and one of a plurality of inverters is selected in each stage to adjust the delay time. A featured oversampling circuit.

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