JP2013089753A - Thin film transistor, thin film transistor array substrate, flexible display element, flexible display device, and manufacturing method of thin film transistor array substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor, a thin film transistor array substrate, a flexible display element, a flexible display device, and a manufacturing method of the thin film transistor array substrate which are suitable for the size increase.SOLUTION: A thin film transistor 200 formed in a flexible resin substrate 60 has a gate and channel integrally formed part 50 where a wire 10 where a part of or an entire peripheral surface is covered by a conductive material 20, an insulation film 30 covering the conductive material, and a thin film semiconductor 40 formed on the conductive material through the insulation film are integrally formed. The gate and channel integrally formed part 50 is provided on a surface or a predetermined position in the resin substrate, and first and second electrodes 70 and 80 are formed at both sides of the thin film semiconductor so as to connect therewith.

Description

  The present invention relates to a thin film transistor, a thin film transistor array substrate, a flexible display element, a flexible display device, and a method for manufacturing the thin film transistor array substrate, and in particular, a thin film transistor formed on a flexible resin substrate, a thin film transistor array substrate, a flexible display element, a flexible display device, and The present invention relates to a method for manufacturing a thin film transistor array substrate.

  Conventionally, flat panels such as LCD (Liquid Crystal Display), PDP (Plasma Display Panel), or organic EL (Electro-Luminescence), from home-use large TVs to PCs and mobile phones. Display is widespread. Conventionally, glass has been used as a substrate for these displays, but a lightweight and flexible plastic substrate is used to further increase the size and weight of the display, and improve storage and impact resistance. Is desired. Furthermore, if an extremely flexible plastic substrate is applied, it will be possible to realize various new displays such as a scroll-type display that can be freely rolled and carried, and a large screen-type display that does not require a projector. Become.

  However, when a plastic film or the like is used as a substrate, heat resistance and chemical resistance are greatly inferior to those of glass, and thus various restrictions arise in advancing the manufacturing process. In general, plastic is greatly deformed by heat, and when an electrode, a thin film transistor, and a pixel electrode are patterned by a conventional photolithography method, as the thermal process is repeated, misalignment occurs at the time of patterning, and the yield is greatly reduced. In particular, the larger the substrate, the greater the effect of substrate expansion and contraction, making it extremely difficult to apply to a large-screen flexible display. In addition, thermal deformation increases as the temperature rises, so when applying materials that require high-temperature processing to semiconductors, insulating films, etc., heating tends to be insufficient, which may lead to deterioration of properties or instability. There was also a problem. Furthermore, since the plastic material causes deterioration due to chemicals, it is difficult to apply the same material and manufacturing process as when a glass substrate is used.

  In order to deal with such problems, a method has been proposed in which a wiring pattern or a thin film transistor is formed on a glass substrate by a conventional manufacturing process, and the glass substrate is melted and bonded to the plastic substrate (for example, see Patent Document 1). As another technique, a transfer technique is also proposed in which a release layer is provided on a glass substrate, patterning is performed by a conventional technique on the glass substrate, and the glass substrate is bonded to a plastic substrate and then peeled off from the glass substrate (for example, Patent Document 2). ~ 5).

JP 2003-323132 A JP 2008-159934 A JP 2008-159935 A JP 2010-10185 A JP 2010-10186 A

  However, the method described in Patent Document 1 requires a chemical for melting the glass substrate, so that not only the plastic material that can be applied is limited, but also the process is complicated, so that high productivity cannot be obtained. was there.

  In addition, in the methods described in Patent Documents 2 to 5, a strong stress is generated in the electrode, the insulating film, the semiconductor layer, and the like when the film is peeled off. was there.

  Therefore, the present invention has been made in view of the above points, and is suitable for upsizing by introducing a process of forming a conductive wire in which an insulating film and a thin film transistor are formed and integrating with a resin as a substrate. Another object of the present invention is to provide a thin film transistor, a thin film transistor array substrate, a flexible display element, a flexible display device, and a method for manufacturing the thin film transistor array substrate.

In order to achieve the above object, a thin film transistor according to one embodiment of the present invention is a thin film transistor formed over a flexible resin substrate,
A wire in which part or all of the peripheral surface is covered with a conductive material;
An insulating film covering the conductive material;
A thin film semiconductor formed on the conductive material through the insulating film, and a gate-channel integrated formation portion integrally formed;
The gate / channel integrated forming portion is provided at a predetermined position on or inside the surface of the resin substrate, and is formed by connecting first and second electrodes to both sides of the thin film semiconductor.

  The wire may have a configuration made of a non-conductive material.

  A plurality of the thin film semiconductors may be formed along the extending direction of the wires.

  The insulating film may cover the entire circumference of the wire, and one thin film semiconductor may be formed in the circumferential direction of the wire.

A thin film transistor array substrate according to another aspect of the present invention includes a pixel electrode formed in a matrix on a flexible resin substrate,
And the thin film transistor provided corresponding to each of the pixel electrodes.

A flexible display element according to another aspect of the present invention includes the thin film transistor array substrate,
A flexible resin substrate disposed to face the thin film transistor array substrate;
Between the resin substrate and the thin film transistor array substrate, a pixel disposed corresponding to the pixel electrode is provided.

A method of manufacturing a thin film transistor array substrate according to another aspect of the present invention is a method of manufacturing a thin film transistor array substrate having pixel electrodes arranged in a matrix on a flexible resin substrate and thin film transistors provided corresponding to the pixel electrodes. There,
A gate insulating film forming step of forming an insulating film around a wire in which a part or the whole of the periphery is covered with a conductive material;
A channel forming step of forming a channel by forming a thin film semiconductor so as to cover the position where the conductive material exists on the insulating film, and a gate-channel integrated formation portion in which the gate and the channel are integrally formed A gate / channel integrated formation process for manufacturing;
A resin substrate forming step of forming a resin substrate by curing a fluid-like resin so that the gate-channel integrated formation portion is disposed at a predetermined position on the surface or inside of the resin substrate;
An electrode forming step of forming first and second electrodes at positions on both ends of the thin film semiconductor.

  In the resin forming step, the fluid-like resin may be cured in a state where both ends of the gate / channel integrated forming portion are fixed and fixed at the predetermined position.

The resin substrate forming step includes: a first resin substrate layer forming step of forming a first resin substrate layer up to a height at which the gate / channel integrated forming portion is disposed;
A positioning step of disposing the gate / channel integrated forming portion on the resin substrate;
A second resin substrate layer forming step of forming a second resin substrate layer so as to fill the gate / channel integrated formation portion,
The electrode forming step may include an opening forming step of forming openings at both ends of the thin film semiconductor of the resin substrate, and the first and second electrodes may be formed so as to fill the openings.

  According to the present invention, it is possible to provide a thin film transistor, a thin film transistor array substrate, a flexible display element, and a flexible display device with few wiring defects even when a flexible substrate is used.

It is the figure which showed an example of the thin-film transistor and thin-film transistor array substrate which concern on Embodiment 1 of this invention. FIG. 1A is a cross-sectional view of the thin film transistor and the thin film transistor array substrate according to the first embodiment. FIG. 1B is a plan view of the thin film transistor and the thin film transistor array substrate according to the first embodiment. It is the figure which showed an example of the thin-film transistor and thin-film transistor array substrate which concern on Embodiment 2 of this invention. FIG. 2A is a cross-sectional view of the thin film transistor and the thin film transistor array substrate according to the second embodiment. FIG. 2B is a plan view of the thin film transistor and the thin film transistor array substrate according to the second embodiment. It is sectional drawing which showed an example of the thin-film transistor and thin-film transistor array substrate which concern on Embodiment 3 of this invention. It is sectional drawing which showed an example of the thin-film transistor and thin-film transistor array substrate which concern on Embodiment 4 of this invention. 1 shows one system for disposing a gate / channel integrated part in a resin substrate layer. FIG. 5A is a diagram showing a state in which a plurality of gate / channel integrated forming portions are arranged in parallel and both ends are fixed by a fixing jig. FIG. 5B is a diagram showing a state in which the resin material 63a is poured. FIG. 5C is a diagram showing a state where the resin substrate layer 63 is formed. It is the figure which showed one system for arrange | positioning a gate-channel integrated formation part on the resin substrate layer. FIG. 6A is a view showing a state in which the gate / channel integrated formation portion is arranged on the resin material. FIG. 6B is a diagram showing a state in which the resin material 63a is completely cured. It is explanatory drawing of the installation method of the gate channel integrated formation part using an auxiliary wire. It is the figure which showed a series of processes of the 1st step of the manufacturing method of the thin-film transistor 203 which concerns on Embodiment 4, and a thin-film transistor array substrate. FIG. 8A is a diagram illustrating an example of a resin material supply process. FIG. 8B is a diagram showing an example of the first resin substrate layer forming step. FIG. 8C is a diagram illustrating an example of the first resin substrate layer extraction process. FIG. 8D is a view showing an example of a first resin substrate layer via hole forming step in the method for manufacturing the thin film transistor 203 and the thin film transistor array substrate according to the fourth embodiment. It is the figure which showed a series of processes of the 2nd step of the manufacturing method of the thin-film transistor which concerns on Embodiment 4, and a thin-film transistor array substrate. FIG. 9A is a diagram showing an example of a resist removal process. FIG. 9B is a diagram showing an example of a wiring wire installation process. FIG. 9C is a diagram showing an example of the fine electrode forming process. FIG. 9D is a diagram showing an example of the resin material supply for the second resin substrate layer. It is the figure which showed a series of processes of the 3rd step of the manufacturing method of the thin-film transistor which concerns on Embodiment 4, and a thin-film transistor array substrate. FIG. 10A is a diagram illustrating an example of a second resin substrate layer forming process. FIG. 10B is a diagram showing an example of the second resin substrate layer extraction step. FIG. 10C is a diagram showing an example of the second resin substrate layer via hole forming step. FIG. 10D is a diagram showing an example of the resist removal process. It is the figure which showed a series of processes of the last step of the manufacturing method of the thin-film transistor and thin-film transistor array substrate which concern on Embodiment 4. FIG. 11A is a diagram showing an example of the second resin substrate layer microelectrode forming step. FIG. 11B is a diagram showing an example of the pixel electrode film forming process. FIG. 11C is a diagram illustrating an example of the pixel electrode patterning process. FIG. 11D is a diagram showing an example of the resist removal process. It is the top view which transparently showed the process of Drawing 8 (c) and (d) and Drawing 9 (a) and (b) from the upper surface. FIG. 12A is a plan view of the first resin substrate layer removal step. FIG. 12B is a plan view of the first resin substrate layer via hole forming step to the resist removing step. FIG.12 (c) is a top view of the wiring wire installation process. It is the top view which showed the process of FIG.9 (c) from the upper surface. FIG. 13A is a plan view showing a conductive film forming step in the first half of the fine electrode forming step. FIG. 13B is a plan view showing a conductive film forming step in the latter half of the fine electrode forming step. It is the figure which showed the process until a via hole formation. FIG. 14A is a plan view of the first resin substrate layer removal step similar to FIG. FIG. 14B is a plan view and a sectional view of the via hole forming step. It is the top view which showed a series of processes which connect a fine electrode and a wire for wiring. FIG. 15A is a diagram showing a conductive film forming step. FIG. 15B is a plan view and a cross-sectional view of the fine electrode forming step. FIG.15 (c) is the top view and sectional drawing which showed the wire installation process for wiring. It is the figure which showed an example of the thin-film transistor and thin-film transistor array substrate which concern on Embodiment 5 of this invention. It is the figure which showed an example of the thin-film transistor and thin-film transistor array substrate which concern on Embodiment 6 of this invention.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

Embodiment 1
FIG. 1 is a view showing an example of a thin film transistor and a thin film transistor array substrate according to Embodiment 1 of the present invention. FIG. 1A is a cross-sectional view of the thin film transistor and the thin film transistor array substrate according to the first embodiment, and FIG. 1B is a plan view of the thin film transistor and the thin film transistor array substrate according to the first embodiment.

  The thin film transistor array substrate means a drive-side substrate that does not include the display element of the flexible display element. Therefore, in the following description, the thin film transistor array substrate may be referred to as a back plane of the flexible display element. .

  1A and 1B, the thin film transistor 200 and the thin film transistor array substrate according to the first embodiment include a first wire 10, a conductive material 20, an insulating film 30, a thin film semiconductor 40, and a resin substrate layer. 60, a first fine electrode 70, a second fine electrode 80, a second wire 90, a conductive material 100, and a pixel electrode 120. The first wire 10, the conductive material 20, the insulating film 30, and the thin film semiconductor 40 constitute a gate / channel integrated forming unit 50. Further, the second wire 90 and the conductive material 100 constitute a wiring wire 110.

  In FIG. 1A, the conductive material 20 covers the first wire 10, and the insulating film 30 covers the conductive material 20. The conductive material 20 has a function of a gate of the thin film transistor 200, and the insulating film 30 has a function of a gate insulating film. A thin film semiconductor 40 is formed on the surface of the insulating film 30 at a position immediately above the conductive material 20. The thin film semiconductor 40 functions as a channel of the thin film transistor 200. The first wire 10, the conductive material 20, the insulating film 30, and the thin film semiconductor 40 are integrally formed, and are provided on the surface of the resin substrate layer 60. On both sides of the thin film semiconductor 40, a first fine electrode 70 and a second fine electrode 80 are formed on each side so as to cover both ends of the thin film semiconductor 40, and are electrically connected to the thin film semiconductor 40. Has been. The first fine electrode 70 and the second fine electrode 80 serve as a source electrode or a drain electrode. A pixel electrode 120 is formed on the surface of the resin substrate layer 60 outside the first fine electrode 70, and the first fine electrode 70 is formed so as to cover the end of the pixel electrode 120. It is connected to the. Inside the resin substrate layer 60, the second wire 90 is arranged extending in a direction orthogonal to the first wire 10, and the conductive material 100 covers the periphery of the second wire 90. The wire 110 for wiring is comprised. A second fine electrode 80 is connected to the conductive material 100 through a via hole 80a. In addition, two thin film transistors 200 are formed in FIG.

  In FIG. 1B, on the surface of the resin substrate layer 60, the first wire 10, the conductive material 20, and the insulating film 30 extend in the vertical direction. Two thin film semiconductors 40 are patterned on the insulating film 30 to form two islands. The first wire 10, the conductive material 20, the insulating film 30, and the thin film semiconductor 40 constitute the gate / channel integrated formation portion 50, and the two gate / channel integrated formation portions 50 are arranged in parallel, A pixel electrode 120 is formed. The first fine electrode 70 is formed in the lateral direction so as to connect the thin film semiconductor 40 and the pixel electrode 120. In addition, a wiring wire 110 is disposed inside the resin substrate layer 60 so as to penetrate the pixel electrode 120, the first and second fine electrodes 70 and 80, and the thin film semiconductor 40 in the lateral direction. (See FIG. 1A).

  Although the thin film transistor 200 according to the first embodiment has such a configuration, the gate / channel integrated formation portion 50 is integrally configured and can be disposed so as to be placed at a predetermined position of the resin substrate layer 60. Matching is extremely easy, and wiring can be easily formed.

  Next, the function of each component will be described.

  The first wire 10 is a member that serves as a base material for the gate / channel integrated forming portion 50. In the thin film transistor 200 according to the first embodiment, the gate / channel integrated formation unit 50 is configured by arranging the first wire 10 at the center and forming the conductive material 20, the insulating film 30, and the thin film semiconductor 40 around the first wire 10. Therefore, the gate and the channel can be configured separately from the resin substrate layer 60. The resin substrate layer 60 is made of a resin such as plastic and has a property that it is weak against heat and easily deformed. On the other hand, the insulating film 30 and the thin film semiconductor 40 need to be heated sufficiently for formation. When the insulating film 30 and the thin film semiconductor 40 are directly formed on the resin substrate layer 60, sufficient heating can be performed due to the heat resistance problem of the resin substrate layer 60. Can not.

  Therefore, in the present embodiment, the gate / channel integrated formation portion 50 is configured as a separate body from the resin substrate layer 60 and is configured to be sufficiently heat-processed. At that time, a base material for forming a gate and a channel is required, but the first wire 10 plays the role of such a base material.

  Although the 1st wire 10 may be comprised from various materials, for example, it may be comprised from nonelectroconductive materials, such as an insulator. Since the circumference | surroundings of the 1st wire 10 are coat | covered with the electroconductive material 20, it does not need to be an electroconductive material and can use a desired material. For example, an insulating wire may be used for the first wire 10. Further, the first wire 10 may be made of a material having lower conductivity than the wiring material, such as a piano wire made of various metals such as nickel and iron. Even when a material that is not highly conductive, such as a piano wire, is used, the conductive material 20 is required to have high conductivity at a wiring metal level such as gold, copper, and aluminum. Therefore, similarly to the case of using an insulating wire, the covering with the conductive material 20 is also performed.

  The first wire 10 is preferably made of a material having a lower coefficient of thermal expansion than the surrounding conductive film to be coated. For example, copper or aluminum that is relatively conductive and inexpensive is used for the wiring for the display, but rather than the first wire 10 itself made of those metal materials, for example, piano wire or piano wire. By preparing a wire having a low coefficient of linear expansion as the first wire 10 and coating the periphery of the first wire 10 with those metal materials, it is possible to achieve both a low coefficient of linear expansion and high conductivity. it can. This makes it possible to manufacture a highly reliable element with low circuit resistance and low performance degradation due to heat.

  Furthermore, in the case of a conductive wire using a metal, depending on the production process, oxidation of the metal surface or deterioration due to chemicals becomes a major issue. However, in the thin film transistor 200 according to the first embodiment, the two-layer structure of the first wire 10 and the conductive film 20 is excellent in chemical resistance, for example, in the conductive material formed on the surface according to the manufacturing process. Therefore, it is possible to deal with those problems sufficiently.

  As described above, the thin film transistor 200 according to the first embodiment employs a dual structure of the first wire 10 and the conductive film 20, so that both the first wire 10 and the conductive material 20 can be used and manufactured. It is configured to allow a wide range of material selection according to the process.

  The conductive material 20 serves as a gate electrode. As long as the conductive material 20 can be used as a wiring, various materials may be used. For example, a highly conductive metal material such as copper, aluminum, gold, and silver may be used. These metal materials are materials that have already been used as wiring metal materials, and can be suitably used for the conductive material 20. Note that the conductive material 20 may be configured to cover the entire circumference of the first wire 10 or may be configured to partially cover the first wire.

  Examples of the combination of the first wire 10 and the conductive material 20 include a piano wire whose surface is plated with copper.

  As the insulating film 30, various insulating materials can be used as long as they can function as a gate insulating film.

  The thin film semiconductor 40 serves as a channel for the thin film transistor 200. In FIG. 1, the thin film semiconductor 40 is provided on the upper surface, but can be provided at various positions as long as it is directly above the conductive material 20 with the insulating film 30 interposed therebetween.

  The thin film semiconductor 40 may be made of an organic semiconductor material, or may be made of an inorganic semiconductor material made of silicon or oxide.

  The resin substrate layer 60 is a flexible substrate layer made of resin, and may be made of, for example, a plastic substrate layer.

  The first fine electrode 70 and the second fine electrode 80 are electrodes that serve as a source electrode or a drain electrode. The first fine electrode 70 and the second fine electrode 80 are made of a conductive material. For example, you may comprise from a metal material. In FIG. 1A, the first fine electrode 70 is formed on the surface of the resin substrate layer 60 because the surfaces of the resin substrate layer 60 may be connected to each other. Since it is necessary to be connected to the conductive material 100 in the resin substrate layer 60, the via hole 80 a formed in the resin substrate layer 60 is filled.

  The wiring wire 110 is provided for wiring in the horizontal direction, and is configured such that the conductive material 100 covers the periphery of the second wire 90. The second wire 90 and the conductive material 100 may be made of the same material as the first wire 10 and the conductive material 20.

  Note that, unlike the first wire 10, the wiring wire 110 does not necessarily have to pay great attention to lowering the thermal expansion coefficient or the linear expansion coefficient, and uses a conductive wire using a wiring metal or the like. Is also possible. When a conductive wire made of a wiring metal or a conductive material equivalent to this is used, the conductive material 20 or 100 does not necessarily need to be coated.

  The pixel electrode 120 is an electrode for applying a voltage to the pixel, and may be composed of a conductive film. For example, as a display element used for a pixel, various elements can be used depending on applications, and a liquid crystal element, an organic EL (Electro-luminescence) element, an inorganic EL element, electronic ink, or an electronic powder fluid can be used. . In this embodiment, an example is given in which the display element is a liquid crystal element.

  According to the thin film transistor 200 and the thin film transistor array substrate according to the first embodiment, the gate / channel integrated formation unit 50 is configured as a separate body from the resin substrate layer 60, thereby enabling sufficient heat processing, and the resin substrate. By disposing on the surface of the layer 60, the thin film transistor 200 can be easily positioned and formed.

[Embodiment 2]
FIG. 2 is a view showing an example of a thin film transistor and a thin film transistor array substrate according to Embodiment 2 of the present invention. 2A is a cross-sectional view of the thin film transistor and the thin film transistor array substrate according to the second embodiment, and FIG. 2B is a plan view of the thin film transistor and the thin film transistor array substrate according to the second embodiment.

  2A, the thin film transistor 201 and the thin film transistor array substrate according to the second embodiment include a first wire 11, a conductive material 21, an insulating film 31, a thin film semiconductor 41, a resin substrate layer 61, and a first substrate. 1 fine electrode 71, second fine electrode 81, second wire 91, conductive material 101, and pixel electrode 121. Further, the first wire 11, the conductive material 21, the insulating film 31, and the thin film semiconductor 41 constitute a gate / channel integrated formation portion 51. Further, the second wire 91 and the conductive material 101 constitute a wiring wire 111.

  In FIG. 2A, a thin film transistor 201 according to the second embodiment includes a gate / channel integrated portion 51 including a first wire 11, a conductive material 21, an insulating film 31, and a thin film semiconductor 41. The thin film transistor 200 is different from the thin film transistor 200 according to the first embodiment in that the thin film transistor is disposed inside the thin film transistor 61. Correspondingly, the wiring wire 111 extending in the lateral direction is different from the first embodiment in that it is formed on the surface of the resin substrate layer 61. The pixel electrode 121 is formed on the surface of the resin substrate layer 61 in the same manner as the thin film transistor 200 and the thin film transistor array substrate according to the first embodiment. The first fine electrode 71 and the second fine electrode 81 are arranged inside the resin substrate layer 61 so as to cover both sides of the thin film semiconductor 41 and extend upward. The first fine electrode 71 is connected to the pixel electrode 121 on the surface of the resin substrate layer 61 through the via hole 71a, and the second fine electrode 81 is also on the surface of the resin substrate layer 60 through the via hole 81a. The conductive material 101 is connected.

  2B, on the surface of the resin substrate layer 61, there are two pixel electrodes 121 and two wiring wires 111 in which a part or the entire surface of the second wire 91 is covered with the conductive material 101. In FIG. A state in which the gate / channel integrated formation portion 51 is formed in the resin substrate layer 61 in the vertical direction so as to extend in the direction and to be orthogonal to the direction is shown. The two wiring wires 111 on the surface of the resin substrate layer 61 are disposed at both ends so as to sandwich the pixel electrode 121, and are disposed so as not to overlap each other.

  Since each component is the same as that of the first embodiment, each component is given the same reference numeral added to the reference symbol of the first embodiment, and the description thereof is omitted.

  Also in the thin film transistor 201 and the thin film transistor array substrate according to the second embodiment, the gate / channel integrated formation portion 51 can be configured separately from the resin substrate layer 61, and thus can be processed by heating sufficiently. It can be performed. Then, when the resin substrate layer 61 is formed, the thin film transistor 201 is easily formed in the resin substrate layer 61 by disposing the gate / channel integrated formation portion 51 so as to be embedded in the resin substrate layer 61. be able to.

  In addition, by providing a pixel including a display element and driving the pixel with the thin film transistor 201, a flexible display element having excellent characteristics by sufficient heating can be configured.

[Embodiment 3]
FIG. 3 is a cross-sectional view showing an example of a thin film transistor and a thin film transistor array substrate according to Embodiment 3 of the present invention.

  In FIG. 3, the thin film transistor 202 and the thin film transistor array substrate according to the third embodiment include a first wire 12, a conductive material 22, an insulating film 32, a thin film semiconductor 42, a resin substrate layer 62, and a first fine substrate. The electrode 72, the second fine electrode 82, the second wire 92, the conductive material 102, and the pixel electrode 122 are included. Further, the first wire 12, the conductive material 22, the insulating film 32, and the thin film semiconductor 42 constitute a gate / channel integrated formation portion 52. Further, the second wire 92 and the conductive material 102 constitute a wiring wire 112.

  Since the configuration of the gate / channel integrated forming portion 52 is the same as that of the gate / channel integrated forming portions 50 and 51 according to the first and second embodiments, the description thereof is omitted.

  In the thin film transistor 202 and the thin film transistor array substrate according to the third embodiment, the gate / channel integrated formation portion 52 is formed inside the resin substrate layer 62, and the pixel electrode 122 is formed on the surface of the resin substrate layer 62. In this respect, the wiring wire 112 in which a part or the whole of the periphery of the second wire 92 is covered with the conductive material 102 is the resin substrate layer 62, although it is similar to the thin film transistor 201 and the thin film transistor array substrate according to the second embodiment. Is different from the thin film transistor 202 and the thin film transistor array substrate according to the second embodiment.

  As described above, the gate / channel integrated forming portion 52 and the wiring wire 112 may be arranged inside the resin substrate layer 62. Accordingly, the first fine electrode 72 is connected to the upper pixel electrode 122 through the via hole 72a, and the second fine electrode 82 is connected to the lower conductive material 112 through the via hole 82a.

  According to the thin film transistor 202 and the thin film transistor array substrate according to the third embodiment, since only the pixel electrode 122 is formed on the surface of the resin substrate layer 60, it is possible to increase the pixel area, increase the pixel definition, and the aperture ratio. It is advantageous for improving brightness.

[Embodiment 4]
FIG. 4 is a cross-sectional view showing an example of a thin film transistor and a thin film transistor array substrate according to Embodiment 4 of the present invention.

  In FIG. 4, the thin film transistor 203 and the thin film transistor array substrate according to the fourth embodiment include a first wire 13, a conductive material 23, an insulating film 33, a thin film semiconductor 43, a resin substrate layer 63, and a first fine substrate. The electrode 73, the second fine electrode 83, the second wire 93, the conductive material 103, and the pixel electrode 123 are included. Further, the first wire 13, the conductive material 23, the insulating film 33, and the thin film semiconductor 43 constitute a gate / channel integrated formation portion 53. Further, the second wire 93 and the conductive material 103 constitute a wiring wire 113.

  Since the configuration of the gate / channel integrated forming portion 53 is the same as that of the gate / channel integrated forming portions 50 to 52 according to the first to third embodiments, the description thereof is omitted.

  In FIG. 4, the thin film transistor 203 and the thin film transistor array substrate according to the fourth embodiment includes a wiring wire 113 in which a gate / channel integrated formation portion 53 and a second wire 93 are covered with a conductive material 103 inside the resin substrate layer 63. Is the same as the thin film transistor 202 and the thin film transistor array substrate according to the third embodiment, except that the wiring wire 113 is provided above the gate / channel integrated formation portion 53 instead of below. This is different from the thin film transistor 202 and the thin film transistor array substrate according to the third embodiment.

  As described above, the wiring wire 113 may be provided inside the resin substrate layer 63 above the gate / channel integrated formation portion 53. The pixel electrode 123 is formed on the surface of the resin substrate layer 63 as in the first to third embodiments. With such an arrangement, both the first fine electrode 73 and the second fine electrode 83 extend upward through the via holes 73a and 83a. The first fine electrode 73 is the pixel electrode 123, and the second fine electrode 83 is conductive. Connected to material 103.

  Also in the thin film transistor 203 and the thin film transistor array substrate according to the fourth embodiment, since only the pixel electrode 123 exists on the surface of the resin substrate layer 63, it is possible to increase the pixel area, increase the pixel definition, the aperture ratio, The configuration is advantageous for improving the luminance.

  As described above, the thin film transistors 200 to 203 and the thin film transistor array substrate according to the first to fourth embodiments have been described. However, in any of the first to fourth embodiments, the insulating films 30 to 33 and the thin film semiconductors 40 to 43 are resin substrate layers 60 to 63. Are formed directly on the first wires 10 to 13 before being integrated with each other, and all have the same functions only in the configuration.

  With the configuration of the thin film transistor array substrate according to Embodiments 1 to 4, in any display element driven by the thin film transistors 200 to 203, for example, by driving a liquid crystal, an organic EL, an inorganic EL, electronic ink, an electronic powder fluid, or the like in the pixel portion. A flexible display element can be configured. As the structure, any structure used in an existing element including a counter electrode can be applied.

  In order to configure a flexible display element using the thin film transistor array substrate according to the first to fourth embodiments, a flexible resin substrate is disposed so as to face the thin film transistor array substrate, and between the two substrates, the thin film transistor Each pixel may be formed at a position corresponding to the pixel electrodes 120 to 123 of the array substrate. Each pixel may include a display element as described above. In addition, a flexible display device can be configured by further including a drive circuit that drives and controls the thin film transistors 200 to 203 of the thin film transistor array substrate.

  As the wires 10 to 13 and 90 to 93, elongated metal wires, bundles of metal wires, or bundles of fibers using a polymer material can be used. Since it is possible to obtain conductivity by coating with a material or the like, it is not particularly necessary to use a material exhibiting conductivity for the wire itself.

  The cross sections of the wires 10 to 13 and 90 to 93 may be any shape such as a circle or an ellipse, and in particular, the upper part such as a rectangle is flat to form the thin film semiconductors 40 to 43 on the upper part. Is desirable.

  In general, the thickness of the wires 10 to 13 and 90 to 93 can be freely changed in a range of about 5 μm to 500 μm depending on the definition of the pixel. However, in order to easily perform processing such as patterning. Is preferably in the range of about 10 to 50 μm. Although not shown in FIGS. 1 to 4, the pixel area is made very small, and the pixel electrodes 120 to 123 are not formed on the surface of the resin substrate layer 60, using the thick wires 10 to 13 whose top is flat, When the pixel electrodes 120 to 123 are also formed on the wires 10 to 13, the wires 10 to 13 and 90 to 93 of 500 μm or more may be used depending on the size of the pixel. Note that when applied to a screen-type large display or the like, it is effective to use a wire of 500 μm or more without forming a pixel electrode on the wire.

  The wires 10 to 13 and 90 to 93 are preferably made of, for example, a material used for a piano wire and not easily cut. As materials for the wires 10 to 13 and 90 to 93, any material of organic / inorganic or a hybrid structure thereof may be used, but it is preferable to apply a material that hardly causes thermal expansion and contraction. Alternatively, a conductive wire coated with an insulating film may be used.

  The conductive materials 20 to 23 and 100 to 103 formed on the wires 10 to 13 and 90 to 93 can ensure high conductivity by covering the entire surfaces of the wires 10 to 13 and 90 to 93. However, it is only necessary to cover the portion where the thin-film semiconductors 40 to 43 are directly above, and it is not always necessary to cover the entire surface. In the case where the conductive materials 20 to 23 and 100 to 103 cover only a part of the wires 10 to 13 and 90 to 93, the materials of the wires 10 to 13 and 90 to 93 may be polymer materials or conductive materials. It is preferable to apply a low metal or the like.

  For example, in the case where a highly insulating material such as a polymer resin is used for the wires 10 to 13 and 90 to 93, the conductive materials 20 to 23 and 100 to 103 are formed so that the conductivity is made only at a desired position. It becomes possible to reduce the capacitance due to the intersection of the wires 10 to 13 and 90 to 93 to which conductivity is imparted, or to electrically insulate adjacent TFTs (Thin Film Transistors). In addition, the degree of freedom in designing the thin film semiconductors 40 to 43 can be increased.

  Further, the wire material may be different for each of the wires 10 to 13 and 90 to 93, and the shape may be different for each of the wires 10 to 13 and 90 to 93. In order to suppress this, it is preferable to use the same material as much as possible.

  However, regarding the wire in which the thin film semiconductors 40 to 43 and the electrodes 70 to 73 and 80 to 83 are not formed on the upper side, the wire itself is made of a highly conductive material when the capacity at the crossing portion of the wires is not a problem. Therefore, it is not always necessary to form the surrounding conductive materials 20 to 23 and 100 to 103.

  Examples of the materials of the conductive materials 20 to 23 and 100 to 103 formed on the wires, and the wires 10 to 13 and 90 to 93 in the case where the conductive materials are made of a highly conductive material include gold, silver, copper, and zinc. , Aluminum, Iridium, Calcium, Nickel, Beryllium, Magnesium, Molybdenum, Rhodium, Titanium, Tantalum, Platinum, Chromium, Tungsten, Iron, Tin, etc. and their alloys (eg Nichrome, Constantan, Brass etc.), ITO, There are oxides such as ZnO and IGZO, conductive polymer materials such as polyethylenedioxythiophene, carbon nanotubes, fullerenes, graphene and other carbon materials, and composite materials thereof. It is not limited to the material, it is possible to apply various materials

  The insulating films 30 to 33 formed on the wires 10 to 13 are all coating techniques and printing methods such as dipping, spray coating, bar coating, die coating, flexographic printing, ink jet, sputtering, CVD, vacuum deposition, and spin coating. Although it can be formed by using a film forming technique, when the conductive materials 20 to 23 coated on the wires 10 to 13 are metal, they can be formed by anodic oxidation of the metal. Moreover, you may heat-process in the formation process of the insulating films 30-33 as needed.

As the material of the insulating film 30 to 33, for _example, it is possible to use an inorganic material such as _{SiO 2, SiN, Ta 2 O} 5, Al 2 O 3. Organic materials include light irradiation, methacrylic resin, acrylic resin, urethane resin, polyvinyl chloride, vinyl acetate, phenolic resin, epoxy resin, cellulose resin, polyethylene, polyethylene terephthalate, Polybutylene terephthalate, polypropylene, melamine resin, polyester, polyvinyl butyral, polyvinyl carbazole, polyvinyl acetate, polycarbonate, polystyrene, polysulfone, polyethersulfone, polyarylate, polyetherimide, acetylcellulose, silicone resin, fluororesin, or these Copolymers and modified products can be used. It is also possible to apply a polymer resin other than these, and any material having insulating properties can be applied.

  The thickness of the insulating films 30 to 33 can be freely set in view of the dielectric constant and insulating properties of the material, but is controlled in the range of about 20 to 300 nm in order to realize low voltage driving. It is preferable. The insulating films 30 to 33 do not need to completely cover the wires 10 to 13 and 90 to 93, but at least the portions where the thin film semiconductors 40 to 43 and the fine electrodes 70 to 73 and 80 to 83 are formed It is important to ensure sufficient insulation.

As materials for the thin film semiconductors 40 to 43, inorganic semiconductor materials such as silicon semiconductors (poly-Si, a-Si, etc.), GaAs, oxide semiconductors (InGaZnO, ZnO, GaZnO, ZnO, InO), pentacene, anthracene, etc. Any semiconductor material such as an organic semiconductor can be used, and heat treatment at a high temperature may be performed in the formation process.
For example, in the case of using InGaZnO, it is desirable to perform thermal annealing at about 300 ° C. in order to ensure high mobility and On-Off ratio, but before integration with the resin substrates 60 to 63, By performing the annealing, it is possible to prevent the resin substrates 60 to 63 from being deformed. In addition, as a simple method for heating the semiconductor, a method of heating with a heater, an oven, or the like can be given, but any heating method such as a method of irradiating with an ultraviolet ray or an excimer laser can be applied.

  Note that when a plastic substrate with low heat resistance is used, the influence of thermal expansion and contraction is large, and when forming the insulating films 30 to 33 and the thin film semiconductors 40 to 43, depending on the plastic material, the metal wiring can be heated even at 100 ° C. Pattern deviation is likely to occur. Even if the resin substrates 60 to 63 are attached to glass and heated, patterning defects may occur when heated to about 120 ° C. On the other hand, in this method, since the wires 10 to 13 and 90 to 93 can be directly heated before being integrated with the resin substrates 60 to 63, direct damage to the resin substrate layers 60 to 63 is prevented. Is possible. That is, a heat treatment at 120 ° C. or higher can be performed.

  As a method for forming an organic semiconductor material, a vacuum deposition method or a spin coating method can be cited as representative methods, but other methods include die coating, bar coating, silk screen printing, resin letterpress printing, flexographic printing, gravure printing, It can be formed by using any coating / film forming technique such as offset printing, printing technique including ink jet method and the like.

  In addition, as a method for forming an inorganic semiconductor, a sputtering method, a CVD method, a vacuum deposition method, and the like are typical, but when using a material that can be applied and formed, dipping, spray coating, bar coating, die coating, It can be formed using any coating technique, printing technique, and film forming technique such as flexographic printing, inkjet, and spin coating.

  The fine electrodes (source / drain electrodes) 80 to 83 formed on the thin film semiconductors 40 to 43 are not necessarily formed before being integrated with the resin material, but may be partially formed in advance. It becomes.

  In the first to fourth embodiments, the wires 10 to 13 on which the thin film semiconductors 40 to 43 are formed and the wiring wires 110 to 113 arranged in the vertical direction are connected by the fine electrodes 70 to 73 and 80 to 83. However, it can also be set as the structure made to contact on the thin film semiconductors 40-43. At that time, the magnitude of contact resistance can be controlled via a metal, or thermocompression bonding can be performed using a conductive polymer material.

  When connecting to the gate / channel integrated forming portions 50 to 53, the wiring wires 110 to 113 and the pixel electrodes 120 to 123 by the fine electrodes 70 to 73 and 80 to 83, patterning is performed on the resin substrate layers 60 to 63. However, since the heat treatment is about the resist curing temperature and the number of patterning times can be greatly reduced, pattern defects due to misalignment can be achieved compared to the conventional technique of stacking and patterning on a plastic substrate. Can be suppressed.

  In addition, in the case of a device configuration in which a metal or an organic conductive polymer is patterned on the resin substrate layer 60 instead of the second wires 90 to 93, the insulating films 30 to 33 and the thin film are compared with the conventional method. Since the semiconductors 40 to 43 are formed in advance, the number of times of patterning on the plastic substrate is greatly reduced and high temperature processing of the semiconductor and the insulating film is not required, so that pattern defects due to misalignment are greatly suppressed. it can.

  As the material of the resin substrate layers 60 to 63, methacrylic resin, acrylic resin, urethane resin, polyvinyl chloride, vinyl acetate, phenol resin, epoxy resin, cellulose resin formed by light irradiation, thermal curing or reaction curing. , Polyethylene, polyethylene terephthalate, polybutylene terephthalate, polypropylene, melamine resin, polyester, polyvinyl butyral, polyvinyl carbazole, polyvinyl acetate, polycarbonate, polystyrene, polysulfone, polyethersulfone, polyarylate, polyetherimide, acetylcellulose, silicone resin, A fluororesin, or a copolymer or modified body thereof may be used, but the material is not limited to these materials.

  Next, a method for integrally forming the gate / channel integrated formation portion 53 with the resin substrate layer 63 in the thin film transistor 203 and the thin film transistor array substrate according to the fourth embodiment will be described. Hereinafter, the thin film transistor 203 and the thin film transistor array according to the fourth embodiment will be described as an example, but such a method can be commonly used in the first to fourth embodiments.

  FIG. 5 shows one method for disposing the gate / channel integrated forming portion 53 in the resin substrate layer 63.

  FIG. 5A is a diagram showing a state in which a plurality of gate / channel integrated forming portions 53 are arranged in parallel and both ends are fixed by a fixing jig 140. Although not shown in FIG. 5A, the gate / channel integrated forming portion 53 and the fixing jig 140 are installed in a container capable of holding a fluid. At this time, it is desirable to apply appropriate tension to the wire 53.

  FIG. 5B is a diagram showing a state in which the resin material 63a is poured. As shown in FIG. 5B, the resin material 63a is poured and supplied in a state where the gate / channel integrated forming portions 53 are arranged in parallel, and the gate / channel integrated forming portion 53 is immersed in the resin material 63a. The resin material 63a is in the form of a fluid such as a liquid before curing, and a resin material 63a having a property of being cured by heating or irradiation with ultraviolet rays is used.

  When supplying the resin material 63a, in order to control the thickness of the resin substrate 60, it is desirable to pour the resin material 63a in a state where the row of gate / channel integrated formation portions 53 is placed in a sealed container. At that time, it is possible to suppress the mixing of bubbles into the resin by evacuating the sealed container.

  FIG. 5C is a diagram showing a state where the resin substrate layer 63 is formed. As shown in FIG. 5C, the supplied resin material 63 a is cured by heating, ultraviolet irradiation, or the like to form a resin substrate layer 63. With the formation of the resin substrate layer 63, the gate / channel integrated formation portion 53 is embedded in the resin substrate layer 63.

  FIG. 5 shows an example in which resin is poured from above the row of gate / channel integrated forming portions 53. For example, the row of gate / channel integrated forming portions 53 is placed in a mold and the resin material 63a is inserted. A method of injecting may also be used. As the mold, any generally used technique such as a box-shaped container provided with an inlet for the resin material 63a can be applied.

  When pouring the resin material 63a, a method of controlling the film thickness using, for example, die coating, bar coating, screen printing, gravure printing, offset printing, resin relief printing, ink jet method, flexographic printing method, spin coating method, or the like is used. However, the present invention is not limited thereto, and any coating technique can be applied. It is also possible to use a method of controlling the film thickness by spin coating after pouring the resin material.

  As a method for curing the resin material 63a, a thermosetting method, a photocuring method using ultraviolet rays or visible light, a reaction curing method, or the like can be used, but it is important to use an optimum method according to the resin material 63a. It is.

  For example, when an ultraviolet curable resin is used, it is necessary to use a container that transmits ultraviolet rays, such as glass or quartz, even when forming in a container. Moreover, when performing thermosetting, the resin material 63a can be hardened | cured exactly by using a heater as a container or applying a container with favorable heat conductivity.

  FIG. 6 is a view showing one method for disposing the gate / channel integrated forming portion 53 on the resin substrate layer 63.

  FIG. 6A is a view showing a state in which the gate / channel integrated forming portion 53 is arranged on the resin material 63a. As shown in FIG. 6A, the gate / channel integrated forming portion 53 having both ends fixed by the fixing jig 140 is disposed on the upper part of the resin material 63a that has not been completely cured or has not been completely cured. If the resin material 63a has a certain degree of hardness and is not completely cured, the gate / channel integrated formation portion 53 can be placed on the resin material 63a as it is.

  FIG. 6B is a diagram showing a state in which the resin material 63a is completely cured. As shown in FIG. 6B, the resin material 63 a is cured to form the resin substrate layer 63, thereby integrating the resin substrate layer 63 and the gate / channel integrated formation portion 53. At this time, a part of the gate / channel integrated forming portion 53 can be pushed into the substrate by a method of applying a suitable pressure using a roller or the like on the top or a method of applying a pressure to the fixing jig 140. Note that if a stronger pressure is applied to the gate / channel integrated formation portion 53, the gate / channel integrated formation portion 53 can be embedded in the substrate layer.

  Further, FIG. 6 shows a method of disposing the resin material 63a not completely cured, but as another method, a thin resin is applied on a flexible substrate, and the method of FIG. It is also possible to integrate with the gate / channel integrated forming portion 53 by curing the resin in the same manner as in FIG.

  Further, after integration by the method of installing on the upper part of the substrate shown in FIG. 6, the gate / channel integrated formation portion 53 can be embedded in the resin substrate layer 60 by further applying and curing the resin material 63a on the upper part. It becomes possible. At this time, the second layer resin material 63a to be embedded does not necessarily need to use the same material as the first layer resin material 63a. In forming the second layer, all the techniques used for forming the first layer described with reference to FIG. 5 can be applied.

In the above-described example, the method of applying two types of resin materials 63a in the first layer and the second layer has been described. However, a plurality of resin materials 63a may be stacked in each layer as necessary. In addition, an inorganic film such as SiO ₂ or SiN can be laminated between the resin layers 63a to add an effect of increasing the barrier property. In this case, since only the resin material 63a in the portion where the gate / channel integrated forming portion 53 is disposed is not completely cured, the lower layer resin material 63a may be completely cured. However, it is important to select the resin material 63a appropriately so that expansion and contraction due to heat or the like does not occur as much as possible when the upper resin material 63a is cured.

  In order to vertically arrange the gate / channel integrated forming portion 53 and the wire 93 that are perpendicular to each other, all combinations of the methods for arranging the one-stage gate / channel integrated forming portion 53 described in FIGS. 5 and 6 are applied. As the simplest method, there is a method in which the gate / channel integrated forming portion 53 and the wire 93 are vertically arranged at a desired distance, and a resin is poured into the method. At this time, in order to control the vertical height, it is desirable to apply appropriate tension to the gate / channel integrated forming portion 53 and the wire 93 using the fixing jig 140 shown in FIGS. The fixing jig 140 may be used individually for the upper wire 93 and the lower gate / channel integrated forming portion 53, but it is desirable to fix the upper and lower thicknesses with one fixing jig in order to accurately control the upper and lower thicknesses. .

  Alternatively, after the upper wire 93 and the lower gate / channel integrated portion 53 are pushed into the resin material 63a that is not completely cured, the resin material 63a is cured and integrated. Also in this case, the fixing jig 140 may be used individually at the upper stage and the lower stage, or may be used either by fixing with a single fixing jig.

  In addition, the method of embedding in two stages is also effective. In this method, first, the lower gate / channel integrated formation portion 53 is embedded in the resin substrate layer 63 by any of the methods described with reference to FIGS. Next, the upper wiring wire 113 is placed on the resin substrate layer 63 and, if necessary, via holes 73a and 83a are formed before and after that by a photolithography method, etc., and the thin film semiconductor 43 and the wiring wire 113 are finely formed. Connection is made by wiring 83. Further, the upper wiring wires 113 and the gate / channel integrated formation portion 53 are integrated with the resin substrate layer 63 by embedding the upper wiring wires 113 in the resin substrate layer 63 by the method described with reference to FIG.

  Even in the case where only the lower stage is embedded and the upper stage is installed on the resin substrate 63, it can be integrated by combining the methods described with reference to FIGS. At that time, via holes 73a and 83a may be formed or connected by fine wiring by a photolithography method or the like as needed during each step.

  As described above, the gate / channel integrated formation portion 53 and the wiring wire 113 can be installed in the resin substrate layer 60 by various methods. In FIGS. 5 and 6, the example of the fourth embodiment is described, but the same applies to the first to third embodiments.

  FIG. 7 is a view for explaining an installation method of the gate / channel integrated forming portion 53 using the auxiliary wire. In FIG. 7, the auxiliary wire 130 is installed orthogonal to the gate / channel integrated forming portion 53, and both ends of the gate / channel integrated forming portion 53 and the auxiliary wire 130 are fixed by the fixing jig 141.

  The auxiliary wire 130 is a wire made of a non-conductive material. As shown in FIG. 7, when fixing the gate / channel integrated forming portion 53, the non-conductive auxiliary wire 130 is installed in a direction perpendicular to the gate / channel integrated forming portion 53 and fixed by the fixing jig 141. In this case, the influence of in-plane distortion of the wire 13 due to the non-uniformity of the tension can be reduced, so that it is possible to integrate with higher accuracy.

  Here, the auxiliary wire 130 does not need to be a single step, and may be installed above and below the gate / channel integrated formation portion 53 or may be passed through the gate / channel integrated formation portion 53 in a woven manner. Further, it is not always necessary to install the gate / channel integrated forming portion 53 in the vertical direction.

  In FIG. 7, the example in which the auxiliary wire 130 is used for the gate / channel integrated forming portion 53 has been described. However, the present invention can be similarly applied to the wiring wire 113. Further, the present invention can be similarly applied to the gate / channel integrated forming portions 50 to 52 and the wiring wires 110 to 112 of the first to third embodiments.

  The pixel electrodes 120 to 123 are patterned on the resin substrate layers 60 to 63 in a step after the gate / channel integrated formation portions 50 to 53 are integrated with the resin substrate layers 60 to 63. As a patterning method, etching using a photolithography method or lift-off is generally used. However, when an electrode material that can be applied and formed is used, direct patterning may be performed using a printing technique including ink jet. Is possible.

  The pixel electrodes 120 to 123 are formed in the thin film semiconductors 40 to 43 on the gate / channel integrated formation portions 50 to 53 in the step before the gate / channel integrated formation portions 50 to 53 are integrated with the resin substrate layers 60 to 63. It is also possible to form it directly in a different region. In addition, only the pixel electrodes 120 to 123 are formed in advance on the gate / channel integrated formation portions 50 to 53, and are disposed on or inside the resin substrate layers 60 to 63 in the same manner as in FIGS. It is also possible. Both approaches are effective for reducing the patterning process.

  Here, when the pixel electrodes 120 to 123 are embedded in the resin substrate layers 60 to 63 together with the gate / channel integrated formation portions 50 to 53, the resin substrate layer 60 is formed by forming an opening in the upper portion thereof by dry etching or the like. It can be easily exposed on the surface of ~ 63.

  In addition, the thin electrodes 40 to 43 and the fine electrodes 70 to 73 and 80 to 83 on the gate / channel integrated formation portions 50 to 53 and the transparent electrodes are connected, and the transparent electrodes are formed by etching using a photolithography method. Since the formation of a via hole and a patterning step are required, the resin substrate layers 60 to 63 may be expanded and contracted due to heating, but sufficient tension is applied by the fixing jigs 140 and 141 to maintain the wiring pattern with high accuracy. It becomes possible to make it.

  Next, a method for manufacturing the thin film transistor 203 and the thin film transistor array substrate according to the fourth embodiment will be described with reference to FIGS.

  FIG. 8 is a diagram showing a series of steps in the first stage of the method of manufacturing the thin film transistor 203 and the thin film transistor array substrate according to the fourth embodiment. Note that the same reference numerals as those in the fourth embodiment are given to the respective components, and the description thereof is omitted.

  FIG. 8A is a view showing an example of a resin material supply process of the method for manufacturing the thin film transistor 203 and the thin film transistor array substrate according to the fourth embodiment. In the resin material supplying step, the gate / channel integrated forming portion 53 formed by forming the conductive material 23, the insulating film 33, and the thin film semiconductor 43 around the wire 13 is disposed in the resin molding container 150, and dispenser The resin material 63a is poured into the resin forming container 150 using 160, and supplied. The supply amount of the resin material 63a is such that the gate / channel integrated formation portion 53 can be immersed in the resin material 63a.

  FIG. 8B is a diagram illustrating an example of the first resin substrate layer forming step of the method of manufacturing the thin film transistor 203 and the thin film transistor array substrate according to the fourth embodiment. In the first resin substrate layer forming step, the resin material 63 a is cured to form a first resin substrate layer 63 b that is the first layer of the resin substrate layer 63.

  FIG. 8C is a diagram illustrating an example of a first resin substrate layer extraction step in the method for manufacturing the thin film transistor 203 and the thin film transistor array substrate according to the fourth embodiment. In the first resin substrate layer taking-out step, the first resin substrate layer 63b formed in the resin molding container 150 is taken out.

  FIG. 8D is a view showing an example of a first resin substrate layer via hole forming step in the method for manufacturing the thin film transistor 203 and the thin film transistor array substrate according to the fourth embodiment. In the first resin substrate layer via hole forming step, a photoresist 170 is formed on the surface of the first resin substrate layer 63b, and the first resin substrate layer 63b is etched from the opening 171 to form a via hole 83a.

  FIG. 9 is a diagram illustrating a series of steps in the second stage of the method of manufacturing the thin film transistor and the thin film transistor array substrate according to the fourth embodiment.

  FIG. 9A is a view showing an example of a resist removal process of the method for manufacturing the thin film transistor and the thin film transistor array substrate according to the fourth embodiment. In the resist removal step, the resist 170 is removed from the surface of the first resin substrate layer 63b. A via hole 83a is formed on the surface of the first resin substrate layer 63b so as to reach the thin film semiconductor 43 of the integrated gate / channel portion 53.

  FIG. 9B is a diagram illustrating an example of a wiring wire installation step in the method for manufacturing the thin film transistor and the thin film transistor array substrate according to the fourth embodiment. In the wiring wire installation step, the wiring wire 113 in which the conductive material 103 is coated around the wire 93 is installed on the surface of the first resin substrate layer 63b.

  FIG. 9C is a diagram illustrating an example of a microelectrode forming process of the method for manufacturing the thin film transistor and the thin film transistor array substrate according to the fourth embodiment. In the fine electrode forming step, the fine electrode 83 to be the source electrode or the drain electrode is formed by filling the via hole 83a with a conductive material. Thus, one end of the thin film semiconductor 43 and the wiring wire 113 are connected.

  FIG. 9D is a diagram illustrating an example of the resin material supply for the second resin substrate layer in the method for manufacturing the thin film transistor and the thin film transistor array substrate according to the fourth embodiment. In the second resin substrate layer resin material supplying step, the first resin substrate layer 63b is again disposed in the resin molding container 150, and the resin material 63c is poured into the resin molding container 150 using the dispenser 161, Resin material 63c is supplied to the surface of one resin substrate layer 63b.

  FIG. 10 is a diagram showing a series of steps in the third stage of the method of manufacturing the thin film transistor and the thin film transistor array substrate according to the fourth embodiment.

  FIG. 10A is a diagram illustrating an example of a second resin substrate layer forming step of the method for manufacturing the thin film transistor and the thin film transistor array substrate according to the fourth embodiment. In the second resin substrate layer forming step, the supplied resin material 63c is cured, and a second resin substrate layer 63d serving as a second layer is formed on the first resin substrate layer 63b.

  FIG. 10B is a diagram illustrating an example of a second resin substrate layer extraction step in the method for manufacturing the thin film transistor and the thin film transistor array substrate according to the fourth embodiment. In the second resin substrate layer extraction step, the formed second resin substrate layer 63d is extracted from the resin molding container 150.

  FIG. 10C is a diagram illustrating an example of a second resin substrate layer via hole forming step of the method for manufacturing the thin film transistor and the thin film transistor array substrate according to the fourth embodiment. In the second resin substrate layer via hole forming step, a photoresist 172 is formed on the surface of the second resin substrate layer 63d, and the second resin substrate layer 63d and the first resin substrate layer 63b are etched from the opening 173. A via hole 73a is formed in the etched portion of the second resin substrate layer 63d and the first resin substrate layer 63b.

  FIG. 10D is a view showing an example of a resist removing process of the method for manufacturing the thin film transistor and the thin film transistor array substrate according to the fourth embodiment. In the resist process, the resist 172 is removed from the surface of the second resin substrate layer 63d. A via hole 73a reaching the other end of the thin film semiconductor 43 is formed on the surface of the second resin substrate layer 63d.

  FIG. 11 is a diagram illustrating a series of steps in the final stage of the method for manufacturing the thin film transistor and the thin film transistor array substrate according to the fourth embodiment.

  FIG. 11A is a view showing an example of a second resin substrate layer microelectrode formation step in the method of manufacturing the thin film transistor and the thin film transistor array substrate according to the fourth embodiment. In the second resin substrate layer fine electrode forming step, the via hole 73a is filled with a conductive material, and the fine electrode 73 is formed.

  FIG. 11B is a diagram illustrating an example of a pixel electrode film forming process of the method for manufacturing the thin film transistor and the thin film transistor array substrate according to the fourth embodiment. In the pixel electrode film forming step, a conductive film 123a to be the pixel electrode 123 is formed on the surface of the second resin substrate layer 63d. As a film formation method, various film formation methods such as a CVD method, an evaporation method, and a sputtering method can be used.

  FIG. 11C is a diagram illustrating an example of a pixel electrode patterning step in the method for manufacturing the thin film transistor and the thin film transistor array substrate according to the fourth embodiment. In the pixel electrode patterning step, a photoresist 174 is formed on the conductive film 123a, etching is performed from the opening 175, the conductive film 123a is patterned and divided, and the pixel electrode 123 is formed.

  FIG. 11D is a view showing an example of a resist removing process of the method for manufacturing the thin film transistor and the thin film transistor array substrate according to the fourth embodiment. In the resist removal process, the photoresist 174 is removed from the surface of the pixel electrode 123. The pixel electrode 123 is formed corresponding to each pixel and the thin film transistor 203.

  In the series of processes described with reference to FIGS. 8 to 11, the fine electrodes 73 and 83 functioning as a source electrode or a drain electrode can be patterned by wet etching or dry etching using a photoresist. The resin materials 63a and 63c can be appropriately cured according to the material of the resin materials 63a and 63c, such as thermosetting, photocuring, and reaction curing.

  Next, the state of the upper surface of the steps shown in FIGS. 8C and 8D and FIGS. 9A to 9C will be described with reference to FIGS.

  FIG. 12 is a plan view transparently showing the steps of FIGS. 8C and 8D and FIGS. 9A and 9B from the upper surface. FIG. 12A is a plan view of the first resin substrate layer taking-out step shown in FIG. FIG. 12A shows a state in which the gate / channel integrated formation portion 53 is embedded and installed in the first resin substrate layer 63b. The wire 13, the conductive material 23, and the insulating film 33 penetrate the inside of the first resin substrate layer 63 b in the vertical direction, and the thin film semiconductor 43 is formed in an island shape in a partial region on the insulating film 33. .

  FIG. 12B is a plan view of the first resin substrate layer via hole forming step to the resist removing step shown in FIGS. 8D and 9A. FIG. 12B shows a state in which a via hole 83a is formed in the first resin substrate layer 63a. The via hole 83a is formed so as to have an overlapping region 43a with the thin film semiconductor 43 so that the via hole 83a can be connected to the thin film semiconductor 43 when filled with a conductive material.

  FIG.12 (c) is a top view of the wiring wire installation process shown in FIG.9 (b). FIG. 12C shows a state in which the wiring wire 113 is installed on the surface of the first resin substrate layer 63a.

  FIG. 13 is a plan view showing the process of FIG. 9C from above. FIG. 13A is a plan view showing a conductive film forming step in the first half of the fine electrode forming step shown in FIG. FIG. 13A shows a state in which a conductive film 83b is formed on the entire surface of the first resin substrate layer 63b. Thus, when the fine electrode 83 is formed, the conductive film 83b is initially formed on the entire surface of the first resin substrate layer 63b. When the conductive film 83b is formed, the via hole 83a is filled with the conductive film 83b, and a via wiring portion of the fine electrode 83 is formed.

  FIG. 13B is a plan view showing a conductive film forming step in the latter half of the fine electrode forming step shown in FIG. FIG. 13B shows a fine electrode 83 formed by patterning the conductive film 83 b so as to cover the upper portion of the via hole 83 a and to reach the wiring wire 113. Thereby, the fine electrode 83 is electrically connected to the wiring wire 113. As described above, the fine electrode 83 and the wiring wire 113 can be connected by accurately patterning. Here, the wiring wire 113 is installed after the via hole 83a is formed. However, the wiring wire 113 can be installed before the via hole 83a is formed if necessary. In FIGS. 9B and 9C, the process of FIG. 13A is omitted, but actually, the fine electrode 83 is formed through the process of FIG. 13A. It is formed.

  As described above, according to the method of manufacturing the thin film transistor 203 and the thin film transistor array substrate according to the fourth embodiment, the process of forming the insulating film 33 and the thin film semiconductor 43 generally involving a high-temperature heating process is preceded by the gate / channel integrated formation portion 53. Thus, it is possible to perform the heating process at a sufficient heating temperature, and thereafter, the gate / channel integrated forming portion 53 can be incorporated into the resin substrate layer 63 by a relatively low temperature process. Furthermore, the number of times of patterning on the substrate can be greatly reduced. Therefore, it is possible to significantly suppress heat deformation and the like in the resin substrate layer 63, and a large-sized thin film transistor array substrate having good operating characteristics can be manufactured.

  Next, another method for connecting the thin film semiconductor 43 and the wiring wire 113 will be described with reference to FIGS. 14 and 15.

  FIG. 14 is a diagram showing a process up to formation of a via hole. FIG. 14A is a plan view of the first resin substrate layer removal step similar to FIG. In FIG. 14A, a gate / channel integrated forming portion 53 is provided through the inside of the first resin substrate layer 63b. The thin film semiconductor 43 is formed in an island shape on a part of the insulating film 33.

  FIG. 14B is a plan view and a sectional view of the via hole forming step. In the plan view on the left side and the cross-sectional view on the right side of FIG. 14B, a state in which the via hole 83a is formed in the first resin substrate layer 63a is shown. As shown in the plan view and the cross-sectional view of FIG. 14B, the via hole 83 a has an overlap region 43 a with the thin film semiconductor 43 in plan view, and has a depth that reaches the thin film semiconductor 43 in depth. It is formed. The via hole 83a is formed using a photoresist or the like.

  FIG. 15 is a plan view showing a series of steps for connecting the fine electrode and the wiring wire. FIG. 15A is a diagram showing a conductive film forming step. In the conductive film forming step, the conductive film 83b is formed so as to cover the entire surface of the first resin substrate layer 63b. At this time, the via hole 83a is filled with the conductive film 83b, and a via wiring is formed.

  FIG. 15B is a plan view and a cross-sectional view of the fine electrode forming step. In the fine electrode formation step, as shown in the plan view of FIG. 15B, the conductive film 83b is patterned using a photoresist or the like, and the fine electrode 83 is formed so as to cover a region slightly larger than the via hole 83a. Is done.

  FIG.15 (c) is the top view and sectional drawing which showed the wire installation process for wiring. In the wiring wire installation step, the wiring wire 113 is installed on the surface of the fine electrode 83. When the wiring wire 113 is in contact with the upper surface of the fine electrode, both are connected.

  Here, in order to accurately connect the conductive material 103 of the wiring wire 113 and the fine electrode 83, the upper surface of the fine electrode 83 or the surface of the conductive material 103 contains conductive resin or conductive fine particles. You may use the method of apply | coating resin and adhere | attaching by heating or photocuring. Furthermore, a material having the above characteristics can be applied to the conductive material 103 and the material of the fine electrode 83 itself. Further, if the patterned fine electrode 83 and the wiring wire 113 are sufficiently in contact with each other, the two are sufficiently fixed while maintaining conductivity when forming the second resin substrate layer 63d (second layer). be able to.

  As described above, if the connection between the fine electrode 83 and the wiring wire 113 is secured, the wiring wire 113 can be arranged at various positions. Connections can also be made by various methods.

  12 to 15, the connection between the fine electrode 83 and the wiring wire 113 of the fourth embodiment has been described as an example. However, the same method can be applied to the fine electrode 73, and other implementations are also possible. The present invention can also be applied to the connection between the fine electrodes 70 to 72 and 80 to 82 and the wiring wires 110 to 112 according to the first to fourth aspects.

[Embodiment 5]
FIG. 16 is a view showing an example of a thin film transistor and a thin film transistor array substrate according to Embodiment 5 of the present invention. Embodiments 1 to 4 show an example in which one pixel is driven by one transistor, and can be applied to, for example, a display element using an existing liquid crystal. However, an organic EL or the like basically requires a selection transistor and a driving transistor, and needs to be driven by a plurality of thin film transistors. In the fifth embodiment, an example in which two thin film transistors are provided corresponding to each pixel will be described.

  In FIG. 16, the thin film transistor and the thin film transistor array substrate according to the fifth embodiment includes a selection thin film transistor 204 and a driving thin film transistor 205. The selection thin film transistor 204 is a pixel selection thin film transistor, and the drive thin film transistor 205 is a pixel drive thin film transistor.

  The selection thin film transistor 204 includes a wire 14, a conductive material 24 that covers the entire surface or part of the wire 14, an insulating film 34 that covers the periphery of the conductive material 24, and a thin film patterned on the insulating film 34. The semiconductor 44 includes a first fine electrode 74 and a second fine electrode 84 formed on the thin film semiconductor 44. Here, the gate / channel integrated formation portion 53 including the wire 14, the conductive material 24, the insulating film 34, and the thin film semiconductor 44 is a resin substrate in which wiring wires 115 are arranged in a direction perpendicular to the thin film semiconductor 44. Located on top of layer 64 and integrated.

  In addition, a wiring wire 114 is connected to the selection thin film transistor 204, and the wiring wire 114 is configured by covering the wire 94 with the conductive material 104. Further, the thin film transistor array substrate includes a pixel electrode 124. Such a configuration is basically the same as that of the thin film transistor array substrate according to the first to fourth embodiments driven by one thin film transistor.

  On the other hand, the driving thin film transistor 205 includes a wire 15, a conductive material 25, an insulating film 35, a thin film semiconductor 45, a first fine electrode 75, and a second fine electrode 85. Here, the wire 15, the conductive material 25, the insulating film 35, and the thin film semiconductor 45 constitute a gate / channel integrated forming portion 55.

  The second fine electrode 85 of the driving thin film transistor 205 is connected to a wiring wire 115 in which the periphery of the wire 95 is covered with the conductive material 106. Further, the first fine electrode 75 is connected to the pixel electrode 124 and constitutes a thin film transistor array substrate.

  Here, the driving thin film transistor 205 has the same components as the first thin film transistor 204, but the entire circumference of the wire 15 is not covered with the conductive material 25, but on the surface of the wire 15. It differs from the thin film transistor 204 for selection in that the conductive material 25 is formed in an island shape in a part of the region and only covers a part of the wire 15. Further, with the configuration of the island-shaped conductive material 25, the insulating film 35 is also provided in an island shape so as to cover the conductive material 25, and the thin film semiconductor 45 is also formed on the insulating film 35 in an island shape. This is different from the thin film transistor 204 for selection. In FIG. 16, the area of the upper surface of the wire 15 is configured to be several times wider than that of the wire 14 because the conductive material 25 is formed on a part of the upper surface of the wire 15. It is possible to set freely according to the characteristics of the TFT.

  As described above, the driving thin film transistor 205 according to this embodiment does not cover the entire circumference of the wire 15 with the conductive material 25 and the insulating film 35 but covers a part of the wire 15 with the conductive material 25 and the insulating material 35. The thin film semiconductor 45 may be formed on the insulating film 35. Even in this case, the basic structure of the transistor in which the gate made of the conductive material 25 is insulated by the insulating film 35 which is a gate oxide film, and the thin film semiconductor 45 disposed on the insulating film 35 functions as a channel. Therefore, the thin film transistor 205 can perform a transistor function.

  In a pixel circuit including two transistors, a pixel selection transistor and a pixel driving transistor, it is necessary to adopt a configuration in which the output terminal of the pixel selection transistor is connected to the gate of the pixel driving transistor. Therefore, it is preferable that all the gates of the pixel driving transistors are not covered so that they can be connected from the outside. Therefore, in the driving thin film transistor 205 according to the fifth embodiment, a part of the wire 15 is formed on the surface of the wire 15 having a sufficient area so as not to cover the entire periphery of the conductive material 25 functioning as a gate. The island-like shape is formed so as to cover the island, and the island-like insulating film 35 can be easily exposed. Thereby, the connection between the first fine electrode 74 of the selection thin film transistor 204 and the conductive material 25 can be facilitated, and the entire configuration of the thin film transistor array substrate can be simplified.

  Also in the driving thin film transistor 205, the gate / channel integrated forming portion 55 is independently formed through a heating process. That is, the conductive material 25, the insulating film 35, and the thin film semiconductor 45 are formed in advance on the wire 15 before the manufacturing process to be integrated with the flexible resin substrate layer 64. These layers are generally formed by vacuum deposition, CVD, sputtering, various coating techniques, etc., and then patterned by photolithography, but direct patterning using printing techniques, etc. May be performed.

  The thin film transistors 204 and 205 and the thin film transistor array substrate according to the fifth embodiment correspond to the thin film transistor 200 and the thin film transistor array substrate according to the first embodiment shown in FIG. 15 is installed on the upper part of the resin substrate layer 64, and wiring wires 114 and 115 are formed inside the resin substrate layer 64. The thin film transistor and the thin film transistor according to the embodiments 2 to 4 shown in FIGS. Corresponding to the thin film transistor array substrate, the same effect can be basically obtained regardless of whether the respective wires are placed at the upper and lower positions.

  In general, the thickness of the wires 14 and 15 can be freely changed within a range of about 5 μm to 500 μm depending on the definition of the pixel. A range of about 50 μm is desirable. When the pixel electrode 124 is also formed on the wire 74, a wire of 500 μm or more may be used depending on the size of the pixel. When applied to a large screen type display or the like, it is effective to use a wire of 500 μm or more even when a pixel electrode is not formed on the wire.

  In the thin film transistor and the thin film transistor array substrate according to the first to fourth embodiments, the two wires 10 to 13 and 90 to 93 are arranged in two upper and lower stages, but the thin film transistors 204 and 205 and the thin film transistor array according to the present embodiment. In the board | substrate, you may install in how many steps according to the kind of wire 14,15,114,115, The combination can be set freely. Any method described with reference to FIGS. 5 to 7 can be applied to the method of integrating the gate / channel integrated forming portions 54 and 55 and the wiring wires 114 and 115 with the resin substrate layer 64.

  In FIG. 16, only the thin film semiconductor 45 is formed on the wire 15. However, if the pixel electrode 124 is also formed in advance in a part different from the thin film semiconductor 45, the deformation of the resin substrate layer 64 due to pixel patterning, etc. Can be suppressed.

  Further, the thin film semiconductors 44 and 45 formed on the same wires 14 and 15 do not have to be one for each pixel, and the pixels can be driven by the thin film semiconductors 44 and 45 having a plurality of types and different shapes. is there. For example, a thin film semiconductor that has the function of a transistor for selection is formed on an insulating film on a wire, and an electrode and an insulating film are stacked on an insulating film in another range, and a thin film that shows the function of a driving transistor is formed thereon. A semiconductor may be formed.

  According to the thin film transistors 204 and 205 and the thin film transistor array substrate according to the fifth embodiment, two thin film transistors 204 and 205 of a pixel selection transistor and a pixel driving transistor can be provided corresponding to one pixel, and an organic EL or the like The present invention can be applied to a flexible display element that requires two transistors for pixel driving.

[Embodiment 6]
FIG. 17 is a view showing an example of a thin film transistor and a thin film transistor array substrate according to Embodiment 6 of the present invention. Embodiment 6 shows an example in which two thin film transistors are formed on one wire.

  In FIG. 17, the thin film transistors 206 and 207 and the thin film transistor array substrate according to the sixth embodiment include a selection thin film transistor 206 and a driving thin film transistor 207.

  The selection thin film transistor 206 includes a wire 16, a conductive material 26, an insulating film 36, a thin film semiconductor 46, a first fine electrode 76, and a second fine electrode 86. Here, the wire 16, the conductive material 26, the insulating film 36, and the thin film semiconductor 46 constitute a gate / channel integrated formation portion 56.

  The driving thin film transistor 207 includes a wire 16, a conductive material 27, an insulating film 37, a thin film semiconductor 47, a first fine electrode 77, and a second fine electrode 87. Here, the wire 16, the conductive material 27, the insulating film 37, and the thin film semiconductor 47 constitute a gate / channel integrated formation portion 57.

  The second fine electrode 86 of the selection thin film transistor 206 is connected to the wiring wire 116, and the first fine electrode 76 is connected to the conductive material 27 of the driving thin film transistor 207. Here, the wiring wire 116 is configured such that the conductive material 106 is covered around the wire 96.

  Similarly, the second fine electrode 87 of the driving thin film transistor 207 is connected to the wiring wire 117, and the first fine electrode 77 is connected to the pixel electrode 126. The wiring wire 117 is configured by covering the wire 97 with the conductive material 107.

  In the thin film transistors 206 and 207 and the thin film transistor substrate according to the sixth embodiment, the conductive material 26 and the insulating film 36 formed in a line shape are stacked on a part of the surface of the single common wire 16 having a wide width, A thin film semiconductor 46 functioning as a selection transistor is formed thereon. Further, in another region of the wire 16, a conductive material 27 and an insulating film 37 are stacked in an island shape, and a thin film semiconductor 47 that functions as a driving transistor is formed thereon. Thus, two thin film transistors 206 and 207 may be formed on one wire 16. By using a wire 16 that is made of a non-conductive material and has a width that allows the two conductive materials 26 and 27 to be arranged, the selection thin film transistors 206 and the drive thin film transistors 207 can be arranged in two rows. it can.

  In the thin film transistors 206 and 207 according to the sixth embodiment, the gate / channel integrated forming portions 56 and 57 are further integrally formed. Similarly to the first to fifth embodiments, the gate / channel integrated forming portions 56 and 57 can be formed independently of the resin substrate layer 66 and can be installed on the surface after the resin substrate layer 66 is formed. it can. Therefore, the gate / channel integrated formation portions 56 and 57 can be integrated with the resin substrate layer 66 after being sufficiently heated by a heating process, and deformation of the resin substrate layer 66 can be prevented.

  In FIG. 17, the pixel electrode 126 is formed on the resin substrate 66, but the pixel electrode 126 may be formed on the same wire 16.

  In the thin film transistors 200 to 207 and the thin film transistor array substrate according to the first to sixth embodiments, the wires 10 to 16 and 110 to 117 do not have to be one, for example, a plurality of wires are bundled and handled as one set of wires. be able to. At that time, it is possible to combine wires of different materials and shapes.

  Moreover, as a method of bundling the above-mentioned plurality of wires, a method of hardening with a thermosetting resin or a photocurable resin, a method of winding each wire, or the like can be used. When using a method of curing with a thermosetting resin or a photo-curable resin, a method of curing the resin with the wire pulled from the right and left with an appropriate force is effective in order to suppress the effects of resin expansion and contraction. is there.

  The thin film transistors 200 to 207 and the thin film transistor array substrate according to the first to sixth embodiments show basic wiring patterns, and the direction and shape of the wiring are not limited to these, and can be freely set. You can do it. Similarly, the fine electrodes 70 to 77 and 80 to 87 on the thin film semiconductors 40 to 47 may be freely set. For example, any pattern can be applied such as making the source / drain electrodes of the transistor into a comb shape. .

  The flexible display element manufactured using the above-described thin film transistor array substrate or backplane can introduce all structures conventionally used in various display methods such as liquid crystal, organic EL, inorganic EL, electronic ink, and electronic powder fluid. In a liquid crystal display, for example, an alignment film, a spacer, a counter electrode, a liquid crystal layer, a backlight, a polarizing plate, a color filter, a black matrix, a depleted film, and the like are of course not limited thereto. Absent.

  In addition, examples of the display device using the flexible display element according to this embodiment include a television, a personal computer, a mobile phone, electronic paper, a touch panel, a display monitor attached to various devices, and the like. Instead, all display devices are included.

〔Example〕
As an example of the present invention, a result of manufacturing a part of a back plane portion of a flexible display element in which a conductive wire on which an insulating film and a thin film transistor are formed integrally with a resin substrate will be described. The manufacturing method is as follows.

  First, a conductive wire composed of a 50 μm piano wire plated with about 2.5 μm thick brass on the surface was placed on a glass plate (170 mm × 110 mm), and both ends of the wire were fixed with tape. A solution containing a fluororesin as a main component was dipped on the surface and heated at 120 to 170 ° C. to cure the fluororesin, thereby forming an insulating layer around the conductive film. Further, an oxide semiconductor (InGaZnO) having a thickness of 50 μm was formed by sputtering on a wire and fixed to a sputtering apparatus holder through a mask. Then, both ends of the conductive wire in which the oxide semiconductor was formed and the above-described conductive wire were fixed to a metal rod, and they were fixed in a box-type plastic container. A silicone resin (PDMS) material was poured therein and heated to 100 ° C. or lower to cure the resin.

  When the resin substrate embedded with the conductive wire produced by the above method was curved, it was confirmed that it could be rounded without disconnection of the wire.

  As described above, according to the thin film transistor and the thin film transistor array substrate according to the embodiments and examples of the present invention, a process of forming a conductive wire on which an insulating film and a thin film transistor are formed and integrating with a resin serving as a substrate is introduced. Accordingly, a flexible display element having a large area with few wiring defects can be provided even when a flexible substrate is used. Therefore, by applying the thin film transistor and the thin film transistor array substrate according to the present invention, various new displays such as a scroll-type display that can be freely rolled and carried and a screen-type large display that does not require a projector can be expected.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the present invention. Can be added.

  The present invention can be used for flexible displays including liquid crystal displays, organic EL displays, and the like, and in particular, can be used for flexible displays of large screens.

10-16, 90-97 Wire 20-27, 100-107 Conductive material 30-37 Insulating film 40-47 Thin film semiconductor 50-57 Gate / channel integrated formation part 60-67 Resin substrate 70-77, 80-87 Fine Electrode 110-117 Wiring wire 120-124, 126 Pixel electrode 130 Auxiliary wire 140, 141 Fixing jig 150 Resin molding container 160, 161 Dispenser 170, 172, 174 Resist 171, 173, 175 Opening 200-207 Thin film transistor

Claims (9)

A thin film transistor formed on a flexible resin substrate,
A wire in which part or all of the peripheral surface is covered with a conductive material;
An insulating film covering the conductive material;
A thin film semiconductor formed on the conductive material through the insulating film, and a gate-channel integrated formation portion integrally formed;
A thin film transistor, wherein the gate / channel integrated formation portion is provided at a predetermined position on or inside the surface of the resin substrate, and the first and second electrodes are connected to both sides of the thin film semiconductor.   The thin film transistor according to claim 1, wherein the wire is made of a metal material having lower conductivity than the conductive material.   The thin film transistor according to claim 2, wherein a plurality of the thin film semiconductors are formed along an extending direction of the wire.   4. The thin film transistor according to claim 1, wherein the insulating film covers the entire circumference of the wire, and one thin film semiconductor is formed in a circumferential direction of the wire. 5. . Pixel electrodes formed in a matrix on a flexible resin substrate;
5. A thin film transistor array substrate comprising: the thin film transistor according to claim 1 provided corresponding to each of the pixel electrodes. A thin film transistor array substrate according to claim 5;
A flexible resin substrate disposed to face the thin film transistor array substrate;
A flexible display element comprising: a pixel disposed corresponding to the pixel electrode between the resin substrate and the thin film transistor array substrate. A method of manufacturing a thin film transistor array substrate having pixel electrodes arranged in a matrix on a flexible resin substrate and thin film transistors provided corresponding to the pixel electrodes,
A gate insulating film forming step of forming an insulating film around a wire in which a part or the whole of the periphery is covered with a conductive material;
A channel forming step of forming a channel by forming a thin film semiconductor so as to cover the position where the conductive material exists on the insulating film, and a gate-channel integrated formation portion in which the gate and the channel are integrally formed A gate / channel integrated formation process for manufacturing;
A resin substrate forming step of forming a resin substrate by curing a fluid-like resin so that the gate-channel integrated formation portion is disposed at a predetermined position on the surface or inside of the resin substrate;
An electrode forming step of forming first and second electrodes at both ends of the thin film semiconductor. A method of manufacturing a thin film transistor array substrate, comprising:   8. The thin film transistor according to claim 7, wherein in the resin forming step, the fluid resin is cured in a state where both ends of the gate / channel integrated forming portion are fixed and fixed at the predetermined position. A method for manufacturing an array substrate. The resin substrate formation step includes a first resin substrate layer formation step of forming the first resin substrate layer up to a height at which the gate / channel integrated formation portion is disposed;
A positioning step of disposing the gate / channel integrated forming portion on the resin substrate;
A second resin substrate layer forming step of forming a second resin substrate layer so as to fill the gate / channel integrated formation portion,
The electrode forming step includes an opening forming step of forming openings at both ends of the thin film semiconductor of the resin substrate, and the first and second electrodes are formed so as to fill the openings. A method for manufacturing a thin film transistor array substrate according to claim 8.

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