JP2013081116A - Image pickup device and image display system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image pickup device, etc. which makes it possible to heighten the picture quality of shot images.SOLUTION: The image pickup device comprises: an image pickup unit which incorporates a plurality of pixels, each including a photoelectric conversion element; a drive unit which drives each pixel so that a readout operation for reading out electrical charges obtained by the photoelectric conversion elements as signals and a reset operation for resetting the electrical charges in the pixels will respectively be performed; and a signal processing unit which executes prescribed signal processing on the basis of the signals obtained by the readout operation to generate an output signal. The drive unit drives each pixel so that the readout and the reset operations will respectively be executed intermittently a number of times within a prescribed unit period. The signal processing unit executes at least addition processing as signal processing on the basis of a first signal obtained by the first readout operation in a unit period and a second signal obtained by the second and subsequent readout operations performed after the first reset operation is executed, to generate an output signal.

Description

  The present disclosure relates to an imaging apparatus having a photoelectric conversion element and an imaging display system including such an imaging apparatus.

  2. Description of the Related Art Conventionally, various types of imaging devices have been proposed that incorporate a photoelectric conversion element in each pixel (imaging pixel). For example, Patent Document 1 includes a so-called optical touch panel, a radiation imaging apparatus, and the like as an example of an imaging apparatus having such a photoelectric conversion element.

JP 2011-135561 A

  By the way, in the imaging apparatus as described above, a captured image is obtained by driving (imaging driving) a plurality of pixels. Various methods for improving the image quality have been proposed for the captured image obtained in this way, but it is desired to propose an imaging device that can realize further image quality improvement.

  The present disclosure has been made in view of such problems, and an object of the present disclosure is to provide an imaging device capable of realizing high image quality of a captured image, and an imaging display system including such an imaging device. It is in.

  The imaging device according to the present disclosure includes an imaging unit having a plurality of pixels each including a photoelectric conversion element, a read operation for reading out a charge obtained by the photoelectric conversion element as a signal, and a charge in the pixel. A driving unit that drives each pixel so that a reset operation for resetting is performed, and a signal processing unit that performs predetermined signal processing based on a signal obtained by the readout operation and generates an output signal It is provided. The drive unit drives each pixel so that the read operation and the reset operation are intermittently performed a plurality of times within a predetermined unit period. The signal processing unit includes a first signal obtained by the first read operation within the unit period, a second signal obtained by the second and subsequent read operations after the first reset operation is performed, and Based on the above, an output signal is generated by performing at least addition processing as signal processing.

  The imaging display system of the present disclosure includes the imaging device of the present disclosure and a display device that displays an image based on an imaging signal obtained by the imaging device.

  In the imaging device and the imaging display system according to the present disclosure, each pixel is driven so that the reading operation and the resetting operation are performed. At this time, the reset operation is intermittently performed a plurality of times within the unit period, so that the residual charge (remaining amount of signal charge) in the pixel after the reset operation is reduced. Further, based on the first signal obtained by the first read operation within the unit period and the second signal obtained by the second and subsequent read operations after the first reset operation is performed. At least an addition process is performed, and an output signal is generated. That is, an output signal is generated based on the addition process of the first signal as the imaging signal corresponding to the signal charge and the second signal as the signal corresponding to the residual charge (residual charge signal). This improves the contrast in the output signal.

  According to the imaging device and the imaging display system of the present disclosure, each pixel is driven so that the readout operation and the reset operation are intermittently performed a plurality of times within a predetermined unit period, and At least addition processing is performed based on the first signal obtained by the first read operation and the second signal obtained by the second and subsequent read operations after the first reset operation is performed. Since the output signal is generated by the above, residual charges in the pixel after the reset operation can be reduced and the contrast in the output signal can be improved. Therefore, it is possible to achieve high contrast while suppressing afterimages due to such residual charges, and it is possible to achieve high image quality of the captured image.

It is a block diagram showing the example of whole composition of the imaging device concerning one embodiment of this indication. FIG. 2 is a schematic diagram illustrating a schematic configuration example of an imaging unit illustrated in FIG. 1. FIG. 2 is a circuit diagram illustrating a detailed configuration example of a pixel or the like illustrated in FIG. 1. FIG. 2 is a block diagram illustrating a detailed configuration example of a column selection unit illustrated in FIG. 1. FIG. 2 is a block diagram illustrating a detailed configuration example of a frame memory and a signal processing unit illustrated in FIG. 1. It is a circuit diagram showing an example of the operation state in an exposure period and a first readout / reset period. It is a schematic diagram for demonstrating the accumulation | storage state and depletion state in a photoelectric conversion element in the case of being a PIN type photodiode of a lateral type structure. It is a schematic cross section showing the example of a structure of the photoelectric conversion element which consists of a PIN type photodiode of a vertical type structure. It is a circuit diagram for demonstrating the charge distribution phenomenon resulting from the parasitic capacitance in a pixel. It is a characteristic view for demonstrating the mechanism of residual charge generation. It is a characteristic view showing an example of the relationship between the elapsed time after the first read / reset period and the decay current. It is a characteristic view for demonstrating the relationship between residual electric charge amount and Decay electric current. It is a timing waveform diagram for demonstrating the outline | summary of imaging operation. It is a timing waveform diagram showing an example of line sequential imaging drive. It is a circuit diagram showing the example of the operation state in a 2nd read / reset period. It is a characteristic diagram for demonstrating the residual charge amount reduced by the reset operation of the 2nd time. FIG. 5 is a characteristic diagram schematically illustrating an example of a relationship between exposure intensity and charge amount in an imaging signal and a residual charge signal. FIG. 6 is a schematic diagram illustrating a first signal processing technique example by a signal processing unit illustrated in FIG. 5. It is a schematic diagram showing the 2nd example of a signal processing method by the signal processing part shown in FIG. 10 is a block diagram illustrating a configuration example of a frame memory and a signal processing unit according to Modifications 1 and 2. FIG. 10 is a circuit diagram illustrating a configuration of a pixel and the like according to Modification 3. FIG. 10 is a circuit diagram illustrating a configuration of a pixel and the like according to Modification 4. FIG. 10 is a circuit diagram illustrating a configuration of a pixel and the like according to Modification 5. FIG. FIG. 5 is a timing waveform diagram illustrating an example of line-sequential imaging drive in passive and active pixel circuits. 10 is a timing waveform diagram illustrating an example of line-sequential imaging driving and signal processing according to Modification 6. FIG. 10 is a schematic diagram illustrating a schematic configuration of an imaging unit according to modification examples 7 and 8. FIG. It is a schematic diagram showing schematic structure of the imaging display system which concerns on an application example.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be given in the following order.

1. Embodiment (Example 1 of Passive Pixel Circuit)
2. Modifications Modifications 1 and 2 (Other configuration examples of the signal processing unit)
Modification 3 (Example 2 of passive pixel circuit)
Modifications 4 and 5 (example of active pixel circuit)
Modification 6 (Example in which an imaging signal / residual charge signal is acquired using a plurality of frame periods)
Modified examples 7 and 8 (examples of imaging units that perform imaging based on radiation)
3. Application example (application example to imaging display system)
4). Other variations

<Embodiment>
[Overall Configuration of Imaging Device 1]
FIG. 1 illustrates an overall block configuration of an imaging apparatus (imaging apparatus 1) according to an embodiment of the present disclosure. The imaging device 1 reads information on a subject based on imaging light (captures the subject). The imaging apparatus 1 includes an imaging unit 11, a row scanning unit 13, an A / D conversion unit 14, a column scanning unit 15, a system control unit 16, a frame memory 18, and a signal processing unit 19. Among these, the row scanning unit 13, the A / D conversion unit 14, the column scanning unit 15, and the system control unit 16 correspond to a specific example of “driving unit” in the present disclosure.

(Imaging unit 11)
The imaging unit 11 generates an electrical signal according to incident imaging light (imaging region). In the imaging unit 11, a pixel (imaging pixel, unit pixel) 20 having a photoelectric conversion unit (a photoelectric conversion element 21 to be described later) that generates photoelectric charges having a charge amount corresponding to the amount of incident imaging light and accumulates the photoelectric charges therein. Are two-dimensionally arranged in a matrix (matrix). As shown in FIG. 1, the horizontal direction (row direction) in the imaging unit 11 will be described as “H” direction and the vertical direction (column direction) will be described as “V” direction.

  FIG. 2 illustrates a schematic configuration example of the imaging unit 11. The imaging unit 11 is provided with a photoelectric conversion layer 111 in which the plurality of pixels 20 described above are arranged. In the photoelectric conversion layer 111, as shown in the drawing, photoelectric conversion based on the incident imaging light Lin (conversion from the imaging light Lin to a signal charge) is performed.

  FIG. 3 illustrates a circuit configuration example of the pixel 20 (a so-called passive circuit configuration example) together with a circuit configuration example of a column selection unit 17 described later in the A / D conversion unit 14. This passive pixel 20 is provided with one photoelectric conversion element 21 and one transistor 22. The pixel 20 is also connected to a read control line Lread extending along the H direction and a signal line Lsig extending along the V direction.

  The photoelectric conversion element 21 is composed of, for example, a PIN (Positive Intrinsic Negative) type or MIS (Metal Insulator Semiconductor) type photodiode, and as described above, a signal charge having a charge amount corresponding to the amount of incident light (imaging light Lin). Is supposed to be generated. The cathode of the photoelectric conversion element 21 is connected to the storage node N.

  The transistor 22 is turned on in response to the row scanning signal supplied from the read control line Lread, so that the signal charge (input voltage Vin) obtained by the photoelectric conversion element 21 is output to the signal line Lsig (read). Transistor). Here, the transistor 22 is configured by an N-channel (N-type) field effect transistor (FET). However, the transistor 22 may be composed of a P-channel (P-type) FET or the like. The transistor 22 is also configured using a silicon-based semiconductor such as microcrystalline silicon (Si) or polycrystalline silicon (polysilicon). Alternatively, an oxide semiconductor such as indium gallium zinc oxide (InGaZnO) or zinc oxide (ZnO) may be used. Since microcrystalline silicon, polycrystalline silicon, and an oxide semiconductor have higher mobility μ than amorphous silicon (amorphous silicon), for example, signal charges can be read at high speed by the transistor 22.

  In the pixel 20, the gate of the transistor 22 is connected to the read control line Lread, the source is connected to the signal line Lsig, and the drain is connected to the cathode (storage node N) of the photoelectric conversion element 21. In addition, the anode of the photoelectric conversion element 21 is connected to the ground (ground) here.

(Row scanning unit 13)
The row scanning unit 13 illustrated in FIG. 1 includes, for example, a shift register circuit, an address decoder, a logic circuit, and the like (not shown). ) Is a pixel driving unit (row scanning circuit) that performs driving (line sequential scanning). Specifically, such line-sequential scanning is performed in line-sequential imaging driving such as line-sequential readout driving and line-sequential reset driving described later. This line sequential scanning is performed by supplying the above-described row scanning signal to each pixel 20 via the readout control line Lread.

(A / D converter 14)
As shown in FIG. 1, the A / D conversion unit 14 includes a plurality of column selection units 17 provided for each of a plurality (here, four) of signal lines Lsig. A / D conversion (analog / digital conversion) is performed on the basis of the signal voltage (signal charge) input via the signal. As a result, output data (imaging signal D11 or residual charge signal D12 described later) composed of a digital signal is generated and output to a frame memory 18 and a signal processing unit 19 described later.

  Each column selection unit 17 includes, for example, a charge amplifier 172, a capacitive element (capacitor, feedback capacitive element) C1, a switch SW1, a sample hold (S / H) circuit 173, and four switches as shown in FIGS. A multiplexer circuit (selection circuit) 174 including SW2 and an A / D converter 175 are included. Among these, one charge amplifier 172, capacitive element C1, switch SW1, S / H circuit 173 and switch SW2 are provided for each signal line Lsig, as shown in FIG. On the other hand, one multiplexer selection circuit 17 and one A / D converter 175 are provided as the entire column selection unit 17.

  The charge amplifier 172 is an amplifier (amplifier) for converting the signal charge read from the signal line Lsig into a voltage (QV conversion). In the charge amplifier 172, one end of the signal line Lsig is connected to the negative (−) input terminal, and a predetermined reset voltage Vrst is input to the positive (+) input terminal. . The output terminal of the charge amplifier 172 and the negative input terminal are connected in a feedback manner (feedback connection) via a parallel connection circuit of the capacitive element C1 and the switch SW1. That is, one terminal of the capacitive element C 1 is connected to the negative input terminal of the charge amplifier 172, and the other terminal is connected to the output terminal of the charge amplifier 172. Similarly, one terminal of the switch SW1 is connected to the negative input terminal of the charge amplifier 172, and the other terminal is connected to the output terminal of the charge amplifier 172. The on / off state of the switch SW1 is controlled by a control signal (amplifier reset control signal) supplied from the system control unit 16 via the amplifier reset control line Lcarst. Thus, the charge amplifier 172, the capacitive element C1, and the switch SW1 form a charge amplifier circuit that performs the above-described QV conversion.

  The S / H circuit 173 is disposed between the charge amplifier 172 and the multiplexer circuit 174 (switch SW2), and is a circuit for temporarily holding the output voltage Vca from the charge amplifier 172.

  The multiplexer circuit 174 selectively connects each S / H circuit 173 and the A / D converter 175 by sequentially turning on one of the four switches SW2 in accordance with the scanning drive by the column scanning unit 15. Or it is a circuit to cut off.

  The A / D converter 175 performs A / D conversion on the output voltage from the S / H circuit 173 input via the switch SW2, thereby causing the output data (the imaging signal D11 or the residual charge signal D12). Is a circuit that generates and outputs.

(Column scanning unit 15 / system control unit 16)
The column scanning unit 15 includes, for example, a shift register and an address decoder (not shown), and drives the switches SW2 in the column selection unit 17 in order while scanning. A signal (the above-described imaging signal D11 or residual charge signal D12) of each pixel 20 read through each of the signal lines Lsig by the selective scanning by the column scanning unit 15 is used as the frame memory 18 and the signal processing unit. 19 are output in order.

  The system control unit 16 controls operations of the row scanning unit 13, the A / D conversion unit 14, and the column scanning unit 15. Specifically, the system control unit 16 includes a timing generator that generates the various timing signals (control signals) described above, and performs row scanning based on the various timing signals generated by the timing generator. Drive control of the unit 13, the A / D conversion unit 14, and the column scanning unit 15 is performed. In this way, based on the control of the system control unit 16, the row scanning unit 13, the A / D conversion unit 14, and the column scanning unit 15 respectively perform imaging driving (line sequential imaging driving) for the plurality of pixels 20 in the imaging unit 11. ), The output data (imaging signal D11 or residual charge signal D12) is acquired from the imaging unit 11.

(Frame memory 18 / signal processor 19)
The frame memory 18 is a storage unit for temporarily holding output data (the imaging signal D11 and the residual charge signal D12) from the A / D conversion unit 14, and is, for example, an SRAM (Static Random Access Memory) or the like. It is configured using various memories.

  The signal processing unit 19 performs predetermined signal processing, which will be described later, based on data (the imaging signal D11 and the residual charge signal D12) output from the A / D conversion unit 14 and temporarily held in the frame memory 18. Thus, output data Dout (output signal) is generated. Specifically, although details will be described later, the imaging signal D11 (first signal) obtained by the first read operation within a predetermined unit period (here, one frame period) and the first reset operation are The predetermined signal processing is performed based on the residual charge signal D12 (second signal) that is a signal obtained by the second and subsequent reading operations (here, the second time) after being performed. Further, as this predetermined process, at least an addition process, which will be described later, is performed. Here, in addition to the addition process, a weighting process and a linearization process, which will be described later, are also performed.

  FIG. 5 shows a detailed block configuration example in the frame memory 18 and the signal processing unit 19.

  Here, the frame memory 18 includes two frame memories 181 and 182. The frame memory 181 is a frame memory for temporarily holding the imaging signal D11 obtained by the first reading operation described above. On the other hand, the frame memory 182 is a frame memory for temporarily holding the residual charge signal D12 obtained by the second and subsequent reading operations (here, the second time).

  Here, the signal processing unit 19 includes a weighting processing unit 191, an addition processing unit 192, and a linearization processing unit 193.

  The weighting processing unit 191 performs predetermined weighting processing described later on the residual charge signal D12 supplied from the frame memory 182. Specifically, such weighting processing is performed using a predetermined weighting coefficient k described later. Specifically, the weighting processing unit 191 generates a weighting signal (k × D12) by multiplying the residual charge signal D12 by a weighting coefficient k.

  The addition processing unit 192 adds the imaging signal D11 supplied from the frame memory 182 and the weighting signal (k × D12) supplied from the weighting processing unit 191. As a result, a composite signal D2 (= D11 + k × D12), which is a signal after such addition processing, is generated.

  The linearization processing unit 193 generates output data Dout by performing predetermined linearization processing described later on the synthesized signal D2 supplied from the addition processing unit 192. Here, although details will be described later, this linearization processing is processing for linearizing the correspondence between the exposure intensity at the time of imaging and the signal intensity of the output signal (output data Dout).

  In this way, signal processing is performed in the signal processing unit 19, and output data Dout is generated and output to the outside. The details of the signal processing operation in the signal processing unit 19 will be described later.

[Operation and Effect of Imaging Device 1]
(1. Basic operation)
In the imaging apparatus 1, as shown in FIG. 2, when the imaging light Lin is incident on the imaging unit 11 in an exposure period Tex described later, the photoelectric conversion layer 111 (the photoelectric conversion element 21 in each pixel 20 shown in FIG. 3). ), The imaging light Lin is converted into a signal charge (photoelectric conversion). Due to the signal charges generated by the photoelectric conversion, a voltage change corresponding to the storage node capacitance occurs in the storage node N. Specifically, if the storage node capacitance is Cs and the generated signal charge is q, the voltage at the storage node N is reduced by (q / Cs). In response to such a voltage change, the input voltage Vin (voltage corresponding to the signal charge) is applied to the drain of the transistor 22. The input voltage Vin supplied to the transistor 22 is read out from the pixel 20 to the signal line Lsig when the transistor 22 is turned on in accordance with a row scanning signal supplied from the readout control line Lread (readout period). .

  The signal charges read out in this way are input to the column selection unit 17 in the A / D conversion unit 14 for each of a plurality (four in this case) of pixel columns via the signal line Lsig. In the column selection unit 17, first, for each signal charge input from each signal line Lsig, QV conversion (conversion from signal charge to signal voltage) is performed in a charge amplifier circuit including a charge amplifier 172 and the like. Next, for each converted signal voltage (output voltage Vca from the charge amplifier circuit 172), A / D conversion is performed in the A / D converter 175 via the S / H circuit 173 and the multiplexer circuit 174, and a digital signal is formed. Output data (imaging signal D11 or residual charge signal D12) is generated. In this way, the output data is sequentially output from each column selection unit 17 and supplied to the frame memory 18 and the signal processing unit 19. The signal processing unit 19 generates final output data Dout by performing predetermined signal processing using the imaging signal D11 and the residual charge signal D12, and outputs the output data Dout to the outside.

(2. Operation during exposure period Tex and readout period)
Here, with reference to FIGS. 6A and 6B, operations of the pixel 20 and the charge amplifier circuit in the column selection unit 17 in the exposure period Tex and the readout period will be described in detail. In the following, for convenience of explanation, the on / off state of the transistor 22 is illustrated using a switch.

  First, as shown in FIG. 6A, in the exposure period Tex in which the imaging light Lin is incident on the photoelectric conversion element 21 in the pixel 20, the signal charge accumulated in the accumulation node N is a signal during the exposure period Tex. The transistor 22 is off so that it is not output (not read) to the line Lsig side. At this time, since the charge amplifier circuit is in a state after an amplifier reset operation (reset operation of the charge amplifier circuit) described later is performed, the switch SW1 is in an on state, and as a result, a voltage follower circuit is formed. ing.

  On the other hand, the above readout period is also a period for performing a reset operation (pixel reset operation) for resetting charges (signal charges) accumulated in the pixel 20 in the present embodiment. That is, because the pixel 20 of the present embodiment is a passive pixel circuit, the “read operation” for reading the signal charge obtained from the photoelectric conversion element 21 from the pixel 20 and the “reset” described above. "Operation" is performed substantially simultaneously (in parallel). In other words, although details will be described later, a line-sequential readout drive for performing this readout operation in a line-sequential manner and a line-sequential reset drive for performing a reset operation in a line-sequential manner are performed by a single line-sequential drive (substantially). At the same time) Note that the read operation and the reset operation at this time correspond to the first read operation and the reset operation among a plurality of read operations and reset operations described later (here, twice), respectively. Therefore, hereinafter, the period in which the first read operation and the first reset operation are performed substantially simultaneously is referred to as a “first read / reset period Tr1”.

  In the first readout / reset period Tr1, as shown in FIG. 6B, when the transistor 22 is turned on, the signal charge is read from the storage node N in the pixel 20 to the signal line Lsig side ( (See arrow P11 in the figure). The signal charge read in this way is input to the charge amplifier circuit. Here, in the first read / reset period Tr1, the switch SW1 in the charge amplifier circuit is in an OFF state. That is, the charge amplifier circuit is in a read operation state. Therefore, the signal charge input to the charge amplifier circuit is stored in the capacitive element C 1, and a signal voltage (output voltage Vca) corresponding to the stored charge is output from the charge amplifier 172. In this way, the charge amplifier circuit performs conversion from signal charge to signal voltage (QV conversion). As a result of such a first read operation, the imaging signal D11 corresponding to the signal charge is output from the column selector 17 as shown in the figure. The charge accumulated in the capacitive element C1 in this way is reset (amplifier reset operation is performed) when the switch SW1 is turned on during an amplifier reset operation described later. .

  In addition to the first read operation, the first reset operation (first reset operation) is performed in the first read / reset period Tr1 as follows. That is, as indicated by an arrow P12 in the figure, the first reset operation is performed using the virtual short circuit (imaginary short) phenomenon in the charge amplifier circuit (charge amplifier 172). That is, due to this virtual short-circuit phenomenon, the voltage on the negative input terminal side (signal line Lsig side) of the charge amplifier 172 becomes substantially equal to the reset voltage Vrst applied to the positive input terminal. Therefore, the storage node N in the pixel 20 also becomes the reset voltage Vrst. In this way, the charge stored in the storage node N is reset to the predetermined reset voltage Vrst with the first read operation described above.

(3.1 Remaining signal charge in the pixel 20 after the first reset operation)
Incidentally, in spite of performing the first reset operation as described above, a part of the signal charges accumulated before the first reset operation may remain in the pixel 20. When a part of the signal charge remains in the pixel 20 in this way, an afterimage due to the residual charge is generated at the time of the next readout operation (at the time of imaging in the next frame period), and the imaging image quality is deteriorated. End up. Hereinafter, the remaining signal charges (remaining accumulated charges) in the pixel 20 after the first reset operation will be described in detail with reference to FIGS.

  First, when the photoelectric conversion element 21 is a PIN type photodiode (thin film photodiode), it is roughly classified into the following two structures. That is, there are a so-called lateral type (horizontal type) structure as shown in FIGS. 7A and 7B and a so-called vertical type (vertical type) structure as shown in FIG.

  In the case of the lateral type structure shown in FIGS. 7A and 7B, the photoelectric conversion element 21 has a p-type semiconductor layer 21P, an intrinsic semiconductor layer (i layer) 21I, and a lateral direction (in-stack direction). The n-type semiconductor layer 21N is provided in this order. In addition, the gate electrode 21 </ b> G is disposed near the intrinsic semiconductor layer 21 </ b> I with a gate insulating film (not shown) interposed therebetween. On the other hand, in the case of the vertical structure shown in FIG. 8, the photoelectric conversion element 21 has, for example, the lower electrode 211a, the p-type semiconductor layer 21P, the intrinsic semiconductor layer 21I, and the n-type semiconductor layer 21N along the vertical direction (stacking direction). And the upper electrode 211b in this order.

(3-1. Occurrence mechanism when the charge in the pixel 20 is saturated by irradiating with strong external light)
Here, as an example of the mechanism in which the signal charge remains as described above, the case where the charge in the pixel 20 is saturated when irradiated with strong external light is composed of the PIN type photodiode having the lateral structure described above. The photoelectric conversion element 21 will be described as an example. In the photoelectric conversion element 21 having this structure, the intrinsic semiconductor layer 21I is in any of an accumulation state (saturation state), a depletion state, and an inversion state by a gate voltage applied to the gate electrode 21G. Here, in the case of a thin film photodiode, a transition is made from a state where charge is induced at the interface on the gate electrode 21G side in this accumulation state or inversion state (FIG. 7A) to a depletion state (FIG. 7B). Requires several hundreds of microseconds. Normally, a PIN photodiode is used in a depletion state because the photosensitivity is maximized in the depletion state. For example, when a strong external light is irradiated and Vnp <0 V is reached, the PIN type photodiode shifts to an accumulation state. Vnp is the potential of the n-type semiconductor layer 21N viewed from the p-type semiconductor layer 21P side.

  For this reason, for example, even if the environment changes to a dark state immediately after irradiation with strong external light and a reset operation (first reset operation) is performed and the state returns to the state of Vnp> 0, it is several hundred μs. During this time, it is not possible to transition from the accumulated state to the depleted state. At this time, it is known that the capacitance characteristics of the PIN photodiode are different between the depletion state and the accumulation state or the inversion state due to the influence of the charge induced at the interface on the gate electrode 21G side. That is, as shown in FIGS. 7A and 7B, the parasitic capacitance Cgp formed between the gate electrode 21G and the p-type semiconductor layer 21P is large in the accumulation state and small in the depletion state.

  On the other hand, the storage node N (storage capacitor) in the pixel 20 becomes the predetermined reset voltage Vrst by the first reset operation described above, and the transistor 22 transitions from the on state to the off state after the first reset operation. The following phenomenon occurs. That is, for example, as shown in FIG. 9, the potential of the storage node N is reset due to the charge accumulated in the parasitic capacitance in the pixel 20 (parasitic capacitance Cgd formed between the gate and drain of the transistor 22). It fluctuates slightly from the voltage Vrst (see arrow P2 in the figure). Such a phenomenon is called a charge distribution phenomenon (charge injection phenomenon).

  Here, as described above, when the parasitic capacitance Cgp in the PIN type photodiode (photoelectric conversion element 21) connected to the storage node N differs between the depletion state and the storage or inversion normal state, the photoelectric conversion element 21 Depending on the state, the total coupling amount (the size of the parasitic capacitance) in the pixel 20 changes. Due to this, even after the first reset operation, information (charge) of the light (imaging light Lin) that has been incident until just before remains in the storage node N. With such a mechanism, when strong external light is applied and the charge in the pixel 20 is saturated, the charge is accumulated before the first reset operation despite the first reset operation. A part of the signal charge remains in the pixel 20.

(3-2. General generation mechanism)
Next, a general generation mechanism of signal charge remaining (residual charge), which is not limited to the above-described case (the case where the charge in the pixel 20 is saturated by irradiation with strong external light), will be described. That is, even if strong external light that causes a capacitance change as described above is not irradiated, a decay current described below is generated from the photoelectric conversion element 21 (PIN type photodiode), thereby generating residual charges. Explain what to do.

  FIGS. 10A and 10B each show an energy band structure (relation between the position of each layer and the energy level) in the PIN photodiode described above. As can be seen from these figures, the intrinsic semiconductor layer 21I has a large number of defect levels Ed. Then, as shown in FIG. 10A, immediately after the end of the first read / reset period Tr1 (first reset operation), the charge e is trapped in these defect levels Ed. It has become. However, as shown in FIG. 10B, for example, when a certain amount of time has elapsed from the first read / reset period Tr1, the charge e trapped in the defect order Ed is transferred from the intrinsic semiconductor layer 21I to the photodiode (photoelectric). It is emitted to the outside of the conversion element 21) (see broken line arrow in the figure). As a result, the decay current Idacay described above is generated from the photoelectric conversion element 21.

Here, FIGS. 11A and 11B each show an example of the relationship between the elapsed time t after the first read / reset period Tr1 and the decay current Idecay. In FIG. 11A, both the vertical axis and the horizontal axis are shown on a logarithmic scale, and in FIG. 11B, the vertical axis is shown on a logarithmic scale, while the horizontal axis is shown on a linear scale. . In FIGS. 11A and 11B, a part of the common line among the characteristic lines is denoted by reference numeral G1. As can be seen from these figures, the decay current Idecay tends to decrease synergistically with the passage of time from the end of the first read / reset period Tr1 (t = 0) (Idecay = (I ₀ / t), I ₀ : constant value). Further, it can be seen that the residual charge (q1) generated at this time is obtained by integrating the decay current Idecay = (I ₀ / t) with the elapsed time t as shown in FIG. 12, for example.

  Due to the general generation mechanism as described above, a part of the signal charge accumulated before the first reset operation remains in the pixel 20 despite the first reset operation. (The above-mentioned residual charge q1 is generated).

(4. Reducing residual charge using multiple reset operations)
Therefore, in the present embodiment, as shown in FIGS. 13 and 14, for example, the above-described residual charge is reduced by performing the reset operation a plurality of times (here, twice), and an afterimage caused by the residual charge is reduced. I try to suppress it. Hereinafter, the action of reducing the residual charge using the plurality of reset operations will be described in detail.

  13A shows a timing waveform of the potential Vread of the read control line Lread, FIG. 13B shows a timing waveform of the output voltage Vca from the charge amplifier 172, and FIG. 13C shows a timing of the potential Vsig of the signal line Lsig. (D) shows the timing waveform of the potential Vn of the storage node N, respectively. Each of these timing waveforms is for a period before and after one vertical period (one frame period) ΔTv.

  FIG. 14 is a timing waveform diagram showing an example of line-sequential imaging driving (line-sequential readout driving and line-sequential reset driving) according to the present embodiment. Here, (A) to (F) are potentials Vread (1) to Vread (3) of n read control lines Lread (1) to Lread (3) and Lread (n−2) to Lread (n), respectively. ), Vread (n-2) to Vread (n). Further, ΔTh shown in the drawing represents one horizontal period (one horizontal scanning period). Furthermore, ΔTr1 is a line sequential drive period for the first reset operation or the like (operation in the first readout / reset period Tr1), and ΔTr2 is the second reset operation or the like (operation in the second readout / reset period Tr2). The line-sequential driving periods for are respectively shown.

  In this one frame period ΔTv, first, an exposure operation is performed in the exposure period Tex at timings t11 to t12 as described above with reference to FIG. That is, when the imaging light Lin enters the imaging unit 11, the photoelectric conversion element 21 in each pixel 20 converts the imaging light Lin into signal charges (photoelectric conversion). Then, this signal charge is accumulated in the accumulation node N in the pixel 20, and the potential Vn gradually changes (see arrow P31 in FIG. 13). Note that the potential Vn gradually decreases from the reset voltage Vrst side to 0 V with this exposure operation because the cathode side of the photoelectric conversion element 21 is the storage node N here. .

  Next, in the first readout / reset period Tr1 at timings t13 to t14, the first readout operation and the first reset operation (pixel reset operation) are performed as described above with reference to FIG. Is called. That is, the first read operation for acquiring the imaging signal D11 corresponding to the signal charge by reading the signal charge from the pixel 20 and the first reset operation for resetting the signal charge in the pixel 20 are: Done substantially simultaneously. However, as indicated by an arrow P32 in FIG. 13, the potential Vn of the storage node N gradually decreases after the first reset operation, and the above-described residual charge q1 is generated.

  At subsequent timing t15, the switch SW1 in the charge amplifier circuit is turned on, so that the charge accumulated in the capacitive element C1 in the charge amplifier circuit is reset. That is, the reset operation (amplifier reset operation) of the charge amplifier circuit is performed.

  Subsequently, at subsequent timings t16 to t17, a second read operation and a second reset operation (second read / reset operation) described below are performed (second read / reset period Tr2), respectively. That is, in the second read / reset period Tr2, as in the first read / reset period Tr1, the read operation and the reset operation are performed substantially simultaneously (in parallel). In other words, the line-sequential readout drive for performing this readout operation in line-sequential manner and the line-sequential reset drive for performing the reset operation in line-sequential manner are (substantially) performed simultaneously by a single line-sequential drive. . However, in the second read operation, unlike the first read operation described above (operation for acquiring the imaging signal D11), as described below, the above-described residual charge q1 is read from the pixel 20 to read this second read operation. A residual charge signal (Decay signal) D12 corresponding to the residual charge q1 is obtained.

  Specifically, in the second read / reset period Tr2, for example, the second reset operation and the second read operation are performed as in the operation example illustrated in FIG. That is, in this operation example, the second reset operation is performed using the virtual short-circuit phenomenon in the charge amplifier circuit (charge amplifier 172) as in the case of the first reset operation described above (arrow in the figure). (See P42). That is, the potential Vn of the storage node N in the pixel 20 is set to the reset voltage Vrst by this virtual short circuit phenomenon. In this operation example, as in the first readout / reset period Tr1, the transistor 22 in the pixel 20 is in the on state and the switch SW1 in the charge amplifier circuit is in the off state. The read operation state is set. That is, as indicated by the arrow P41 in the figure, in this operation example, the charge remaining at the storage node N (the above-described residual charge q1) can be read out by the charge amplifier circuit. Therefore, by the second read operation, the residual charge signal D12 corresponding to the residual charge q1 is output from the column selector 17 as shown in the figure.

  As described above, in the present embodiment, the reset operation (line-sequential reset driving) of the accumulated charges in the pixel 20 is performed intermittently (independently) within a predetermined unit period (here, one frame period). Performed once. Specifically, the first reset operation (first read / reset period Tr1) and the second reset operation (second read / reset period Tr2) are performed intermittently within one frame period. Is set to Thereby, the residual charge q1 (remaining amount of signal charge) in the pixel 20 after the first reset operation is more reliably reset, and such residual charge q1 is reduced (arrow P33 shown in FIG. 13). reference).

  Specifically, if the time from the end of the first reset operation (Tr1 end) to the end of the second reset operation (Tr2 end) is Δt12 (see FIG. 13), the generated residual The amount of charge to be reduced among the charges q1 is, for example, as shown in FIG. That is, for example, out of the residual charge q1 described in FIG. 12, the charge q12 corresponding to the time integral value from the start time t1 (= 0) to the end time t2 of the time Δt12 is discharged by this second reset operation. This corresponds to the amount of charge (reducing). Further, the charge q23 calculated by (q1-q12) = q23 corresponds to the amount of charge remaining even after the second reset operation. For this reason, it can be said that it is desirable to set the time Δt12 as long as possible. As described above, the residual charge q1 in the pixel 20 after the first reset operation is reduced, and as a result, this is caused by this residual charge during the next readout operation (when imaging in the next frame period). The occurrence of afterimages can be suppressed, and the image quality can be improved.

  It should be noted that such a plurality of reset operations (line-sequential reset drive) are desirably performed intermittently over a period exceeding, for example, one horizontal period (one horizontal scanning period: about 32 μs as an example). . This is due to the following reason. That is, as described above, the state transition in the PIN photodiode takes about several hundreds of μs. From this, it is considered that the generation of residual charges can be reduced by applying the reset voltage Vrst to the storage node N continuously or intermittently for a time of, for example, about 100 μs. However, in practice, it has been confirmed by experiments and the like that the residual charge starts to greatly decrease when the period during which the reset voltage Vrst is applied exceeds one horizontal period (for example, about 32 μs).

(5. High-contrast action of captured images using multiple readout operations)
Further, in the present embodiment, for example, as shown in FIGS. 17 to 19 below, the signal processing unit 19 performs signal processing using multiple (here, twice) read operations. That is, first, a read operation (line sequential read drive) is performed a plurality of times intermittently (independently) within a predetermined unit period (here, one frame period). Then, the signal processing unit 19 performs predetermined signal processing, which will be described below, based on the signals (imaging signal D11 and residual charge signal D12) obtained by such a reading operation, and generates output data Dout (output signal). To do. As a result, the contrast of the captured image is increased. Hereinafter, the effect of increasing the contrast of a captured image using the multiple imaging operations (signal processing operation in the signal processing unit 19) will be described in detail.

  First, as shown in FIG. 17, for example, the exposure intensity (intensity of the imaging light Lin) to the imaging unit 11 at the time of imaging, and signals (imaging signal D11 and residual charge signal D12) corresponding to the charge amount Intensity is proportional to each other. In other words, as the exposure intensity increases, the imaging signal D11 and the residual charge signal D12 each increase linearly. By using such a linear relationship (proportional relationship), the signal processing unit 19 performs signal processing (addition processing or the like) using, for example, the following first or second signal processing technique to increase the contrast in the output data Dout. Is realized.

(First signal processing method)
In the first signal processing method, first, for example, as shown in FIG. 18A, weighting processing and addition processing are performed. That is, first, the weighting processing unit 191 performs weighting processing by multiplying the residual charge signal D12 supplied from the frame memory 182 by a predetermined weighting coefficient k, and generates a weighting signal (k × D12).

  Here, the weighting coefficient k is not a constant value (fixed value), for example, as shown in the lower diagram of FIG. 18A, but is 0 to 1.0 depending on the signal strength of the residual charge signal D12. Set to change between. Specifically, here, the weighting coefficient k is set to be smaller when the signal strength of the residual charge signal D12 is relatively low than when the signal strength is relatively high. In particular, in the first signal processing method, when the signal intensity of the residual charge signal D12 is larger than a predetermined intensity threshold Sth, the weighting coefficient k is set to a fixed value (here, the maximum value is 1.0). When the signal strength is equal to or less than the strength threshold value Sth, the weighting coefficient k is set to be gradually reduced as the signal strength decreases.

  This is because the region where the signal intensity of the residual charge signal D12 is relatively small (the region where the amount of charge is small) is a region where the noise during the read operation (noise) is dominant (noise dominant region). doing. That is, if weighting processing is performed using the weighting coefficient as it is (with a large value) in such a noise dominant region, the S / N ratio is lowered in the subsequent addition processing. Therefore, here, by setting the weight of the residual charge signal D12 in such a noise dominant region to be relatively small, the noise component is attenuated or blocked, and the S / N ratio is improved (the noise level is increased). Without increasing the signal level).

  Next, as shown in the upper diagram of FIG. 18A, the addition processing unit 192 includes the imaging signal D11 supplied from the frame memory 182 and the weighting signal (k × D12) supplied from the weighting processing unit 191. Is added to. As a result, a composite signal D2 (= D11 + k × D12) that is a signal after the addition processing is generated.

Subsequently, for example, as illustrated in FIG. 18B, the linearization processing unit 193 generates output data Dout by performing linearization processing on the combined signal D <b> 2 supplied from the addition processing unit 192. . This linearization processing is processing for linearizing the correspondence between the exposure intensity at the time of imaging and the signal intensity of the output data Dout, as shown in FIG. Specifically, assuming that the ratio of the signal strength of the residual charge signal D12 to the signal strength of the imaging signal D11 (= signal strength of the residual charge signal D12 / signal strength of the imaging signal D11) is d, the linearization processing unit 193 is as follows. (1) is used to perform linearization processing to generate output data Dout. In this way, output data Dout is generated by signal processing using the first signal processing technique.
Dout = {1 / (1 + d × k)} × D2 (1)

  Here, it is desirable to perform such a linearization process for the following reason. That is, since the combined signal D2 is a signal obtained by adding the weighted residual charge signal (k × D12) to the imaging signal D11, for example, as shown in the upper diagram in FIG. The signal intensity is non-linear with respect to the exposure intensity (no longer proportional). If such a signal showing non-linearity remains, it becomes difficult to handle, for example, at the time of subsequent signal processing. Therefore, it is desirable to perform the linear processing as described above.

(Second signal processing technique)
On the other hand, in the second signal processing method, for example, as shown in FIG. 19A, weighting processing and addition processing are performed. That is, first, as in the first signal processing method, the weighting processing unit 191 performs weighting processing by multiplying the residual charge signal D12 by a predetermined weighting coefficient k, and generates a weighting signal (k × D12). To do.

  Also in this second signal processing method, as in the first signal processing method, the weighting coefficient k is not a constant value (fixed value) but a residual charge as shown in the lower diagram of FIG. It is set to change between 0 and 1.0 according to the signal strength of the signal D12. Here, when the signal strength of the residual charge signal D12 is relatively low, the weighting coefficient k is set to be smaller than when the signal strength is relatively high. However, in the second signal processing method, when the signal intensity of the residual charge signal D12 is larger than a predetermined intensity threshold Sth, the weighting coefficient k is set to a fixed value (here, the maximum value is 1.0). On the other hand, when the signal intensity is equal to or less than the intensity threshold Sth, the weighting coefficient is set to 0 (zero). That is, when the signal intensity of the residual charge signal D12 is equal to or less than the intensity threshold value Sth, no substantial weighting process is performed on the imaging signal D11.

  Next, as shown in the upper diagram of FIG. 19A, the addition processing unit 192 performs the addition process on the imaging signal D11 and the weighting signal (k × D12) in the same manner as the first signal processing method. Do. Thereby, the synthesized signal D2 (= D11 + k × D12) is generated.

  Subsequently, for example, as shown in FIG. 19B, the linearization processing unit 193 performs linearization processing on the synthesized signal D2 using the above equation (1), as in the first signal processing method. As a result, output data Dout is generated. In this way, output data Dout is generated by signal processing using the second signal processing technique.

  As described above, in the present embodiment, the imaging signal D11 obtained by the first readout operation within one frame period and the second and subsequent readout operations after the first reset operation are performed. Based on the residual charge signal D12, predetermined signal processing including at least addition processing is performed, and output data Dout is generated. That is, the output signal Dout is generated based on the addition process of the imaging signal D11 corresponding to the signal charge and the residual charge signal D12 corresponding to the residual charge. Thereby, the contrast in the output data Dout is improved.

  As described above, in the present embodiment, each pixel 20 is driven so that the readout operation and the reset operation are intermittently performed a plurality of times within a predetermined unit period (one frame period). At least an addition process is performed based on the imaging signal D11 obtained by the first readout operation and the residual charge signal D12 obtained by the second and subsequent readout operations after the first reset operation. To generate output data Dout. Thereby, the residual charge in the pixel after the reset operation can be reduced, and the contrast in the output data Dout can be improved. Therefore, it is possible to achieve high contrast while suppressing afterimages due to such residual charges, and it is possible to achieve high image quality of the captured image.

  In particular, when the capacitance is saturated in the pixel 20, the amount of afterimage charge increases, and the effect of increasing the contrast by the addition processing is increased. Further, for example, if the signal intensity of the residual charge signal D12 is non-linear with respect to the exposure intensity, which is different from the characteristics shown in FIG. 17, such addition processing of the residual charge signal D12 is performed. As a result, a more accurate captured image can be obtained.

<Modification>
Subsequently, modified examples (modified examples 1 to 8) of the above-described embodiment will be described. In addition, the same code | symbol is attached | subjected to the same thing as the component in embodiment, and description is abbreviate | omitted suitably.

[Modification 1]
FIG. 20A illustrates a block configuration of the frame memory 18 and the signal processing unit (signal processing unit 19A) according to the first modification. The signal processing unit 19A of the present modification has a configuration in which the weighting processing unit 191 and the linearization processing unit 193 are not provided (omitted) in the signal processing unit 19 of the above embodiment. Only the processing unit 192 is included.

  That is, in the addition processing unit 192 of this modification, output data Dout (= D11 + D12) is generated only by the addition processing of the imaging data D11 and the residual charge signal D12.

  As described above, in some cases, the weighting processing unit 191 and the linearization processing unit 193 may not be provided in the signal processing unit. Also in this modified example having such a configuration, it is possible to obtain the same effect as the above-described embodiment. That is, it is possible to achieve high contrast while suppressing afterimages due to residual charges, and it is possible to achieve high image quality of captured images.

[Modification 2]
FIG. 20B illustrates a block configuration of the frame memory 18 and the signal processing unit (signal processing unit 19B) according to the second modification. Unlike the above embodiment, the frame memory 18 of the present modification has three frame memories 181, 182 and 183. The frame memory 181 is a frame memory for temporarily holding the imaging signal D11, and the frame memory 182 is a frame memory for temporarily holding the residual charge signal D12 obtained by the second read operation. . On the other hand, the frame memory 183 is a frame memory for temporarily holding the residual charge signal D13 obtained by the third read operation.

  Further, the signal processing unit 19B according to the present modification generates output data Dout by performing predetermined signal processing based on the imaging signal D11 and the residual charge signals D12 and D13. Specifically, the weighting processing unit 191 performs weighting processing by multiplying the residual charge signal D12 by a weighting coefficient k1, and generates a weighting signal (k1 × D12). At the same time, a weighting process is performed by multiplying the residual charge signal D13 by a weighting coefficient k2 to generate a weighting signal (k2 × D13). The addition processing unit 192 performs addition processing on the imaging signal D11 and the weighting signals (k1 × D12) and (k2 × D13). Thereby, the composite signal D3 (= D11 + k1 × D12 + k2 × D13) is generated. Then, the linearization processing unit 193 generates output data Dout by performing linearization processing on the synthesized signal D3 in the same manner as the above-described equation (1).

  As described above, the reading operation is intermittently performed three or more times within a predetermined unit period (one frame period) so that the residual charge signal is obtained a plurality of times, and the residual charge signal of the plurality of times is obtained. Each may be used to perform signal processing including addition processing. Here, an example in which signal processing is performed using all of a plurality of residual charge signals (two residual charge signals D12 and D13) has been described. (For example, a residual charge signal having a particularly high signal intensity) may be selectively used.

[Modification 3]
FIG. 21 illustrates a circuit configuration of a pixel (pixel 20A) according to Modification 3 together with the circuit configuration example of the column selection unit 17 described in the above embodiment. Similar to the pixel 20 of the embodiment, the pixel 20 </ b> A of this modification has a so-called passive circuit configuration, and includes one photoelectric conversion element 21 and one transistor 22. Similarly to the pixel 20, the pixel 20A is connected to a read control line Lread extending along the H direction and a signal line Lsig extending along the V direction.

  However, in the pixel 20 </ b> A, the arrangement direction (direction) of the photoelectric conversion element 21 is opposite to that of the pixel 20. That is, in the pixel 20A, the anode of the photoelectric conversion element 21 is connected to the storage node N, and the cathode is connected to the ground (ground).

  Even in the imaging apparatus having the pixel 20A having such a configuration, the same effect can be obtained by the same operation as that of the imaging apparatus 1 of the above-described embodiment.

[Modifications 4 and 5]
(Circuit configuration)
FIG. 22 illustrates a circuit configuration of a pixel (pixel 20B) according to Modification 4 together with a circuit configuration example of a column selection unit 17B described below. FIG. 23 illustrates a circuit configuration of a pixel (pixel 20C) according to the modification 5 together with a circuit configuration example of the column selection unit 17B. Unlike the pixels 20 and 20A described so far, the pixels 20B and 20C according to these modification examples 4 and 5 have so-called active circuit configurations.

  Specifically, the active pixels 20B and 20C are provided with one photoelectric conversion element 21 and three transistors 22, 23, and 24. A read control line Lread and a reset control line Lrst extending along the H direction and a signal line Lsig extending along the V direction are also connected to the pixels 20B and 20C.

  In each of the pixels 20B and 20C, the gate of the transistor 22 is connected to the read control line Lread, the source is connected to the signal line Lsig, and the drain is connected to the drain of the transistor 23 constituting the source follower circuit. The source of the transistor 23 is connected to the power supply VDD, the gate is the cathode (pixel 20B shown in FIG. 22) or the anode (pixel 20C shown in FIG. 23) (storage node N) of the photoelectric conversion element 21, and the reset transistor. Is connected to the drain of the transistor 24 functioning as The gate of the transistor 24 is connected to the reset control line Lrst, and the reset voltage Vrst is applied to the source. The anode (pixel 20B) or cathode (pixel 20C) of the photoelectric conversion element 21 is connected to the ground.

  In addition, the column selection unit 17B according to the modification examples 4 and 5 illustrated in FIGS. 22 and 23 includes the constant current source 171 and the column selection unit 17 instead of the charge amplifier 172, the capacitive element C1, and the switch SW1. An amplifier 176 is provided. In the amplifier 176, the signal line Lsig is connected to the positive input terminal, and the negative input terminal and the output terminal are connected to each other to form a voltage follower circuit. One terminal of the constant current source 171 is connected to one end side of the signal line Lsig, and the power source VSS is connected to the other terminal of the constant current source 171.

(Action / Effect)
In the imaging devices of Modifications 4 and 5 having the pixels 20B and 20C having such an active circuit configuration, an imaging operation (line-sequential imaging driving) is performed as follows.

  That is, first, in the imaging apparatus having the pixels 20 and 20A having the passive circuit configuration described so far, for example, line-sequential imaging driving is performed as shown in FIG. Specifically, the line-sequential readout drive and the line-sequential reset drive are performed substantially simultaneously by a single line-sequential drive (drive for performing a line-sequential operation in the first readout / reset period Tr1).

  On the other hand, in the imaging apparatus having the pixels 20B and 20C having the active circuit configuration as in the modification examples 4 and 5, line sequential imaging driving is performed as shown in FIG. 24B, for example. . Specifically, line-sequential readout driving and line-sequential reset driving each time (here, the first and second times) are performed independently of each other. That is, a line sequential read drive for performing a line sequential operation in the first read period Tr1a, a first line sequential reset drive for performing a line sequential operation in a first reset period (first reset period Tr1b), The second line sequential reset drive for performing the line sequential operation in the second reset period (second readout / reset period Tr2) is performed independently of each other. In the case of this active circuit configuration, the reset operation in each line-sequential reset drive is performed when the transistor 24 functioning as a reset transistor is turned on.

  Thus, the same can be said for the imaging device having the pixels 20B and 20C having the active circuit configuration as in the passive circuit configuration described so far. That is, the imaging signal D11 obtained by the first readout operation within the unit period (one frame period) and the residual charge signal D12 obtained by the second and subsequent readout operations after the first reset operation is performed. Based on the above, output data Dout is generated by performing at least an addition process. Thereby, the residual charge in the pixel after the reset operation can be reduced, and the contrast in the output data Dout can be improved. Therefore, it is possible to achieve high contrast while suppressing afterimages due to such residual charges, and it is possible to achieve high image quality of the captured image.

[Modification 6]
FIG. 25 schematically illustrates an example of line-sequential imaging driving and signal processing according to Modification 6 using a timing waveform diagram.

  In the present modification, unlike the above embodiment, the read operation and the reset operation are performed only once each within one frame period (one vertical period) ΔTv. That is, the first read / reset period Tr1 is provided in the one frame period ΔTv, but the second read / reset period Tr2 is not provided. The exposure period Tex is not provided for each frame period ΔTv, and one exposure period Tex is provided for each of a plurality of frame periods (here, three frame periods (3 × ΔTv)). .

  That is, in the present modification, as shown in FIG. 25, the read operation is performed a plurality of times (here, three times) within a plurality of frame periods (here, (3 × ΔTv)) which are predetermined unit periods. Then, an imaging signal D11 and a residual charge signal (here, two residual charge signals D12 and D13) are obtained. Then, output data Dout is generated by performing signal processing similar to that of the above-described embodiment based on the imaging signal D11 and the residual charge signal. Note that such an operation corresponds to setting the frame rate of the read operation and the reset operation higher than the frame rate of the exposure operation and the moving image (here, the frame rate is set to three times).

  As described above, even when a plurality of frame periods are set as a predetermined unit period instead of a single frame period and the same signal processing as that in the above embodiment is performed, the same effect can be obtained. is there. That is, it is possible to achieve high contrast while suppressing afterimages due to residual charges, and it is possible to achieve high image quality of captured images.

[Modifications 7 and 8]
FIGS. 26A and 26B schematically show the schematic configuration of the imaging units (imaging units 11A and 11B) according to the modified examples 7 and 8, respectively.

  First, the imaging unit 11A according to the modified example 7 illustrated in FIG. 26A further includes a wavelength conversion layer 112 in addition to the photoelectric conversion layer 111 described in the above embodiment. Specifically, the wavelength conversion layer 112 is provided on the photoelectric conversion layer 111 (on the light receiving surface (imaging surface) side of the imaging unit 11A).

The wavelength conversion layer 112 converts the wavelength of radiation Rrad (α-ray, β-ray, γ-ray, X-ray, etc.) into the sensitivity range of the photoelectric conversion layer 111, and in the photoelectric conversion layer 111, this radiation Rrad It is possible to read information based on. The wavelength conversion layer 112 is made of a phosphor (for example, a scintillator) that converts radiation such as X-rays into visible light. In such a wavelength conversion layer 112, for example, an organic flattening film, a flattening film made of a spin-on-glass material, or the like is formed on the photoelectric conversion layer 111, and a phosphor film is formed thereon with CsI: T1, Gd ₂ It can be obtained by forming with O ₂ S, CsI, NaI, CaF ₂ or the like.

  On the other hand, an imaging unit 11B according to Modification 8 illustrated in FIG. 26B includes a photoelectric conversion layer 111B instead of the photoelectric conversion layer 111 described in the above embodiment. This photoelectric conversion layer 111B directly generates an electrical signal according to the incident radiation Rrad. That is, the imaging unit 11A of the modified example 7 shown in FIG. 26A is applied to a so-called indirect radiation imaging apparatus, whereas the imaging unit 11B of the modified example 8 is a so-called direct type. It is applied to a radiation imaging apparatus. Note that the photoelectric conversion layer 111B applied to such a direct type is made of, for example, an amorphous selenium (a-Se) semiconductor, a cadmium tellurium (CdTe) semiconductor, or the like.

  In the imaging devices according to the modified examples 7 and 8 having the imaging units 11A and 11B having such a configuration, the imaging units 11A and 11B generate an electrical signal according to the incident radiation Rrad, and the radiation imaging It is configured as a device. Such a radiation imaging apparatus is, for example, a medical device (an X-ray imaging apparatus such as Digital Radiography), an X-ray imaging apparatus for portable object inspection used in an airport or the like, an industrial X-ray imaging apparatus (for example, a danger in a container). The present invention can be applied to an apparatus for inspecting objects and the like, and inspecting contents of bags and the like.

<Application example>
Next, application examples of the imaging apparatus according to the above-described embodiment and each modification (Modifications 1 to 8) to an imaging display system will be described.

  FIG. 27 schematically illustrates a schematic configuration example of an imaging display system (imaging display system 5) according to an application example. The imaging display system 5 includes the imaging device 1 having the imaging unit 11 (11A, 11B) and the like according to the above-described embodiment, the image processing unit 52, and the display device 4, and in this example, radiation is emitted. The imaging display system used (radiation imaging display system) is used.

  The image processing unit 52 generates image data D4 by performing predetermined image processing on output data Dout (imaging signal) output from the imaging device 1. The display device 4 performs image display on the predetermined monitor screen 40 based on the image data D4 generated by the image processing unit 52.

  In the imaging display system 5 having such a configuration, the imaging device 1 (here, the radiation imaging device) emits irradiated light (here, a radiation source such as an X-ray source) 51 toward the subject 50 (here. In this case, the image data Dout of the subject 50 is acquired based on the radiation and is output to the image processing unit 52. The image processing unit 52 performs the predetermined image processing described above on the input image data Dout, and outputs the image data (display data) D4 after the image processing to the display device 4. The display device 4 displays image information (captured image) on the monitor screen 40 based on the input image data D4.

  As described above, in the imaging display system 5 of this application example, the image of the subject 50 can be acquired as an electrical signal in the imaging device 1, so that the acquired electrical signal is transmitted to the display device 4 to display an image. Can do. That is, it is possible to observe the image of the subject 50 without using a conventional radiographic film, and it is also possible to handle moving image shooting and moving image display.

  In this application example, the case where the imaging apparatus 1 is configured as a radiation imaging apparatus and is an imaging display system using radiation has been described as an example. The present invention can also be applied to an apparatus using an imaging apparatus of the above type.

<Other variations>
As described above, the technology of the present disclosure has been described with the embodiment, the modification, and the application example. However, the present technology is not limited to the embodiment and the like, and various modifications can be made.

  For example, the circuit configuration of the pixel in the imaging unit is not limited to the one described in the above embodiment and the like (the circuit configuration of the pixels 20, 20A to 20C), and may be another circuit configuration. Similarly, the circuit configuration of the column selection unit and the like, and the block configuration of the frame memory and the signal processing unit are not limited to those described in the above-described embodiment, and other circuit configurations may be used.

  In the above-described embodiment and the like, the case where the read operation and the reset operation are performed twice or three times within a predetermined unit period (one frame period or a plurality of frame periods) has been described as an example. It is not limited to. That is, for example, four or more read operations and reset operations may be performed within a predetermined unit period (one frame period or a plurality of frame periods).

  Furthermore, the imaging unit, row scanning unit, A / D conversion unit (column selection unit), column scanning unit, and the like described in the above embodiments may be formed on the same substrate, for example. Specifically, by using a polycrystalline semiconductor such as low-temperature polycrystalline silicon, switches and the like in these circuit portions can be formed on the same substrate. For this reason, for example, it becomes possible to perform a driving operation on the same substrate based on a control signal from an external system control unit, and to improve reliability when narrowing the frame (three-side free frame structure) or wiring connection. Can be realized.

In addition, this technique can also take the following structures.
(1)
An imaging unit having a plurality of pixels each including a photoelectric conversion element;
A drive unit that drives each pixel such that a read operation for reading out the charge obtained by the photoelectric conversion element as a signal from the pixel and a reset operation for resetting the charge in the pixel are respectively performed;
A signal processing unit that performs predetermined signal processing based on a signal obtained by the read operation and generates an output signal;
The drive unit drives each pixel such that the readout operation and the reset operation are intermittently performed a plurality of times within a predetermined unit period,
The signal processing unit is obtained by the first signal obtained by the first read operation in the unit period and the second and subsequent read operations after the first reset operation is performed. An imaging device that generates the output signal by performing at least addition processing as the signal processing based on the second signal.
(2)
The signal processing unit performs the addition process on the first signal and a weighted signal obtained by performing a predetermined weighting process on the second signal, thereby obtaining the output signal. Generate the imaging device according to (1).
(3)
The signal processing unit performs the weighting process using a predetermined weighting coefficient,
The imaging according to (2), wherein the weighting coefficient is set to be smaller when the signal strength of the second signal is relatively low than when the signal strength is relatively high. apparatus.
(4)
The imaging device according to (3), wherein when the signal intensity of the second signal is equal to or less than a predetermined threshold, the weighting coefficient is gradually decreased as the signal intensity decreases. .
(5)
The imaging device according to (3), wherein the weighting coefficient is set to 0 (zero) when the signal intensity of the second signal is equal to or less than the threshold value.
(6)
The signal processing unit performs the addition process,
The output signal is generated by performing a linearization process for linearizing a correspondence relationship between an exposure intensity at the time of imaging and a signal intensity of the output signal. Imaging device.
(7)
The driving unit drives each pixel so that the reading operation is intermittently performed three times or more within the unit period,
The signal processing unit outputs the second signal of all times or the second signal of selected times among the second signals obtained by a plurality of read operations after the second time. The imaging apparatus according to any one of (1) to (6), wherein the signal processing is performed.
(8)
The imaging device according to any one of (1) to (7), wherein the unit period is one frame period or a plurality of frame periods.
(9)
The imaging apparatus according to any one of (1) to (8), wherein the readout operation and the reset operation are simultaneously performed by a single drive.
(10)
The drive unit includes a charge amplifier in which a signal line used when performing the read operation is connected to one input terminal and a predetermined reset voltage is input to the other input terminal;
The imaging apparatus according to (9), wherein the reset operation is performed together with the readout operation using a virtual short-circuit phenomenon in the charge amplifier.
(11)
The imaging device according to any one of (1) to (8), wherein the readout operation and the reset operation are individually performed by mutually independent driving.
(12)
Each pixel has a reset transistor,
The imaging device according to (11), wherein the reset operation is performed when the reset transistor is turned on.
(13)
The imaging device according to any one of (1) to (12), wherein the reset operation is intermittently performed a plurality of times over a period exceeding one horizontal period.
(14)
The imaging apparatus according to any one of (1) to (13), wherein the photoelectric conversion element includes a PIN-type or MIS-type photodiode.
(15)
The imaging device according to any one of (1) to (14), wherein the imaging unit generates an electrical signal according to incident radiation and is configured as a radiation imaging device.
(16)
The imaging unit
A photoelectric conversion layer constituting the photoelectric conversion element;
The imaging device according to (15), further comprising: a wavelength conversion layer that converts the wavelength of the radiation into a sensitivity range of the photoelectric conversion layer.
(17)
The imaging device according to (15), wherein the imaging unit includes a photoelectric conversion layer that constitutes the photoelectric conversion element and directly generates the electrical signal in accordance with the radiation.
(18)
The imaging device according to any one of (15) to (17), wherein the radiation is X-rays.
(19)
An imaging device, and a display device that displays an image based on an imaging signal obtained by the imaging device,
The imaging device
An imaging unit having a plurality of pixels each including a photoelectric conversion element;
A drive unit that drives each pixel such that a read operation for reading out the charge obtained by the photoelectric conversion element as a signal from the pixel and a reset operation for resetting the charge in the pixel are respectively performed;
A signal processing unit that performs predetermined signal processing based on a signal obtained by the read operation and generates an output signal;
The drive unit drives each pixel such that the readout operation and the reset operation are intermittently performed a plurality of times within a predetermined unit period,
The signal processing unit is obtained by the first signal obtained by the first read operation in the unit period and the second and subsequent read operations after the first reset operation is performed. An imaging display system that generates the output signal by performing at least addition processing as the signal processing based on a second signal.

  DESCRIPTION OF SYMBOLS 1 ... Imaging device 11, 11A, 11B ... Imaging part, 111, 111B ... Photoelectric conversion layer, 112 ... Wavelength conversion layer, 13 ... Row scanning part, 14 ... A / D conversion part, 15 ... Column scanning part, 16 ... System control unit 17, 17B ... column selection unit, 171 ... constant current source, 172 ... charge amplifier, 173 ... S / H circuit, 174 ... multiplexer circuit, 175 ... A / D converter, 176 ... amplifier, 18, 181-1 183 ... Frame memory, 19, 19A, 19B ... Signal processing unit, 191 ... Weighting processing unit, 192 ... Addition processing unit, 193 ... Linearization processing unit, 20, 20A to 20C ... Pixel (imaging pixel), 21 ... Photoelectric conversion Element, 21P ... p-type semiconductor layer, 21N ... n-type semiconductor layer, 21I ... Intrinsic semiconductor layer (i region), 21G ... Gate electrode, 22, 23, 24 ... Transistor, 4 ... Display device, 4 ... monitor screen, 5 ... imaging display system, 50 ... subject, 51 ... light source (radiation source), 52 ... image processing unit, Lsig ... signal line, Lread ... read control line, Lrst ... reset control line, Lcarst ... amplifier reset control Line, D11 ... Imaging signal, D12, D13 ... Residual charge signal, D2, D3 ... Composite signal, D4 ... Image data, Dout ... Output data, Vrst ... Reset voltage, N ... Storage node, SW1, SW2 ... Switch, C1 ... Capacitance elements, Cgp, Cdp ... parasitic capacitance, ΔTv ... 1 vertical period (1 frame period), ΔTh ... 1 horizontal period, Tex ... exposure period, Tr1 ... first readout / reset period, Tr1a ... first readout period, Tr1b ... First reset period, Tr2 ... second read / reset period, ΔTr1, ΔTr2 ... line sequential drive period, k, k1, k2 ... weighting coefficients, Sth ... intensity threshold, in ... imaging light, Rrad ... radiation.

Claims (19)

An imaging unit having a plurality of pixels each including a photoelectric conversion element;
A drive unit that drives each pixel such that a read operation for reading out the charge obtained by the photoelectric conversion element as a signal from the pixel and a reset operation for resetting the charge in the pixel are respectively performed;
A signal processing unit that performs predetermined signal processing based on a signal obtained by the read operation and generates an output signal;
The drive unit drives each pixel such that the readout operation and the reset operation are intermittently performed a plurality of times within a predetermined unit period,
The signal processing unit is obtained by the first signal obtained by the first read operation in the unit period and the second and subsequent read operations after the first reset operation is performed. An imaging device that generates the output signal by performing at least addition processing as the signal processing based on the second signal. The signal processing unit performs the addition process on the first signal and a weighted signal obtained by performing a predetermined weighting process on the second signal, thereby obtaining the output signal. The imaging device according to claim 1 to generate. The signal processing unit performs the weighting process using a predetermined weighting coefficient,
The imaging device according to claim 2, wherein the weighting coefficient is set to be smaller when the signal strength of the second signal is relatively low than when the signal strength is relatively high. . The imaging apparatus according to claim 3, wherein when the signal intensity of the second signal is equal to or less than a predetermined threshold, the weighting coefficient is set to gradually decrease as the signal intensity decreases. The imaging device according to claim 3, wherein the weighting coefficient is set to 0 (zero) when the signal intensity of the second signal is equal to or less than the threshold value. The signal processing unit performs the addition process,
The imaging apparatus according to claim 2, wherein the output signal is generated by performing a linearization process for linearizing a correspondence relationship between an exposure intensity at the time of imaging and a signal intensity of the output signal. The driving unit drives each pixel so that the reading operation is intermittently performed three times or more within the unit period,
The signal processing unit outputs the second signal of all times or the second signal of selected times among the second signals obtained by a plurality of read operations after the second time. The imaging apparatus according to claim 1, wherein the signal processing is performed. The imaging device according to claim 1, wherein the unit period is one frame period or a plurality of frame periods. The imaging apparatus according to claim 1, wherein the readout operation and the reset operation are simultaneously performed by a single drive. The drive unit includes a charge amplifier in which a signal line used when performing the read operation is connected to one input terminal and a predetermined reset voltage is input to the other input terminal;
The imaging device according to claim 9, wherein the reset operation is performed together with the read operation using a virtual short-circuit phenomenon in the charge amplifier. The imaging apparatus according to claim 1, wherein the readout operation and the reset operation are individually performed by mutually independent driving. Each pixel has a reset transistor,
The imaging device according to claim 11, wherein the reset operation is performed when the reset transistor is turned on. The imaging device according to claim 1, wherein the reset operation is intermittently performed a plurality of times over a period exceeding one horizontal period. The imaging device according to claim 1, wherein the photoelectric conversion element includes a PIN type or MIS type photodiode. The imaging device according to claim 1, wherein the imaging unit generates an electrical signal in accordance with incident radiation, and is configured as a radiation imaging device. The imaging unit
A photoelectric conversion layer constituting the photoelectric conversion element;
The imaging device according to claim 15, further comprising: a wavelength conversion layer that converts the wavelength of the radiation into a sensitivity range of the photoelectric conversion layer. The imaging apparatus according to claim 15, wherein the imaging unit includes a photoelectric conversion layer that constitutes the photoelectric conversion element and directly generates the electrical signal according to the radiation. The imaging device according to claim 15, wherein the radiation is X-rays. An imaging device, and a display device that displays an image based on an imaging signal obtained by the imaging device,
The imaging device
An imaging unit having a plurality of pixels each including a photoelectric conversion element;
A drive unit that drives each pixel such that a read operation for reading out the charge obtained by the photoelectric conversion element as a signal from the pixel and a reset operation for resetting the charge in the pixel are respectively performed;
A signal processing unit that performs predetermined signal processing based on a signal obtained by the read operation and generates an output signal;
The drive unit drives each pixel such that the readout operation and the reset operation are intermittently performed a plurality of times within a predetermined unit period,
The signal processing unit is obtained by the first signal obtained by the first read operation in the unit period and the second and subsequent read operations after the first reset operation is performed. An imaging display system that generates the output signal by performing at least addition processing as the signal processing based on a second signal.

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