JP2013080965A - Fabrication process of epitaxial wafer and epitaxial wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique for fabricating an epitaxial wafer having a steeper and more stable spread resistance (SR) profile.SOLUTION: A fabrication process of an epitaxial wafer comprises: a first growth step (first growth process) for growing, directly over a substrate S made of silicon single crystals containing impurities, a first layer having a lower impurity concentration than that of the substrate S by vapor-phase deposition; and a second growth step (second growth process) for growing by vapor-phase deposition a second layer over the first layer. In the first growth step, air is forcibly discharged so as to grow the layer by vapor-phase deposition under a first pressure RP lower than or equal to atmospheric pressure AP. In the second growth step, the layer is grown by vapor-phase deposition under a second pressure AP higher than the first pressure RP.

Description

  The present invention relates to an epitaxial wafer manufacturing method and an epitaxial wafer in which a thin film layer is formed by epitaxial growth on a substrate containing impurities.

  Conventionally, an epitaxial wafer is manufactured by performing epitaxial growth on a substrate (Substrate).

  When epitaxial growth is performed using a substrate containing a high-concentration impurity (for example, arsenic As), for example, the impurity jumping out of the substrate stays in the chamber of the epitaxial reactor and is taken into the epitaxial layer. . That is, auto dope occurs. When this auto-doping occurs, the resistance of the epitaxial layer is affected and does not become a desired resistance, and the SR (Spread Resistance) profile of the epitaxial wafer becomes gentle (sagging).

  On the other hand, the first vapor phase growth step of vapor-growing the first layer on the substrate and the second layer having a lower impurity concentration than the first layer are vapor-phase grown directly on the first layer. A silicon single crystal in which the dopant concentration is sharply changed by providing an intermediate step of purging impurities in the growth atmosphere by lowering the atmospheric pressure between the two vapor phase growth steps than in the first vapor phase growth step. A technique for manufacturing a thin film is known (for example, Patent Document 1).

Japanese Patent No. 3312553

  By the way, it is required that the characteristics of devices manufactured using an epitaxial wafer do not vary from device to device, and it is required to manufacture an epitaxial wafer having a steeper and more stable SR profile. . There is a demand for further sharpening than the technique of Patent Document 1 described above.

  In addition, by making the inside of the chamber in a reduced pressure state, it is possible to suppress autodoping by removing impurities that have jumped out of the substrate from the inside of the chamber.

However, a growth gas that is difficult to etch the substrate (impact of jumping out impurities), that is, a growth gas that has no or relatively little chlorine component (for example, SiH ₄ (silane), SiH ₂ Cl ₂ (dichlorosilane)) is used. If it is used, it takes a long time to grow the thin film, thereby reducing productivity. On the other hand, when a growth gas containing a large amount of chlorine component (SiHCl ₃ (trichlorosilane)) is used in order to improve productivity, the by-product (for example, chlorine compound) is easily peeled off in the chamber. A large amount adheres to the nozzle and the periphery thereof, and there is a possibility that a defect may be generated in the wafer due to the peeled by-product.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a technique capable of manufacturing an epitaxial wafer having a steeper SR profile. Moreover, the objective of this invention is providing the technique which can improve the productivity of an epitaxial wafer.

  In order to achieve the above object, an epitaxial wafer manufacturing method according to a first aspect of the present invention includes vapor phase growth of a first layer having an impurity concentration lower than that of a substrate on a silicon single crystal substrate containing impurities. A method for manufacturing an epitaxial wafer, comprising: a first growth step to be performed; and a second growth step to vapor-phase grow a second layer above the first layer, wherein the exhaust is forcibly exhausted in the first growth step. And performing vapor phase growth under a first pressure equal to or lower than normal pressure, and in the second growth step, vapor phase growth is performed under a second pressure higher than the first pressure.

  According to such a method, when the first layer having an impurity concentration lower than that of the substrate is vapor-phase grown directly on the substrate, the gas is grown forcibly under the first pressure by being exhausted, so that the first layer jumps out of the substrate. Impurities can be effectively discharged. In addition, since the first layer having an impurity concentration lower than that of the substrate is vapor-phase grown, it is possible to suppress the influence of the impurity jumping out of the substrate or the layer in the subsequent vapor-phase growth step. In addition, since the second layer is vapor-grown under the second pressure, the vapor growth time under the first pressure can be shortened, and the gas under the first pressure can be shortened. The amount of by-products generated during phase growth can be suppressed. Thereby, an epitaxial wafer having a steeper and more stable SR profile can be manufactured.

  In the epitaxial wafer manufacturing method, the impurity concentration of the second layer may be higher than that of the first layer. According to such a method, it is possible to reduce the influence on the second layer due to the jumping out of impurities from the first layer, and to effectively control the SR profile of the second layer to a desired one.

  The epitaxial wafer manufacturing method further includes a temperature raising step for raising the temperature of the substrate to a predetermined temperature before the first growth step, and in the temperature raising step, the first pressure is reduced by forcibly evacuating. The substrate may be heated up below. According to such a method, it is possible to appropriately exclude impurities that jump out of the exposed substrate when the temperature is raised.

  In the epitaxial wafer manufacturing method, the first layer may be a non-doped layer. According to such a method, jumping out of impurities from the substrate can be effectively suppressed.

  The method for producing an epitaxial wafer may further include a third growth step in which at least one or more third layers are vapor-phase grown between the first layer and the second layer, and at least one or more third layers. The vapor phase growth of this layer may be performed under a first pressure by forcibly evacuating. According to this method, it is possible to form a plurality of layers on the substrate while suppressing the influence of the jumping out of impurities from the substrate.

  In the above epitaxial wafer manufacturing method, the total time for vapor phase growth under the first pressure is within a predetermined time, or the thickness of the layer to be vapor phase grown under the first pressure is a predetermined thickness. The following may be used. According to such a method, the amount of by-products generated during vapor phase growth under the first pressure can be suppressed, so that adverse effects due to by-products can be suppressed.

  In order to achieve the above object, an epitaxial wafer according to the second aspect of the present invention includes a substrate, a first layer formed immediately above the substrate and having an impurity concentration lower than that of the substrate, and the first layer. An epitaxial wafer having a transition region in which the resistivity changes sharply upward from the vicinity of the interface between the substrate and the first layer, the second layer being formed above, The average of the ratio of the second resistivity at about 5 μm upward from the transition region to the first resistivity in the vicinity of the surface of the second layer in the upper plurality of locations is 80% or more.

  In order to achieve the above object, an epitaxial wafer according to a third aspect of the present invention includes a substrate, a first layer formed immediately above the substrate and having an impurity concentration lower than that of the substrate, and the first layer. An epitaxial wafer having a transition region in which the resistivity changes sharply upward from the vicinity of the interface between the substrate and the first layer, the second layer being formed above, The minimum value of the ratio of the second resistivity at about 5 μm upward from the transition region to the first resistivity near the surface of the second layer in the upper plurality of locations is 70% or more, and the maximum value of the ratio is 90 percent or more.

  In order to achieve the above object, an epitaxial wafer according to the fourth aspect of the present invention includes a substrate, a first layer formed immediately above the substrate and having an impurity concentration lower than that of the substrate, and the first layer. An epitaxial wafer having a second layer formed above, the resistivity in the vicinity of the surface of the second layer is three orders of magnitude higher than the resistivity of the substrate, and the total layer thickness of the layers on the substrate is If the resistivity at 10 μm is higher than 10 μm and the resistivity in the vicinity of the surface of the second layer is 20 Ωcm or more from the interface between the substrate and the first layer, the surface of the second layer When the resistivity near the surface of the second layer is 15 to 20 Ωcm, it is 60 percent or more of the resistivity near the surface of the second layer.

  In order to achieve the above object, an epitaxial wafer according to a fifth aspect of the present invention includes a substrate, a first layer formed immediately above the substrate and having an impurity concentration lower than that of the substrate, and the first layer. An epitaxial wafer having a second layer formed above, wherein the resistivity in the vicinity of the surface of the second layer is three orders of magnitude higher than the resistivity of the substrate, and the interface between the substrate and the first layer From the above, when the resistivity at a position above the total thickness of the layers on the substrate by about 16.7% is higher than the resistivity near the surface of the second layer is 20 Ωcm or more, When the resistivity in the vicinity of the surface of the second layer is 50% or more and the resistivity in the vicinity of the surface of the second layer is 15 to 20 Ωcm, the resistivity in the vicinity of the surface of the second layer is 60% or more. is there.

  In order to achieve the above object, an epitaxial wafer according to a sixth aspect of the present invention includes a substrate, a first layer formed immediately above the substrate and having an impurity concentration lower than that of the substrate, and the first layer. An epitaxial wafer having a second layer formed above, the resistivity in the vicinity of the surface of the second layer is three orders of magnitude higher than the resistivity of the substrate, and the total layer thickness of the layers on the substrate is 10 μm, the resistivity in the vicinity of the surface of the second layer is 10 Ωcm or more, and the resistivity of the second layer at 10 μm from the interface between the substrate and the first layer is the surface of the second layer The resistivity in the vicinity is larger than 0.167 + 6.16 (Ωcm).

It is a block diagram of the reaction furnace which concerns on one Embodiment of this invention. It is a figure which shows the recipe of a wafer manufacturing process and comparison recipe which concern on one Embodiment of this invention. It is a figure which shows SR profile of the wafer manufactured by the manufacturing process which concerns on one Embodiment of this invention. It is a figure explaining the difference with the manufactured wafer which concerns on one Embodiment of this invention, and the wafer of a comparative example. It is a figure which shows SR profile of the wafer which concerns on one Embodiment of this invention, and SR profile of the wafer of a comparative example. It is a figure explaining the characteristic of the wafer which concerns on one Embodiment of this invention, and the wafer of a comparative example. It is a figure which shows SR profile of the wafer manufactured by the manufacturing process which concerns on the 1st modification of this invention. It is a figure which shows the recipe of the wafer manufacturing process which concerns on the 2nd modification of this invention.

  Embodiments of the present invention will be described with reference to the drawings. The embodiments described below do not limit the invention according to the claims, and all the elements and combinations described in the embodiments are essential for the solution of the invention. Is not limited.

  An epitaxial wafer manufacturing method according to an embodiment of the present invention will be described.

  First, the reactor used for the epitaxial wafer manufacturing method will be described.

  FIG. 1 is a configuration diagram of a reaction furnace according to an embodiment of the present invention. FIG. 1A shows a perspective view of the reaction furnace, and FIG. 1B shows a partial cross-sectional view of the reaction furnace.

  The reaction furnace 1 of the present embodiment is a batch furnace capable of performing an epitaxial growth process on a plurality of substrates S, and is a so-called pancake furnace as an example of a vertical furnace.

  The reaction furnace 1 is provided with a susceptor 3 for placing a plurality of substrates S for forming an epitaxial layer. The susceptor 3 is made of, for example, SiC (silicon carbide) and has a substantially disk shape having an opening at the center. The nozzle 4 is provided to extend upward from below through an opening in the center portion of the susceptor 3. The nozzle 4 is made of, for example, quartz. The nozzle 4 introduces a carrier gas, an epitaxial growth gas, and a dopant gas from a gas supply source (not shown) into the reaction furnace 1.

  A work coil 6 is provided below the susceptor 3, and the temperature of the substrate S placed on the susceptor 3 can be adjusted by adjusting the power supplied to the work coil 6.

  The reaction furnace 1 is provided with a bell jar 2 for accommodating the susceptor 3 in an internal space (inside the furnace). In the present embodiment, the bell jar 2 is pulled up to place the substrate S before the epitaxial growth is performed, and after the substrate S is placed, the bell jar 2 is pulled down to form an internal space for accommodating the susceptor 3 and the like. The bell jar 2 is pulled up to recover the substrate S on which the epitaxial layer manufactured after the epitaxial growth is completed, that is, the epitaxial wafer.

  In the reaction furnace 1, the gas supplied from the nozzle 4 flows above the susceptor 3 toward the outer periphery of the susceptor 3 as shown by an arrow in the drawing, proceeds downward on the outer periphery of the susceptor 3, and passes through the exhaust port 5. Discharged. The exhaust port 5 communicates with a decompression pump (not shown) so that the internal space can be forcibly exhausted and decompressed.

  Next, a specific flow of the epitaxial wafer manufacturing method according to an embodiment of the present invention will be described.

  FIG. 2 is a diagram showing a recipe and a comparison recipe of the manufacturing method according to one embodiment of the present invention. FIG. 2A shows a recipe according to an embodiment, and FIG. 2B shows a comparison recipe used for comparison.

  Here, before carrying out the epitaxial wafer manufacturing method, a plurality of substrates S to be processed are placed on the susceptor 3, the bell jar 2 is pulled down, and the internal space (inside the furnace) is external space by the bell jar 2. Shall be separated from each other. The substrate S contains impurities (for example, arsenic (As)), has a resistivity of, for example, 0.001 to 0.0045 Ωcm, and has a high impurity concentration.

First, in the epitaxial wafer manufacturing method according to the recipe, N ₂ gas is introduced from the nozzle 4 to purge the inside, and then H ₂ gas is introduced from the nozzle 4 to purge the inside (Purge process).

Next, the operation of the decompression pump is started while maintaining the introduction of H ₂ gas from the nozzle 4, and a predetermined pressure (first pressure) in which the pressure in the furnace is lower than the normal pressure from the normal pressure (second pressure). To be. Note that the operation by the decompression pump is continuously performed until the end of the 1st Growth step, and the inside of the furnace is maintained in a predetermined decompression state. Here, the predetermined pressure to be reduced is, for example, a pressure of 100 to 600 Torr (1 Torr≈133.322 Pa). As described above, since the inside of the furnace is forcibly evacuated so as to be in a predetermined reduced pressure state, impurities jumping out of the substrate S can be effectively excluded from the inside of the furnace. Note that the lower the pressure, the higher the amount that can be exhausted, while the amount of impurities jumping out from the substrate 3 may increase. For example, an extremely low pressure state such as a pressure of 100 to 600 Torr. Therefore, it is possible to suppress the influence of auto-doping caused by impurities jumping out from the substrate 3.

  Next, supply of electric power to the work coil 6 is started, and the substrate S is adjusted to a relatively high temperature (for example, 1050 to 1200 degrees) from normal temperature (RT) (Heat Up process). In this step, the substrate S is exposed, and as the temperature of the substrate S rises, more impurities jump out of the substrate S, but the furnace is forced to be exhausted to a predetermined reduced pressure state. Therefore, the impurities jumping out from the substrate S can be effectively removed from the furnace, and the influence of auto-doping can be effectively reduced.

  Next, dry etching is performed by further introducing HCl gas from the nozzle 4 into the furnace (the dry etching may not be performed in some cases). Thereafter, the introduction of HCl gas is stopped, the inside of the furnace is purged, and the inside of the furnace is ventilated.

Next, the epitaxial growth gas is introduced into the furnace while maintaining the forcible exhaust so that the inside of the furnace is in a predetermined reduced pressure state, and the first layer (first layer) is generated on the substrate S. (1st Growth process: 1st growth process). In this embodiment, since, for example, SiHCl ₃ is used as the epitaxial growth gas, the layer growth rate (Growth Rate) can be improved as compared with the case where SiH ₄ or SiH ₂ Cl ₂ is used. The required processing time can be shortened.

  In this embodiment, since the dopant gas is not introduced in this step, the first layer is a non-doped layer and has a lower impurity concentration than the substrate S. In the present embodiment, the first growth process is limited to a predetermined time (for example, 1 minute in the present embodiment), so that a by-product generated by the epitaxial growth gas generated during the epitaxial growth in a reduced pressure state ( (Chlorine compound) can be prevented from adhering to the furnace. In the present embodiment, the first layer has a thickness of 1 μm, for example. In the 1st Growth step, the furnace is forcibly evacuated so as to be in a predetermined reduced pressure state, so that impurities and generated by-products that jump out of the substrate S are effectively excluded from the furnace. be able to.

After the generation of the first layer, the introduction of the epitaxial growth gas is stopped, and the introduction of only the H ₂ gas is continued to purge the inside of the furnace. Next, the operation of the decompression pump is stopped, the interior of the furnace is changed from the decompressed state to the normal pressure state, the introduction of H ₂ gas is continued, and the interior of the furnace is ventilated.

  Thereafter, an epitaxial growth gas and a dopant gas (for example, phosphorus (P)) are further introduced into the furnace to generate a second layer (second layer) on the first layer (2nd Growth step: second Growth process). In the present embodiment, the supply amount of the dopant gas is adjusted so that the generated second layer has a lower impurity concentration than the substrate S and a higher impurity concentration than the first layer. For example, the resistivity in the vicinity of the surface of the second layer is adjusted to be, for example, 9.0 Ωcm so that the resistivity of the substrate S is 3 digits or more (1000 times or more) higher.

After a predetermined time has elapsed from the start of the generation of the second layer, the introduction of H ₂ gas is continued, while the introduction of the epitaxial growth gas is stopped, the furnace is purged, and power is supplied to the work coil 6 To control the substrate S to cool to room temperature. Thereafter, H ₂ gas is introduced from the nozzle 4 to cool the inside, and N ₂ gas is introduced from the nozzle 4 to cool the inside. Thereafter, the bell jar 2 is pulled up, and the substrate S on which the epitaxial layer is formed, that is, the epitaxial wafer can be taken out.

  According to the above-described epitaxial wafer manufacturing method, in the Heat up process and the 1st Growth process, the furnace is forcibly evacuated to a predetermined reduced pressure state. The produced by-product can be effectively removed from the furnace. For this reason, when manufacturing an epitaxial wafer sequentially using the same reactor 1, the SR profile of the epitaxial wafer manufactured sequentially can be stabilized, and the maintenance interval of the reactor 1 can be lengthened. .

  Next, the SR profile of the epitaxial wafer manufactured by this manufacturing process will be described.

  FIG. 3 is a view showing an SR profile of a manufactured wafer according to an embodiment of the present invention. FIG. 3 shows the SR profile of the wafer obtained by the manufacturing method according to the recipe according to the present embodiment and the SR profile of the wafer obtained by the manufacturing method according to the comparative recipe.

  Here, as shown in FIG. 2B, the comparative recipe is a recipe that always executes the manufacturing process under normal pressure (AP), and the recipe according to the present embodiment shown in FIG. 2A is under the normal pressure. The point to do is different.

  As shown in FIG. 3, the SR profile of the wafer manufactured by the manufacturing method according to the recipe according to the present embodiment is the substrate S and the SR profile of the wafer manufactured by the manufacturing method according to the comparative recipe. The rise in resistivity near the interface with the first layer (Depth = 0) is steep.

  Next, the difference between the wafer manufactured by the method according to the present embodiment and the wafer of the comparative example manufactured by the method according to the comparative recipe will be described using the inclination rate.

  FIG. 4 is a diagram illustrating a difference between a manufactured wafer according to an embodiment of the present invention and a wafer of a comparative example. FIG. 4A is a histogram of the gradient for the wafer manufactured according to the recipe according to the present embodiment, and FIG. 4B is a histogram of the gradient for the wafer of the comparative example manufactured according to the comparative recipe.

  Here, before explaining the gradient, the contents related to the gradient will be explained.

  First, a Schottky diode is formed on a wafer, and a resistivity is calculated using a CV (Capacitance Voltage) method. That is, a reverse DC bias is applied to the diode, the capacitance of the depletion layer generated in the wafer is measured, the impurity concentration is calculated based on the measured capacitance, applied voltage, predetermined constant, etc. The resistivity is calculated based on the concentration. As a method for forming a Schottky diode on a wafer, for example, a vapor deposition method by metal vapor deposition, an Hg-Probe method, or the like is known.

  In the present embodiment, for a certain position on the plane of the epitaxial wafer, a capacitance when a DC bias of a relatively low first voltage (for example, 3 V) is applied to a diode corresponding to the certain position is measured and measured. Calculate resistivity based on capacitance. This resistivity corresponds to the resistivity (first resistivity) in the vicinity of the surface of the second layer. Further, the capacitance when a DC bias of a second voltage (for example, 200 V) higher than the first voltage is applied to the diode is measured, and the resistivity is calculated based on the measured capacitance. This resistivity corresponds to the resistivity (second resistivity) at a position of approximately 5 μm upward from the transition region. Here, the transition region refers to a region where the resistivity changes sharply upward (surface direction) from the interface between the substrate and the first layer. In the epitaxial wafer of this embodiment, the substrate and the first layer The transition region is from 3 to 5 μm upward from the interface with the layer. Note that the position 5 μm upward from the transition region is a position where the profile starts to stabilize, and the resistivity at this position is preferably close to the value of the first resistivity.

  The slope is a resistivity (second resistivity) at a position approximately 5 μm upward from the transition region with respect to the resistivity (first resistivity) in the vicinity of the surface of the second layer at a certain position on the plane of the epitaxial wafer. ). That is, the gradient (percentage) is expressed by the second resistivity / first resistivity * 100.

  4A and 4B, the slopes shown in FIGS. 4A and 4B indicate the position of the center on the wafer plane and the position on the first straight line passing through the center for each of the plurality of wafers manufactured in the process corresponding to each figure. The slope ratios at the respective positions of the position (for example, four points) and a plurality of positions (for example, four points) on the second straight line passing through the center and orthogonal to the first straight line are tabulated.

  As shown in FIG. 4A, the inclination rate of the wafer manufactured according to the comparative recipe is 89.13% for the maximum value (MAX), 68.58% for the minimum value (MIN), and 78% for the average (AVE). The standard deviation (STD) is 4.07 percent.

  On the other hand, as shown in FIG. 4B, the inclination rate of the wafer manufactured according to the recipe of the present embodiment is 95.36% for the maximum value (MAX) of the inclination rate, 86.06% for the minimum value (MIN), and the average. (AVE) is 91.49%, and standard deviation (STD) is 2.19%. Unlike the wafer according to the comparative recipe, the wafer according to the recipe of the present embodiment has an average gradient of 80% or more, a maximum gradient of 90% or more, and a minimum gradient of 70% or more. is there.

  Next, a description will be given of a plurality of wafers manufactured so that the resistivity (surface vicinity resistivity) in the vicinity of the surface of the second layer which is the outermost layer (surface layer) is different. Here, wafers having different near-surface resistivity in the second layer can be manufactured by varying the concentration of the dopant gas supplied into the furnace in the 2nd Growth step of the recipe shown in FIG. In this embodiment, the higher the near-surface resistivity of the second layer, the smaller the supply amount of dopant gas.

  FIG. 5 is a diagram illustrating a manufactured wafer according to an embodiment of the present invention, a SR profile of a wafer calculated based on the result, and a SR profile of a comparative wafer. FIG. 5A shows a plurality of wafers calculated from the results of Non Dope growth manufactured according to the comparative recipe so that the resistivity near the surface of the second layer of the wafer is 10, 20, 30, 40, and 50 Ωcm, respectively. FIG. 5B shows a non-dope growth result manufactured according to the recipe according to the embodiment, and the resistivity in the vicinity of the surface of the second layer of the wafer is 3 digits or more (1000 times or more) than the resistivity of the substrate. ) The SR profiles of a plurality of wafers calculated to have high resistivity of 10, 20, 30, 40, and 50 Ωcm, respectively.

  As shown in FIGS. 5A and 5B, for wafers manufactured according to the respective recipes so that the resistivity near the surface of the second layer has the same value, the resistivity near the surface of the second layer is 10, 20 , 30, 40, and 50 Ωcm, it can be seen that the SR profile of the wafer manufactured by the recipe according to this embodiment is steeper than that of the wafer manufactured by the comparative recipe.

  FIG. 6 is a diagram illustrating characteristics of a wafer according to an embodiment of the present invention and a wafer according to a comparison recipe.

  FIG. 6A shows the resistivity near the surface of the second layer in the wafer according to the comparative recipe, the resistivity at a predetermined position from the substrate in the second layer (predetermined position resistivity), and the predetermined position resistivity relative to the resistivity near the surface. FIG. 6B shows the resistivity in the vicinity of the surface of the second layer in the wafer according to the present embodiment, and the resistivity at a predetermined position from the substrate in the second layer (predetermined position resistivity). FIG. 6C shows the resistivity near the surface of the second layer for each of the wafer of this embodiment and the wafer of the comparative example. It is a figure which shows the relationship with a predetermined position resistivity.

  In the present embodiment, the layer thickness of the first layer is, for example, 2 μm, and the total layer thickness (total epitaxial layer thickness) of the first layer and the second layer is more than 10 μm, for example, 60 μm. Here, the predetermined position is a position 10 μm upward from the interface between the substrate and the epitaxial layer in the second layer. Since the epitaxial layer thickness (total layer thickness of the layers on the substrate) of the wafer of this embodiment is 60 μm, the predetermined position is approximately 16.7 percent (10 μm / 60 μm × 100) of the epitaxial layer thickness from the substrate. It can also be called a position.

  As shown in FIG. 6A, when the resistivity near the surface of the second layer is 10 Ωcm, the wafer manufactured according to the comparative recipe has a predetermined position resistivity of 6.5 Ωcm, which is a predetermined relative to the resistivity near the surface. The ratio of the position resistivity is 65%. Similarly, when the resistivity near the surface is 20 Ωcm, the predetermined position resistivity is 9.5 Ωcm and the ratio is 47.5 percent, and when the resistivity near the surface is 30 Ωcm, the predetermined position resistivity is 11.1 Ωcm, the ratio is 37%, and when the resistivity near the surface is 40 Ωcm, the predetermined position resistivity is 12.4 Ωcm, and the ratio of the predetermined position resistivity to the resistivity near the surface is 31% When the resistivity in the vicinity of the surface is 50 Ωcm, the predetermined position resistivity is 13.4 Ωcm, and the ratio of the predetermined position resistivity to the resistivity in the vicinity of the surface is 26.8 percent.

  On the other hand, the wafer manufactured according to the recipe according to the present embodiment has a predetermined position resistivity of 8.81 Ωcm when the resistivity near the surface of the second layer is 10 Ωcm, as shown in FIG. The ratio of the predetermined position resistivity to the nearby resistivity is 88.1 percent. Similarly, when the resistivity near the surface is 15 Ωcm, the predetermined positional resistivity is 12.44 Ωcm and the ratio is 82.93 percent. When the resistivity near the surface is 20 Ωcm, the predetermined positional resistivity is When the resistivity is 15.67 Ωcm, the ratio is 78.35 percent, and the resistivity near the surface is 30 Ωcm, the predetermined position resistivity is 21.17 Ωcm, the proportion is 70.57 percent, and the resistivity near the surface is 40 Ωcm. In this case, the predetermined position resistivity is 25.66 Ωcm, the ratio of the predetermined position resistivity to the resistivity near the surface is 64.15%, and when the resistivity near the surface is 50 Ωcm, the predetermined position resistivity is The positional resistivity is 29.4 Ωcm, and the ratio of the predetermined positional resistivity to the resistivity near the surface is 58.8 percent.

  The wafer manufactured according to the recipe according to the embodiment can have a higher ratio of the predetermined position resistivity to the resistivity near the surface than the wafer manufactured according to the comparison recipe with the resistivity near the same surface, For example, when the resistivity in the vicinity of the surface of the second layer is 20 Ωcm or more, the ratio of the predetermined position resistivity to the resistivity in the vicinity of the surface can be 50% or more, and the resistance in the vicinity of the surface of the second layer can be increased. When the rate is 15 to 20 Ωcm, it can be 60% or more of the resistivity near the surface of the second layer, and when the resistivity near the surface of the second layer is 10 to 20 Ωcm, The resistivity in the vicinity of the surface of the two layers can be 70% or more.

  For a wafer manufactured according to the comparative recipe, as shown in FIG. 6C, the predetermined position resistivity y is 0.167 × resistivity near the surface x + 5.57 when linearly approximated. If the resistivity x near the surface is 10 Ωcm or more, the predetermined position resistivity y of the wafer according to the comparative recipe becomes the upper limit line, that is, 0.167 × resistivity x + 6.16 near the surface.

  On the other hand, as shown in FIG. 6C, the predetermined position resistivity y of the wafer manufactured by the recipe according to the present embodiment is expressed as 0.512 × resistivity x + 4.7789 in the vicinity of the surface when linearly approximated. The predetermined position resistivity y of the wafer manufactured by the recipe according to the present embodiment is a lower limit line, that is, 0.512 × resistivity x + 3.69 near the surface if the resistivity x near the surface is 10 Ωcm or more. It becomes.

  According to FIG. 6C, if the resistivity x near the surface is 10 Ωcm or more, the predetermined position resistivity (Ωcm) of the wafer manufactured by the recipe according to the present embodiment is the resistivity near the same surface by the comparative recipe. It is equal to or higher than the upper limit value (0.167 × surface resistivity x + 6.16) of the predetermined position resistivity y of the wafer having 0.512 × surface resistivity x + 3.69 or more.

  Next, a first modification according to this embodiment will be described.

  The first modification is basically the same as the recipe shown in FIG. 2A, but the specific processing in the 1st Growth process and the 2nd Growth process in the recipe is different. Specifically, in the 1st Growth process, the impurity concentration of the first layer is made lower than the impurity concentration of the substrate S, and in the 2nd Growth process, the impurity concentration of the second layer is lower than the impurity concentration of the first layer. I am doing so.

In the manufacturing method according to the first modification, in the 1st Growth step, under a reduced pressure, together with an epitaxial growth gas (for example, SiHCl ₃ ), an amount of dopant gas whose impurity concentration is lower in the first layer than in the substrate S is introduced The first layer is generated. In the first modification, the flow rate of the dopant gas is adjusted so that the resistivity of the first layer is 1.0 Ωcm. In the 2nd Growth process, the second layer is generated by introducing an amount of dopant gas having an impurity concentration lower than that of the first layer, together with an epitaxial growth gas (for example, SiHCl ₃ ). In this modification, the flow rate of the dopant gas is adjusted so that the resistivity of the second layer is 20.0 Ωcm.

  Next, the SR profile of the epitaxial wafer manufactured by the manufacturing process according to the first modification will be described.

  FIG. 7 is a diagram showing an SR profile of a manufactured wafer according to the first modification of the present invention. FIG. 7 shows the SR profile of the wafer obtained by the manufacturing method according to the first modification and the SR profile of the wafer obtained by the manufacturing method according to the comparative recipe. Here, the comparative recipe is different from the manufacturing process according to the first modification in that all processes are performed under normal pressure.

  As shown in FIG. 7, the SR profile of the wafer manufactured by the manufacturing method according to the first modification has a steeper rise in resistivity than the SR profile of the wafer manufactured by the manufacturing method according to the comparative recipe. It is.

  Next, an epitaxial wafer manufacturing method according to the second modification of the present invention will be described. The second modification is a method for manufacturing an epitaxial wafer having N (N is 3 or more) layers on a substrate S.

  FIG. 8 is a diagram showing a recipe for the manufacturing method according to the second modification of the present invention.

  The recipe according to the second modification is different from the recipe shown in FIG. 2A in that after the 1st Growth process, at least one or more film generation processes (2nd Growth process to (N-1) Growth process) performed under reduced pressure. It contains different points. Each layer is generated so that the impurity concentration is lower than that of the substrate S. The first layer may be a non-doped layer. Here, in the second modified example, the Nth layer corresponds to the second layer, and the second to N-1th layers correspond to the third layer.

  In the second modification, the total time of the layer generation process performed under reduced pressure is set to a predetermined time or less (for example, 5 minutes or less). Thereby, the by-product (for example, chlorine compound) produced | generated during the epitaxial growth under pressure reduction and adhering in a furnace can be suppressed.

  Also in the epitaxial wafer manufacturing method according to the second modification, the rise in resistivity in the vicinity of the interface (Depth = 0) between the substrate S and the first layer (epitaxial layer) is steep as in the above-described embodiment. An epitaxial wafer having an SR profile can be produced.

  Although the present invention has been described based on the embodiments, the present invention is not limited to the above-described embodiments, and can be applied to various other modes. For example, in the second modified example, the plurality of layers are performed under reduced pressure, and only the final layer is performed under normal pressure. For example, the step of generating the plurality of layers immediately before the final layer is performed under normal pressure. You may make it implement.

  In the above embodiment, the second pressure, which is higher than the first pressure, is normal pressure. However, the present invention is not limited to this, and the second pressure may be lower than normal pressure. The pressure may be higher than the pressure.

  Further, in the above embodiment, the vapor phase growth under reduced pressure is performed within a predetermined time, but the present invention is not limited to this, for example, the thickness of the layer by the vapor phase growth under reduced pressure. May be less than or equal to a predetermined thickness.

  Moreover, in the said embodiment, although the pancake type | mold reactor was used, this invention is not limited to this, For example, you may make it use other epitaxial growth furnaces, such as a cylinder type | mold reactor.

1 reactor, 2 bell jars, 3 susceptors, 4 nozzles, 5 outlets, 6 work coils, S substrate.

Claims (4)

Forcibly evacuating and directly using trichlorosilane as an epitaxial growth gas under a first pressure not higher than normal pressure directly above a silicon single crystal substrate containing impurities so that the impurity concentration is lower than that of the substrate. A first growth step of controlling the supply of dopant gas to form an epitaxial layer;
After the first growth step, a second growth step of forming an epitaxial layer by supplying a dopant gas so as to have an impurity concentration lower than that of the substrate under a second pressure higher than the first pressure;
A method of manufacturing an epitaxial wafer having The method for manufacturing an epitaxial wafer according to claim 1, wherein the supply of the dopant gas is controlled so that the dopant gas is not supplied in the first growth step. The manufacturing method of the epitaxial wafer of Claim 1 or Claim 2 which uses a trichlorosilane as an epitaxial growth gas in a said 2nd growth process. A third growth step of forming an epitaxial layer by supplying a dopant gas so as to have an impurity concentration lower than that of the substrate under the first pressure between the first growth step and the second growth step; The method for producing an epitaxial wafer according to any one of claims 1 to 3, further comprising:

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