JP2013074041A - Cmos semiconductor device manufacturing method and cmos semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a CMOS semiconductor device manufacturing method, featuring fine-pattern electric circuits and high productivity, which uses a micro-contact printing plate as an intaglio.SOLUTION: The CMOS semiconductor device manufacturing method includes: a process in which a P-channel region 101 of a P-channel field effect transistor and an N-channel region 102 of an N-channel field effect transistor are formed by printing using an intaglio 601 which has a first concavity 602 and a second concavity 603, the first concavity 602 being supplied with a P-type semiconductor ink 111 and the second concavity 602 being supplied with an N-type semiconductor ink 112 by an ink jet method; and a process in which the intaglio 601, after ink supply, is pressed against a printing target substrate 001, whereby the P-type semiconductor ink 111 supplied to the first concavity 602 and the N-type semiconductor ink 112 supplied to the second concavity 603 are collectively transcribed to the printing target substrate 001.

Description

  The present invention relates to a thin film transistor (TFT), and more particularly to a semiconductor device using a complementary metal oxide semiconductor (CMOS).

  Conventionally, photolithography and vacuum processes have been used to form electronic components such as circuit boards and display devices. In recent years, with the advancement of electronic technology, the size of elements has become smaller and the pattern forming the elements has been required to be miniaturized, while the size of the mother substrate has increased. . Therefore, compared with the manufacturing method using a conventional photoresist, a fine pattern using various printing methods instead of the photolithography method for productivity, cost, high accuracy, large area, and further miniaturization. The manufacturing method of this is proposed.

Printing methods include printing methods such as letterpress printing, intaglio printing, planographic printing, screen printing, and ink jet printing. These methods have a resolution limit of about 30 [• ang and low resolution to form a semiconductor device or a display device.
Among the printing methods, microcontact printing can be cited as a printing method capable of forming a fine line pattern (Non-Patent Document 1). These printing methods use a relatively soft plate with low surface energy, such as polydimethylsiloxane (PDMS), to transfer the dried (semi-dried) ink from the plate to the substrate without tearing the ink (cohesive failure). You can get a highly detailed pattern by doing

Langmuir, 10, 1498 (1994)

  The problem to be solved by the present invention is to use a microcontact printing plate as an intaglio to provide a fine electric circuit and a highly productive manufacturing method.

  As a means for solving the above problems, a method of manufacturing a CMOS semiconductor device according to claim 1 includes a CMOS circuit including a CMOS circuit configured by combining a P-channel field effect transistor and an N-channel field effect transistor. A P-channel region constituting the P-channel field effect transistor and an N-channel region constituting the N-channel field effect transistor are formed by a printing method using an intaglio, and the intaglio Comprises a first recess for forming the P channel region and a second recess for forming the N channel region, and the printing method using the intaglio is a non-contact inking method, Supplying a P-type semiconductor ink to the first recess and supplying an N-type semiconductor ink to the second recess; and After supplying the body ink and the N-type semiconductor ink, the intaglio is pressed against the substrate to be printed, and the P-type semiconductor ink supplied to the first recess and the N-type semiconductor ink supplied to the second recess are collectively And transferring to a substrate to be printed.

Furthermore, the method for manufacturing a CMOS semiconductor device according to claim 2 is characterized in that the non-contact inking method is one of a dispenser method and an ink jet method with respect to the configuration of claim 1. .
Furthermore, the method for manufacturing a CMOS semiconductor device according to claim 3 is the method for forming the P-type semiconductor ink and the N-channel region for forming the P-channel region in the configuration of the first or second aspect. N-type semiconductor ink is characterized by having a viscosity of 1 [mPa · s] to 30 [mPa · s].

Furthermore, in the method of manufacturing a CMOS semiconductor device according to claim 4, the P-type semiconductor ink and the N-type semiconductor ink are 1 [atm] in comparison with any one of the configurations of claims 1 to 3. It is characterized by containing a chemical solution having a boiling point of 130 [° C.] or higher.
Further, in the method of manufacturing a CMOS semiconductor device according to claim 5, in contrast to the structure of any one of claims 1 to 4, the intaglio is formed on a surface made of silicone resin or fluororesin by a molding method. A groove structure portion as a recess including the first recess and the second recess, and a flat portion obtained by flattening a portion other than the groove structure portion, and the width of the groove structure portion is 1 [· The surface is made of the silicone resin or the fluororesin and has a Shore A hardness of 30 to 80.

  Furthermore, in the method for manufacturing a CMOS semiconductor device according to claim 6, the intaglio includes a P-type semiconductor contained in the P-type semiconductor ink and the N-type in the configuration according to any one of claims 1 to 5. In accordance with the field effect mobility of the N-type semiconductor contained in the semiconductor ink, the first recess and the second recess so that at least one of the channel length and the channel width of the P channel region and the N channel region is different from each other. It is characterized by being formed.

  On the other hand, as means for solving the above-mentioned problem, the CMOS semiconductor device according to claim 7 comprises a P-channel field effect transistor by the method of manufacturing a CMOS semiconductor device according to any one of claims 1 to 6. And a CMOS circuit in which an N channel region constituting an N channel field effect transistor is formed.

Furthermore, a CMOS semiconductor device according to an eighth aspect is characterized in that, in addition to the configuration according to the seventh aspect, a NAND circuit including the CMOS circuit is provided.
According to a ninth aspect of the present invention, in the configuration of the seventh aspect, the NOR circuit including the CMOS circuit is provided.

  As described above, according to the present invention, by using a microcontact printing plate as an intaglio, a highly productive and high resolution circuit can be obtained.

1 is a cross-sectional view of a CMOS semiconductor device according to an embodiment. FIG. 2 is a plan view of the CMOS semiconductor device of FIG. 1 excluding a gate insulating film 401. It is a schematic diagram which shows an example of the manufacturing method of the COMS semiconductor device concerning embodiment. It is a figure which shows an example of the circuit structure of the CMOS semiconductor device concerning embodiment. 1 is a diagram illustrating an example of a circuit configuration of a NAND circuit according to an embodiment. FIG. It is a figure which shows an example of the circuit structure of the NOR circuit concerning embodiment. It is a top view of the CMOS semiconductor device concerning the modification of embodiment.

Embodiments of a CMOS semiconductor device manufacturing method and a CMOS semiconductor device according to the present invention will be described below with reference to the drawings. 1 to 7 are diagrams showing a CMOS semiconductor device manufacturing method and a CMOS semiconductor device according to an embodiment of the present invention.
(Constitution)
FIG. 1 is a cross-sectional view of a CMOS semiconductor device according to an embodiment of the present invention. FIG. 2 is a plan view of the CMOS semiconductor device of FIG. 1 excluding the gate insulating film 401.
As shown in FIG. 1, the CMOS semiconductor device 501 according to this embodiment includes a gate electrode 301, a gate insulating film 401, a first source electrode 201, a drain electrode 203, and a second source electrode 202 on a substrate 000. A P channel region 101 and an N channel region 102 are formed as channel portions. In FIG. 1, a substrate to be printed 001 is obtained by removing the channel portion from the CMOS semiconductor device 501.

Although a bottom gate / bottom contact type CMOS circuit is illustrated in FIG. 1, the CMOS semiconductor device (CMOS circuit) according to this embodiment may be a bottom gate or a top gate, and may be a bottom contact or a top contact.
In this embodiment, as shown in FIG. 2, the channel length Lp and the channel width Zp of the P channel region 101 and the channel length Ln and the channel width Zn of the N channel region 102 constituting the channel portion are “Lp”. = Ln "and" Zp = Zn ".

(Production method)
Next, a method for manufacturing the CMOS semiconductor device 501 having the above configuration will be described with reference to FIG. FIG. 3 is a schematic view showing an example of a method for manufacturing the CMOS semiconductor device 501.
Note that the manufacturing process of the substrate 001 to be printed is the same as a known manufacturing process, and thus description thereof is omitted. Hereinafter, the step of forming the channel portion on the substrate 001 to be printed by microcontact printing using the intaglio, which is a characteristic part of the present invention, will be specifically described.
First, as shown in (1) of FIG. 3, the P-type semiconductor ink jet head 701 supplies the P-type semiconductor ink 111 to the first recess 602, which is one of the groove structures formed on the intaglio 601. Further, the N-type semiconductor ink 112 is supplied to the second recess 603 which is one of the groove structures formed in the intaglio 601 by the N-type semiconductor inkjet head 702.

Note that at least the number of first recesses 602 and the second recesses 603 corresponding to the number of CMOS circuits formed on the substrate to be printed is formed on the intaglio 601.
Further, when ink is supplied, ink droplet diameter control or landing control, ink is easily repelled by the boundary edge between the groove structure portion and the flat portion 604, and ink is inked only at a predetermined position. .

In the present embodiment, the first recess 602 and the second recess 603 of the intaglio 601 are such that the channel length Lp and channel width Zp of the P channel region 101 and the channel length Ln and channel width Zn of the N channel region 102 are “ It is formed so as to have a relationship of “Lp = Ln” and “Zp = Zn”.
As shown in (2) in FIG. 3, after inking the semiconductor ink, the intaglio 601 is brought into contact with the device forming surface of the substrate 001 to be printed. After that, through heat treatment and the like, the ink is collectively transferred to the substrate to be printed 001 as indicated by (3) in FIG. Since the ink is attached only at a predetermined position, a desired pattern can be transferred to the substrate with high accuracy.

Here, the transfer of the ink may be direct transfer from the intaglio 601 illustrated in FIG. 3 to the substrate 001 to be printed, but is not limited thereto, and may be indirect transfer via a blanket, and is not particularly limited. The shape of the intaglio 601 may be a flat plate shape or a roll shape.
In this manner, by inking the P-type semiconductor ink 111 and the N-type semiconductor ink 112 into the intaglio 601 and transferring them collectively to the substrate 001 to be printed, it is possible to shorten the process and build a compact manufacturing line. Become. In addition, the problem of shrinkage and expansion of plastic film substrates due to fluctuations in temperature and humidity has been pointed out, but performing multiple colors at once can minimize dimensional fluctuations between colors, resulting in a large area. It is also possible to contribute to high-precision alignment. Furthermore, since each process is performed continuously, surface contamination and the like can be suppressed, and improvement in process stability, device performance and reliability can be expected.

  The P-type semiconductor ink 111 and the N-type semiconductor ink 112 are those having a viscosity of 1 [mPa · s] to 30 [mPa · s] at 23 [° C.]. In order to obtain a semiconductor layer thickness of approximately 20 [nm] or more, a viscosity of 1 [mPa · s] or more is required, and for stable coating during inking, 30 [mPa · s] or less. Is required. Further, by containing a chemical having a boiling point of 1 [atm] of 130 [° C.] or more, drying of the ink after inking on the intaglio 601 is moderately delayed, and a printing margin can be secured. When the drying of the ink is too slow, the ratio of the chemical solution having a boiling point of less than 130 [° C.] and a fast drying rate may be increased and adjusted.

  The chemicals used are aliphatic hydrocarbon solvents such as hexane, alicyclic hydrocarbon solvents such as cyclohexane, unsaturated hydrocarbon solvents such as pentene, aromatic hydrocarbon solvents such as xylene, and ketones such as acetone. A solvent, an ether solvent such as diethyl ether, an acetate solvent such as butyl acetate, an alcohol solvent such as isopropyl alcohol, a halogen solvent such as chloroform, an aqueous solvent, or a mixed solvent thereof can be used, but is not limited thereto. .

The P-type semiconductor ink 111 and the N-type semiconductor ink 112 include silicon nanoparticle ink, oxide semiconductor precursor ink, oxide semiconductor nanoparticle ink, organic semiconductor ink, fullerene, carbon nanotube, and carbon semiconductor ink made of graphene. Can be used. By doping the semiconductor, the P-type and N-type may be reversed.
As the material of the N-type semiconductor, Si nanoparticles, Si precursor, metal oxide, low molecular organic semiconductor, or high molecular organic semiconductor can be used.

  As an oxide semiconductor material containing a metal oxide as a main component, one or more of zinc (Zn), indium (In), tin (Sn), tungsten (W), magnesium (Mg), and gallium (Ga) are used. Zinc oxide (ZnO), indium oxide (InO), indium zinc oxide (In—Zn—O), tin oxide (SnO), tungsten oxide (WO), and zinc gallium indium oxide (including oxides) In-Ga-Zn-O) and the like can be given, but the present embodiment is not limited to these materials. The ink of these materials may be either a metal oxide nanoparticle dispersion or a metal oxide precursor.

  Organic semiconductor materials include oligomers and polymers having pyridine and derivatives thereof as skeletons, oligomers and polymers having quinoline and derivatives thereof as skeletons, ladder polymers based on benzophenanthrolines and derivatives thereof, and polymers such as cyano-polyphenylene vinylene. , Fluorinated metal-free phthalocyanine, fullerene derivatives, carbon nanotubes, graphene, fluorinated metal phthalocyanines and derivatives thereof, perylene and derivatives thereof (PTCDA, PTCDI, etc.), naphthalene derivatives (NTCDA, NTCDI, etc.), bathocuproin, fluorinated condensation poly Low molecular organic compounds such as ring aromatic hydrocarbons, TCNQ derivatives, and p-chloroanil can be used.

A metal oxide or an organic semiconductor can be used as the material of the P-type semiconductor.
Examples of oxide semiconductor materials mainly composed of metal oxides include Cu ₂ O, NiO, CuAlO ₂ , CuGaO ₂ , ZnRh ₂ O ₄ , SnO, and LaCuOSe, and inks of these materials are metal oxides. Any of a nanoparticle dispersion of a product and a metal oxide precursor may be used.
Organic semiconductor materials include oligomers and polymers with thiophene and its derivatives in the skeleton, oligomers and polymers with phenylene-vinylene and its derivatives as the skeleton, oligomers and polymers with fluorene and its derivatives as the skeleton, benzofuran and its derivatives as the skeleton Oligomers and polymers with skeletons, oligomers and polymers with thienylene-vinylene and its derivatives as skeletons, oligomers and polymers with aromatic tertiary amines and their derivatives as triphenylamine and their derivatives, carbazole and their derivatives Oligomers and polymers having oligomers and polymers, vinylcarbazole and derivatives thereof in the backbone, oligomers and polymers having backbones of pyrrole and derivatives, oligomers and polymers having backbones of acetylene and derivatives thereof, Oligomers and polymers having sotianaphene and its derivatives in the backbone, polymers such as oligomers and polymers having the backbone in heptadiene and its derivatives, metal-free phthalocyanines, metal phthalocyanines and their derivatives, diamines, phenyldiamines and their derivatives Acenes such as rubrene and pentacene and their derivatives, porphyrin, tetramethylporphyrin, tetraphenylporphyrin, tetrabenzporphyrin, monoazotetrabenzporphyrin, diazotetrabenzporphine, triazotetrabenzporphyrin, octaethylporphyrin, octaalkylthioporphyrazine Metal-free porphyrins such as octaalkylaminoporphyrazine, hemiporphyrazine, and chlorophyll, metalloporphyrins, and the like Derivatives can be used. As the central metal of metal phthalocyanine and metal porphyrin, magnesium, zinc, copper, silver, aluminum, silicon, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, tin, platinum, lead and other metals, metal oxides, Metal halides can be used.

  In addition, the intaglio 601 of the present embodiment can use a silicone resin or a fluororesin mainly composed of PDMS as a material constituting the plate. These are materials characterized by low surface energy, and liquids such as ink are difficult to spread. The surface of the plate may be surface-modified with UV, ozone, ashing or the like with an appropriate strength. However, if the surface is excessively modified, the transferability deteriorates. The plate may be composed of a plurality of layers, but the outermost layer needs to be a silicone resin or a fluororesin for good ink transferability. KE-106 / CAT-RG (manufactured by Shin-Etsu Chemical) can be used for the silicone resin, SIFEL (manufactured by Shin-Etsu Chemical) can be used for the fluororesin, and the Shore A hardness needs to be 40-80. If the hardness is too high, contact failure and transfer failure occur frequently during printing, and if the hardness is too low, the intaglio formability and printing durability are significantly deteriorated.

  The groove structure portion of the intaglio 601 (including the first recess portion 602 and the second recess portion 603) and the flat portion 604 which is a flat surface other than the groove structure portion are molding methods used as a known technique in microcontact printing. Formed by. Specifically, it can be formed from a mold made of quartz glass, a photoresist pattern, electroforming, or the like, but is not limited to these methods.

  In the present embodiment, the substrate 000 is glass or plastic film such as soda glass or quartz glass. Examples of plastic film resin materials include polyethylene terephthalate, polyethylene naphthalate, polyethersulfone, polyetherimide, polyetheretherketone, polyetherketone, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, cycloolefin polymer, polyolefin , Polyvinyl chloride, liquid crystal polymer, epoxy resin, phenol resin, urea resin, melamine resin, silicone resin, and other materials can be used. Polymer alloys combining these resins and one or more of the above resins can be used. It can also be constituted as a plastic film having a multilayer structure in which materials are laminated.

After the channel portion is formed by microcontact printing using the intaglio 601, the CMOS semiconductor device 501 having the circuit configuration shown in FIG.
FIG. 4 is a diagram showing an example of a circuit configuration of the CMOS semiconductor device 501 according to the present embodiment.

As shown in FIG. 4, the CMOS semiconductor device 501 includes a first power supply line 231, a second power supply line 232, a P-channel field effect transistor 511, an N-channel field effect transistor 512, and an input terminal IN. And an output terminal OUT.
A P-channel field effect transistor 511 and an N-channel field effect transistor 512 are provided between the first power supply line 231 and the second power supply line 232. The first source electrode 201 of the P-channel field effect transistor 511 is connected to the first power supply line 231. The second source electrode 202 of the N-channel field effect transistor 512 is connected to the second power supply line 232. The P-channel field effect transistor 511 and the N-channel field effect transistor 512 have a common drain electrode 203, and the common drain electrode 203 is connected to the output terminal OUT. The P-channel field effect transistor 511 and the N-channel field effect transistor 512 have a common gate electrode 301, and the common gate electrode 301 is connected to the input terminal IN. With such a configuration, the signal input from the input terminal IN is inverted and output from the output terminal OUT.

  Here, the electrodes and wirings can be formed by a known method such as photolithography after forming a metal such as Al, Cr, Mo, Cu, Au, Pt, Pd, Fe, Mn, and Ag by PVD or CVD. Further, a metal paste, a metal nanoparticle dispersion, a conductive polymer solution, or the like can be formed by a printing method. The printing method used can be a pattern printing method such as letterpress printing, intaglio printing, planographic printing, reverse offset printing, screen printing method, microcontact printing, ink jet, thermal transfer printing, dispenser, etc. Other printing methods may be used for the components.

  Moreover, when forming an electrode and wiring by a printing method, a metal nanoparticle can be used for a conductive ink. Metal nanoparticles are nanoparticles made of gold, silver, copper, platinum, palladium, nickel, cobalt, iron, aluminum, manganese metals, or gold, silver, copper, platinum, palladium, nickel, cobalt, iron, aluminum Further, nanoparticles of an alloy composed of two or more kinds of metals selected from metals of manganese and molybdenum, metal oxides such as silver oxide, and organometallic compounds such as organic silver can also be used. The average particle size of the metal used is preferably an average particle size of 50 nm or less from the viewpoint of dispersibility in ink, and an average particle size of 10 to 30 [nm] is preferable from the viewpoint of stable production of particles, but is not limited thereto. .

  The gate insulating film and the interlayer insulating film can be formed by a known method such as photolithography after forming an oxide film or nitride film of a metal such as Al, Si, Zr, Y, Hf, and La by PVD or CVD. Insulating ink and insulating paste, bar coating, spray coating, die coating, cap coating, roll coating, gravure coating, knife coating, lip coating, etc., letterpress printing, intaglio printing, planographic printing, reverse offset printing, screen It can also be formed by a printing method such as a printing method, microcontact printing, ink jet, thermal transfer printing, or dispenser.

  Insulating ink is polyimide, polyamide, polyester, polyvinylphenol, polyvinyl alcohol, polyvinyl acetate, polyurethane, polysulfone, polyvinylidene fluoride, cyanoethyl pullulan, epoxy resin, phenol resin, benzocyclobutene resin, acrylic resin, polystyrene, polycarbonate, cyclic Polyolefin, fluororesin, silicone resin, and polymer alloys and copolymers of these resins can be used. The gate insulating film and the interlayer insulating film may be made of a composite material including an organic / inorganic feeler.

(Other circuit configuration examples)
A CMOS semiconductor device having the following circuit configuration can be manufactured using the semiconductor device 501 (CMOS circuit shown in FIG. 4) manufactured using the method for forming a channel portion by microcontact printing using the intaglio 601. Is possible.
FIG. 5 is a diagram illustrating an example of a circuit configuration of the NAND circuit according to the present embodiment. FIG. 6 is a diagram illustrating an example of a circuit configuration of the NOR circuit according to the present embodiment.
5 includes a first P-channel field effect transistor 511, a first N-channel field effect transistor 512, a second P-channel field effect transistor 521, and a second N-channel type. And a field effect transistor 522.

A CMOS circuit is formed by combining the first P-channel field effect transistor 511 and the first N-channel field effect transistor 512. This CMOS circuit is manufactured by using the channel portion forming method.
The NAND circuit further includes a first power supply line 231, an input terminal IN1, an input terminal IN2, and an output terminal OUT.

The source electrode 211 of the second P-channel field effect transistor 521 is connected to the first power supply line 231, and the drain electrode 212 of the second P-channel field effect transistor 521 is connected to the common drain electrode 203 of the CMOS circuit. And connected to the output terminal OUT of the NAND circuit.
Further, the gate electrode 303 of the second P-channel field effect transistor 521 is connected to the gate electrode 302 of the second N-channel field effect transistor 522 and also to the input terminal IN2 of the NAND circuit. Further, the common gate electrode 301 of the CMOS circuit is connected to the input terminal IN1 of the NAND circuit.

On the other hand, the NOR circuit shown in FIG. 6 includes a first P-channel field effect transistor 511, a first N-channel field effect transistor 512, a second P-channel field effect transistor 521, and a second N-channel field effect transistor 521. A channel field-effect transistor 522.
A CMOS circuit is formed by combining the first P-channel field effect transistor 511 and the first N-channel field effect transistor 512. This CMOS circuit is manufactured by using the channel portion forming method.

Further, the source electrode 221 of the second P-channel field effect transistor 521 is connected to the first power supply line 231, and the drain electrode 222 of the second P-channel field effect transistor 521 is the first source electrode of the CMOS circuit. 201 is connected.
Further, the source electrode 211 of the second N-channel field effect transistor 522 is connected to the second power supply line 232, and the drain electrode 212 of the second N-channel field effect transistor 522 is connected to the drain electrode 203 of the CMOS circuit. And connected to the output terminal OUT of the NOR circuit.

  Further, the gate electrode 304 of the second P-channel field effect transistor 521 is connected to the gate electrode 305 of the second N-channel field effect transistor 522 and also to the input terminal IN1 of the NOR circuit. Further, the common gate electrode 301 of the CMOS circuit is connected to the input terminal IN2 of the NOR circuit.

(Modification)
Next, a method for manufacturing the CMOS semiconductor device according to the above embodiment and a modification of the CMOS semiconductor device will be described with reference to FIG.
FIG. 7 is a plan view showing an example of a CMOS semiconductor device 501 according to this modification.
In this modification, the first recess 602 and the second recess 603 of the intaglio 601 are such that the channel length Lp of the P channel region 101 is narrower than the channel length Ln of the N channel region 102 and the P channel region 101 The length and width are formed such that the channel width Zp is wider than the channel width Zn of the N channel region 102. Except for this, the CMOS semiconductor device 501 is manufactured in the same manner as in the above embodiment.

In this modification, the channel lengths Lp and Ln and the channel widths Zp and Zn are determined according to the difference in field effect mobility between the P-type semiconductor and the N-type semiconductor forming the channel portion. Yes. Here, the current value of the field effect transistor is inversely proportional to the channel length and proportional to the channel width.
Thus, by adjusting the channel lengths Lp and Ln and the channel widths Zp and Zn of the P-channel field effect transistor and the N-channel field effect transistor, the field-effect mobility of the P-type semiconductor and the N-type semiconductor can be increased. Even in different cases, the magnitude of the current value of the transistor can be made similar.

The above embodiments are preferable specific examples of the present invention, and various technically preferable limitations are given. However, the scope of the present invention is particularly limited in the above description. As long as there is no description, it is not restricted to these forms. In the drawings used in the above description, for convenience of illustration, the vertical and horizontal scales of members or parts are schematic views different from actual ones.
Further, the present invention is not limited to the above-described embodiment, and modifications, improvements, and the like within a scope that can achieve the object of the present invention are included in the present invention.

Next, examples using the manufacturing method of the CMOS semiconductor device of the above embodiment will be described.
As a printing pattern, a 4-inch CMOS array having an alignment mark arranged around each layer was used. In this embodiment, a gate layer composed of a gate electrode, a capacitor, and a bus line is formed on a substrate, an insulating film is formed on the gate layer, and a source / drain electrode is formed on the insulating film. A semiconductor layer composed of a P-type semiconductor and an N-type semiconductor is patterned.

  As the ink, a poly-3-hexylthiophene solution was used as a P-type semiconductor ink, and fullerene was used as an N-type semiconductor ink. As the intaglio plate, about 120 [• Jiang Atsushi PET substrate was laminated with 200 [• Ko Atsushi silicone resin. The intaglio is formed by molding from a resist pattern, and has a shape in which a plate depth of 8 [• river, a minimum width of groove structure 30 [• river, a 5-inch substrate, and a CMOS array pattern are arranged. As the ink, a silver nanoparticle dispersion was used. Furthermore, a film thickness of 120 [• Jiang PEN substrate was used as the substrate to be printed. A printed pattern was formed on the substrate to be printed according to the following procedure using the substrate.

1) On the intaglio, ink was applied with a coating length of 120 [mm] by an ink jet apparatus using a head having a width of 120 [mm]. An ink jet head for P-type semiconductor ink and an ink-jet head for N-type semiconductor ink were arranged, and each ink was supplied to a predetermined position on the intaglio.
2) The ink coating film was dried to obtain P-type semiconductor and N-type semiconductor ink patterns on the intaglio.

3) Printing was completed by transferring the ink patterns of the P-type semiconductor and N-type semiconductor on the intaglio to the substrate to be printed at once.
The substrate to be printed on which the printing pattern was formed was annealed with a heating device, and a P-type semiconductor layer (P channel region) and an N type semiconductor layer (N channel region) of the CMOS array were formed. By using the printing method of the present invention, a high-definition TFT array was efficiently obtained.

  The circuit of the present invention provides a highly productive electric circuit because a CMOS semiconductor device is formed by a printing method. Furthermore, since the P-type semiconductor layer and the N-type semiconductor layer can be formed in a lump, it is effective in achieving simplification of the process, improvement in process stability, and improvement in device reliability.

000 Substrate 001 Printed substrate 101 P-type semiconductor 102 N-type semiconductor 111 P-type semiconductor ink 112 N-type semiconductor ink 201 First source electrode 202 Second source electrode 203 Drain electrode 211, 221 Source electrode 212, 222 Drain electrode 231 First power line 232 Second power line 301, 302, 303, 304, 305 Gate electrode 401 Gate insulating film 501 CMOS semiconductor device 511 First P-channel field effect transistor 512 First N-channel field effect transistor 521 Second P-channel field effect transistor 522 Second N-channel field effect transistor 601 Intaglio 602 First recess 603 Second recess 604 Flat portion 701 P-type semiconductor inkjet head 702 N-type semiconductor inkjet head

Claims (9)

A method of manufacturing a CMOS semiconductor device including a CMOS circuit configured by combining a P-channel field effect transistor and an N-channel field effect transistor,
Forming a P-channel region constituting the P-channel field effect transistor and an N-channel region constituting the N-channel field effect transistor by a printing method using an intaglio;
The intaglio includes a first recess for forming the P channel region and a second recess for forming the N channel region,
The printing method using the intaglio is
Supplying a P-type semiconductor ink to the first recess by a non-contact inking method and supplying an N-type semiconductor ink to the second recess;
After supplying the P-type semiconductor ink and the N-type semiconductor ink, the intaglio is pressed against the substrate to be printed, and the P-type semiconductor ink supplied to the first recess and the N-type semiconductor ink supplied to the second recess are collectively And transferring to the substrate to be printed. A method for manufacturing a CMOS semiconductor device, comprising:   2. The method of manufacturing a CMOS semiconductor device according to claim 1, wherein the non-contact inking method is one of a dispenser method and an ink jet method.   The P-type semiconductor ink for forming the P-channel region and the N-type semiconductor ink for forming the N-channel region have a viscosity of 1 [mPa · s] to 30 [mPa · s]. The method for manufacturing a CMOS semiconductor device according to claim 1, wherein the method is a semiconductor device.   The said P-type semiconductor ink and the said N-type semiconductor ink contain the chemical | medical solution whose boiling point in 1 [atm] is 130 [degreeC] or more, The any one of Claim 1 thru | or 3 characterized by the above-mentioned. Of manufacturing a CMOS semiconductor device. The intaglio is formed by a molding method on a surface made of silicone resin or fluororesin, and planarizes a groove structure portion as a recess including the first recess and the second recess and portions other than the groove structure. With a flat portion
The width of the groove structure part is 1 [· more than 50 [· e,
5. The method of manufacturing a CMOS semiconductor device according to claim 1, wherein a Shore A hardness of a surface made of the silicone resin or the fluororesin is 30 or more and 80 or less.   The intaglio is formed in accordance with a difference in field effect mobility between a P-type semiconductor contained in the P-type semiconductor ink and an N-type semiconductor contained in the N-type semiconductor ink. 6. The CMOS semiconductor device according to claim 1, wherein the first recess and the second recess are formed so that at least one of a length and a channel width is different from each other. Method.   7. A method of manufacturing a CMOS semiconductor device according to claim 1, wherein a P channel region constituting a P channel field effect transistor and an N channel region constituting an N channel field effect transistor are formed. A CMOS semiconductor device comprising the formed CMOS circuit.   The CMOS semiconductor device according to claim 7, further comprising a NAND circuit including the CMOS circuit.   The CMOS semiconductor device according to claim 7, further comprising a NOR circuit including the CMOS circuit.

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