JP2013066074A - Image processing device, and image-data transmission and reception method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To properly assign signals.SOLUTION: A transmission section assigns image data and a synchronous signal to each bit of first parallel data. A first conversion section converts the first parallel data into serial data and transmits the serial data. A second conversion section converts the serial data into second parallel data and transmits the second parallel data. A receiving section reads out the synchronous signal from the bit to which the synchronous signal is assigned for the second parallel data received in a first period, and reads out the image data from the bits to which the image data is assigned for the second parallel data received in a second period. Moreover, the transmission section assigns the synchronous signal to the bit for assigning the synchronous signal among bits of the first parallel data and assigns the synchronous signal to the bits for assigning the image data to assign two or more bits of the synchronous signal to the parallel data in the first period.

Description

  The present invention relates to an image processing apparatus and an image data transmission / reception method.

  Conventionally, in an image processing apparatus such as a multifunction machine, for example, in transmission / reception of image data from an image reading unit to an image processing unit in the image processing apparatus, the transmission side converts parallel data into serial data, and transmits it. Many receivers receive serial data converted into parallel data. In this transmission / reception, a synchronization signal for synchronizing the transmission side and the reception side is also transmitted / received. That is, the transmission side converts image data into serial data together with a synchronization signal and transmits the data, and the reception side converts received serial data into parallel data, and receives the image data as parallel data together with the synchronization signal.

  Here, in order to transmit and receive image data normally and prevent malfunction, it is important to accurately reproduce the synchronization signal on the receiving side. For example, when a signal of 1 bit is not transmitted / received normally, if the signal is image data, an image becomes a partial abnormality, but the signal is a synchronization signal and can be synchronized. If not, a synchronization error or the like occurs, resulting in a serious image abnormality. Therefore, the synchronization signal is extremely important in transmission / reception of image data. For this reason, for example, there is a technique in which the transmission side continuously allocates and transmits a plurality of synchronization signals in serial data, and the reception side receives a central signal among the plurality of synchronization signals as a synchronization signal. .

  However, in the above-described method of allocating a plurality of synchronization signals in serial data, for example, when there is no vacant serial data allocation, the number of serial data transmission / reception channels must be increased. For example, when the image processing apparatus transmits and receives image data of 8 bits for each of RGB (24 bits in total), if 7 bits per channel, 4 channels are sufficient even if 4 bits are allocated to the synchronization signal. However, in addition to the synchronization signal, when transmitting an image processing signal used for image processing such as a photo sensor signal or an image effective period signal in the sub-scanning direction, the number of channels must be increased. For example, when the image processing apparatus transmits / receives 9-bit RGB data (27 bits in total), it is necessary to increase the number of channels in order to allocate a plurality of synchronization signals.

  The present invention has been made in view of the above, and an object thereof is to provide an image processing apparatus and an image data transmission / reception method capable of appropriately performing signal allocation.

  In order to solve the above-described problems and achieve the object, the present invention is an image processing apparatus, which includes a transmission unit, a first conversion unit, a second conversion unit, and a reception unit. The transmission unit allocates image data and a synchronization signal of the image data to each bit of the first parallel data, and transmits the first parallel data. The first conversion unit converts the first parallel data into serial data and transmits the serial data. The second conversion unit converts the serial data into second parallel data, and transmits the second parallel data. For the second parallel data received in the first period included in the period in which the image data is transmitted, the receiving unit performs the synchronization from the bit to which the synchronization signal is allocated among the bits of the second parallel data. For the second parallel data received in the second period included in the period in which the signal is read and the image data is transmitted, the image data from the bit to which the image data is allocated among the bits of the second parallel data. Is read. In addition, the transmission unit allocates a synchronization signal to a bit to which a synchronization signal is allocated among bits of the first parallel data, and allocates a synchronization signal to a bit to which image data is allocated, whereby the first parallel data in the first period is allocated. Is assigned a synchronization signal of 2 bits or more.

  The present invention is an image processing apparatus, which includes a transmission unit, a first conversion unit, a second conversion unit, and a reception unit. The transmission unit allocates image data and an image processing signal used for image processing of the image data to each bit of the first parallel data, and transmits the first parallel data. The first conversion unit converts the first parallel data into serial data and transmits the serial data. The second conversion unit converts the serial data into second parallel data, and transmits the second parallel data. For the second parallel data received in the first period included in the period in which the image data is transmitted, the receiving unit starts from the bit to which the image processing signal is allocated among the bits of the second parallel data. With respect to the second parallel data received in the second period included in the period in which the image processing signal is read and the image data is transmitted, the bit from the bit to which the image data is allocated among the bits of the second parallel data. Read image data. The transmission unit allocates an image processing signal to the first parallel data in the first period by allocating an image processing signal to a bit for allocating image data among the bits of the first parallel data.

  In addition, the present invention is an image data transmission / reception method executed by an image processing apparatus, and includes a transmission step, a first conversion step, a second conversion step, and a reception step. In the transmission step, image data and a synchronization signal of the image data are allocated to each bit of the first parallel data, and the first parallel data is transmitted. The first conversion step converts the first parallel data into serial data and transmits the serial data. The second conversion step converts the serial data into second parallel data and transmits the second parallel data. In the reception step, for the second parallel data received in the first period included in the period in which the image data is transmitted, the synchronization is started from the bit to which the synchronization signal is allocated among the bits of the second parallel data. For the second parallel data received in the second period included in the period in which the signal is read and the image data is transmitted, the image data from the bit to which the image data is allocated among the bits of the second parallel data. Is read. In the transmission step, the first parallel data of the first period is assigned by allocating a synchronization signal to a bit to which a synchronization signal is allocated and assigning a synchronization signal to a bit to which image data is allocated. Is assigned a synchronization signal of 2 bits or more.

  According to the present invention, it is possible to appropriately perform signal allocation.

FIG. 1 is a block diagram illustrating a configuration example of an image processing apparatus according to the first embodiment. FIG. 2 is a diagram for explaining the digital image signal and the synchronization signal in the first embodiment. FIG. 3 is a diagram for explaining parallel / serial conversion and serial / parallel conversion in the first embodiment. FIG. 4 is a diagram for explaining the digital image signal and the synchronization signal in the first embodiment. FIG. 5 is a diagram for explaining a synchronization signal in the first embodiment. FIG. 6 is a diagram for explaining allocation of photosensor signals and the like in the second embodiment.

  Embodiments of an image processing apparatus and an image data transmission / reception method will be described below in detail with reference to the accompanying drawings.

(First embodiment)
As will be described below, the image processing apparatus 10 according to the first embodiment increases the number of channels by allocating a synchronization signal to bits that originally allocate image data during a period when the image data is not received on the receiving side. Realizes the allocation of multiple synchronization signals. That is, as will be described later, for the parallel data received during the “invalid period”, the receiving side reads out the synchronization signal from the bit to which the synchronization signal is assigned, and receives it during the “valid period”. For the parallel data, the image data is read from the bit to which the image data is allocated among the bits of the parallel data. For this reason, the image processing apparatus 10 according to the first embodiment uses one bit separately for the image data and the synchronization signal depending on whether it is the “valid period” or the “invalid period”. Make efficient use of bits.

  FIG. 1 is a block diagram illustrating a configuration example of an image processing apparatus 10 according to the first embodiment. As shown in FIG. 1, the image processing apparatus 10 includes an image reading unit 4, a timing signal generation unit 5, a transmission data creation unit 6, an LVDS (Low Voltage Differential Signaling) transmitter 7, an LVDS receiver 8, and a reception. And a data creation unit 9. FIG. 1 shows a configuration example of a part of the image processing apparatus 10 for convenience of explanation, and the image processing apparatus 10 may include other units not shown in FIG.

  The image reading unit 4 includes an image reading sensor 1 (hereinafter referred to as “CCD 1”) such as a CCD (Charge Coupled Device), an analog processing unit 2, and an ADC (Analog Digital Converter) 3. The CCD 1 outputs RGB read signals (red, green, blue) to the analog processing unit 2. The analog processing unit 2 performs processing such as amplification on the read signal input from the CCD 1, and outputs the processed read signals (ad_r, ad_g, ad_b) to the ADC 3. The ADC 3 converts the read signal input from the analog processing unit 2 into a digital image signal of 9 bits for each of RGB, and transmits the converted digital image signals (td_r8 to 0, td_g8 to 0, td_b8 to 0) as a transmission data creation unit 6 is output. In FIG. 1, the numeral “9” under “/” indicates that each digital image signal is 9 bits.

  The timing signal generation unit 5 supplies various timing signals to the image reading unit 4 under the control of a control unit (CPU (Central Processing Unit), etc.) not shown in FIG. A clock signal (clkin) and a synchronization signal (lsync_tx) are supplied. In the first embodiment, the synchronization signal is a synchronization signal for one line of image data.

  The transmission data creation unit 6 creates transmission data by allocating various signals input from the image reading unit 4 and the timing signal generation unit 5 to each bit of parallel data, and outputs the created transmission data to the LVDS transmitter 7. When transmitting a photosensor signal or the like, as shown in FIG. 1, since the photosensor signal or the like is also input to the transmission data creation unit 6, the transmission data creation unit 6 sends various signals including the photosensor signal and the like. Assign to each bit of parallel data.

  In the first embodiment, the transmission data creation unit 6 allocates various signals to parallel data of 4 channels (txd6 to 0, txd13 to 7, txd20 to 14, txd27 to 21) with 7 bits per channel. In FIG. 1, the numeral “7” under “/” indicates that each channel has 7 bits.

  The LVDS transmitter 7 (parallel / serial converter) converts the parallel data input from the transmission data creation unit 6 into serial data, and transmits the serial data using LVDS signals (lvds_ch1 to lvds_ch4 and lvds_clk). The LVDS transmitter 7 is a transmission technology called LVDS realized by a general-purpose IC (Integrated Circuit) or ASIC (Application Specific Integrated Circuit). In the first embodiment, since the serial data is a differential signal, it is resistant to noise. For this reason, the image processing apparatus 10 can stably transmit and receive even when the distance from the transmission side to the reception side is long.

  The LVDS receiver 8 (serial / parallel converter) converts the LVDS signal input from the LVDS transmitter 7 from serial data to parallel data, and has four channels (rxd6-0, rxd13-7, rxd20-14, rxd27-21). Return to parallel data. In FIG. 1, the numeral “7” under “/” indicates that each channel has 7 bits. The LVDS receiver 8 is a transmission technology called LVDS realized by a general-purpose IC or ASIC. In the first embodiment, transmission / reception by LVDS is assumed, but the embodiment is not limited to this, and transmission / reception may be performed by other transmission technologies.

  The reception data creation unit 9 receives, from the parallel data input from the LVDS receiver 8, a digital image signal of 9 bits for each RGB (rd_r8-0, rd_g8-0, rd_b8-0) and a synchronization signal (lsync_rx). Data is created, and the created received data is output to a subsequent processing unit (not shown in FIG. 1). Note that the reception data creation unit 9 creates reception data further including a photosensor signal or the like when a photosensor signal or the like is also received.

  Next, FIG. 2 is a diagram for explaining the digital image signal and the synchronization signal in the first embodiment. 2 shows a synchronization signal (lsync_tx) input from the timing signal generator 5 to the transmission data generator 6 and digital image signals (td_r8-0, td_g8-0, td_b8-0) input from the image reader 4. It shows.

  Here, in transmission / reception of image data, there are an “effective period” in which the received signal is processed as valid image data and an “invalid period” in which the received signal is not processed as valid image data. As shown in FIG. 2, the “valid period” is a period starting after “predetermined number of pixels” from the synchronization signal (lsync_tx) and ending after, for example, “image data for one line” from the start. . On the other hand, the “invalid period” is a period between the “valid period” and the “valid period”.

  Next, FIG. 3 is a diagram for explaining parallel / serial conversion and serial / parallel conversion in the first embodiment. As shown in FIG. 3, for example, parallel data (txd6 to 0) input from the transmission data creation unit 6 to the LVDS transmitter 7 is converted into serial data “D6” to “D0” in the LVDS transmitter 7 and converted to LVDS. Sent by signal. Further, the LVDS receiver 8 that has received the LVDS signal returns the serial data at the positions “D6” to “D0” to parallel data (rxd6 to 0) according to the phase with lvds_clk.

  Now, the outline of the image processing apparatus 10 according to the first embodiment has been described so far. Hereinafter, processing by the transmission data creation unit 6 and processing by the reception data creation unit 9 will be described in detail.

(Processing by transmission data creation unit 6)
The transmission data creation unit 6 uses one bit separately for the image data and the synchronization signal depending on whether it is the “valid period” or the “invalid period”. Specifically, the transmission data creation unit 6 assigns the synchronization signal to the bits to which the synchronization signal is assigned and also assigns the image data when creating the “invalid period” parallel data among the bits of the parallel data. By assigning a synchronization signal to a bit, a synchronization signal of 2 bits or more is assigned to parallel data of “invalid period”.

  For example, the transmission data creation unit 6 converts various signals input from the image reading unit 4 and the timing signal generation unit 5 into four channels (txd6 to 0, txd13 to 7, txd20 to 14, txd27 to Assign to the parallel data of 21).

  That is, the transmission data creation unit 6 outputs “td_r6 to 0”, which is 7 bits, of the digital image signals (td_r8 to 0, td_g8 to 0, td_b8 to 0) input from the image reading unit 4 for one channel. Assigned to parallel data (txd27 to 21). The parallel data (txd27 to 21) is converted into serial data by the LVDS transmitter 7 and transmitted by the LVDS signal (lvds_ch4). Similarly, the transmission data creation unit 6 assigns “td_g6 to 0”, which is 7 bits, to 1-channel parallel data (txd20 to 14). The parallel data (txd20 to 14) is converted into serial data by the LVDS transmitter 7 and transmitted by the LVDS signal (lvds_ch3). Further, the transmission data creation unit 6 assigns “td_b6 to 0”, which is 7 bits, to 1-channel parallel data (txd13 to 7). The parallel data (txd13 to 7) is converted into serial data by the LVDS transmitter 7 and transmitted by the LVDS signal (lvds_ch2).

  Further, the transmission data creation unit 6 converts the digital image signals (td_r8 to 7, td_g8 to 7, td_b8 to 7) and the synchronization signal (lsync_tx) input from the timing signal generation unit 5 into 1-channel parallel data ( Assign to txd6 ~ 0). The parallel data (txd6 to 0) is converted into serial data by the LVDS transmitter 7 and transmitted by the LVDS signal (lvds_ch1).

  Here, as shown in FIG. 3, the data (txd6 to 0) transmitted by the LVDS signal (lvds_ch1) is “txd6”, “txd5”, “txd4”, “txd3”, “txd2” on the LVDS signal. ”,“ Txd1 ”,“ txd0 ”. Therefore, the transmission data creation unit 6 assigns the image data to the bits adjacent to the bits to which the synchronization signal is assigned and corresponding to the bits before and after the bits to which the synchronization signal is assigned in the order of the serial data (on the LVDS signal). . For example, as shown in Table 2 below, the transmission data creation unit 6 performs allocation so that image data is before and after the synchronization signal. That is, the transmission data creation unit 6 assigns the image data (td_g8, td_g7) to “txd4” and “txd2” before and after “txd3” to which the synchronization signal (lsync_tx) is assigned.

  Also, “txd4” and “txd2” that are before and after “txd3” to which the synchronization signal (lsync_tx) is assigned, but as shown in FIG. There is an “invalid period”, and the synchronization signal is asserted during the “invalid period”. Therefore, the transmission data creation unit 6 assigns image data (td_g8, td_g7) to “txd4” and “txd2” during the “valid period” and a synchronization signal (lsync_tx) during the “invalid period”.

  By allocating in this way, during the “invalid period”, “D4”, “D3”, and “D2” among the LVDS signals shown in FIG. Then, even if “D4” or “D2” other than “D3” is sampled as a synchronization signal due to occurrence of clock skew or the like on the reception side, the reception side receives a correct synchronization signal. be able to. Note that the clock skew means that clock signals transmitted from the clock circuit arrive at different timings in a clock synchronous circuit.

  FIG. 4 is a diagram for explaining the digital image signal and the synchronization signal in the first embodiment. As shown in FIG. 4, for example, the reception data creation unit 9 masks the input of the synchronization signal to prevent noise from the reception of the synchronization signal until the end of the effective period (“synchronization signal mask period” in FIG. 4). . In this regard, the transmission data creation unit 6 can obtain a necessary effect of appropriately transmitting and receiving the synchronization signal by assigning a plurality of synchronization signals (lsync_tx) during the “invalid period”.

  In the above description, an example has been described in which allocation is performed so that one bit before and after the synchronization signal becomes image data, but the embodiment is not limited to this. In general, the greater the number of bits to which the synchronization signal is allocated, such as 2 bits or 3 bits before and after the synchronization signal, the greater the tolerance to clock skew. Also, the number of bits before and after may not be the same.

(Processing by the reception data creation unit 9)
Subsequently, the reception data creation unit 9 reads a plurality of synchronization signals assigned to a plurality of bits for the parallel data received during the “invalid period”, and based on the comparison result between the plurality of read synchronization signals, A synchronization signal used for data synchronization is selected.

  FIG. 5 is a diagram for explaining a synchronization signal in the first embodiment. In addition to masking the synchronization signal, the reception data creation unit 9 removes short pulse noise that is detected as an assert / negate when the assert / negate polarity continues for a predetermined number of pixels. However, as shown in FIG. 5, when noise is applied to the edge portion of the synchronization signal, the reception data creation unit 9 cannot detect this as noise, and as a result, detects an incorrect synchronization signal position. For example, the main scanning position of the image is shifted. For example, when the (correct) sync signal (lsync) and the (wrong) sync signal (lsync) in FIG. 5 are compared, the edge portion is shifted by one clock. There is a possibility that an erroneous synchronization signal may be received as a synchronization signal because it cannot be detected as noise.

  In this regard, in the first embodiment, since the transmission data creation unit 6 allocates and transmits a plurality of synchronization signals during the “invalid period”, for example, as shown in FIG. The synchronizing signal is also transmitted during the “invalid period” for the bits (“image data bit” in FIG. 5).

  Accordingly, the reception data creation unit 9 according to the first embodiment reads a plurality of synchronization signals assigned to a plurality of bits for the parallel data received during the “invalid period”. Then, the reception data creation unit 9 detects whether or not the synchronization signal detected in the synchronization signal line to which the synchronization signal is allocated is different from the synchronization signal detected in the image data line to which the image data is allocated. . If they are different, the reception data creation unit 9 selects a synchronization signal used for synchronization of image data using a predetermined determination condition. Here, the determination condition is, for example, whether the sync signal detected on the sync signal line is different from all sync signals detected on the image data line side (all sync signals detected on the image data line side are Or the synchronization signal detected on the synchronization signal line is different from a predetermined number or more of the synchronization signals detected on the image data line side. When the determination condition is met, the reception data creation unit 9 determines that the synchronization signal detected on the image data line side is a correct synchronization signal based on a policy that emphasizes a large number of results, for example, in the synchronization signal line. Correct the detected sync signal. As a result, even when noise is applied to the edge portion of the synchronization signal, the reception data creation unit 9 can detect it as noise and can receive the correct synchronization signal.

(Effects of the first embodiment)
As described above, according to the first embodiment, it is possible to appropriately assign signals. That is, according to the first embodiment, one bit is properly used for the image data and the synchronization signal according to the “valid period” or “invalid period”, so that the number of channels is not increased. Even when a plurality of synchronization signals are allocated and a clock skew or the like occurs, the receiving side can receive a correct synchronization signal.

  Further, according to the first embodiment, the receiving side reads a plurality of synchronization signals from the parallel data received during the “invalid period”, and synchronizes image data based on the comparison result between the plurality of synchronization signals. Since the synchronization signal to be used is selected, it is possible to detect even when noise is applied to the edge portion of the synchronization signal and select the correct synchronization signal.

(Second Embodiment)
Next, the image processing apparatus 10 according to the second embodiment will be described. In the second embodiment, the transmission data creation unit 6 assigns an image processing signal used for image processing of image data to a bit to which image data is assigned among each bit of parallel data. Assign image processing signals to parallel data. On the other hand, for the parallel data received during the “invalid period”, the reception data creation unit 9 reads the image processing signal from the bit to which the image processing signal is assigned among the bits of the parallel data, and the synchronization signal is assigned. Read the sync signal from the bit. In addition, for the parallel data received during the “valid period”, the reception data creation unit 9 reads the image data from the bits to which the image data is allocated among the bits of the parallel data.

  That is, in the second embodiment, the transmission data creation unit 6 allocates an image processing signal to a bit to which image data is allocated among each bit of parallel data in the “invalid period”. Here, the image processing signal used for the image processing is a photo sensor signal, an image effective period signal in the sub-scanning direction, or the like.

  Even if the photo sensor signal, the image valid period signal in the sub-scanning direction, and the like are not always detected continuously, for example, even if detection is performed for each line of image data, there is often no problem in signal detection. Therefore, in the “invalid period”, the transmission data creation unit 6 according to the second embodiment assigns the image data to the bits to which the image data is assigned, as in the first embodiment in which the synchronization signal is assigned to the bits to which the image data is assigned. A photo sensor signal, an image valid period signal in the sub-scanning direction, and the like are assigned.

  For example, the transmission data creation unit 6 assigns these image processing signals to serial data (LVDS signal), for example, 3 or more consecutive bits. On the other hand, the reception data creation unit 9 may receive these image processing signals as a signal at the center or near the center of the allocated consecutive bits of 3 bits or more.

  For example, when the allocation of a plurality of synchronization signals is in time for the current number of channels, but the allocation of image processing signals is not in time for the current number of channels, the image processing apparatus 10 is one as in the first embodiment. By using the bit separately for the image data and the image processing signal, the bit may be used efficiently.

  FIG. 6 is a diagram for explaining the allocation of photosensor signals and the like in the second embodiment. For example, as shown in FIG. 6, the “invalid period” is further divided into two periods based on a predetermined number of pixels, and for the “first half invalid period”, the transmission data creation unit 6 transmits each bit of parallel data. Among them, a synchronization signal is assigned to a bit to which a synchronization signal is assigned, and a synchronization signal is assigned to a bit to which image data is assigned, whereby a synchronization signal of 2 bits or more is assigned to parallel data in the “first invalid period”. On the other hand, with respect to the “second half invalid period”, the transmission data creation unit 6 assigns the photo sensor signal or the like to the bit to which the synchronization signal is assigned or the bit to which the image data is to be assigned. Assign signals etc.

  In this case, for the parallel data received in the “first half invalid period”, the reception data creation unit 9 reads out the synchronization signal from the bit to which the synchronization signal is allocated among the bits of the parallel data. For the parallel data received in the “second half invalid period”, the image processing signal is read from the bit to which the image processing signal is allocated among the bits of the parallel data. For the parallel data received during the “valid period”, the image data is read from the bit to which the image data is allocated among the bits of the parallel data.

  Then, it is possible to simultaneously realize the allocation of the synchronization signal and the allocation of the image processing signal in the first embodiment.

  Note that the synchronization signal selection executed by the reception data creation unit 9 described in the first embodiment may be incorporated as hard logic, or incorporated in advance in a ROM (Read Only Memory) or the like as a program. May be provided. Alternatively, the program is a file in an installable or executable format, and is a computer-readable recording such as a CD (Compact Disc) -ROM, a flexible disk (FD), a CD-R, and a DVD (Digital Versatile Disk). You may comprise so that it may record and provide on a medium. Furthermore, the program may be provided by being stored on a computer connected to a network such as the Internet and downloaded via the network. The program may be configured to be provided or distributed via a network such as the Internet.

  The program has a module configuration including each processing procedure described above. As actual hardware, the CPU reads the program from the ROM and executes it, so that each processing procedure is loaded on the main storage device. Each processing procedure is generated on the main storage device.

  Note that the image processing apparatus in the above embodiment may be, for example, a multifunction machine having at least two functions of a copy function, a printer function, a scanner function, and a facsimile function, or, for example, a copier, a printer, a scanner apparatus, A facsimile machine or the like may be used.

1 CCD
2 Analog processing section 3 ADC
4 Image Reading Unit 5 Timing Signal Generation Unit 6 Transmission Data Creation Unit 7 LVDS Transmitter 8 LVDS Receiver 9 Reception Data Creation Unit

Japanese Patent No. 3612219

Claims (7)

A transmission unit for allocating image data and a synchronization signal of the image data to each bit of the first parallel data, and transmitting the first parallel data;
A first converter for converting the first parallel data into serial data and transmitting the serial data;
A second converter that converts the serial data into second parallel data and transmits the second parallel data;
For the second parallel data received in the first period included in the period in which the image data is transmitted, the synchronization signal is read from the bit to which the synchronization signal is assigned among the bits of the second parallel data, and the image For the second parallel data received in the second period included in the period in which the data is transmitted, a receiving unit that reads the image data from the bits to which the image data is allocated among the bits of the second parallel data; With
The transmission unit assigns a synchronization signal to a bit to which a synchronization signal is assigned among bits of the first parallel data and assigns a synchronization signal to a bit to which image data is assigned, whereby 2 bits are assigned to the first parallel data in the first period. An image processing apparatus characterized by allocating a synchronization signal of bits or more.   The transmission unit allocates image data to bits adjacent to a bit to which a synchronization signal is allocated and corresponding to a bit before and after the bit to which the synchronization signal is allocated in the order on the serial data, and in the first period, The image processing apparatus according to claim 1, wherein a synchronization signal is further assigned to at least one of the bits corresponding to.   The reception unit reads a plurality of synchronization signals assigned to a plurality of bits for the second parallel data received in the first period, and based on a comparison result between the plurality of read synchronization signals, The image processing apparatus according to claim 1, wherein a synchronization signal used for synchronization is selected. The first period is further divided into a first period first period and a first period latter period,
In the first period of the first period, the transmission unit allocates a synchronization signal to a bit to which a synchronization signal is allocated among each bit of the first parallel data, and allocates a synchronization signal to a bit to which image data is allocated. By assigning a synchronization signal of 2 bits or more to the first parallel data of the previous period, and assigning an image processing signal used for image processing to each bit of the first parallel data in the latter part of the first period, The image processing apparatus according to claim 1, wherein an image processing signal is assigned to the first parallel data.   The image processing apparatus according to claim 1, wherein the serial data transmitted by the first conversion unit is a differential signal. A transmission unit for allocating image data and an image processing signal used for image processing of the image data to each bit of the first parallel data, and transmitting the first parallel data;
A first converter for converting the first parallel data into serial data and transmitting the serial data;
A second converter that converts the serial data into second parallel data and transmits the second parallel data;
For the second parallel data received in the first period included in the period in which the image data is transmitted, the image processing signal is read from the bit to which the image processing signal is allocated among the bits of the second parallel data. For the second parallel data received in the second period included in the period in which the image data is transmitted, reception of reading out the image data from the bit to which the image data is allocated among each bit of the second parallel data With
The transmitting unit allocates an image processing signal to the first parallel data in the first period by allocating an image processing signal to a bit to which image data is allocated among each bit of the first parallel data. Processing equipment. An image data transmission / reception method executed by an image processing apparatus,
A transmission step of assigning image data and a synchronization signal of the image data to each bit of the first parallel data, and transmitting the first parallel data;
A first conversion step of converting the first parallel data into serial data and transmitting the serial data;
A second conversion step of converting the serial data into second parallel data and transmitting the second parallel data;
For the second parallel data received in the first period included in the period in which the image data is transmitted, the synchronization signal is read from the bit to which the synchronization signal is assigned among the bits of the second parallel data, and the image For the second parallel data received in the second period included in the period during which data is transmitted, a receiving step of reading the image data from the bits to which the image data is allocated among the bits of the second parallel data; Including
The transmission step assigns 2 to the first parallel data in the first period by assigning a synchronization signal to a bit to which a synchronization signal is assigned and assigning a synchronization signal to a bit to which image data is assigned. An image data transmission / reception method characterized by assigning a synchronization signal of bits or more.

Images