JP2013066027A - Pipeline type a/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pipeline type A/D converter capable of suppressing generation of linearity errors and amplifying only a signal generated by the pipeline type A/D converter independently of a gain of a digital PGA, even in the case that the pipeline type A/D converter includes the digital PGA.SOLUTION: An A/D converter 102-1' processing an MSB side of a digital output signal Dout has output value fixing switching elements 151 and 152 whose conduction states are controlled by comparator output control signals CP1 and CP1' outputted from a controller 105'. By controlling the conduction states of those switching elements depending on a predetermined gain by a digital PGA 202, comparator output values of A/D converters 102-1' and 102-2' are fixed so as not to switch a reference voltage to be added to or subtracted from a signal in the middle of processing, like in a normal operation state.

Description

  The present invention relates to a pipeline type A / D converter, and in particular, a pipeline type A / D in which a plurality of A / D converters are connected to each other in multiple stages to perform a plurality of A / D conversion processes in one clock. Concerning the converter.

  Electronic devices such as various image sensors and image processing devices that need to convert analog signals into digital signals are required to process a large amount of data at high speed. A pipe capable of performing a plurality of A / D conversion processes in one clock by configuring a plurality of A / D converters connected in cascade in multiple stages so that such a process can be performed. A line type A / D converter is known.

As a conventional pipeline type A / D converter, for example, there is a pipeline type A / D converter of Non-Patent Document 1.
First, the configuration of a conventional general pipeline type A / D converter 100 will be described with reference to FIG. FIG. 5 is a block diagram showing a configuration of a conventional general pipeline type A / D converter 100.

The pipeline type A / D converter 100 shown in FIG. 5 includes a sample and hold circuit 101, k A / D converters 102-1 to 102-k connected in cascade, a memory 103, an arithmetic circuit 104, and a control. Unit 105.
The sample hold circuit 101 is a circuit for sampling and holding the analog input signal Ain and sending the held analog input signal Ain to the first A / D converter 102-1.

The A / D converters 102-1 to 102-k are connected in cascade, and based on the analog input signal Vin input to each stage, the A / D converters 102-1 to 102-k have the resolution corresponding to the A / D converters 102-1 to 102-k. D conversion processing is performed, and s digit digital output signals d _j (j = 1, 2,..., K) are sent to the memory 103. Further, A / D converters 102-1 to 102-k includes an analog input signal Vin in each stage, the digital output signal _{d j} of the D / A conversion result and the next stage analog output signal Vout obtained from the A / D Send to converter.

The memory 103 receives and stores s-digit digital output signals d _j determined by the k A / D converters 102-1 to 102-k. That is, the memory 103 may be a semiconductor memory that has at least k addresses and can store s bits of data per address.
Computing circuit 104 combines the digital output signal _{d j} stored in the memory 103, calculates a digital output signal Dout of the S bit. The calculation method in the calculation circuit 104 is as follows. First, it adds the least significant digit of the most significant digit and d _k-1 of d _k in binary. Next, based on this result, the most significant digit of d _k−1 and the least significant digit of d _k−2 are similarly added in the binary system. Hereinafter, by repeating this, matched finally added and the least significant bits of d _1, the most significant bit of d _2. Thus, we summed the result is a digital output signal Dout for all d _j.

The control unit 105 sets each switching element in the A / D converters 102-1 to 102-k in order to perform an operation of sampling and holding the analog input signal Vin in accordance with an internally generated master clock signal φ. This is for generating switching element control signals φ1 and φ2 for electrically switching to either the connected state or the disconnected state.
Since the A / D converters 102-1 to 102-k are the same circuit having the same elements, the circuit configuration of the A / D converter 102-1 will be described with reference to FIG. .

FIG. 6 is a circuit diagram showing a circuit configuration of the A / D converter 102-1 when the resolution in charge is 1.5 bits. The resolution of 1.5 bits indicates that the digital output signal output from the A / D converter 102-1 is ternary.
An A / D converter 102-1 shown in FIG. 6 includes sample-and-hold switching elements 121 to 125, sample-and-hold capacitors 126 and 127, an operational amplifier 128, an A / D sub-converter 129, and a multi-value output circuit 130. And is configured.

  Based on switching element control signals φ1 and φ2 output from the control unit 105, the sample hold switching elements 121 to 125 change the electrical connection state to either the connected state or the disconnected state in order to perform the sample hold operation. It is for switching. The sample and hold switching elements 121 and 122 are connected between an input terminal for inputting the analog input signal Vin and input terminals of the sample and hold capacitors 126 and 127. The sample and hold switching element 123 is connected between the output terminals of the sample and hold capacitors 126 and 127 and the analog ground. The sample and hold switching element 124 is connected between the output terminal of the operational amplifier 128 and the input terminal of the sample and hold capacitor 126. The sample and hold switching element 125 is connected between the output terminal of the multi-value output circuit 130 and the input terminal of the sample and hold capacitor 127. Each of the switching elements is connected when the switching element control signals φ1 and φ2 are at the H level, and is disconnected when the switching element control signals φ1 and φ2 are at the L level.

The sample and hold capacitors 126 and 127 are for charging and discharging charges corresponding to the sampled analog input signal Vin with reference to the reference voltage output from the multilevel output circuit 130.
In the operational amplifier 128, analog ground is connected to the non-inverting (+) input terminal, sample hold capacitors 126 and 127 are connected to the inverting (−) input terminal, and the potential difference between the signals input to the two input terminals is calculated. Amplify.

A / D sub-converter 129 is composed of two comparators, not shown, it is used to convert the analog input signal Vin into a digital output signal d _j.
The multilevel output circuit 130 includes multilevel output switching elements 131 to 133. The switching elements 131 to 133 are connected between a voltage source that outputs −Vref (V), 0 (V), and + Vref (V), which are predetermined voltages, and an output terminal of the multilevel output circuit 130. Based on the output result of the / D sub-converter 129, the electrical connection state is switched to either the connected state or the disconnected state. The multi-value output circuit 130, on the basis of the digital output signal _{d j,} by the switched electrical connection of the switching elements 131 to 133, any -Vref of (V), 0 (V) , + Vref (V) One reference voltage is output. Vref (V) is a predetermined voltage determined by the input range of the A / D conversion process, and 0 (V) is an analog ground voltage.

The operation of the A / D converter 102-2 is divided into a sample operation phase and a hold operation phase, and the sample operation and the hold operation are alternately repeated.
First, during the sample operation, the sample-and-hold switching elements 121 to 123 are connected, and the sample-and-hold switching elements 124 and 125 are disconnected. Then, the analog input signal Vin input from the A / D converter 102-1 at the previous stage is sampled by the sample and hold capacitors 126 and 127. In addition, the A / D sub-converter 129 performs an A / D conversion process on the analog input signal Vin input from the A / D converter 102-1 in the previous stage, so that any one value of −1, 0, 1 is obtained. Output. Precisely, −1 when Vin is smaller than −0.25 Vref (V), 0 when Vin is larger than −0.25 Vref (V) and smaller than +0.25 Vref (V), and Vin is +0.25 Vref. When 1 is larger than (V), 1 is output.
The multi-value output circuit 130 outputs a reference voltage of −Vref (V) when the output result of the A / D sub-converter 129 is −1, 0 (V) when it is 0, and + Vref (V) when it is 1. To do.

  In the hold operation, the sample-hold switching elements 121 to 123 are disconnected, and the sample-hold switching elements 124 and 125 are connected. A capacitor 126 is connected between the output terminal and the inverting input terminal of the operational amplifier 128 and used as a feedback element. This amplifies the voltage of the analog input signal Vin twice. Further, according to the output result of the A / D sub-converter 129, the electrical connection state of any one of the switching elements 131 to 133 becomes a connection state, and −Vref (V), 0V, + Vref (V) is connected to the capacitor 127. Any one of the voltages is output. As a result, the analog output signal Vout that can be taken within the range of the analog input signal Vin amplified twice is within the output range of the A / D converter of its own stage, that is, the input range of the A / D converter of the next stage. To fit in. This analog output signal Vout becomes the analog input signal Vin of the A / D converter 102-2 connected to the subsequent stage of the A / D converter 102-1.

Next, the relationship between the input range of the analog input signal Vin of the A / D converter 102-1 and the output range of the analog output signal Vout will be described with reference to FIG. FIG. 7 is a graph showing the relationship between the input range of the analog input signal Vin of the A / D converter 102-1 and the output range of the analog output signal Vout.
The horizontal axis of the graph shown in FIG. 7 indicates the voltage of the analog input signal Vin input to the A / D converter 102-1. The vertical axis indicates the voltage of the analog output signal Vout output from the A / D converter 102-1. The input analog input signal Vin is amplified by a factor of 2, and Vref (V) is added in a range smaller than −0.25Vref (V), and Vref (V) in a range larger than + 0.25Vref (V). V) is subtracted. Thus, the analog output signal Vout of the own stage A / D converter does not exceed the output range of the own stage A / D converter, that is, the input range of the next stage A / D converter.

  In addition, a digital programmable gain amplifier (hereinafter referred to as “digital PGA”) for controlling the gain of the signal processed by the pipeline type A / D converter 100 at the subsequent stage of the pipeline type A / D converter 100 as described above. May be provided.). In recent years, from the viewpoint of reducing the manufacturing cost, an analog programmable gain amplifier is not provided on the front side of the pipeline type A / D converter, but a digital PGA is provided on the rear side of the pipeline type A / D converter. In many cases, digital data after conversion processing is amplified by a digital PGA.

  FIG. 8 is a block diagram showing a circuit configuration of a pipeline type A / D converter 200 in which a digital PGA 202 is connected to the rear side of the pipeline type A / D converter main body 201. A pipeline type A / D converter 200 shown in FIG. 8 includes a pipeline type A / D converter main body 201, a digital PGA 202, and a limiter 203.

The pipeline type A / D converter main body 201 has the same circuit configuration as the pipeline type A / D converter 100 described in FIG. Here, the pipeline type A / D converter 100 outputs 0 to (2 ^k −1) as an output value. The digital output signal Dout output from the pipeline type A / D converter 100 is input to the digital PGA 202.

The digital PGA 202 amplifies the digital output signal Dout according to a preset gain (set gain) and outputs the signal as the digital output signal Dout2. Further, the digital output signal Dout2 output from the digital PGA 202 is input to the limiter 203.
The limiter 203 outputs the digital output signal Dout2 as the digital output signal Dout3 when the digital output signal Dout2 does not exceed the maximum output value of the pipeline type A / D converter 100. Further, when the digital output signal Dout2 exceeds the maximum output value of the pipeline type A / D converter, the limiter 203 outputs a signal obtained by rounding the digital output signal Dout2 to the maximum output value as the digital output signal Dout3. .

  More specifically, assuming that the pipeline A / D converter body 201 is a 10-bit pipeline A / D converter, the maximum output value of the pipeline A / D converter body 201 is 1023. is there. However, as described above, when the digital output signal Dout is amplified by the digital PGA 202, the output value may exceed 1023. Therefore, when the output value becomes 1024 or more, the limiter 203 performs processing for rounding the output value to 1023 which is the maximum output value. In the pipeline A / D converter 200 described above, when the output value output from the digital PGA 202 exceeds the maximum output value of the pipeline A / D converter 100 in this way, The limiter 203 makes the output value of the pipeline type A / D converter 100 fall within the maximum output value.

On the other hand, this means that the input range of the pipelined A / D converter 100 is narrowed as the gain of the digital PGA 202, that is, the amplification factor increases.
FIG. 9 is a graph showing input / output characteristics of the A / D converter 102-1 of the pipeline type A / D converter main body 201 to which the digital PGA 202 is connected. FIG. 10 is a graph showing input / output characteristics of the A / D converter 102-2 of the pipeline type A / D converter main body 201 to which the digital PGA 202 is connected.

In the graph shown in FIG. 9, the input range R ₁₁ of each A / D converter 102-1 when the gain of the digital PGA 202 is 1 time, and each A / D converter when the gain of the digital PGA 202 is 2 times. An input range R _{12 of} 102-1 and an input range R ₁₄ of each A / D converter 102-1 when the gain of the digital PGA 202 is four times are shown. As shown in FIG. 9, in the A / D converter 102-1, when the gain of the digital PGA 202 is doubled from 1 to 2, the input range of the A / D converter 102-1 is narrowed to 1/2. Further, when the gain of the digital PGA 202 is doubled to four times, the input range of the A / D converter 102-1 is narrowed to ½.

Further, in the graph shown in FIG. 10, the input range R ₂₁ of each A / D converter 102-1 when the gain of the digital PGA 202 is 1 time, and each A / D when the gain of the digital PGA 202 is 4 times. It indicates the input range _{R 34} in D converter 102-1. As shown in FIG. 10, also in the A / D converter 102-2 connected to the rear stage side of the A / D converter 102-1, when the gain of the digital PGA 202 increases from 1 to 4, the A / D converter 102 The input range of -1 is reduced to 1/2.

IEEE Journal of Solid State Circuits. Vol. 32. No3. March 1997. P312 to P320

  In the pipeline type A / D converter as described above, for example, the finite gain of the operational amplifier is affected by switching the reference voltage added to or subtracted from the signal being processed at each stage, or the switched capacitor is switched. Circuit mismatch may occur. Due to these causes, an error (error) is generated in the signal processing of the pipeline type A / D converter, and this error is finally a discontinuous linearity error, in particular, differential non-linearity (DNL). ) An error occurs. Such a linearity error may affect the characteristics of the pipeline type A / D converter.

  Therefore, in the case where the digital PGA is connected to the rear stage side of the pipeline type A / D converter, the digital PGA is not only the signal generated by the pipeline type A / D converter but also this discontinuous linearity. The error is amplified as it is. For this reason, the higher the gain of the digital PGA, the higher the linearity required for the pipeline type A / D converter itself. Further, if high linearity is required as it is, the integration area and power consumption may increase.

  In addition, the linearity error as described above often occurs more significantly in the stage that processes the most significant bit (MSB) side of the digital output signal, that is, in the leading stage. Further, such a discontinuous linearity error often affects the characteristics of the image sensor particularly when A / D conversion processing is performed in an LSI (Large Scale Integration) for the image sensor.

  Therefore, in view of the above problems, the present invention suppresses occurrence of a linearity error regardless of the gain of the digital PGA, even in a pipeline A / D converter including a digital PGA. An object of the present invention is to provide a pipeline type A / D converter capable of amplifying only a signal generated by the A / D converter.

In order to achieve the above object, a pipeline type A / D converter according to the present invention is configured as follows.
A first pipeline type A / D converter according to an aspect of the present invention includes an arithmetic circuit that synthesizes digital output signals output from a plurality of A / D converters connected in cascade to each other in multiple stages, and the arithmetic circuit A digital programmable gain amplifier that amplifies the combined digital output signal with a predetermined setting gain; and a control unit that controls circuit operations of the plurality of A / D converters. At least one of the A / D converters includes an output value fixing unit that operates to fix a converter output value output from an internal A / D sub-converter, and the control unit includes the digital programmable gain. The operation state of the output value fixing unit is fixed so that the converter output value is fixed according to the set gain of the amplifier. And controlling the.

  According to the first pipeline type A / D converter, at least one A / D converter among the plurality of A / D converters converts the converter output value output from the internal A / D sub-converter. An output value fixing unit that operates so as to be fixed is provided. Then, the control unit controls the operation state of the output value fixing unit so that the converter output value output from the A / D converter including the output value fixing unit is fixed according to the gain of the digital programmable gain amplifier. .

  In other words, when the signal is amplified by a digital programmable gain amplifier, for example, twice or further four times, the A in the A / D converter of at least one of the pipeline type A / D converters. The converter output value of the / D sub-converter is fixed. As a result, the reference voltage added to or subtracted from the signal being processed is not switched as in the normal operation state. Thereby, it becomes possible to suppress the occurrence of discontinuous linearity errors caused by switching the reference voltage in each A / D converter.

That is, even when a digital programmable gain amplifier is connected to the downstream side of the pipeline type A / D converter, the digital PGA is not only a signal generated by the pipeline type A / D converter but also this discontinuous. The linearity error is not amplified as it is.
A second pipeline type A / D converter according to an aspect of the present invention is an i-th stage (i is an arbitrary integer of 1 or more) from the top of the pipeline type A / D converter. When the number of conversion bits of the / D converter is n (i) +0.5 bits (n is an arbitrary integer of 1 or more), the control unit is in the m-th stage from the beginning (m is an arbitrary number) When the converter output value of the A / D converter is fixed, the set gain of the digital digital programmable gain amplifier is 2 ^{n (1) + n (2) +... + N (m)} The operation state of the output value fixing unit is fixed so that the converter output value is fixed within a range in which the analog output signal output from the m-th stage A / D converter does not exceed the output range when the value is equal to or greater than twice. Characterized by controlling To do.

According to the second pipeline A / D converter, when the gain of the digital programmable gain amplifier is multiplied by a predetermined value, the input range of the A / D converter becomes narrow.
Therefore, when the conversion bit of the i-th A / D converter is n (i) +0.5 bits, the set gain of the digital digital programmable gain amplifier is 2 ^{n (1) + n (2) +... + N (m )} If the A / D converter's analog output signal does not exceed the output range, that is, the input range of the A / D converter in the next stage, The operation state of the output value fixing switching element is controlled so as to fix the converter output value to an appropriate value.

  In other words, any pipe such as a pipelined A / D converter composed of a multi-bit A / D converter or a pipelined A / D converter composed of a combination of A / D converters having different numbers of bits. Even in the case of a line type A / D converter, when the converter output value is fixed, the analog output signal of its own A / D converter exceeds the output range, that is, the input range of the next stage A / D converter. In such a range, the converter output value may be fixed to an appropriate value. As a result, it is possible to suppress discontinuous linearity errors in each A / D converter caused by switching the reference voltage added to or subtracted from the signal being processed in each stage as in the normal operation state.

  In a third pipeline A / D converter according to an aspect of the present invention, the number of conversion bits of the first and second A / D converters from the top of the pipeline A / D converter is 1. When the setting gain of the digital programmable gain amplifier is 2 times or more and less than 4 times, the control unit fixes the converter output value of the first stage A / D converter from the top, When the set gain of the digital programmable gain amplifier is not less than 4 times and less than 8 times, the operation of the output value fixing unit is further fixed so that the converter output value of the A / D converter in the second stage from the top is fixed. It is characterized by controlling the state.

  Specifically, according to the third pipeline A / D converter, if the number of conversion bits of the first and second A / D converters from the top is 1.5 bits, the control unit Controls the operating state of the output value fixing unit so that the converter output value of the first A / D converter from the beginning is fixed when the set gain of the digital programmable gain amplifier is 2 times or more and less than 4 times Just do it. In addition, the control unit sets the operation state of the output value fixing unit so that when the set gain is 4 times or more and less than 8 times, the converter output value of the A / D converter in the second stage from the top is also fixed. Just control.

  In a fourth pipelined A / D converter according to an aspect of the present invention, the output value fixing unit switches the output value to be switched so that any one of an analog input signal and a constant voltage is input. The control unit controls a conduction state of the output value fixing switching element so that the converter output value is fixed in accordance with a set gain of the digital programmable gain amplifier. .

  According to the fourth pipeline A / D converter described above, at least one A / D converter among a plurality of A / D converters converts a signal input to its own circuit from an analog input signal and a constant voltage. An output value fixing switching element for switching to any one of the voltages is provided. Then, the control unit controls the conduction state of the output value fixing switching element according to the set gain of the digital programmable gain amplifier, so that the A / D inside the A / D converter including the output value fixing switching element is controlled. The converter output value output from the sub-converter can be fixed.

  In a fifth pipelined A / D converter according to an aspect of the present invention, the output value fixing switching element is connected between a terminal to which the constant voltage is input and an input terminal of the A / D sub-converter. A first switching element, a terminal to which the analog input signal is input, and a second switching element connected between an input terminal of the A / D sub-converter, and the control unit includes: When the converter output value is not fixed, the conduction state of the first switching element is turned off and the conduction state of the second switching element is turned on. When the conduction state of the switching element 2 is controlled and the converter output value is fixed, the conduction state of the first switching element is turned on and the second switching element is turned on. As the conductive state of the switching element is turned off, and controls the conduction state of the first switching element and the second switching element.

According to the fifth pipeline type A / D converter, the output value fixing switching elements are two switching elements of the first switching element and the second switching element as described above.
Therefore, the control unit performs control so that the conduction state of the first switching element is turned on and the conduction state of the second switching element is turned off. Then, it is possible to fix the converter output value within a range where the analog output signal of the A / D converter of the own stage does not exceed the output range, that is, the input range of the A / D converter of the next stage. Further, when the converter output value is not fixed, the control unit may perform control so that the conduction state of the first switching element is turned off and the conduction state of the second switching element is turned on.

  According to the present invention, by fixing the converter output value of the A / D converter to an appropriate value in accordance with the gain of the digital PGA, a problem that occurs when the signal output from the pipeline type A / D converter is amplified. Suppresses the occurrence of continuous linearity errors. The digital PGA can amplify the A / D converted signal with few discontinuous linearity errors.

It is a block diagram which shows the circuit structure of the pipeline type A / D converter 10 which concerns on this embodiment. 2 is a circuit diagram showing a circuit configuration of an A / D converter 102-1 ′ constituting a pipeline type A / D converter 10. FIG. It is a graph which shows the input-output characteristic of A / D converter 102-1 'which can control a comparator output value. It is a graph which shows the input-output characteristic of A / D converter 102-2 'which can control a comparator output value. 1 is a block diagram showing a configuration of a conventional general pipeline type A / D converter 100. FIG. It is a circuit diagram which shows the circuit structure of the A / D converter 102-1 when the resolution in charge is 1.5 bits. It is a graph which shows the relationship between the input range of the analog input signal Vin of the A / D converter 102-1, and the output range of the analog output signal Vout. 2 is a block diagram showing a circuit configuration of a pipeline type A / D converter 200 in which a digital PGA 202 is connected to the rear stage side of the pipeline type A / D converter main body 201. FIG. 4 is a graph showing input / output characteristics of an A / D converter 102-1 of a pipeline type A / D converter main body 201 to which a digital PGA 202 is connected. 6 is a graph showing input / output characteristics of an A / D converter 102-2 of a pipeline type A / D converter main body 201 to which a digital PGA 202 is connected.

Hereinafter, a preferred embodiment of a pipeline type A / D converter of the present invention will be described in detail with reference to the accompanying drawings.
(Circuit configuration of pipeline type A / D converter 10)
First, a circuit configuration of a pipeline type A / D converter 10 according to an embodiment of the present invention will be described with reference to FIG.

FIG. 1 is a block diagram showing a circuit configuration of a pipeline type A / D converter 10 according to the present embodiment. A pipeline type A / D converter 10 shown in FIG. 1 includes a pipeline type A / D converter main body 201 ′, a digital PGA 202, and a limiter 203.
The pipeline A / D converter 10 shown in FIG. 1 and the pipeline A / D converter 200 shown in FIG. 8 are the same in that a digital PGA 202 and a limiter 203 are provided. However, the pipeline type A / D converter main body 201 ′ included in the pipeline type A / D converter 10 is different in circuit configuration from the pipeline type A / D converter main body 201 included in the pipeline type A / D converter 200. ing.

Similar to the pipeline type A / D converter 100 shown in FIG. 5, the pipeline type A / D converter body 201 ′ includes a sample hold circuit 101 and k A / D converters 102-1 connected in cascade. ', 102-2', 102-3 to 102-k, a memory 103, an arithmetic circuit 104, and a control unit 105 '.
The control unit 105 ′ is a circuit unit corresponding to the control unit 105 of the pipeline type A / D converter 100 illustrated in FIG. 5 and has a function of the control unit 105. However, in addition to these functions, the control unit 105 ′ generates comparator output control signals CP1, CP1 ′, CP2, CP2 ′ and outputs them to the A / D converters 102-1 ′, 102-2 ′. Have

  Specifically, the control unit 105 ′ outputs the comparator output control signal CP1 to the A / D converter 102-1 ′ at an H level that is a predetermined voltage level or an L level that is a voltage level lower than the H level. Similarly, the control unit 105 ′ outputs the comparator output control signal CP1 ′ to the A / D converter 102-1 ′ at the H level or the L level. However, the comparator output control signal CP1 ′ is output to the A / D converter 102-1 ′ so as to be an inverted signal of the comparator output control signal CP1. That is, when the voltage level of the comparator output control signal CP1 is H level, the voltage level of the comparator output control signal CP1 ′ is L level. On the other hand, when the voltage level of the comparator output control signal CP1 is L level, the voltage level of the comparator output control signal CP1 ′ is H level.

Further, the control unit 105 ′ outputs the comparator output control signals CP2 and CP2 ′ to the A / D converter 102-2 ′. The comparator output control signals CP2 and CP2 ′ are also used for the voltage levels of the comparator output control signals CP2 and CP2 ′. It is the same as CP1 and CP1 ′.
The A / D converters 102-1 'and 102-2' are circuit units corresponding to the A / D converters 102-1 and 102-2 of the pipeline type A / D converter 100 shown in FIG. The A / D converters 102-1 and 102-2 have functions. However, in addition to these functions, the A / D converters 102-1 'and 102-2' have a comparator output value output from the internal A / D sub-converter output from the control unit 105 '. It has a function of controlling to be fixed based on the output control signals CP1, CP1 ′, CP2, CP2 ′.

That is, in the pipeline type A / D converter 10, the control unit 105 ′ generates the comparator output control signals CP1, CP1 ′, CP2, CP2 ′, and based on the comparator output control signals CP1, CP1 ′, CP2, CP2 ′. Thus, it has a comparator output value control function for controlling the comparator output values of the A / D sub-converters of the A / D converters 102-1 'and 102-2' to be fixed.
(Circuit configuration of A / D converter 102-1 ')
Next, the circuit configuration of the A / D converter 102-1 ′ will be described with reference to FIG.

  FIG. 2 is a circuit diagram showing a circuit configuration of the A / D converter 102-1 ′ constituting the pipeline type A / D converter 10. The A / D converter 102-1 ′ illustrated in FIG. 2 includes a circuit portion and elements similar to the A / D converter 102-1 illustrated in FIG. However, the A / D converter 102-1 ′ is different from the A / D converter 102-1 in that it further includes output value fixing switching elements 151 and 152.

  Note that the A / D converter 102-2 ′ also includes switching elements having the same functions as the output value fixing switching elements 151 and 152 in addition to the circuit units and elements similar to the A / D converter 102-2. Composed. Also in the A / D converter 102-2 ′, the comparator output control signals CP2 and CP2 ′ output from the control unit 105 ′ are input. However, since the circuit configuration and circuit operation of the A / D converter 102-2 'are substantially the same as those of the A / D converter 102-1', the circuit configuration of the A / D converter 102-1 'is the same. I will explain only.

The conduction state of the output value fixing switching elements 151 and 152 is switched between the on state and the off state depending on the voltage levels of the comparator output control signals CP1 and CP1 ′.
Specifically, the conduction state of the output value fixing switching element 151 is turned on when the voltage level of the comparator output control signal CP1 is H level. On the other hand, when the voltage level of the comparator output control signal CP1 is L level, the conduction state is turned off.

Further, the output value fixing switching element 152 is turned on when the voltage level of the comparator output control signal CP1 ′ is H level. On the other hand, when the voltage level of the comparator output control signal CP1 ′ is L level, the conduction state is turned off.
As already described above, the comparator output control signal CP1 ′ is an inverted signal of the comparator output control signal CP1. Therefore, when the conduction state of the output value fixing switching element 151 is on, the conduction state of the output value fixing switching element 152 is off. Further, when the conduction state of the output value fixing switching element 151 is OFF, the conduction state of the output value fixing switching element 152 is ON.
(Circuit operation of A / D converters 102-1 'and 102-2')

Next, circuit operations of the A / D converters 102-1 'and 102-2' will be described with reference to FIGS.
FIG. 3 is a graph showing the input / output characteristics of the A / D converter 102-1 'capable of controlling the comparator output value. FIG. 4 is a graph showing the input / output characteristics of the A / D converter 102-2 'that can control the comparator output value.
In the graph shown in FIG. 3, the input range R ₁₂ ′ of each A / D converter 102-1 ′ when the gain of the digital PGA 202 is doubled, and each A / D when the gain of the digital PGA 202 is four times. The input range R ₁₄ ′ of the D converter 102-1 ′ is shown respectively. Also, the graph shown in FIG. 4 shows the input range R ₂₄ ′ of each A / D converter 102-1 ′ when the gain of the digital PGA 202 is four times.

  In the pipeline type A / D converter 10, the basic circuit configuration and circuit operation are the same as those of the pipeline type A / D converter 200 shown in FIG. 8 described in the background art. However, the pipeline A / D converter 10 has an output value fixing switching element whose conduction state is controlled by the comparator output control signals CP1, CP1 ′, CP2, CP2 ′ output from the control unit 105 ′. ing. Then, the pipeline A / D converter 10 controls the conduction state of these switching elements according to the gain of the digital PGA 202, thereby amplifying the signal according to the predetermined gain by the digital PGA 202. The comparator output values of the A / D sub-converters of the D converters 102-1 'and 102-2' can be fixed.

In order to fix the comparator output value, the voltage levels of the control signals CP1, CP1 ′, CP2, CP2 ′ are changed, and the inputs of the A / D converters 102-1 ′, 102-2 ′, that is, A / D The input signals of the D converters 102-1 ′ and 102-2 ′ may be switched from the analog input signal Vin to a constant voltage such as a ground voltage or a power supply voltage. In the description of the circuit operation, the pipeline type A / D converter 10 is described as outputting an output value of 0 to (2 ^k −1).

  First, when the gain of the digital PGA 202 is less than twice, the circuit operation of the A / D converter 102-1 'is the same as the circuit operation of the A / D converter 102-1 described in the background art. Therefore, the control unit 105 ′ outputs the comparator output control signal CP1 whose voltage level is L level. Then, the conduction state of the output value fixing switching element 151 is turned off. On the other hand, the control unit 105 ′ outputs a comparator output control signal CP1 ′ whose voltage level is H level. Then, the conduction state of the output value fixing switching element 152 is turned on. Therefore, the analog input signal Vin is input to the A / D converter 102-1 ′. The circuit operation of the A / D converter 102-2 ′ is the same as that of the A / D converter 102-1.

  Further, when the gain of the digital PGA 202 becomes 2 times or more and less than 4 times, the control unit 105 ′ outputs a comparator output control signal CP 1 whose voltage level is H level to the A / D converter 102-1 ′. Then, the conduction state of the output value fixing switching element 151 is turned on. On the other hand, the control unit 105 ′ outputs a comparator output control signal CP1 ′ having a voltage level of L level to the A / D converter 102-1 ′. Then, the conduction state of the output value fixing switching element 152 is turned off. Therefore, the ground voltage is input to the A / D converter 102-1 ′.

  As a result, the analog output signal Vout output from the A / D converter of the own stage is converted into the A / D converter within the output range of the A / D converter of the own stage, that is, within the input range of the A / D converter of the next stage. The comparator output value of the A / D sub-converter 129 of the D converter 102-1 ′ is not changed and is kept fixed at the minimum value of −1. The input / output characteristics of the A / D converter 102-1 'at this time are as shown in FIG. First, since the comparator output value is fixed, the reference voltage is switched according to the voltage of the analog input signal Vin in the input range of the A / D converter 102-1 'as in the normal operation state, and the processing is performed. The reference voltage added to or subtracted from the intermediate signal is not switched. For this reason, the analog output Vout is not folded back as shown in FIG. 9 at the position of the arrow A shown in FIG. Therefore, as described in the background art, a discontinuous linearity error caused by switching the reference voltage added to or subtracted from the signal being processed in each stage does not occur.

  Since the digital PGA 202 is connected to the subsequent stage of the pipeline type A / D converter main body 201 ′, the input range of the A / D converter 102-1 ′ is as shown in FIG. 3 according to the gain of the digital PGA 202. Narrow. And the signal value beyond the input range is naturally ignored. Therefore, when processing valid signal values in the input range, the reference voltage to be added to or subtracted from the signal being processed is not switched, so that a discontinuous linearity error does not occur as much as possible. Yes.

Further, although the reference voltage is not switched, naturally, the output of the A / D converter 102-1 'remains the same as the input range of the next stage, so that there is a conversion error in each A / D converter. It does not occur.
Further, when the gain of the digital PGA 202 is 4 times or more and less than 8 times, not only the A / D converter 102-1 'but also the comparator output value of the A / D sub-converter of the A / D converter 102-2' is the minimum value. It is fixed to -1. The control unit 105 ′ outputs a comparator output control signal CP2 whose voltage level is H level to the A / D converter 102-2 ′. Further, the control unit 105 ′ outputs a comparator output control signal CP2 ′ having a voltage level of L level to the A / D converter 102-2 ′. Then, the ground voltage is input to the A / D converter 102-2 ′, similarly to the A / D converter 102-1 ′.

  As a result, the comparator output value of the A / D sub-converter of the A / D converter 102-2 'is also fixed to the minimum value -1. The input / output characteristics of the A / D converter 102-2 ′ at this time are as shown in FIG. 4, but signals in the middle of processing as in the normal operation state within the input range of the A / D converter 102-2 ′. The reference voltage to be added to or subtracted from is not switched. For this reason, the analog output Vout is not folded back as shown in FIG. 10 at the position of the arrow B shown in FIG. Therefore, also in the A / D converter 102-2 ', as described in the background art, the reference voltage added to or subtracted from the signal being processed in each stage is switched and the signal generated during the processing is folded back. There is no continuous linearity error. Similarly, even if the reference voltage is not switched, the output of the A / D converter 102-2 'remains the same as the input range of the next stage, so that a conversion error may occur in each A / D converter. Absent.

  As described above, even when the gain of the digital PGA 202 is increased to 2 times or even 4 times, the analog output signal Vout of the A / D converter of the own stage is not changed in the A / D converter of each A / D converter. The comparator output value is fixed to the minimum value within the range not exceeding the output range of the / D converter, that is, the input range of the next stage A / D converter. As a result, the reference voltage added to or subtracted from the signal being processed is not switched as in the normal operation state, and the signal being processed is not folded. For this reason, it is possible to eliminate a discontinuous linearity error in each A / D converter caused by turning back a signal being processed. Regarding the series of effects described above, among the A / D converters constituting the pipeline type A / D converter 10, particularly, the MSB side of the digital output signal Dout that is highly susceptible to discontinuous linearity errors is used. The higher the A / D converter to process, the higher. In the description of the present embodiment, the comparator output values of only the A / D converters 102-1 'and 102-2' can be fixed. Of course, when the gain of the digital PGA 202 is higher, it The comparator output values of the subsequent A / D converters 102-3 to 102-n may be fixed.

In the description of the present embodiment, the output value of the pipeline type A / D converter 10 has been described as being 0 to (2 ^k −1). However, the output value of the pipeline type A / D converter is not limited to this. It is not limited. For example, the output value of the pipeline A / D converter including the negative value in the range of the output value of the pipeline A / D converter is set to (−2 ^k−1 ) to (2 ^k−1 −1). Also good. In this case, the digital PGA 202 amplifies the signal around the output value 0 of the pipeline type A / D converter. For this reason, when the comparator output value is fixed, the comparator output value is not fixed to −1 which is the minimum output value, but may be fixed to 0 which is an intermediate value between the maximum output value and the minimum output value. In other words, when the output value of the comparator is fixed, whatever the output range of the pipeline type A / D converter is, when the gain of the digital PGA 202 is amplified and the input range becomes narrower, The A / D converter analog output signal Vout should be fixed to an appropriate value within the range that does not exceed the output range of its own A / D converter, that is, the input range of the next-stage A / D converter. It ’s fine.

In the description of the present embodiment, the description is limited to the 1.5-bit A / D converter. However, the present invention is not limited to this. In a pipeline type A / D converter constituted by a multi-bit type A / D converter other than a 1.5 bit type, or a pipeline type A / D converter constituted by combining A / D converters having different numbers of bits Can also be implemented in the same manner. Specifically, the number of bits of the A / D converter at the i-th stage (i is an arbitrary integer greater than or equal to 1) from the head is n (i) +0.5 bits (n is an arbitrary 1 or greater) In the A / D converter at the m-th stage (m is an arbitrary integer of 1 or more) counting from the head side, the gain of the digital PGA 202 is 2 ^{n (1) + n (2) +... + N (m)} times or more, the analog output signal Vout of the own stage A / D converter is the output range of the own stage A / D converter, that is, the A / D converter of the next stage. What is necessary is just to fix a comparator output value in the range which does not exceed an input range.

  Furthermore, in the description of the present embodiment, the control unit 105 ′ causes the A / D converters 102-1 ′ and 102-2 to be switched so that the voltages input to the A / D converters 102-1 ′ and 102-2 ′ are switched. The comparator output value (converter output value) of the A / D sub-converter is fixed by controlling the conduction state of the output value fixing switching element included in '. However, the method of fixing the converter output value of the A / D sub-converter is not limited to this. For example, a circuit instead of an output value fixing switching element is provided as an output value fixing unit inside the A / D sub-converter, and the control unit 105 ′ controls the operation state of the circuit, whereby the digital PGA 202. The converter output values of the A / D converters 102-1 'and 102-2' can be fixed according to the set gain.

(Summary of description of each embodiment)
As described above, the pipeline type A / D converter 10 has the same basic circuit configuration and circuit operation as the pipeline type A / D converter 200 shown in FIG. 8 described in the background art. . However, in the pipeline type A / D converter 10, the comparator output values of the A / D sub-converters of the A / D converters 102-1 'and 102-2' are fixed according to the gain of the digital PGA 202. I was able to keep it.

  Therefore, when a signal is amplified according to a predetermined gain by the digital PGA, the A / D converter A / D converter that processes the MSB side of the digital output signal Dout among the A / D converters of the pipeline type A / D converter. The comparator output value of the D sub-converter is kept fixed. This prevents the A / D converter from switching the reference voltage that is added to or subtracted from the signal being processed as in the normal operation state.

  Thereby, in the pipeline type A / D converter 10, at each stage, the reference voltage added to or subtracted from the signal being processed is switched, and the pipeline type A / D generated when the signal being processed is turned back. It is less likely to cause errors in the converter, and the occurrence of discontinuous linearity errors is suppressed. Therefore, it is possible to suppress the linearity error from affecting the characteristics of the pipeline type A / D converter. The digital PGA can amplify the A / D converted signal with few discontinuous linearity errors.

  The pipeline type A / D converter of the present invention amplifies only the signal generated by the pipeline type A / D converter while suppressing the linearity error even in the pipeline type A / D converter including the digital PGA. As a pipeline type A / D converter that can be used, it is integrated in an LSI such as an image sensor.

10 …… Pipeline type A / D converter 201 ′ …… Pipeline type A / D converter main body 202 …… Digital PGA
203 …… Limiter 101 …… Sample hold circuit 102-1 ′, 102-2 ′, 102-3 to 102-k …… A / D converter 103 …… Memory 104 …… Operation circuit 105 ′ …… Control unit 151 152 …… Switching element for fixing output value

Claims (5)

An arithmetic circuit for synthesizing digital output signals output from a plurality of A / D converters connected in cascade to each other in multiple stages;
A digital programmable gain amplifier that amplifies the digital output signal synthesized by the arithmetic circuit with a predetermined set gain;
A control unit for controlling circuit operations of the plurality of A / D converters;
With
Further, at least one A / D converter of the plurality of A / D converters includes an output value fixing unit that operates to fix a converter output value output from an A / D sub-converter inside the A / D converter. ,
The pipeline type A / D converter, wherein the control unit controls an operation state of the output value fixing unit so that the converter output value is fixed in accordance with a set gain of the digital programmable gain amplifier. . The number of conversion bits of the A / D converter at the i-th stage (i is an arbitrary integer of 1 or more) from the top of the pipeline type A / D converter is n (i) +0.5 bits ( n is an arbitrary integer of 1 or more)
The controller is
When the converter output value of the A / D converter at the m-th stage from the beginning (m is an arbitrary integer of 1 or more) is fixed, the set gain of the digital digital programmable gain amplifier is 2 ^{n (1) + n (2) + ... + n (m)} times or more, so that the converter output value is fixed in a range where the analog output signal output from the m-th stage A / D converter does not exceed the output range. The pipeline type A / D converter according to claim 1, wherein an operation state of the output value fixing unit is controlled. When the number of conversion bits of the first-stage and second-stage A / D converters from the top of the pipeline type A / D converter is 1.5 bits,
The controller is
When the set gain of the digital programmable gain amplifier is not less than 2 times and less than 4 times, the converter output value of the first stage A / D converter from the top is fixed,
When the set gain of the digital programmable gain amplifier is not less than 4 times and less than 8 times, the operation of the output value fixing unit is further fixed so that the converter output value of the A / D converter in the second stage from the top is fixed. The pipeline A / D converter according to claim 2, wherein the state is controlled. The output value fixing unit is:
An output value fixing switching element that switches so that any one of an analog input signal and a constant voltage is input,
The said control part controls the conduction | electrical_connection state of the said output value fixing switching element so that the said converter output value may be fixed according to the setting gain of the said digital programmable gain amplifier. The pipeline type A / D converter according to any one of the above. The output value fixing switching element is:
A first switching element connected between a terminal to which the constant voltage is input and an input terminal of the A / D sub-converter;
A second switching element connected between a terminal to which the analog input signal is input and an input terminal of the A / D sub-converter;
The controller is
When the converter output value is not fixed, the conduction state of the first switching element is turned off and the conduction state of the second switching element is turned on. Control the conduction state of the two switching elements,
When the converter output value is fixed, the conduction state of the first switching element is turned on, and the conduction state of the second switching element is turned off. The pipeline type A / D converter according to claim 4, wherein the conduction state of the two switching elements is controlled.

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