JP2013058878A - Signal transmission device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal transmission device with galvanic input/output isolation for use in the fields of hybrid vehicles, electric vehicles, household appliances, industrial apparatuses and medical apparatuses which normally activates noise cancellation even when noise levels input into two transformers connected in parallel are different from each other.SOLUTION: A signal transmission device 100 comprises: a transformer T1 having a primary winding T11 and a secondary winding T12 galvanically separated and connected to different ground potentials; a first comparator CM1 and a second comparator CM_M1 into which an output from the secondary winding T12 of the transformer T1 is input; a delayed signal generation section 141a into which an output of the first comparator CM1 is input; and a masking signal generation section 143a into which an output of the second comparator CM_M1 is input.

Description

  The present invention relates to a signal transmission device, and particularly to a device having a noise canceling function.

Conventionally, in the fields of hybrid vehicles, electric vehicles, household electrical appliances, industrial equipment, and medical equipment, signal transmission devices using isolators are used to galvanically isolate the input and output and transmit signals. ing.

As an apparatus for transmitting a pulse-like signal using an isolator, that is, an insulating transformer, for example, Patent Document 1 (Japanese Patent Application No. 2010-104192), Patent Document 2 (Japanese Patent Application No. 2010-283929), and Patent Document 3 (Japanese Patent Application Laid-Open No. 2002-283929) Application No. 2011-129825) and Patent Document 4 (Japanese Patent Laid-Open No. 2010-10762) have been proposed.

Patent Document 1 (Japanese Patent Application No. 2010-104192), Patent Document 2 (Japanese Patent Application No. 2010-283929), and Patent Document 3 (Japanese Patent Application No. 2011-129825) relate to the present applicant, and noise is applied continuously. In this case, a noise removal circuit that can transmit and receive signals while electrically insulating the low-voltage side and the high-voltage side while reducing the effect of noise superimposed on the input signal, and a signal transmission circuit using an insulation transformer And a power converter.

Patent Document 4 (Japanese Patent Laid-Open No. 2010-10762) relates to the present applicant and discloses a power semiconductor drive circuit device having a self-diagnosis function and a signal transmission device used therefor.

FIG. 9 shows a conventional signal transmission device 900. The signal transmission device includes an electronic control device 110, an input side circuit 120, a transformer circuit 130, comparators CM1 and CM2, a noise cancellation circuit 140, a flip-flop FF, and an output terminal 150.

In the signal transmission device 900, the electronic control device 110 is an electronic control unit (ECU) for exchanging signals with, for example, a control mechanism of a hybrid vehicle and controlling the entire vehicle.

The input side circuit 120 includes a first pulse conversion circuit 121, a second pulse conversion circuit 123, and an inverter 125.

The transformer circuit 130 includes a first transformer T1 and a second transformer T2. As disclosed in Patent Document 1 and Patent Document 2, the transformer circuit 130 can be formed on or in an IC chip, and these transformers are sometimes referred to as microtransformers or isolators.

The first transformer T1 includes a primary winding T11 and a secondary winding T12. One end of each of the primary winding T11 and the secondary winding T12 is connected to the ground potential. One end of the primary winding T11 is connected to the first ground potential GND1, and one end of the secondary winding T12 is connected to the second ground. The potentials GND2 are connected to different ground potentials. That is, the primary winding T11 and the secondary winding T12 are separated in a direct current manner.

A comparator CM1 is connected to the secondary winding T12 side of the first transformer T1.

The signal output from the secondary winding T12 side is input to the noise cancellation circuit 140 via the comparator CM1.

The second transformer T2 includes a primary winding T21 and a secondary winding T22. One end of each of the primary winding T21 and the secondary winding T22 is connected to the ground potential. One end of the primary winding T21 is connected to the first ground potential GND1, and one end of the secondary winding T22 is connected to the second ground. The potentials GND2 are connected to different ground potentials. That is, also in the transformer T2, the primary winding T21 and the secondary winding T22 are separated in a direct current manner.

A comparator CM2 is connected to the secondary winding T22 side of the second transformer T2.

The signal output from the secondary winding T22 side is input to the noise cancellation circuit 140 via the comparator CM2.

Two signals are extracted from the noise cancellation circuit 140. One is a set signal Ps synchronized to the first transformer T1 side, and the other is a reset signal Pr synchronized to the second transformer T2 side.

The noise cancellation circuit 140 includes a first delay signal generation circuit 141a, a second delay signal generation circuit 141b, a first masking signal generation circuit 143a, a second masking signal generation circuit 143b, a first logic operation circuit unit 145a, and a second logic operation. A circuit portion 145b is provided.

The signal transmission device 900 having the above-described configuration operates to transmit a signal for switching the output from low to high and a signal for switching the output from high to low by different transformers, that is, transformers T1 and T2. In addition, when a signal that is not a regular signal, that is, noise is simultaneously input to the transformer T1 and the transformer T2, noise above the reference potential of the comparators CM1 and CM2 is flip-flops by the operation of the comparators CM1 and CM2 and the noise cancellation circuit 140. It has a function of not being output to the FF.

Japanese Patent Application No. 2010-104192 Japanese Patent Application No. 2010-283929 Japanese Patent Application No. 2011-129825 JP 2010-10762 A

  However, in the conventional signal transmission device, when the noise levels input to the transformers T1 and T2 are different from each other, the noise cancellation does not operate normally, causing a malfunction.

In the signal transmission device of the present invention, the primary winding and the secondary winding are separated in a DC manner, and the primary winding and the secondary winding are connected to different ground potentials; The first comparator and the second comparator to which the output from the secondary winding of the transformer is input, the delay signal generation circuit to which the output of the first comparator is input, and the masking to which the output of the second comparator is input And a signal generation circuit.

The first comparator and the second comparator may comprise a hysteresis comparator or a window comparator.

An output from the secondary winding of the transformer is input to first input terminals of the first comparator and the second comparator, and a first reference potential is applied to a second input terminal of the first comparator. A second reference potential is applied to the second input terminal of the second comparator, and the first reference potential is greater than the absolute value of the second reference potential.

More preferably, the transformer includes a first transformer and a second transformer, and a third comparator and a fourth comparator to which an output from a secondary winding of the second transformer is input, and an output of the third comparator is an input. And a masking signal generation circuit to which the output of the fourth comparator is input.

A first delayed signal set to a first pulse width by delaying an output from the first comparator, and a first delayed signal set to a pulse width larger than the first pulse width by delaying an output from the second comparator. 1 masking signal, the second delayed signal set to the second pulse width by delaying the output from the third comparator, and the pulse width for delaying the output from the fourth comparator and larger than the second pulse width A logical operation of the second masking signal set to 1, a first logical operation circuit unit for logically processing the first delayed signal and the second masking signal, and a logical operation of the second delayed signal and the first masking signal A second logic operation circuit for processing, and the noise superimposed on the first delay signal and the second delay signal is the second noise masking signal and the first noise masking respectively. It is masked by the signal.

  The pulse width of the first masking signal is larger than that of the second delayed signal, and the pulse width of the second masking signal is larger than that of the first delayed signal.

The first logical operation circuit unit and the second logical operation circuit unit each include at least one of a logical sum circuit, a negative logical sum circuit, a logical product circuit, and a negative logical product circuit. The signal transmission device according to claim 1.

The signals output from the first logic operation circuit unit and the second logic operation circuit unit are used as a flip-flop set signal and reset signal, respectively.

The signal transmission device according to the present invention includes a first pulse generation circuit that detects a rising edge of a transmission signal and generates a first conversion pulse smaller than a pulse width of the transmission signal; and the pulse-shaped transmission signal A pulse conversion circuit having a second pulse generation circuit that detects a falling edge and generates a second conversion pulse smaller than a pulse width of the transmission signal, wherein the pulse conversion circuit has the first conversion pulse Input to the primary winding side of the first transformer, transmit the conversion pulse to the secondary winding side, the second conversion pulse is input to the primary winding side of the second transformer, 2 The converted pulse is transmitted to the next winding side.

Since the signal transmission device of the present invention does not malfunction even if noises with different noise levels are superimposed, a highly reliable signal transmission circuit is provided.

It is a circuit diagram which shows the signal transmission apparatus concerning Embodiment 1 of this invention. It is a block diagram which shows the 1st delay production | generation circuit concerning Embodiment 1 of this invention, and its peripheral part. It is a block diagram which shows the 2nd delay production | generation circuit concerning Embodiment 1 of this invention, and its periphery part. It is the timing chart which showed typically the signal which arises in the noise cancellation circuit concerning Embodiment 1 of this invention. 4 shows a timing chart of the transmission signal Sin, the first input signal IN11, and the second input signal IN22 according to the present invention. It is a timing chart which shows the regular signal in the signal transmission apparatus concerning this invention. 6 is a first timing chart prepared for explaining a state in which noise is canceled by a noise cancellation circuit in the signal transmission device according to the present invention. 6 is a second timing chart prepared for explaining a state in which noise is canceled by a noise cancellation circuit in the signal transmission device according to the present invention. 6 is a third timing chart prepared for explaining a state in which noise is canceled by a noise cancellation circuit in the signal transmission device according to the present invention. It is a circuit diagram which shows the signal transmission apparatus concerning Embodiment 2 of this invention. It is a circuit diagram which shows the conventional signal transmission apparatus.

(Embodiment 1)
FIG. 1 is a circuit diagram schematically showing a signal transmission device according to Embodiment 1 of the present invention. The signal transmission device 100 includes an electronic control device 110, an input side circuit 120, a transformer circuit 130, comparators CM1, CM2, CM_M1, CM_M2, a noise cancellation circuit 140, a flip-flop FF, and an output terminal 150.

In the signal transmission device 100, the electronic control unit 110 exchanges signals with, for example, a control mechanism of a hybrid vehicle, and controls the entire vehicle. In the electronic control unit 110, for example, a pulsed transmission signal Sin is generated.

The input side circuit 120 includes a first pulse conversion circuit 121, a second pulse conversion circuit 123, and an inverter 125. The transmission signal Sin generated by the electronic control unit 110 has a predetermined pulse width smaller than the pulse width of the transmission signal Sin in the first pulse conversion circuit 121 and the second pulse conversion circuit 123 constituting the input side circuit 120, respectively. Converted.

The first pulse conversion circuit 121 detects a rising edge of the transmission signal Sin and generates a first conversion pulse (not shown). The second pulse conversion circuit 123 detects the falling edge of the transmission signal Sin and generates a second conversion pulse (not shown). As described above, the pulse widths of the first conversion pulse and the second conversion pulse are set to be smaller than the pulse width of the transmission signal Sin, and the magnitude thereof is, for example, the pulse width of the transmission signal Sin is 25 μS. At this time, the first and second conversion pulses Sa1 and Sa2 are set to about 5 nS, for example. As a result, power consumption in the input side circuit 120 and the transformer circuit 130 is reduced.

The inverter 125 is prepared for detecting the falling edge of the transmission signal Sin. If the inverter 125 is prepared, the first pulse conversion circuit 121 and the second pulse conversion circuit 123 can be configured by the same circuit. Of course, the inverter 125 may be built in the second pulse conversion circuit 123 without being provided alone. The first pulse conversion circuit 121 may detect the falling edge of the transmission signal Sin, and the second pulse conversion circuit 123 may detect the rising edge.

The transformer circuit 130 includes a first transformer T1 and a second transformer T2. The transformer circuit 130 can be formed on or in an IC chip, and these transformers are sometimes referred to as microtransformers or isolators.

The first transformer T1 includes a primary winding T11 and a secondary winding T12. One end of each of the primary winding T11 and the secondary winding T12 is connected to the ground potential. One end of the primary winding T11 is connected to the first ground potential GND1, and one end of the secondary winding T12 is connected to the second ground. The potentials GND2 are connected to different ground potentials. The ground potential GND1 and the ground potential GND2 are galvanically isolated from each other. As a result, the input side circuit 120 connected to the primary winding T11 side of the first transformer T1, the noise cancel circuit 140, the flip-flop FF, etc., which will be described later, connected to the secondary winding T12 side of the first transformer T1. It is insulated from DC. Note that being galvanically insulated means that the ground potential of both is not connected by a conductor. The reason why the primary winding side and the secondary winding side of the first transformer T1 and the second transformer T2 are galvanically insulated from each other is called an isolator.

If the signal transmission rate from the primary winding side T11 to the secondary winding T12 side of the first transformer T1 is 1, and the signal delay between the two is neglected, the primary winding is on the secondary winding T12 side. A signal equivalent to the signal input to the T11 side can be extracted. Here, “equivalent” means that the amplitude and phase are substantially equal. The same applies to the second transformer T2 as the first transformer T1. That is, the signals Sa1 and Sa2, which are signals generated in the secondary windings T12 and T22, are equivalent to the first conversion pulse and the second conversion pulse described above, respectively.

Comparators CM1 and CM_M1 are connected to the secondary winding T12 side of the first transformer T1. The comparators CM1 and CM_M1 have a role of coupling the front and rear stages thereof. That is, impedance matching is performed, for example, in order to buffer a problem that occurs when the transformer circuit 130 and the noise cancellation circuit 140 are directly electrically connected. Further, if a predetermined reference potential is applied to the second input terminals of the comparators CM1 and CM_M1, waveform shaping can be performed using the reference potential as a reference. Note that the comparators CM1 and CM_M1 may have amplification means or attenuation means. Further, the signal Sa1 taken out to the secondary winding T12 side may be transmitted to the noise canceling circuit 140 with almost the same magnitude, but the amplitude of the signal may be increased or decreased.

The second conversion pulse (not shown) output from the second pulse conversion circuit 123 is input to the primary winding T21 of the second transformer T2 as described above, and the signal Sa2 is output from the secondary winding T22 side. . The signal Sa2 output from the secondary winding T22 side is input to the first input terminals of the comparator CM2 and the comparator CM_M2. Outputs from the comparators CM2 and CM_M2 are respectively input to the noise cancellation circuit 140. The comparators CM2 and CM_M2 have a role of coupling the front stage part and the rear stage part thereof. That is, impedance matching is performed, for example, in order to buffer a problem that occurs when the transformer circuit 130 and the noise cancellation circuit 140 are directly electrically connected. Further, if a predetermined reference potential is applied to the second input terminals of the comparators CM2 and CM_M2, waveform shaping can be performed using this as a reference. Note that the comparators CM2 and CM_M2 may have amplification means or attenuation means. Further, the signal Sa2 extracted to the secondary winding T22 side may be transmitted to the noise cancellation circuit 140 with almost the same size, but the amplitude of the signal may be increased or decreased.

A predetermined reference potential Vth_A for transmitting a normal signal is applied to the second input terminals of the comparators CM1 and CM2. Further, a predetermined reference potential Vth_B for noise removal is applied to the second input terminals of the comparators CM_M1 and CM_M2. A major feature of the present invention resides in providing comparators having different reference potentials Vth_A and Vth_B. The configuration of the comparator and the detailed circuit configuration will be clarified later.

Note that an amplifier and a phase shift unit may be provided on at least one side of the comparators CM1, CM_M1, CM2, and CM_M2 in order to shift the phase to a predetermined amplitude and a predetermined level.

Two signals are extracted from the noise cancellation circuit 140. One is a set signal Ps synchronized to the first transformer T1 side, and the other is a reset signal Pr synchronized to the second transformer T2 side.

The noise cancellation circuit 140 is prepared to remove noise superimposed on signals input to the comparators CM1, CM2, CM_M1, and CM_M2. Another feature of the present invention is that a noise cancellation circuit 140 is provided. The detailed circuit configuration of the noise cancellation circuit 140 will be clarified later.

The noise cancellation circuit 140 includes a first delay signal generation circuit 141a, a second delay signal generation circuit 141b, a first masking signal generation circuit 143a, a second masking signal generation circuit 143b, a first logic operation circuit unit 145a, and a second logic operation. A circuit portion 145b is provided. In the embodiment of the present invention, the first logic operation circuit unit 145a and the second logic operation circuit unit 145b are used, but the present invention is not limited to this. In addition to the negative logical sum circuit (NOR), at least one of a logical product circuit (AND), a negative logical product circuit (NAND), and a logical sum circuit (OR) can be used. These so-called logic circuits may be combined. Thus, at least one of the various logic circuits can constitute a logic operation circuit section in this document.

In this document, the term “noise masking” and the term “noise cancellation” are used. As the “noise masking” and “noise cancellation”, for example, a method of generating pseudo noise and adding or subtracting the pseudo noise to the original noise to remove or attenuate the original noise is known. However, “noise masking” used in this document refers to performing a logical operation using a logical operation circuit unit so that the original noise is not output, rather than generating pseudo noise. “Noise cancellation” is used to indicate the entire circuit composed of several noise masking circuits.

The first delay signal generation circuit 141a is prepared for delaying the first input signal IN11 output from the comparator CM1 and generating the first delay signal IN1S. Note that “delay” used in this document refers to signal processing so that at least one of a rising edge and a falling edge of a signal occurs later in time. Therefore, the pulse width is the same or small (narrow) between the signal before being “delayed” and the signal after being “delayed”. Or it can happen to be large (wide). The purpose of delaying the first input signal IN11 is simply to normally perform a logical operation with a second masking signal IN2M described later in the first logical operation circuit unit 145a. Details will be made clear later.

The first masking signal generation circuit 143a is prepared for masking the noise superimposed on the delay signal IN2S extracted from the second delay signal generation circuit 141b. That is, the first masking output signal IN1M generated by the first masking signal generation circuit 143a is generated based on the first masking input signal IN12 extracted from the comparator CM1_M1, but the generated signal is extracted from the comparator CM2. Prepared to mask the noise superimposed on the generated signal.

The second delay signal generation circuit 141b is prepared for delaying the second input signal IN21 and generating the delay signal IN2S. The purpose of delaying the second input signal IN21 is the same as that for generating the delay signal IN1S described above. That is, the second logic operation circuit 145b performs a predetermined logic operation with the first masking output signal IN1M.

The second mask signal generation circuit 143b is prepared for masking noise superimposed on the delay signal IN1S extracted from the signal generation circuit 141a. That is, the second masking signal IN2M generated by the second masking signal generation circuit 143b is generated based on the first masking input signal IN12 extracted from the comparator CM_M2, but the generated signal is extracted from the comparator CM1. It is prepared to mask the noise superimposed on the received signal.

The flip-flop FF is prepared to restore the same state as the transmission signal Sin output from the electronic control device 110. Here, “restoration” refers to restoring the original signal form and position. That is, the transmission signal Sin is subjected to signal processing with a reduced pulse width in order to reduce power consumption in the input side circuit 120 and the transformer circuit 130, but in order to finally return the signal to the original state. A flip-flop FF is prepared as a restoration circuit.

The set signal Ps is input to the set terminal S of the flip-flop FF. Thereby, the flip-flop FF is placed in the set state. The reset signal Pr is input to the reset terminal R of the flip-flop FF. As a result, the flip-flop FF is placed in the reset state.

The output signal Sout output from the flip-flop FF is taken out to the output terminal 150. The output signal Sout taken out to the output terminal 150 is used for controlling on / off of an IGBT (not shown), for example.

FIG. 2A shows the internal circuit of the first delay signal generation circuit 141a shown in FIG. 1, and the peripheral circuit portion is extracted. That is, the first masking circuit unit 140A includes a first delay signal generation circuit 141a, a second masking signal generation circuit 143b, and a first logic operation circuit unit 145a.

The first input signal IN11 extracted from the comparator CM1 is input to the first input terminal x1 of the NAND circuit 149a that forms part of the first delay signal generation circuit 141a, and is also input to the signal delay circuit 147a. The The delayed signal IN1D is extracted from the signal delay circuit 147a, and the extracted delayed signal IN1D is input to the second input terminal x2 of the NAND circuit 149a.

A delay signal IN1S obtained by performing a NAND operation on the first input signal IN11 and the delay signal IN1D is output to the output terminal x3 of the NAND circuit 149a.

The first logic operation circuit unit 145a has two input terminals. The delay signal IN1S is input to the first input terminal y1, and the second masking signal IN2M is input to the second input terminal y2. The second masking signal IN2M is generated by the second masking signal generation circuit 143b. When the first input signal IN11 and the first masking input signal IN21 are input at the same timing, the second masking signal IN2M has a predetermined phase difference between the delayed signal IN1S and the second masking signal IN2M.

The first logic operation circuit unit 145a performs a negative OR operation between the delay signal IN1S and the second masking signal IN2M, and a high level appears at the output terminal y3 only when both signals are at a low level. Therefore, the first conversion pulse Sa1 extracted from the first pulse conversion circuit 121 is extracted via the first transformer T1, the comparators CM1 and CM_M1, the first delay signal generation circuit 141a, and the first logic operation circuit unit 145a. The delay signal IN1S is restricted by the second masking signal IN2M generated through the second pulse conversion circuit 123, the second transformer T2, the comparator CM_M2, and the second masking signal generation circuit 143b. That is, during the period in which the second masking signal IN2M is at a high level, the noise component superimposed on the delay signal IN1S is masked by the first logic operation circuit unit 145a.

The set signal Ps output from the first logic operation circuit unit 145a is input to the set terminal S of the flip-flop FF to set the subsequent flip-flop FF.

The second noise masking circuit unit 140B shown in FIG. 2B constitutes the noise cancellation circuit 140 in cooperation with the first masking circuit unit 140A shown in FIG. 2A.

FIG. 2B shows the inside of the second delay signal generation circuit 141b and its peripheral circuit portion. That is, the second masking circuit unit 140B includes a second delay signal generation circuit 141b, a first masking signal generation circuit 143a, and a second logic operation circuit unit 145b.

The second input signal IN22 extracted from the comparator CM2 is input to the first input terminal x1 of the NAND circuit 149b and input to the signal delay circuit 147b. The delay signal IN2D extracted from the signal delay circuit 147b. Is input to the second input terminal x2 of the AND circuit 149b.

The output terminal x3 of the AND circuit 149b outputs a delay signal IN2S obtained by performing a NAND operation on the second input signal IN22 and the delay signal IN2D.

The second logic operation circuit unit 145b is provided with two input terminals. The delay signal IN2S is input to the first input terminal y1, and the first masking signal IN1M is input to the second input terminal y2. The first masking signal IN1M is generated by the mask first masking signal generation circuit 143a. When the first input signal IN12 and the second masking input signal IN22 are input at the same timing, the first masking signal IN1M has a predetermined phase difference between the delayed signal IN2S and the first masking signal IN1M.

The second logic operation circuit unit 145b performs a negative OR operation on the delay signal IN2S and the first masking signal IN1M, and only when both signals are at a low level, a high level appears at the output. Therefore, the second conversion pulse Sa2 extracted from the second pulse conversion circuit 123 is extracted via the second transformer T2, the comparators CM2 and CM_M2, the second delay signal generation circuit 141b, and the second logic operation circuit unit 145b. The delay signal IN2S is restricted by the first masking signal IN1M generated through the first pulse conversion circuit 121, the first transformer T1, the comparator CM_M2, and the first masking signal generation circuit 143a. That is, during the period when the first masking signal IN1M is at a high level, the noise superimposed on the delay signal IN2S is not output to the second logic operation circuit unit 145b. This is why it is called a noise cancellation circuit.

The reset signal Pr output from the output terminal y3 of the second logic operation circuit unit 145b is input to the reset terminal R of the flip-flop FF to reset the flip-flop FF.

As described above, the noise cancellation circuit 140 includes the first masking circuit unit 140A and the second masking circuit unit 140B.

FIG. 3 schematically shows various signals generated in the first and second masking circuit units 140A and 140B shown in FIGS. 2A and 2B. The first input signal IN11 and the second input signal IN22 are input to the first input terminal x1 of the AND circuits 149a and 149b, respectively. The first masking input signal IN12 and the first masking input signal IN21 are signals input to the first masking signal generation circuit 143a and the second masking signal generation circuit 143b, respectively. Delay signals IN1S and IN2S are output from AND circuits 149a and 149b, respectively, and first masking signal IN1M and second masking signal IN2M are output from first masking signal generation circuit 143a and second masking signal generation circuit 143b, respectively. The

FIG. 3 shows the top row. As described above, the first input signal IN11, the second input signal IN22, the first masking input signal IN12, and the first masking input signal IN21 are output from the comparator CM1, the comparator CM2, the comparator CM_M1, and the comparator CM_M2, respectively. It is a signal, and its pulse width W1 is selected to be about 5 ns, for example. The size of the pulse width W1 is a design matter and depends on the frequency and pulse width of the transmission signal Sin, and the electrical characteristics of the first pulse conversion circuit 121, the second pulse conversion circuit 123, the first transformer T1, and the second transformer T2. Is set as appropriate. The first input signal IN1 and the second input signal IN2 have a rising edge Tr1 and a falling edge Tf1, respectively.

The delay signals IN1D and IN2D are taken out from the signal delay circuits 147a and 147b shown in FIGS. 2A and 2B, respectively, and they are obtained from the first input signal IN11 and the second input signal IN22 by a predetermined delay time Δt1. The pulse width W2 is set to be equal to or greater than the pulse width W1. The delay signals IN1D and IN2D have a rising edge Tr2 and a falling edge Tf2, respectively. The rising edge Tr2 is delayed by a time Δt1 from the rising edge Tr1 of the first input signal IN1 and the second input signal IN2, and falls. The edge Tf2 shows a state delayed by the time Δt2 from the falling edge Tf1. Note that FIG. 3 illustrates the case where the time Δt2 is larger than the time Δt1 for the sake of drawing, but the setting of the magnitude relationship between the two is merely a design matter. Therefore, the time Δt1 and Δt2 may be set to be substantially equal, the time Δt1 may be larger than Δt2, or the time Δt1 may be smaller than Δt2.

In other words, the magnitudes of the times Δt1 and Δt2 may be set so that noise superimposed on the first input signal IN11 and the second input signal IN22 is appropriately masked.

The delay signal IN1S is a signal generated by performing an AND operation on the first input signal IN1 and the delay signal IN1D in the AND circuit 149a. The delay signal IN2S is a signal generated by performing an AND operation on the second input signal IN2 and the delay signal IN2D in the AND circuit 149b. Therefore, the delay signals IN1S and IN2S are at the high level when the first input signal IN11, the second input signal IN22, and the delay signals IN1D and IN2D are at the high level. , IN2D becomes a low level at the rising timing Tr2, and becomes a high level at the falling timing Tf1 of the first input signal IN1 and the second input signal IN2. The pulse width W3 is smaller (narrower), for example, by about 3 ns than the pulse widths W1 and W2.

The first masking signal IN1M and the second masking signal IN2M are generated by the first masking signal generation circuit 143a and the second masking signal generation circuit 143b based on the first masking input signal IN21 and the second masking input signal IN22, respectively. . The pulse width W4 of these signals is larger than the pulse widths W1 to W3, and is selected to be, for example, 7 to 10 ns. In other words, the times Δt1 and Δt2 are adjusted so that the pulse width W4 is set to such a magnitude. The pulse width W4 of the first masking signal IN1M and the second masking signal IN2M is sufficiently large so that the logical product operation is not hindered even if the rising timing Tr3 and falling timing Tf3 of the delay signals IN1S and IN2S vary. Set to (width). In addition, when performing the logical product operation in the first logic operation circuit unit 145a and the second logic operation circuit unit 145b, the first input signal IN11, the second input are used as target signals of the second masking signal IN2M and the first masking signal IN1M. The reason why the delay signals IN1S and IN2S are used instead of the signal IN22 and the delay signals IN1D and IN2D is to perform the AND operation in the first logic operation circuit unit 145a and the second logic operation circuit unit 145b without any trouble. is there.

Note that the periods indicated by the pulse widths W1, W2, W3, and W4 of the various signals shown in FIG. 3 are effective portions of these various signals, and the logic depends on whether these effective portions are high level or low level. A product operation is performed. The effective portion of various signals refers to a signal portion where the signal itself exists, and does not necessarily specify a high level and does not specify a low level. Therefore, the signal effective part becomes a high level or a low level depending on the circuit configuration.

The concept of the noise cancellation circuit 140 shown in FIGS. 2A, 2B, 3 and 4 is summarized as follows. That is, the noise cancellation circuit 140 according to the present invention generates the delay signals IN1D and IN2D separately based on the signals of the two first input signals IN11 and second input signal IN22. Further, a first masking signal IN1M and a second masking signal IN2M are generated based on the second input signal IN22, the first masking input signal IN12, and the first masking input signal IN21, respectively. When the first input signal IN11 and the second input signal IN22 are input at the same timing, the delay times Δt1 and Δt2 so that the effective signal portion of the delay signal IN2S is accommodated in the effective signal portion of the first masking signal IN1M. Adjust. Further, the delay times Δt1 and Δt2 are adjusted so that the effective signal portion of the delay signal IN1S is accommodated in the effective signal portion of the second masking signal IN2M.

FIG. 4 shows the phase relationship between the transmission signal Sin generated by the electronic control unit 110 in FIG. 1 and the first input signal IN11 and the second input signal IN22 extracted from the first transformer T1 and second transformer T2 sides. It is a timing chart which shows typically.

For convenience of explanation and drawing, the transmission signal Sin shown in FIG. 4A represents a pulse-like signal, for example, a signal having a rising edge Tr, a falling edge Tf, and a duty ratio of 50%.

As is clear from the above description, the first input signal IN11 shown in FIG. 4B is taken out from the first transformer T1 side, and detects the rising edge Tr of the transmission signal Sin to obtain a predetermined value. The signal is adjusted to the pulse width W1.

The second input signal IN22 shown in FIG. 4C is an input signal extracted from the second transformer T2 side as apparent from the above description, and detects the falling edge Tf of the transmission signal Sin. , A signal adjusted to a predetermined pulse width. The pulse width W1 of the second input signal IN2 is the same as the pulse width W1 of the first input signal IN1.

The first input signal IN11 and the second input signal IN22 are obtained by detecting the rising edge Tr and the falling edge Tf of the transmission signal Sin. In the final stage of the signal transmission device of the present invention, these input signals are used as the basis. Thus, the original transmission signal Sin is restored.

In FIG. 4B, a signal section in which the first input signal IN11 and the first masking input signal IN12 appear is indicated by a section P1, and a signal section in which the second masking input signal IN21 and the second input signal IN22 appear is indicated by a section P2. . That is, the area P1 is a signal portion where the first input signal IN11 and the first masking input signal IN12 appear but the second masking input signal IN21 and the second input signal IN22 do not appear, and the area P2 is the second masking input signal. A signal portion in which IN21 and the second input signal IN22 appear but the first input signal IN11 and the first masking input signal IN12 do not appear is shown.

FIG. 5 is a timing chart of various signals in the main part of the signal transmission device shown in FIG.

FIG. 5A shows the transmission signal Sin generated by the electronic control unit 110. The transmission signal Sin is shown as maintaining a high level during the period from time t1 to time t5. That is, the period from the rising edge Tr0 to the falling edge Tf0 is shown as being at a high level.

FIG. 5B shows a signal Sa1 that is a signal before and after the transformer T1. The signal Sa1 is a signal that is generated by the first pulse conversion circuit 121 upon detection of the rising edge Tr0 of the transmission signal Sin and is output through the first transformer T1. The signal Sa1 is further extracted as the first input signal IN11 or the first masking input signal IN22 via the comparator CM1 or the comparator CM_M1. For example, the signal Sa1 is shown as a rising edge Tr1, a falling edge Tf1, and a pulse width W1 in the period from time t1 to time t3. Note that the signal Sa1 is considered to be substantially equivalent before and after the transformer T1.

The signal Sa1 is extracted as IN11 or IN12 through the comparator CM1 or the comparator CM_M1. At this time, the reference potential Vth_A is set in the comparator CM1, and the reference potential Vth_B is set in the comparator CM_M1.

The reference potential Vth_A is prepared for discriminating a regular signal, and the reference potential Vth_B is prepared for noise masking. At this time, the absolute values of the reference potential Vth_A and the reference potential Vth_B are | Vth_A |> | Vth_B |. Furthermore, the reference potential Vth_B is preferably selected to be, for example, 99.9% or less of the size of the reference potential Vth_A, more preferably 95% or less. It may be selected so that it is preferably 90% or less. The comparator CM1 outputs a high level as the signal IN11 when the voltage of the signal Sa1 is equal to or higher than the reference potential Vth_A. The comparator CM_M1 outputs a high level as the signal IN12 when the voltage of the signal Sa1 is equal to or higher than the reference potential Vth_B. Each comparator outputs a low level when a signal less than the reference potential of each comparator is input.

FIG. 5C shows a signal Sa2 that is a signal before and after the transformer T2. The signal Sa2 is a signal that is generated by the second pulse conversion circuit 123 upon detection of the falling edge Tf0 of the transmission signal Sin and is output through the second transformer T2. The signal Sa2 is further extracted via the comparator CM2 or the comparator CM_M2. For example, in the period from time t5 to time t7, the signal Sa2 is a regular signal represented by a rising edge Tr2, a falling edge Tf2, and a pulse width W1.

The signal Sa2 is further extracted as IN22 or IN12 via the comparator CM2 or the comparator CM_M2. At this time, the reference potential Vth_A is set in the comparator CM1, and the reference potential Vth_B is set in the comparator CM_M1.

As described above, the reference potential Vth_A is prepared for discriminating a normal signal, and the reference potential Vth_B is prepared for noise masking. The comparator CM2 outputs a high level as the signal IN2 when the voltage of the signal Sa2 is equal to or higher than the reference potential Vth_A. The comparator CM_M2 outputs a high level as the signal IN21 when the voltage of the signal Sa2 is equal to or higher than the reference potential Vth_B. Each comparator outputs a low level when a signal less than the reference potential of each comparator is input.

FIG. 5D shows the delay signal IN1S extracted from the first delay signal circuit 141a. The first delay signal IN1S is generated from the signal Sa1, but since it is delayed by the first delay signal circuit 141a, it becomes low level at the rising timing of the delay signal IN1D (not shown in FIG. 5) as described in FIG. The signal Sa1 becomes high level at the falling timing. The pulse width is smaller (narrower) than the pulse width of the signal Sa1 and the delay signal IN1D not shown in FIG.

FIG. 5E shows the second masking signal IN2M extracted from the second masking signal generation circuit 143b. The second masking signal IN2M occurs at the same timing as the rising edge Tr1 of the signal Sa2, that is, at time t1. The falling edge Tf1 side of the signal Sa2 indicates a delayed signal. The second masking signal IN2M transitions from the low level to the high level at the time t1, and the high level continues until the time t4. The pulse width W3 is set to be larger than the pulse width W1 of the signals Sa1 and Sa2. ing.

FIG. 5F shows the second masking signal IN1M extracted from the first masking signal generation circuit 143a. The first masking signal IN1M occurs at substantially the same timing as the rising edge Tr1 of the signal Sa1, that is, t1. The first masking signal IN1M transitions from the low level to the high level at time t1, and continues to the high level until time t4, and the pulse width W3 is set to be larger than the pulse width W1 of the signals Sa1 and Sa2. ing.

FIG. 5G shows the delay signal IN2S extracted from the second delay signal circuit 141b. The delay signal IN2S is generated from the signal Sa2, but is delayed by the delay signal circuit 141b. Therefore, as described in FIG. 3, the delay signal IN2S becomes low level at the rising timing of the delay signal IN1D not shown in FIG. It becomes high level at the falling timing. The pulse width is smaller (narrower) than the pulse width of the signal Sa2 and the delay signal IN2D (not shown in FIG. 5).

FIG. 5H shows the set signal Ps. The set signal Ps is output when the signal Sa1 is at a high level, the delay signal IN1S is at a low level, and the second masking signal IN2M is at a low level. Therefore, since the set signal Ps is output between the times t2 and t3, the flip-flop FF is set from the low level to the high level at the time t2.

FIG. 5 (i) shows the reset signal Pr. The reset signal Ps is output when the signal Sa2 is at a high level, the delay signal IN2S is at a low level, and the first masking signal IN1M is at a low level. Therefore, the reset signal Pr is output between the times t6 and t7, and the flip-flop FF is reset from the high level to the low level at the time t6.

FIG. 5 (j) shows the output signal Sout output from the output Q of the flip-flop FF, that is, the output terminal 150. The output Q of the flip-flop FF is set by the set signal Ps output from the first logic operation circuit unit 145a, and is reset by the reset signal Pr output from the second logic operation circuit unit 145b.

FIG. 6A schematically shows a state in which noises N1 and N2 superimposed on the signals Sa1 and Sa2 are applied in the same phase.

FIG. 6A (a) shows a transmission signal Sin generated by the electronic control unit 110. FIG. Since the normal signal is not generated now, the transmission signal Sin is always at the low level.

FIG. 6A (b) shows the noise N1 superimposed on the signal Sa1. The noise N1 is shown as rising at time t1 and falling at time t4. That is, the noise N1 indicates a state of being superimposed in the signal Sa1 between times t1 and t3.

The noise superimposed on the signal Sa1 is extracted as the first input signal IN11 or the first masking input signal IN12 via the comparator CM1 or the comparator CM_M1. At this time, the reference potential Vth_A is set in the comparator CM1, and the reference potential Vth_B is set in the comparator CM_M1.

As described above, the reference potential Vth_A is prepared for discriminating a normal signal, and the reference potential Vth_B is prepared for noise masking. The comparator CM1 sets the first input signal IN11 to the high level when the voltage of the signal Sa1 is equal to or higher than the reference potential Vth_A. The comparator CM_M1 sets the first masking input signal IN12 to a high level when the voltage of the signal Sa1 is equal to or higher than the reference potential Vth_B. Each comparator outputs a low level signal when a signal less than the reference potential of each comparator is input. Note that the timing of the signal output from each comparator is the same as that of the signal Sa1.

FIG. 6A (c) shows the noise N2 superimposed on the signal Sa2. The noise N2 is shown as occurring at the same timing as the noise N1. That is, no phase difference is generated between the noise N2 and the noise N1.

The noise superimposed on the signal Sa2 is extracted as the second input signal IN21 or the second masking input signal IN22 via the comparator CM2 or the comparator CM_M2. At this time, the reference potential Vth_A is set in the comparator CM2, and the reference potential Vth_B is set in the comparator CM_M2.

As described above, the reference potential Vth_A is prepared for discriminating a normal signal, and the reference potential Vth_B is prepared for noise masking. The comparator CM2 sets the second input signal IN21 to the high level when the voltage of the signal Sa2 is equal to or higher than the reference potential Vth_A. The comparator CM_M2 sets the second masking input signal IN22 to the high level when the voltage of the signal Sa2 is equal to or higher than the reference potential Vth_B. Each comparator outputs a low level when a signal less than the reference potential of each comparator is input. Note that the timing of the signal output from each comparator is the same as that of the signal Sa2.

FIG. 6A (d) shows noise N3 superimposed on the delay signal IN1S extracted from the first delay signal generation circuit 141a. The first delay signal IN1S is generated from the signal Sa1, but since it is delayed by the first delay signal circuit 141a, as described in FIG. 3, the first delay signal IN1S becomes low level at the rising timing of the delay signal IN1D not shown in FIG. 6A. The signal Sa1 becomes high level at the falling timing. The pulse width is smaller (narrower) than the pulse width of the signal Sa1 and the delay signal IN1D (not shown in FIG. 6A). Therefore, the noise N3 superimposed on the delay signal IN1S changes from the high level to the low level at time t3, and changes from the low level to the high level at time t4.

FIG. 6A (e) shows the noise N4 superimposed on the second masking signal IN2M extracted from the second masking signal generation circuit 143b. Since the level of the second masking signal IN2M changes at the same timing as the rising edge of the signal Sa2, the second masking signal IN2M changes from the low level to the high level at time t1. At time t6, the high level is changed to the low level. The second masking signal IN2M is a signal obtained by delaying the falling edge side of the signal Sa2. Therefore, the noise N4 is delayed from the falling edge side of the noise N2.

FIG. 6A (f) shows noise N5 superimposed on the first masking signal IN1M extracted by the first masking signal generation circuit 143a. The first masking signal IN1M transitions from the high level to the low level at time t1, and transitions from the low level to the high level at time t6. The first masking signal IN1M is a signal obtained by delaying the falling edge side of the first input signal IN1. Therefore, the noise N5 is delayed from the falling edge side of the noise N1.

FIG. 6A (g) shows the noise N6 superimposed on the delay signal IN2S extracted from the second delay signal generation circuit 141b. The second delay signal IN2S is generated from the signal Sa2, but is delayed by the signal delay circuit 147b. Therefore, as described in FIG. 3, the second delay signal IN2S becomes low level at the rising timing of the delay signal IN2D (not shown in FIG. 6A). It becomes high level at the falling timing of Sa2. The pulse width is smaller (narrower) than the pulse width of the signal Sa2 and the delay signal IN2D (not shown in FIG. 6A). Therefore, the noise N6 superimposed on the delay signal IN1S changes from the high level to the low level at time t3, and changes from the low level to the high level at time t4.

6A (h) shows the output signal Sout output from the output Q of the flip-flop FF, that is, the output terminal 150. FIG. The output Q of the flip-flop FF is set by the set signal Ps output from the first logic operation circuit unit 145a, and the signal reset by the reset signal Pr output from the second logic operation circuit unit 145b is output.

The set signal Ps (not shown in FIG. 6A) is output when the signal Sa1 is at a high level, the delay signal IN1S is at a low level, and the second masking signal IN2M is at a low level. That is, the superimposed noise appears when the noise N1 is at a high level, N3 is at a low level, and N4 is at a low level. The period during which the noise N3 is at the low level is from time t3 to t4. However, since the noise N4 is at the high level during this period, no noise appears in the set signal Ps. That is, since the noises N1 and N3 are masked by the noise N4, the set signal Ps remains at a low level. Therefore, the flip-flop FF is not set and does not operate.

The reset signal Pr (not shown in FIG. 6A) is output when the signal Sa2 is at a high level, the delay signal IN2S is at a low level, and the first masking signal IN2M is at a low level. That is, the superimposed noise appears when the noise N2 is at a high level, N5 is at a low level, and N6 is at a low level. The period during which the noise N5 is at the low level is from time t3 to t4. However, since the noise N4 is at the high level during this period, no noise appears in the set signal Ps. That is, since the noises N2 and N6 are masked by the noise N5, the set signal Ps remains at a low level. Therefore, the flip-flop FF is not set and does not operate.

When both the set signal Ps and the reset signal Pr are not output, that is, when both are at the high level or the low level, the output of the flip-flop FF, that is, the output signal Sout output from the output terminal 150 is at the low level. A low level is output over this period, and no noise is output, so that a noise canceling effect is achieved.

FIG. 6B schematically shows a state in which a phase difference occurs in the noises N1 and N2 superimposed on the signals Sa1 and Sa2, respectively. Note that the noise N1 superimposed on the signal Sa1 and the noise N2 superimposed on the signal Sa2 are generated at the same timing in FIG. 6A described above. Accordingly, the noise cancellation performance shown in FIG. 6B is required to be higher than that shown in FIG. 6A because there is a phase difference between the noise N1 and the noise N2.

FIG. 6B (a) shows the transmission signal Sin generated by the electronic control unit 110. FIG. Since the normal signal is not generated now, the transmission signal Sin is always at the low level.

FIG. 6B (b) shows the noise N1 superimposed on the signal Sa1. The noise N1 is shown as rising at time t1 and falling at time t4. That is, the noise N1 is superimposed between the times t1 and t4 in the signal Sa1.

The noise superimposed on the signal Sa1 is extracted as the first input signal IN11 or the first masking input signal IN12 via the comparator CM1 or the comparator CM_M1. At this time, the reference potential Vth_A is set in the comparator CM1, and the reference potential Vth_B is set in the comparator CM_M1.

As described above, the reference potential Vth_A is prepared for discriminating a normal signal, and the reference potential Vth_B is prepared for noise masking. The comparator CM1 sets the first input signal IN11 to the high level when the voltage of the signal Sa1 is equal to or higher than the reference potential Vth_A. The comparator CM_M1 sets the first masking input signal IN12 to a high level when the voltage of the signal Sa1 is equal to or higher than the reference potential Vth_B. Each comparator outputs a low level signal when a signal less than the reference potential of each comparator is input. Note that the timing of the signal output from each comparator is the same as that of the signal Sa1.

FIG. 6B (c) shows the noise N2 superimposed on the signal Sa2. Noise N2 rises at time t3 and falls at time t6. Accordingly, the noise N2 is delayed from the noise N1 by the time (t3-t1).

The noise superimposed on the signal Sa2 is extracted as the second input signal IN21 or the second masking input signal IN22 via the comparator CM2 or the comparator CM_M2. At this time, the reference potential Vth_A is set in the comparator CM2, and the reference potential Vth_B is set in the comparator CM_M2.

As described above, the reference potential Vth_A is prepared for discriminating a normal signal, and the reference potential Vth_B is prepared for noise masking. The comparator CM_M2 sets the second masking input signal IN22 to the high level when the voltage of the signal Sa2 is equal to or higher than the reference potential Vth_B. Each comparator outputs a low level signal when a signal less than the reference potential of each comparator is input. Note that the timing of the signal output from each comparator is the same as that of the signal Sa2.

FIG. 6B (d) shows the noise N3 superimposed on the delay signal IN1S extracted from the first delay signal generation circuit 141a. The first delay signal IN1S is generated from the signal Sa1, but is delayed by the signal delay circuit 147a. Therefore, as described in FIG. 3, the first delay signal IN1S becomes low level at the rising timing of the delay signal IN1D not shown in FIG. It becomes high level at the falling timing of Sa1. The pulse width is smaller (narrower) than the pulse width of the signal Sa1 and the delay signal IN1D (not shown in FIG. 6B). Therefore, the noise N3 superimposed on the delay signal IN1S changes from the high level to the low level at time t3, and changes from the low level to the high level at time t4.

FIG. 6B (e) shows the noise N4 superimposed on the second masking signal IN2M extracted from the second masking signal generation circuit 143b. Since the noise N4 occurs at the rising timing of the noise N2 shown in FIG. 6B (b), it transitions from the low level to the high level at time t3, and transitions from the high level to the low level at time t8. The second masking signal IN2M is a signal obtained by delaying the falling edge side of the signal Sa2. That is, the fall of the signal Sa2 is at time t6, while the fall of the first masking signal IN1M is at a later time t7.

FIG. 6B (f) shows noise N5 superimposed on the first masking signal IN1M extracted by the first masking signal generation circuit 143a. Noise N5 is equivalent to that shown in FIG. 6A (f), and transitions from a low level to a high level at time t1, and from a high level to a low level at time t6.

FIG. 6B (g) shows the noise N6 superimposed on the delay signal IN2S extracted from the second delay signal generation circuit 141b. The second delay signal IN2S is generated from the signal Sa2, but is delayed by the signal delay circuit 147b. Therefore, as described in FIG. 3, the second delay signal IN2S becomes low level at the rising timing of the delay signal IN2D not shown in FIG. It becomes high level at the falling timing of Sa2. The pulse width is smaller (narrower) than the pulse width of the signal Sa2 and the delay signal IN2D (not shown in FIG. 6B). Therefore, the noise N6 superimposed on the delay signal IN1S changes from the high level to the low level at time t5, and changes from the low level to the high level at time t6.

FIG. 6B (h) shows the output signal Sout output from the output Q of the flip-flop FF, that is, the output terminal 150. The output Q of the flip-flop FF is set by the set signal Ps output from the first logic operation circuit unit 145a, and the signal reset by the reset signal Pr output from the second logic operation circuit unit 145b is output.

The set signal Ps not shown in FIG. 6B is output when the signal Sa1 is at a high level, the delay signal IN1S is at a low level, and the second masking signal IN2M is at a low level. That is, the superimposed noise appears when the noise N1 is at a high level, N3 is at a low level, and N4 is at a low level. The period during which the noise N3 is at the low level is from time t3 to t4. However, since the noise N4 is at the high level during this period, no noise appears in the set signal Ps. That is, since the noises N1 and N3 are masked by the noise N4, the set signal Ps remains at a low level. Therefore, the flip-flop FF is not set and does not operate.

The reset signal Pr (not shown in FIG. 6B) is output when the signal Sa2 is at a high level, the delay signal IN2S is at a low level, and the second masking signal IN2M is at a low level. That is, the superimposed noise appears when the noise N2 is at a high level, N5 is at a low level, and N6 is at a low level. The period during which the noise N6 is at the low level is from time t5 to t6. Since the noise N5 is at the high level during this period, no noise appears in the set signal Ps. That is, since the noises N2 and N6 are masked by the noise N5, the set signal Ps remains at a low level. Therefore, the flip-flop FF is not set and does not operate.

When both the set signal Ps and the reset signal Pr are not output, that is, when both are at the high level or the low level, the output of the flip-flop FF, that is, the output signal Sout output from the output terminal 150 is at the low level. A low level is output over this period, and no noise is output, so that a noise canceling effect is achieved.

FIG. 7 shows a case where noises N1 and N2 superimposed on the signals Sa1 and Sa2 are applied in the same phase, and the respective noise levels are different.

FIG. 7A shows the transmission signal Sin generated by the electronic control unit 110. Since the normal signal is not generated now, the transmission signal Sin is always at the low level.

FIG. 7B shows the noise N1 superimposed on the signal Sa1. The noise N1 is shown as rising at time t1 and falling at time t4. That is, the noise N1 indicates a state of being superimposed in the signal Sa1 between times t1 and t3.

FIG. 7C shows the noise N2 superimposed on the signal Sa2. The noise N2 is generated at the same timing as the noise N1, but the signal intensity, that is, the noise level is different. In the figure, the noise N2 is applied as a value smaller than the reference voltage Vth_A and larger than the reference voltage Vth_B. When this noise level is input to each comparator, the comparators CM1 and CM2 output a low level, but the comparators CM_1 and CM_M2 output a high level.

FIG. 7D shows noise N3 superimposed on the delay signal IN1S extracted from the first delay signal generation circuit 141a. The first delay signal IN1S is generated from the signal Sa1, but since it is delayed by the first delay signal circuit 141a, it becomes low level at the rising timing of the delay signal IN1D not shown in FIG. 7 as described in FIG. The signal Sa1 becomes high level at the falling timing. The pulse width is smaller (narrower) than the pulse width of the signal Sa1 and the delay signal IN1D not shown in FIG. Therefore, the noise N3 superimposed on the delay signal IN1S changes from the high level to the low level at time t3, and changes from the low level to the high level at time t4.

FIG. 7E shows noise N4 superimposed on the second masking signal IN2M extracted from the second masking signal generation circuit 143b. Since the noise N2 is larger than the reference voltage Vth_B, the comparator CM_M2 outputs the second masking input signal IN21 as a high level, and the second masking signal generation circuit 143b receives the second masking input signal IN21 as a high level. Since the level of the second masking signal IN2M changes at the same timing as the rising edge of the signal Sa2, the second masking signal IN2M changes from the low level to the high level at time t1. At time t6, the high level is changed to the low level. The second masking signal IN2M is a signal obtained by delaying the falling edge side of the signal Sa2. Therefore, the noise N4 is delayed from the falling edge side of the noise N2.

FIG. 7F shows the noise N5 superimposed on the first masking signal IN1M extracted by the first masking signal generation circuit 143a. The first masking signal IN1M transitions from the high level to the low level at time t1, and transitions from the low level to the high level at time t6. The first masking signal IN1M is a signal obtained by delaying the falling edge side of the first input signal IN1. Therefore, the noise N5 is delayed from the falling edge side of the noise N1.

FIG. 7G shows noise N6 superimposed on the delay signal IN2S extracted from the second delay signal generation circuit 141b. The second delay signal IN2S is generated from the signal Sa2, but since the noise level of the noise N2 is smaller than the reference voltage Vth_A of the comparator CM1, a low level is output to the second input signal IN22, and therefore the delay signal IN2S. The high level is maintained.

FIG. 7H shows the output Q of the flip-flop FF, that is, the output signal Sout output from the output terminal 150. The output Q of the flip-flop FF is set by the set signal Ps output from the first logic operation circuit unit 145a, and the signal reset by the reset signal Pr output from the second logic operation circuit unit 145b is output.

The set signal Ps not shown in FIG. 7 is output when the signal Sa1 is at a high level, the delay signal IN1S is at a low level, and the second masking signal IN2M is at a low level. That is, the superimposed noise appears when the noise N1 is at a high level, the noise N3 is at a low level, and the noise N4 is at a low level. The period during which the noise N3 is at the low level is from time t3 to t4. However, since the noise N4 is at the high level during this period, no noise appears in the set signal Ps. That is, since the noises N1 and N3 are masked by the noise N4, the set signal Ps remains at a low level. Therefore, the flip-flop FF is not set and does not operate.

The reset signal Pr (not shown in FIG. 7) is output when the signal Sa2 is at a high level, the delay signal IN2S is at a low level, and the first masking signal IN2M is at a low level. That is, the superimposed noise appears when the noise N2 is high level, the noise N5 is low level, and the noise N6 is low level. There is no period when the noise N6 is at a low level, and no noise appears in the set signal Ps.

When both the set signal Ps and the reset signal Pr are not output, that is, when both are at the high level or the low level, the output of the flip-flop FF, that is, the output signal Sout output from the output terminal 150 is at the low level. A low level is output over this period, and no noise is output, so that a noise canceling effect is achieved.

As described above, FIG. 6A illustrates the circuit operation of the noise cancellation circuit 140 when the noise superimposed on the signals Sa1 and Sa2 is completely in phase, that is, common noise. In the case of common noise, it was found that the noise cancellation circuit 140 operates normally.

FIG. 6B illustrates the circuit operation of the noise cancellation circuit 140 when a phase difference is generated in the noise superimposed on the signals Sa1 and Sa2. Even when a phase difference occurs between the two, if it is within the design range, it has been found that the noise cancellation circuit 140 operates normally in the same manner as shown in FIG. 6A.

As described above, even when a phase shift occurs between the application states of the noise N1 and the noise N2, the noise can be masked normally if the shift is within a predetermined range of the design (for example, the phase difference 1w). Further, when optimizing the phase difference 1w from the viewpoint of operation delay and noise resistance characteristics, the phase difference 1w can be implemented relatively easily only by changing the combination of the buffer and the inverter without changing the circuit configuration itself.

In summary, the noise cancellation circuit 140 according to the present invention generates first and second delay signals based on two input signals, respectively. Further, first and second masking signals are generated based on the input signal. Each delay time is adjusted so that the effective portion of the second delay signal is contained in the effective signal portion of the first masking signal. Further, each delay time is subjected to a logical operation process by an OR circuit negating logic circuit so that the effective part of the first delay signal fits in the effective signal part of the second masking signal.

Further, as a major feature of the present invention, FIG. 7 illustrates the circuit operation of the noise cancellation circuit 140 when the noise levels of the noises superimposed on the signals Sa1 and Sa2 are different. Comparators for shaping and transmitting each signal are provided with a reference potential Vth_A for transmitting a normal signal and a reference voltage Vth_B for noise cancellation. By appropriately selecting these reference potential values, a masking signal can be generated even when there is a difference between the noise levels of the signals Sa1 and Sa2. Can be masked.

The example shown in FIG. 7 shows a case where the noise level of the noise N2 is lower than the noise level of the noise N1, but conversely, when the noise level of the noise N1 is lower than the noise level of the noise N2, It is clear that the configuration of the present invention is also effective even when the noise levels of the noise level N1 and the noise level N2 are different and the phases are different, that is, in the case corresponding to FIG. 6B.

(Embodiment 2)
FIG. 8 is a circuit diagram showing a signal transmission device according to the second embodiment of the present invention. In the second embodiment, the comparator is configured by a hysteresis comparator.

A hysteresis comparator CM1_H is connected to the secondary winding T12 side of the first transformer T1. The hysteresis comparator CM1_H has a role of coupling the front stage part and the rear stage part thereof. That is, impedance matching is performed, for example, in order to buffer a problem that occurs when the transformer circuit 130 and the noise cancellation circuit 140 are directly electrically connected. The hysteresis comparator CM1_H has a predetermined hysteresis width and two threshold voltages corresponding to the hysteresis width. The hysteresis comparator CM1_H may have an amplifying unit or an attenuating unit. Further, the signal Sa1 taken out to the secondary winding T12 side may be transmitted to the noise canceling circuit 140 with almost the same magnitude, but the amplitude of the signal may be increased or decreased.

A hysteresis comparator CM2_H is connected to the secondary winding T22 side of the second transformer T2. Since the role of the hysteresis comparator CM2_H is the same as that of the hysteresis comparator CM_M1 described above and is redundant, detailed description thereof is omitted.

Since the hysteresis comparators CM_H1 and CM_H2 have two threshold voltages for the input signal, the respective threshold voltages can be regarded in the same manner as the reference voltages Vth_A and Vth_B described above. Therefore, the effects of the present invention described so far can also be exhibited by replacing the comparator with a hysteresis comparator as in the present embodiment.

Further, since the hysteresis comparator has two threshold voltages in one comparator, the number of comparators is reduced as compared with the first embodiment in which two threshold voltages, that is, reference potentials are prepared using two comparators. There is an advantage that can be.

The comparators CM1, CM_M1, CM2, and CM_M2 may be configured by window comparators.

  Since the signal transmission device of the present invention includes a comparator for processing a regular signal and a comparator for adding a noise cancellation function, it is possible to provide a signal transmission device having excellent noise resistance characteristics. Therefore, its industrial applicability is extremely high.

DESCRIPTION OF SYMBOLS 100 Signal transmission apparatus 110 Electronic controller 120 Input side circuit 121 1st pulse conversion circuit 123 2nd pulse conversion circuit 130 Transformer circuit 140 Noise cancellation circuit 140A 1st masking circuit part 140B 2nd masking circuit part 141a 1st delay signal generation circuit 141b Second delay signal generation circuit 143a First masking signal generation circuit 143b Second masking signal generation circuit 145a First logic operation circuit section 145b Second logic operation circuit sections 149a and 149b AND circuits 147a and 147b Signal delay circuit 150 Output terminal FF flip-flops CM1, CM2, CM_M1, CM_M2 comparators CM1_H, CM2_H hysteresis comparator IN11 first input signal IN21 second input signal IN12 first masking input signal IN22 first Masking the input signal IN1D, IN1S, IN2D, IN2S delayed signal INIM first masking signal IN2M second masking signal Pr reset signal Ps set signal Sin transmitted signals Sa1, Sa2 signal T1 first transformer T2 second transformer

Claims (11)

A primary winding and a secondary winding are separated from each other in direct current, and the primary winding and the secondary winding are connected to different ground potentials;
A first comparator and a second comparator to which an output from the secondary winding of the transformer is input;
A delay signal generator to which the output of the first comparator is input;
A masking signal generator to which the output of the second comparator is input;
A signal transmission device comprising: The signal transmission device according to claim 1, wherein the first comparator and the second comparator include one hysteresis comparator or one window comparator. The first reference potential is applied to the first input terminal of the first comparator, and the second reference potential is applied to the first input terminal of the second comparator. 2. The signal transmission device according to 1. The first reference potential is
The signal transmission device according to claim 3, wherein the signal transmission device is larger than an absolute value of the second reference potential. The signal transmission device according to claim 1, wherein the transformer includes a first transformer and a second transformer. A third comparator and a fourth comparator to which an output from the secondary winding of the second transformer is input;
A delay signal generator to which the output of the third comparator is input;
A masking signal generator to which the output of the fourth comparator is input;
The signal transmission device according to claim 5, further comprising: A first delayed signal set to a first pulse width by delaying the output from the first comparator;
A first masking signal that delays the output from the second comparator and is set to a pulse width greater than the first pulse width;
A second delayed signal set to a second pulse width by delaying the output from the third comparator;
A second masking signal that delays the output from the fourth comparator and is set to a pulse width greater than the second pulse width;
A first logical operation circuit unit for performing logical operation on the first delay signal and the second masking signal;
A second logic operation circuit for performing a logic operation on the second delay signal and the first masking signal;
The noise superimposed on the first delay signal and the second delay signal is masked by the second noise masking signal and the first noise masking signal, respectively. 2. The signal transmission device according to item 1.   The signal transmission device according to claim 7, wherein a pulse width of the first masking signal is larger than that of the second delay signal, and a pulse width of the second masking signal is larger than that of the first delay signal. The said 1st logical operation circuit part and the said 2nd logical operation circuit part have at least 1 of a logical sum circuit, a negative logical sum circuit, a logical product circuit, and a negative logical product circuit, respectively. The signal transmission device according to any one of the above. 10. The signal according to claim 7, wherein signals output from the first logic operation circuit unit and the second logic operation circuit unit are used as a set signal and a reset signal of a flip-flop, respectively. Transmission device. A first pulse generator that detects a rising edge of a transmission signal and generates a first conversion pulse smaller than a pulse width of the transmission signal;
A pulse conversion circuit having a second pulse generation unit that detects a falling edge of the pulse-shaped transmission signal and generates a second conversion pulse smaller than a pulse width of the transmission signal;
The pulse conversion circuit includes:
The first conversion pulse is input to the primary winding side of the first transformer, and the conversion pulse is transmitted to the secondary winding side;
The said 2nd conversion pulse is input into the primary winding side of the said 2nd transformer, The said conversion pulse is transmitted to the secondary winding side, The any one of Claims 5-10 characterized by the above-mentioned. The signal transmission device according to item.

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