JP2020010086A - Signal transmission device - Google Patents

Abstract

To reduce signal delay by accelerating noise cancellation processing.SOLUTION: A noise cancellation circuit 150 has a reception signal generating section 151 for generating a reception signal RCVH according to an input signal INH, a reception signal generating section 152 for generating a reception signal RCVL according to an input signal INL inputted in parallel with the input signal INH, a mask signal generating section 153 for generating a mask signal MSKH according to the input signal INL, a mask signal generating section 154 for generating a mask signal MSKL according to the input signal INH, a logical gate 155 for generating an output signal CLKH by logically operating the reception signal RCVH and the mask signal MSKL, a logical gate 156 for generating an output signal CLKL by logically operating the reception signal RCVL and the mask signal MSKL, a discharge transistor 157 for discharging the input signal INH by using the mask signal MSKH, and a discharge transistor 158 for discharging the input signal INL by using the mask signal MSKL.SELECTED DRAWING: Figure 2

Description

  The invention disclosed in this specification relates to a signal transmission device.

  2. Description of the Related Art Conventionally, a signal transmission device that transmits a pulse signal while electrically insulating input and output is used for various applications (such as a power supply device and a motor drive device).

  In addition, as an example of the related art related to the above, Patent Documents 1 to 4 can be cited.

JP 2014-007502 A JP 2018-014549A JP 2014-003515 A JP 2010-010762 A

  However, in the conventional signal transmission device, further cancellation processing of instantaneous transient common-mode noise (so-called CMTI [common mode transient immunity] noise) superimposed on the received pulse signals input in parallel to the secondary-side pulse receiving circuit is further performed. There was room for improvement.

  The present invention disclosed in the present specification has been made in view of the above-described problems found by the inventor of the present application, and a signal transmission device capable of speeding up a noise canceling process and reducing a signal delay, and used in the signal transmission device. It is an object to provide a noise canceling circuit.

  The noise cancellation circuit disclosed in the present specification includes a first reception signal generation unit that generates a first reception signal according to a first input signal, and a second input that is input in parallel with the first input signal. A second reception signal generation unit that generates a second reception signal according to a signal; a first mask signal generation unit that generates a first mask signal according to the second input signal; A second mask signal generator for generating a second mask signal; a first logic gate for performing a logical operation on the first received signal and the first mask signal to generate a first output signal; A second logic gate for performing a logical operation on the second mask signal and the second mask signal to generate a second output signal; a first discharge transistor for discharging the first input signal using the first mask signal; Discharging the second input signal using a mask signal; It has a configuration having a second discharge transistor, a (first configuration).

  In the noise cancellation circuit having the first configuration, the first reception signal generation unit generates the first reception signal having a first pulse width when the first input signal exceeds a threshold, The second reception signal generation unit generates the second reception signal having the first pulse width when the second input signal exceeds a threshold, and the first mask signal generation unit outputs the second input signal. When the signal exceeds a threshold, the first mask signal having a second pulse width larger than the first pulse width is generated, and the second mask signal generation unit determines that the first input signal has exceeded a threshold. In some cases, a configuration (second configuration) for generating the second mask signal having the second pulse width may be used.

  In the noise cancellation circuit having the above-described second configuration, each of the first reception signal generation unit and the second reception signal generation unit has a first delay time from a timing at which its own input signal exceeds a threshold. At the time point when the output signal is switched from the logic level at the steady state to the logic level at the time of pulse generation, the second delay time longer than the first delay time elapses from the timing when the input signal exceeds the threshold. At this point, the first pulse width is set to a difference value between the first delay time and the second delay time by switching the output signal from the logic level at the time of pulse generation to the logic level at the steady state. A delay stage, wherein each of the first mask signal generation unit and the second mask signal generation unit has its own without delay at a timing when its own input signal exceeds a threshold. While the input signal is switched from the logic level at the time of unmasking to the logic level at the time of masking, at the time when the third delay time has elapsed after the second delay time has elapsed after the timing when the input signal has exceeded the threshold value, A second delay stage for setting the second pulse width to an added value of the second delay time and the third delay time by switching an output signal from a logic level at the time of masking to a logic level at the time of masking off; A configuration (third configuration) may be used.

  In the noise canceling circuit having the third configuration, the second pulse width is longer than the pulse duration of the first input signal and the second input signal, and the third delay time is equal to the pulse duration. A configuration shorter than the period (fourth configuration) may be used.

  In the noise cancellation circuit having the third or fourth configuration, the first discharge transistor and the second discharge transistor are included in the first reception signal generation unit and the second reception signal generation unit, respectively. A configuration (fifth configuration) connected between the input terminal and the ground terminal of the first delay stage is preferable.

  In addition, the signal transmission device disclosed in this specification includes a pulse generation circuit that generates a first transmission pulse signal and a second transmission pulse signal in response to an input signal, and the first and second input and output signals while insulating the input and output. An insulating circuit for transmitting a transmission pulse signal and the second transmission pulse signal to a subsequent stage as a first reception pulse signal and a second reception pulse signal, respectively, and the first reception pulse signal having any one of the first to fifth configurations; And the second reception pulse signal are respectively input as the first input signal and the second input signal, and the first output signal and the second output signal are respectively subjected to the noise cancellation of the first reception pulse signal and the second output signal. (2) a noise canceling circuit for outputting the received pulse signal as a received pulse signal, and a receiving pulse corresponding to the first received pulse signal and the second received pulse signal after noise cancellation A pulse receiving circuit for generating a scan signal, may be configured to have an output driver circuit which generates an output signal corresponding to the received pulse signal (sixth configuration).

  With the signal transmission device disclosed in this specification, it is possible to speed up the noise cancellation processing and reduce the signal delay.

Diagram showing a configuration example of a signal transmission device Diagram showing one configuration example of a noise canceling circuit Timing chart showing basic operation of noise cancellation circuit Timing chart showing mask time setting example (without discharge transistor) Timing chart showing an example of operation when noise is applied (no discharge transistor) Timing chart showing mask time setting example (with discharge transistor) Timing chart showing operation example (with discharge transistor) when noise is applied Timing chart showing the minimum input pulse width during normal operation

<Signal transmission device>
FIG. 1 is a diagram illustrating a configuration example of a signal transmission device. The signal transmission device 100 of this configuration example includes a pulse generation circuit 110, an insulation circuit 120, a pulse reception circuit 130, and an output drive circuit 140.

  The pulse generation circuit 110 generates transmission pulse signals S11 and S12 according to the input signal Si. More specifically, when notifying that the input signal Si is at the high level, the pulse generation circuit 110 performs pulse driving (single or multiple transmission pulse output) of the transmission pulse signal S11 and outputs the input signal Si. Is low level, the transmission pulse signal S12 is pulsed. That is, the pulse generation circuit 110 pulse-drives one of the transmission pulse signals S11 and S12 according to the logic level of the input signal Si.

  The insulation circuit 120 transmits the transmission pulse signals S11 and S12 to the pulse reception circuit 130 as reception pulse signals S21 and S22, respectively, while insulating input and output using insulation elements 121 and 122 such as transformers.

  The pulse receiving circuit 130 generates a reception pulse signal S30 according to the reception pulse signals S21 and S22. More specifically, the pulse receiving circuit 130 receives the pulse driving of the reception pulse signal S21 and raises the reception pulse signal S30 to a high level, and receives the pulse driving of the reception pulse signal S22 and changes the reception pulse signal S30. Fall to low level. That is, the pulse receiving circuit 130 switches the logical level of the received pulse signal S30 according to the logical level of the input signal Si.

  The output driving circuit 140 generates an output signal So according to the received pulse signal S30 input from the pulse receiving circuit 130. More specifically, the output drive circuit 140 sets the output signal So to a high level when the reception pulse signal S30 is at a high level, and sets the output signal So to a low level when the reception pulse signal S30 is at a low level. .

<Noise cancellation circuit>
FIG. 2 is a diagram illustrating a configuration example of a noise canceling circuit provided between the insulating circuit 120 and the pulse receiving circuit 130.

  The noise cancellation circuit 150 of this configuration example uses the received pulse signals S21 and S22 input in parallel from the insulating elements 121 and 122 as input signals INH and INL, respectively, and superimposes instantaneous transient common-mode noise (so-called CMTI noise). The clock signals CLKH and CLKL are generated by canceling the clock signals CLKH and CLKL (hereinafter simply abbreviated as common-mode noise), and output to the pulse receiving circuit 130 (for example, the RS flip-flop 131) as noise-cancelled reception pulse signals.

  The noise canceling circuit 150 includes, as its components, received signal generation units 151 and 152, mask signal generation units 153 and 154, NOR gates 155 and 156, discharge transistors 157 and 158 (all NMOSFETs in this figure). ).

  The reception signal generation unit 151 is a circuit block that generates a reception signal RCVH according to the input signal INH, and includes a resistor R1 and a delay stage DLY1.

  The first terminal of the resistor R1 is connected to the application terminal of the input signal INH (= the secondary output terminal of the insulating element 121). The second terminal of the resistor R1 is connected to the input terminal of the delay stage DLY1.

  For example, when the input signal INH rises to a high level, the delay stage DLY1 raises the reception signal RCVH from a high level (= a logic level in a steady state) when a predetermined delay time T11 has elapsed from the rising timing of the input signal INH. The reception signal RCVH falls from a low level to a high level when a predetermined delay time T12 (> T11) has elapsed from the rising timing of the input signal INH.

  That is, when the input signal INH rises to a high level, the reception signal generation section 151 generates a reception signal RCVH having a predetermined pulse width W1 (= T12−T11).

  The reception signal generator 152 is a circuit block that generates a reception signal RCVL according to the input signal INL, and includes a resistor R2 and a delay stage DLY2.

  The first terminal of the resistor R2 is connected to the application terminal of the input signal INL (= the secondary output terminal of the insulating element 122). The second terminal of the resistor R2 is connected to the input terminal of the delay stage DLY2.

  For example, when the input signal INL rises to the high level, the delay stage DLY2 changes the reception signal RCVL from the high level (= the logic level in a steady state) when a predetermined delay time T11 has elapsed from the rise timing of the input signal INL. It falls to a low level (= logic level at the time of pulse generation), and rises the reception signal RCVL from a low level to a high level when a predetermined delay time T12 (> T11) has elapsed from the rising timing of the input signal INL.

  That is, when the input signal INL rises to a high level, the reception signal generation unit 152 generates a reception signal RCVL having a predetermined pulse width W1 (= T12−T11).

  Even if the pulse widths of the input signals INH and INL are very narrow, the pulse reception processing (= set / reset of the RS flip-flop 131) is performed even if the pulse widths of the input signals INH and INL are extremely narrow by the waveform shaping processing in the reception signal generation units 151 and 152 described above. ) Can be performed reliably.

  The mask signal generation unit 153 is a circuit block that generates a mask signal MSKH according to the input signal INL, and includes a resistor R3 and a delay stage DLY3.

  The first terminal of the resistor R3 is connected to the application terminal of the input signal INL (= the secondary output terminal of the insulating element 122). The second terminal of the resistor R3 is connected to the input terminal of the delay stage DLY3.

  For example, when the input signal INL rises to a high level, the delay stage DLY3 changes the mask signal MSKH from a low level (= a logic level at a steady state) to a high level (= at the time of pulse generation) without delay at the rising timing of the input signal INL. (Logic level), and the mask signal MSKH falls from a high level to a low level when a predetermined delay time T13 has elapsed after a predetermined delay time T12 has elapsed from the rising timing of the input signal INL.

  That is, when the input signal INL rises to a high level, the mask signal generation unit 153 generates a mask signal MSKH having a pulse width W2 (= T12 + T13) larger than the pulse width W1.

  The mask signal generation unit 154 is a circuit block that generates a mask signal MSKL according to the input signal INH, and includes a resistor R4 and a delay stage DLY4.

  The first terminal of the resistor R4 is connected to the application terminal of the input signal INH (= the secondary output terminal of the insulating element 121). The second terminal of the resistor R4 is connected to the input terminal of the delay stage DLY4.

  For example, when the input signal INH rises to a high level, the delay stage DLY4 changes the mask signal MSKL from a low level (= a logic level in a steady state) to a high level (= at the time of pulse generation) without delay at the rising timing of the input signal INH. (Logic level), and the mask signal MSKL falls from the high level to the low level when a predetermined delay time T13 has elapsed after a predetermined delay time T12 has elapsed from the rising timing of the input signal INH.

  That is, when the input signal INH rises to a high level, the mask signal generation unit 154 generates a mask signal MSKL having a pulse width W2 (= T12 + T13) larger than the pulse width W1.

  NOR gate 155 generates a clock signal CLKH by performing a NOR operation on reception signal RCVH and mask signal MSKH. Therefore, when the mask signal MSKH is at the low level, a logically inverted signal of the received signal RCVH is output as the clock signal CLKH. On the other hand, when the mask signal MSKH is at the high level, the clock signal CLKH is fixed at the low level regardless of the logic level of the received signal RCVH. The clock signal CLKH thus generated is used as a set signal of the RS flip-flop 131.

  NOR gate 156 generates a clock signal CLKL by performing a NOR operation of reception signal RCVL and mask signal MSKL. Therefore, when the mask signal MSKL is at a low level, a logically inverted signal of the received signal RCVL is output as the clock signal CLKL. On the other hand, when the mask signal MSKL is at the high level, the clock signal CLKL is fixed at the low level regardless of the logic level of the reception signal RCVL. The clock signal CLKL thus generated is used as a reset signal for the RS flip-flop 131.

  The drain of the discharge transistor 157 is connected to the input terminal of the delay stage DLY1. The source and the back gate of the discharge transistor 157 are connected to the ground terminal. The mask signal MSKH is input to the gate of the discharge transistor 157. The discharge transistor 157 connected in this manner turns off when the mask signal MSKH is at a low level, and turns on when the mask signal MSKH is at a high level. Therefore, when the mask signal MSKH is at the high level, the input signal INH (particularly the voltage applied to the input terminal of the delay stage DLY1) is discharged via the discharge transistor 157. That is, when receiving the input signal INL, the discharge transistor 157 invalidates the reception of the input signal INH.

  The drain of the discharge transistor 158 is connected to the input terminal of the delay stage DLY2. The source and the back gate of the discharge transistor 158 are connected to the ground terminal. The gate of the discharge transistor 158 receives the mask signal MSKL. The discharge transistor 158 thus connected turns off when the mask signal MSKL is at a low level, and turns on when the mask signal MSKL is at a high level. Therefore, when the mask signal MSKL is at the high level, the input signal INL (particularly the voltage applied to the input terminal of the delay stage DLY2) is discharged via the discharge transistor 158. That is, the discharge transistor 158 invalidates the reception of the input signal INL when receiving the input signal INH.

  FIG. 3 is a timing chart showing the basic operation of the noise canceling circuit 150. The input signals INH and INL (= reception pulse signals S21 and S22), the reception signals RCVH and RCVL, the mask signals MSKH and MSKL, and , Clock signals CLKH and CLKL (= reception pulse signal after noise cancellation).

  At time t31, when a normal pulse (= a valid pulse input from the insulating element 121) rises in the input signal INH, the reception signal RCVH having the pulse width W1 (time t32 to t33) and the mask signal having the pulse width W2 MSKL (time t31 to t34) are respectively generated. On the other hand, at time t31, since the pulse has not risen in input signal INL, received signal RCVL and mask signal MSKH each remain at the logic level in the steady state.

  As described above, when the mask signal MSKH is at the low level, a logically inverted signal of the received signal RCVH is output as the clock signal CLKH. When the mask signal MSKL is at the high level, the clock signal CLKL is fixed at the low level regardless of the logic level of the reception signal RCVL. It should be noted that the clock signal CLKL should originally be maintained at the low level, so that no mismatch occurs.

  At time t35, when a normal pulse (= a valid pulse input from the insulating element 122) rises in the input signal INL, the input signal INL has a received signal RCVL having a pulse width W1 (time t36 to t37) and a pulse width W2. Mask signals MSKH (time t35 to t38) are respectively generated. On the other hand, at time t35, since the pulse has not risen in input signal INH, reception signal RCVH and mask signal MSKL each remain at the logic level in the steady state.

  As described above, when the mask signal MSKL is at the low level, a logically inverted signal of the received signal RCVL is output as the clock signal CLKL. When the mask signal MSKH is at the high level, the clock signal CLKH is fixed at the low level regardless of the logic level of the reception signal RCVH. It should be noted that the clock signal CLKH should originally be kept at the low level, so that no mismatch occurs.

  Next, consider a case where in-phase noise is superimposed on both input signals INH and INL. For example, at time t39, when a noise pulse rises in both the input signals INH and INL, the reception signals RCVH and RCVL having the pulse width W1 (time t40 to t41) and the mask signal MSKH having the pulse width W2 and MSKL (time t39 to t42) are respectively generated.

  Here, when the mask signal MSKH is at the high level, the clock signal CLKH is fixed at the low level regardless of the logic level of the received signal RCVH. Similarly, when the mask signal MSKL is at the high level, the clock signal CLKL is fixed at the low level regardless of the logic level of the reception signal RCVL. Therefore, it is possible to appropriately cancel the common-mode noise superimposed on both the input signals INH and INL.

  In order to reliably cancel the common-mode noise, the pulse width W2 of the mask signals MSKH and MSKL is wider than the pulse width W1 of the reception signals RCVH and RCVL caused by the superimposition of the noise, and the pulse width W2 is larger than the pulse width. It is desirable that the width W1 completely overlaps.

  That is, as shown in this figure, after the mask signals MSKH and MSKL rise to a high level (= logic level at the time of masking), the reception signals RCVH and RCVL rise to a low level (= logic level at the time of pulse generation). The reception signals are set such that the reception signals RCVH and RCVL rise to a high level (= logic level in a steady state) and then the mask signals MSKH and MSKL fall to a low level (= logic level in a mask release state). It is desirable to generate RCVH and RCVL and mask signals MSKH and MSKL.

  Note that at least the mask time of the mask cancel circuit 150 (= the pulse width W2 of the mask signals MSKH and MSKL) elapses after one of the transmission pulse signals S11 and S12 is pulse-driven in the pulse generation circuit 110 on the transmission side. Until the above, there is a restriction that the other pulse drive of the transmission pulse signals S11 and S12 must be waited.

  That is, if the pulse width W2 of each of the mask signals MSKH and MSKL can be reduced, the noise canceling process can be speeded up accordingly, and the signal delay of the signal transmission device 100 can be reduced. In the following, the technical significance of the discharge transistors 157 and 158 introduced to realize this will be described in detail by comparing the behavior when they are not introduced and the behavior when they are introduced. .

  FIG. 4 is a timing chart showing a setting example of the mask time (= pulse width W2) when the discharge transistors 157 and 158 are not introduced. In order from the top, the input signals INH and INL (= the reception pulse signal S21 and S22), the reception signal RCVH, the mask signal MSKH, the reception signal RCVL, the mask signal MSKL, the clock signals CLKH and CLKL, and the reception pulse signal S30 (and the output signal So) are depicted.

  As shown in the figure, during pulse driving of the input signal INH, the reception signal RCVH falls from the high level to the low level when the delay time T11 has elapsed from the timing when the input signal INH has exceeded the reception threshold Vth. When the delay time T12 (> T11) elapses from the timing when the input signal INH exceeds the reception threshold Vth, it rises from the low level to the high level (see times t52 to t54). As a result, the pulse width W1 of the received signal RCVH is set to the difference value between the delay times T11 and T12 (= T12-T11).

  Further, the mask signal MSKL rises from the low level to the high level without delay at the timing when the input signal INH exceeds the reception threshold Vth, and further after the delay time T12 elapses from the timing when the input signal INH exceeds the reception threshold Vth. When the delay time T13 'has elapsed, the signal falls from the high level to the low level (see times t52 to t56'). As a result, the pulse width W2 'of the mask signal MSKL is set to the sum of the delay times T12 and T13' (= T12 + T13 ').

  Similarly, during the pulse driving of the input signal INL, the reception signal RCVL falls from the high level to the low level when the delay time T11 elapses from the timing when the input signal INL exceeds the reception threshold Vth, while the input signal INL Rises from a low level to a high level when a delay time T12 (> T11) elapses from the timing at which the signal exceeds the reception threshold Vth (see times t58 to t60). As a result, the pulse width W1 of the received signal RCVL is set to a difference value (= T12-T11) between the delay times T11 and T12.

  Further, the mask signal MSKH rises from the low level to the high level without delay at the timing when the input signal INL exceeds the reception threshold Vth, and further after the delay time T12 elapses from the timing when the input signal INL exceeds the reception threshold Vth. When the delay time T13 'has elapsed, the signal falls from the high level to the low level (see times t58 to t62'). As a result, the pulse width W2 'of the mask signal MSKH is set to the sum (T12 + T13') of the delay times T12 and T13 '.

  If the discharge transistors 157 and 158 are not introduced, the delay time T13 'must be longer than the pulse duration Tw of the input signals INH and INL. Note that the above-described pulse duration Tw refers to a period from when a high-level normal pulse rises in the input signals INH and INL to when it converges to a low level (= logic level in a steady state) again (time t51). To t55 and times t57 to t71).

  Hereinafter, the reason why T13 '> Tw must be satisfied when the discharge transistors 157 and 158 are not introduced will be described in detail with reference to FIG.

  FIG. 5 is a timing chart showing an operation example when common-mode noise is applied when the discharge transistors 157 and 158 are not introduced. As in FIG. 6, the input signals INH and INL (= the reception pulse signal S21 And S22), the reception signal RCVH, the mask signal MSKH, the reception signal RCVL, the mask signal MSKL, the clock signals CLKH and CLKL, and the reception pulse signal S30 (and the output signal So).

  As shown in FIG. 3 described above, when common-mode noise is simultaneously superimposed on both the input signals INH and INL, the noise canceling circuit 150 can appropriately cancel the superimposed common-mode noise. it can.

  However, during the pulse driving of the input signals INH and INL (= during reception of the normal pulse), a period during which the input signals INH and INL swing to a negative potential (= lower potential than a low level in a steady state) (time t53 to t56) , And times 59 to t62), and if in-phase noise is superimposed during this period, only one of the input signals INH and INL may exceed the reception threshold Vth.

  In the figure, the common mode noise is superimposed during the period when the input signal INH swings to the negative potential (= time t5x), so that only the input signal INL exceeds the reception threshold value Vth, and only the reception signal RCVL has noise. The resulting pulse is occurring. On the other hand, since the input signal INH does not exceed the reception threshold value Vth, a trigger for raising the mask signal MSKL to a high level again is not applied.

  Therefore, in order to cancel a pulse caused by noise generated in the received signal RCVL, the mask signal MSKL already at a high level due to the normal pulse of the input signal INH is replaced with the delay time T13 ′ even after the delay time T12 has elapsed. Must be maintained at a high level over a period of time.

  In particular, if T13 '> Tw is set, even in the worst case where the in-phase noise is superimposed immediately before the end of the pulse duration Tw, it is possible to appropriately cancel the noise-induced pulse generated in the received signal RCVL. Can be. Therefore, unnecessary pulses do not occur in the clock signal CLKL, and there is no hindrance to driving of the reception pulse signal S30 (and thus the output signal So).

  However, when the discharge transistors 157 and 158 are not introduced, the pulse width W2 '(= T12 + T13') of the mask signals MSKH and MSKL increases, so that there is room for further improvement in speeding up the noise cancellation processing.

  FIG. 6 is a timing chart showing a setting example of the mask time (= pulse width W2) when the discharge transistors 157 and 158 are introduced. As in FIGS. 4 and 5, the input signals INH and INL (= reception pulse signals S21 and S22), reception signal RCVH, mask signal MSKH, reception signal RCVL, mask signal MSKL, clock signals CLKH and CLKL, and reception pulse signal S30 (and output signal So) are depicted. ing.

  As shown in this figure, when the discharge transistors 157 and 158 are introduced, it is sufficient that the pulse width W2 (= T12 + T13) of the mask signals MSKH and MSKL is longer than the pulse duration Tw of the input signals INH and INL. , The delay time T13 can be set shorter than the pulse duration Tw of the input signals INH and INL.

  That is, by introducing the discharge transistors 157 and 158, the pulse width W2 of the mask signals MSKH and MSKL can be shorter than the pulse width W2 'when not introduced (Tw <W2 <W2').

  Hereinafter, the reason why T13 <Tw can be set by introducing the discharge transistors 157 and 158 will be described in detail with reference to FIG.

  FIG. 7 is a timing chart showing an operation example when common-mode noise is applied when the discharge transistors 157 and 158 are introduced. As in FIGS. 4 to 6, the input signals INH and INL (= receiving The pulse signals S21 and S22), the reception signal RCVH, the mask signal MSKH, the reception signal RCVL, the mask signal MSKL, the clock signals CLKH and CLKL, and the reception pulse signal S30 (and the output signal So) are depicted.

  In this figure, as in FIG. 5, in-phase noise is superimposed during a period in which the input signal INH swings to a negative potential (= time t5x) due to the pulse driving of the input signal INH.

  Here, if the pulse width W2 (= T12 + T13) of the mask signal MSKL is set longer than the pulse duration Tw of the input signals INH and INL, the worst case in which common-mode noise is superimposed immediately before the end of the pulse duration Tw. Even in the case, the mask signal MSKL can be maintained at a high level at the time of the noise superposition.

  When the mask signal MSKL is at the high level, the input signal INL is discharged via the discharge transistor 158 as described above. As a result, the in-phase noise superimposed on the input signal INL is quickly discharged and does not exceed the reception threshold value Vth, so that a pulse due to noise does not occur in the reception signal RCVL. Therefore, it is not necessary to mask the received signal RCVL with the mask signal MSKL, so that the delay time T13 can be shortened and the pulse width W2 of the mask signal MSKL can be reduced to a necessary minimum (T13 <Tw <W2).

  FIG. 8 is a timing chart showing the minimum input pulse width in the normal operation. In order from the top, the input signal Si, the input signals INH and INL (= reception pulse signals S21 and S22), the reception signal RCVH, and the mask signal MSKH , The reception signal RCVL, the mask signal MSKL, the clock signals CLKH and CLKL, and the reception pulse signal S30 (and the output signal So).

  As described above, the pulse generation circuit 110 on the transmission side drives at least one of the transmission pulse signals S11 and S12 after pulse driving, and then sets at least the mask time of the mask cancellation circuit 150 (= the pulse width of the mask signals MSKH and MSKL). There is a restriction that the other pulse drive of the transmission pulse signals S11 and S12 must be waited until W2) elapses. That is, the transmission standby time Twwait (= signal delay from pulse edge detection of the input signal Si to pulse driving) of the pulse generation circuit 110 becomes shorter as the pulse width W2 of the mask signals MSKH and MSKL becomes narrower.

  Therefore, if the discharge transistors 157 and 158 are introduced, the pulse width W2 of the mask signals MSKH and MSKL can be narrowed and the noise canceling process can be speeded up, so that the signal delay of the signal transmission device 100 can be reduced. Become. Further, the drive frequency fsw of the switch output unit 10 can be increased by shortening the transmission standby time Twwait.

<Other modifications>
Note that the signal transmission device disclosed in this specification is applicable to all applications that need to perform signal transmission while electrically insulating input and output (for example, an insulated gate driver handling a high voltage, a motor driver, an isolator). , Or other ICs).

  Further, various technical features disclosed in the present specification can be variously modified without departing from the spirit of the technical creation in addition to the above-described embodiment. For example, mutual replacement between a bipolar transistor and a MOS field effect transistor and inversion of the logic level of various signals are optional. That is, the above-described embodiment is to be considered in all respects as illustrative and not restrictive. The technical scope of the present invention is not limited to the above-described embodiment, and It is to be understood that the meaning equivalent to the range and all the changes belonging to the range are included.

  The invention disclosed in this specification can be used, for example, for all applications that need to perform signal transmission while electrically insulating input and output.

REFERENCE SIGNS LIST 100 Signal transmission device 110 Pulse generating circuit 120 Insulating circuit 121, 122 Insulating element 130 Pulse receiving circuit 131 RS flip-flop 140 Output driving circuit 150 Noise canceling circuit 151, 152 Received signal generator 153, 154 Mask signal generator 155, 156 NOR Gate 157, 158 Discharge transistor (NMOSFET)
DLY1, DLY2, DLY3, DLY4 Delay stage R1, R2, R3, R4 Resistance

Claims (6)

A first reception signal generation unit that generates a first reception signal according to the first input signal;
A second reception signal generation unit that generates a second reception signal according to a second input signal input in parallel with the first input signal;
A first mask signal generation unit that generates a first mask signal according to the second input signal;
A second mask signal generation unit that generates a second mask signal according to the first input signal;
A first logic gate for performing a logical operation on the first reception signal and the first mask signal to generate a first output signal;
A second logic gate for performing a logical operation on the second reception signal and the second mask signal to generate a second output signal;
A first discharge transistor that discharges the first input signal using the first mask signal;
A second discharge transistor that discharges the second input signal using the second mask signal;
A noise cancellation circuit comprising: The first reception signal generation unit generates the first reception signal having a first pulse width when the first input signal exceeds a threshold,
The second reception signal generation unit generates the second reception signal having the first pulse width when the second input signal exceeds a threshold,
The first mask signal generation unit generates the first mask signal having a second pulse width larger than the first pulse width when the second input signal exceeds a threshold,
The second mask signal generation unit generates the second mask signal having the second pulse width when the first input signal exceeds a threshold.
The noise cancellation circuit according to claim 1, wherein: The first reception signal generation unit and the second reception signal generation unit each include:
At the time when the first delay time elapses from the timing when the input signal of the own device exceeds the threshold value, the output signal of the own device is switched from the logical level at the steady state to the logical level at the time of pulse generation, while the input signal exceeds the threshold value. The output signal is switched from a logic level at the time of pulse generation to a logic level at a steady state at a point in time when a second delay time longer than the first delay time has elapsed from the timing, thereby reducing the first pulse width to the first delay time. A first delay stage set to a difference value between the time and the second delay time,
The first mask signal generation unit and the second mask signal generation unit each include:
At the timing when the input signal exceeds the threshold, the output signal is switched without delay from the logical level at the time of unmasking to the logical level at the time of masking, and the second delay time starts from the timing when the input signal exceeds the threshold. The output signal is switched from the logic level at the time of masking to the logic level at the time of unmasking at the time when the third delay time has further elapsed after the elapse of the second delay time, thereby setting the second pulse width to the second delay time and the third delay time. Including a second delay stage set to an added value with the delay time;
3. The noise canceling circuit according to claim 2, wherein:   4. The apparatus of claim 3, wherein the second pulse width is longer than a pulse duration of the first input signal and the second input signal, and the third delay time is shorter than the pulse duration. Noise cancellation circuit.   The first discharge transistor and the second discharge transistor are connected between an input terminal and a ground terminal of the first delay stage included in the first reception signal generation unit and the second reception signal generation unit, respectively. The noise canceling circuit according to claim 3 or 4, wherein A pulse generation circuit that generates a first transmission pulse signal and a second transmission pulse signal according to an input signal;
An insulation circuit for transmitting the first transmission pulse signal and the second transmission pulse signal to a subsequent stage as a first reception pulse signal and a second reception pulse signal, respectively, while insulating input and output;
The first reception pulse signal and the second reception pulse signal are input as the first input signal and the second input signal, respectively, and the first output signal and the second output signal are respectively subjected to noise cancellation of the first signal. The noise cancellation circuit according to any one of claims 1 to 5, wherein the noise cancellation circuit outputs the reception pulse signal and the second reception pulse signal.
A pulse reception circuit that generates a reception pulse signal according to the first reception pulse signal and the second reception pulse signal after noise cancellation,
An output driving circuit that generates an output signal according to the reception pulse signal;
A signal transmission device comprising:

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