CN202798646U - Signal transmission device - Google Patents
Signal transmission device Download PDFInfo
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- CN202798646U CN202798646U CN201220449713.2U CN201220449713U CN202798646U CN 202798646 U CN202798646 U CN 202798646U CN 201220449713 U CN201220449713 U CN 201220449713U CN 202798646 U CN202798646 U CN 202798646U
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Abstract
The utility model relates to a signal transmission device. The signal transmission device comprises a transformer (T1), a first comparator (CM1) and a second comparator (CM2), a delay signal generation portion (141a) and a shielding signal generation portion (143a). The transformer (T1) enables a primary winding (T11) and a secondary winding (T12) to be separated in a direct current mode, so that the primary winding (T11) and the secondary winding (T12) are mutually connected at different ground potential; outputs from the secondary winding (T12) of the transformer (T1) are input in the first comparator (CM1) and the second comparator (CM2) ; outputs of the first comparator (CM1) are input in the delay signal generation portion (141a); and outputs of the second comparator (CM2) are input in the shielding signal generation portion (143a).
Description
Technical field
The utility model relates to a kind of device for signalling, relates in particular to a kind of device for signalling with noise elimination function.
Background technology
In the past, in the field of hybrid vehicle, electric automobile, home appliance, industrial equipment and Medical Devices, using had the device for signalling that direct current ground between input/output terminal is insulated and use isolator for the transmission of carrying out signal.
As using isolator, being the device that insulating transformer transmits pulse-like signal, propose to have such as patent documentation 1 (Japan Patent Patent 2010-104192 number), patent documentation 2 (Japan Patent Patent 2010-283929 number), patent documentation 3 (Japan Patent Patent 2011-129825 number) and patent documentation 4 (Japanese Patent Laid-Open 2010-10762 communique) etc.
Patent documentation 1 (Japan Patent Patent 2010-104192 number), patent documentation 2 (Japan Patent Patent 2010-283929 number), patent documentation 3 (Japan Patent Patent 2011-129825 number) are relevant with the applicant, even if provide in the situation that applies continuously noise, also can reduce the impact of the noise that is superimposed upon input signal and can one side be electrically insulated the noise of giving and accepting that one side carries out signal of low-pressure side and high-pressure side be removed signal transfer circuit and the power inverter that circuit, use have insulating transformer:.
Patent documentation 4 (Japanese Patent Laid-Open 2010-10762 communique) is relevant with the applicant, has wherein disclosed the driving circuit device of the power semiconductor with self-diagnosing function and has used its device for signalling.
Fig. 9 represents device for signalling 900 in the past.Device for signalling comprises electronic-controlled installation 110, input side circuit 120, transformer circuit 130, comparator C M1, CM2, noise suicide circuit 140, flip-flop FF and lead-out terminal 150.
In device for signalling 900, electronic-controlled installation 110 for example and the controlling organization of hybrid vehicle between carry out the exchange of signal, it is the electronic control unit (ECU, Electronic Control Unit) that carries out the control of car integral body.
The 1st transformer T1 comprises winding T11 and secondary winding T12.Each end of winding T11 and secondary winding T12 all is connected to earthing potential, but an end that is connected to the 1st earthing potential GND1, secondary winding T12 at the end of a winding T11 is connected in the situation of the 2nd earthing potential GND2, is connected to separately different earthing potentials.That is, a winding T11 separates with secondary winding T12 direct current ground.
Secondary winding T12 side at the 1st transformer T1 is connected with comparator C M1.
Input to noise suicide circuit 140 from the signal of secondary winding T12 side output via comparator C M1.
The 2nd transformer T2 comprises winding T21 and secondary winding T22.Each end of winding T21 and secondary winding T22 all is connected to earthing potential, but an end that is connected to the 1st earthing potential GND1, secondary winding T22 at the end of a winding T21 is connected in the situation of the 2nd earthing potential GND2, is connected to separately different earthing potentials.That is, in transformer T2, one time winding T21 also separates on direct current ground with secondary winding T22.
Secondary winding T22 side at the 2nd transformer T2 is connected with comparator C M2.
Input to noise suicide circuit 140 from the signal of secondary winding T22 side output via comparator C M2.
Take out two signals from noise suicide circuit 140.One is the signalization Ps synchronous with the 1st transformer T1 side, and another is the reset signal Pr synchronous with the 2nd transformer T2 side.
Device for signalling 900 with described formation is being that transformer T1 and T2 transmit and switch from low to high the signal of output and move with the mode of switching from high to low the signal of output by different transformers respectively.In addition, at the same time to transformer T1 and transformer T2 output non-type signal is arranged is in the situation of noise, by the effect of comparator C M1, CM2 and noise suicide circuit 140, have and make that comparator C M1, CM2's do not export the function of flip-flop FF to reference to the noise more than the current potential.
[prior art document]
[patent documentation]
[patent documentation 1] Japan Patent Patent 2010-104192 number
[patent documentation 2] Japan Patent Patent 2010-283929 number
[patent documentation 3] Japan Patent Patent 2011-129825 number
[patent documentation 4] Japanese Patent Laid-Open 2010-10762 communique
The utility model content
[utility model problem to be solved]
Yet in the device for signalling of described past case, in the mutually different situation of the noise level that inputs to transformer T1, T2, the noise elimination can't normally be worked and be caused malfunction.
[technological means of dealing with problems]
Device for signalling of the present utility model comprises: transformer a winding is separated with secondary winding direct current ground, and a winding is interconnected on different earthing potentials from secondary winding; The 1st comparator and the 2nd comparator are transfused to the output from the secondary winding of described transformer; The inhibit signal generating unit is transfused to the output of described the 1st comparator; And the shielded signal generating unit, be transfused to the output of described the 2nd comparator.
Described the 1st comparator and described the 2nd comparator also can comprise hysteresis comparator or window comparator.
To the output of the 1st input of described the 1st comparator and described the 2nd comparator input from the secondary winding of described transformer, the 2nd input to described the 1st comparator is endowed the 1st with reference to current potential, the 2nd input to described the 2nd comparator is endowed the 2nd with reference to current potential, the described the 1st with reference to current potential greater than the described the 2nd absolute value with reference to current potential.
And then preferred described transformer comprises the 1st transformer and the 2nd transformer, and device for signalling comprises: the 3rd comparator and the 4th comparator are transfused to the output from the secondary winding of described the 2nd transformer; The inhibit signal generative circuit is transfused to the output of described the 3rd comparator; And the shielded signal generative circuit, be transfused to the output of described the 4th comparator.
Device for signalling comprises: the 1st inhibit signal makes from the output delay of the 1st comparator and is set as the 1st pulse duration; The 1st shielded signal makes from the output delay of the 2nd comparator and is set as the large pulse duration of more described the 1st pulse duration; The 2nd inhibit signal makes from the output delay of the 3rd comparator and is set as the 2nd pulse duration; The 2nd shielded signal makes from the output delay of the 4th comparator and is set as the large pulse duration of more described the 2nd pulse duration; The 1st logical operation circuit section carries out the logical operation processing to described the 1st inhibit signal and described the 2nd shielded signal; And the 2nd logical operation circuit, described the 2nd inhibit signal and described the 1st shielded signal are carried out the logical operation processing; And be superimposed upon the noise of described the 1st inhibit signal and described the 2nd inhibit signal respectively by described the 2nd noise isolation signal and described the 1st noise isolation signal shielding.
The pulse duration of the 1st shielded signal is greater than the pulse duration of the 2nd inhibit signal, and the pulse duration of the 2nd shielded signal is greater than the pulse duration of the 1st inhibit signal.
According to each described device for signalling in technology contents 7 or 8, wherein the 1st logical operation circuit section and the 2nd logical operation circuit section comprise respectively at least one in OR circuit, OR-NOT circuit, AND circuit and the NAND gate circuit.
Be used separately as separately signalization and the reset signal of flip-flop from the signal of the 1st logical operation circuit section and the output of described the 2nd logical operation circuit section.
In addition, device for signalling of the present utility model is pulse conversion circuit, and this pulse conversion circuit comprises: the 1st pulse generate section, the rising edge that detect to transmit signal along and generate the 1st commutation pulse less than the pulse duration of described transmission signal; And the 2nd pulse generate section, detect described pulse type the transmission signal trailing edge along and generate the 2nd commutation pulse less than the pulse duration of described transmission signal; And in the described pulse conversion circuit, described the 1st commutation pulse is input to a winding side of described the 1st transformer, and transmit described commutation pulse to its secondary winding side, and described the 2nd commutation pulse is input to a winding side of described the 2nd transformer, and transmits described commutation pulse to its secondary winding side.
[effect of utility model]
Even if the different noise stack of device for signalling noise level of the present utility model can not produce malfunction yet, therefore can provide reliability higher signal transfer circuit.
Description of drawings
Fig. 1 is the circuit diagram of the device for signalling of expression example 1 of the present utility model.
Fig. 2 A is the block diagram that the 1st of expression example 1 of the present utility model postpones generative circuit and periphery thereof.
Fig. 2 B is the block diagram that the 2nd of expression example 1 of the present utility model postpones generative circuit and periphery thereof.
Fig. 3 is the sequential chart that schematically shows the signal that generates in the noise suicide circuit of example 1 of the present utility model.
Fig. 4 represents the sequential chart of transmission signal Sin of the present utility model and the 1st input signal IN11, the 2nd input signal IN22.
Fig. 5 is the sequential chart of the standard signal in the expression device for signalling of the present utility model.
Fig. 6 A is the 1st sequential chart in order to illustrate that the state that abates the noise by noise suicide circuit is prepared in device for signalling of the present utility model.
Fig. 6 B is the 2nd sequential chart in order to illustrate that the state that abates the noise by noise suicide circuit is prepared in device for signalling of the present utility model.
Fig. 7 is the 3rd sequential chart in order to illustrate that the state that abates the noise by noise suicide circuit is prepared in device for signalling of the present utility model.
Fig. 8 is the circuit diagram of the device for signalling of expression example 2 of the present utility model.
Fig. 9 is the circuit diagram that represents device for signalling in the past.
[explanation of symbol]
100 device for signalling
110 electronic-controlled installations
120 input side circuit
121 the 1st pulse conversion circuits
123 the 2nd pulse conversion circuits
130 transformer circuits
140 noise suicide circuits
140A the 1st screened circuit section
140B the 2nd screened circuit section
141a the 1st inhibit signal generative circuit
141b the 2nd inhibit signal generative circuit
143a the 1st shielded signal generative circuit
143b the 2nd shielded signal generative circuit
145a the 1st logical operation circuit section
145b the 2nd logical operation circuit section
149a, 149b AND circuit
147a, 147b signal delay circuit
150 lead-out terminals
The FF flip-flop
CM1, CM2, CM_M1, CM_M2 comparator
CM1_H, CM2_H hysteresis comparator
IN11 the 1st input signal
IN21 the 2nd input signal
IN12 the 1st shielding input signal
IN22 the 2nd shielding input signal
IN1D, IN1S, IN2D, IN2S inhibit signal
INIM the 1st shielded signal
IN2M the 2nd shielded signal
The Pr reset signal
The Ps signalization
Sin transmits signal
Sa1, Sa2 signal
T1 the 1st transformer
T2 the 2nd transformer
Embodiment
(example 1)
Fig. 1 is the circuit diagram that schematically shows the device for signalling of example 1 of the present utility model.Device for signalling 100 comprises electronic-controlled installation 110, input side circuit 120, transformer circuit 130, comparator C M1, CM2, CM_M1, CM_M2, noise suicide circuit 140, flip-flop FF, reaches lead-out terminal 150.
In device for signalling 100, electronic-controlled installation 110 for example and the controlling organization of hybrid vehicle between carry out the exchange of signal and carry out the control of car integral body.The transmission signal Sin of production burst shape for example in electronic-controlled installation 110.
The 1st pulse conversion circuit 121 detects the rising edge edge of transmitting signal Sin and generates the 1st not shown commutation pulse.The 2nd pulse conversion circuit 123 detects the trailing edge edge of transmitting signal Sin and generates the 2nd not shown commutation pulse.As before, the pulse duration of the 1st commutation pulse and the 2nd commutation pulse is set as less than the pulse duration that transmits signal Sin, but when its size was 25 μ S in the pulse duration that for example transmits signal Sin, the 1st and the 2nd commutation pulse Sa1, Sa2 were set as for example about 5nS.Realize thus the reduction of the power consumption of input side circuit 120 and transformer circuit 130.
The 1st transformer T1 comprises winding T11 and secondary winding T12.Each end of winding T11 and secondary winding T12 all is connected to earthing potential, is connected to separately different earthing potentials but be connected at the end that the end of a winding T11 is connected to the 1st earthing potential GND1, secondary winding T12 in the situation of the 2nd earthing potential GND2.Earthing potential GND1 and the insulation of the mutual direct current of earthing potential GND2 ground.Thus, be connected to the input side circuit 120 and the direct current ground insulation such as the noise suicide circuit described later 140 that is connected to the secondary winding T12 side of the 1st transformer T1, flip-flop FF of the winding T11 side of the 1st transformer T1.In addition, so-called direct current ground insulation refers to that both earthing potentials are not to connect with conductor.Because winding side and the insulation of secondary winding side direct current ground of the 1st transformer T1, the 2nd transformer T2 is called as isolator.
Signal transfer rate from from the winding side T11 of the 1st transformer T1 to secondary winding T12 side is made as 1, if ignore both signal delay, then can goes out signal with the signal equivalence that exports a winding T11 side at secondary winding T12 side-draw.Herein " equivalence " refer to amplitude and phase place about equally.In addition, also can say for the 2nd transformer T2 identical with the 1st transformer T1.That is the signal that, produces among secondary winding T12, the T22 is that signal Sa1, Sa2 are equivalent with above-mentioned the 1st commutation pulse and the 2nd commutation pulse separately.
Secondary winding T12 side at the 1st transformer T1 is connected with comparator C M1 and CM_M1.Comparator C M1 and CM_M1 have the effect that makes its leading portion section and the coupling of back segment section.That is, the bad situation that produces when in order to be buffered in transformer circuit 130 directly being electrically connected with noise suicide circuit 140 is for example carried out impedance matching.In addition, if the 2nd input of comparator CM1 and CM_M1 is given specific with reference to current potential, then can carry out take the reference current potential as benchmark waveform shaping.In addition, also can make comparator C M1 and CM_M1 have enlarger or damping mechanism.In addition, the signal Sa1 that goes out at secondary winding T12 side-draw also can be sent to noise suicide circuit 140 with originally size roughly, but the amplitude of signal both can amplify, and also can dwindle in addition.
Export as mentioned above the winding T21 of the 2nd transformer T2 to from the 2nd not shown commutation pulse of the 2nd pulse conversion circuit 123 output, from secondary winding T22 side output signal Sa2.Input to the 1st input of comparator C M2 and comparator C M_M2 from the signal Sa2 of secondary winding T22 side output.Output from comparator C M2 and CM_M2 inputs to respectively noise suicide circuit 140.Comparator C M2 and CM_M2 have the effect that makes its leading portion section and the coupling of back segment section.That is, for example carry out impedance matching in order to be buffered in the bad situation that produces when transformer circuit 130 directly is electrically connected with noise suicide circuit 140.In addition, if the 2nd input of comparator CM2 and CM_M2 is given specific with reference to current potential, then can carry out waveform shaping with reference to it.In addition, also can make comparator C M2 and CM_M2 have enlarger or damping mechanism.In addition, the signal Sa2 that goes out at secondary winding T22 side-draw also can be sent to noise suicide circuit 140 with originally size roughly, but the amplitude of signal both can amplify, and also can dwindle in addition.
The 2nd input of comparator CM1 and CM2 is given transmitting the specific with reference to potential vt h_A of standard signal.In addition, the 2nd input of comparator CM_M1 and CM_M2 is given removing the specific with reference to potential vt h_B of noise.Of the present utility model one is characterised in that greatly to arrange to have different comparators with reference to potential vt h_A, Vth_B.The formation of comparator and detailed circuit are formed in the aftermentioned in addition clear and definite.
In addition, also can enlarger, phase shift mechanism be set in leading portion or at least one side in the back segment of comparator C M1, CM_M1, CM2, CM_M2, with phase shift to the size of particular amplitude and specific size.
Take out two signals from noise suicide circuit 140.One is the signalization Ps synchronous with the 1st transformer T1 side, and another is the reset signal Pr synchronous with the 2nd transformer T2 side.
The noise that noise suicide circuit 140 is superimposed upon in the signal that inputs to comparator C M1, CM2, CM_M1 and CM_M2 in order to removal is prepared.Of the present utility model another is characterised in that noise suicide circuit 140 is set.The detailed circuit of noise suicide circuit 140 is formed in and is able in the aftermentioned clearly.
This specification uses the statement of " noise isolation " and the statement of " noise elimination ".The known method that has following " noise isolation " to reach " noise elimination " namely produces for example pseudo-noise, is added or deducts this puppet noise and noise originally is removed or decays by noise originally.Yet " noise isolation " as used in this specification refers to not produce pseudo-noise and uses logical operation circuit section to carry out logical operation in the mode of not exporting noise originally.In addition, " noise elimination " conduct refers to the circuit integral body person who is made of several noise isolation circuit and uses.
The 1st inhibit signal generative circuit 141a is with so that postpone and generate the 1st inhibit signal IN1S and prepare from the 1st input signal IN11 of comparator C M1 output.In addition, " delay " as used in this specification refer to the rising edge of signal along and the mode that produces more behindhand in time of at least one party's side on trailing edge edge carry out signal and process.Thereby at " delay " signal before and " delay " signal afterwards between the two, pulse duration can be identical, and (narrowing down) perhaps diminishes.Perhaps can cause and become large (broadening).In addition, the purpose that the 1st input signal IN11 is postponed, direct being normally carried out logical operation with the 2nd shielded signal IN2M described later by the 1st 145a of logical operation circuit section.Details are able in aftermentioned clearly.
The 1st shielded signal generative circuit 143a prepares in order to the noise that shielding is superimposed upon the inhibit signal IN2S that takes out from the 2nd inhibit signal generative circuit 141b.Namely, the 1st shielding output signal IN1M that is generated by the 1st shielded signal generative circuit 143a generates as the basis take the 1st shielding input signal IN12 that takes out from comparator C M1_M1, but the signal that generates is prepared in order to the noise that shielding is superimposed upon the signal that takes out from comparator C M2.
The 2nd inhibit signal generative circuit 141b generates inhibit signal IN2S for the 2nd input signal IN21 is postponed and prepares.Make purpose that the 2nd input signal IN21 postpones identical with the situation of described generation inhibit signal IN1S before.That is, in order to by the 2nd logical operation circuit 145b and the 1st shielding output signal IN1M between carry out specific logical operation.
The 2nd shielded signal generative circuit 143b prepares in order to the noise that shielding is superimposed upon the inhibit signal IN1S that takes out from signal generating circuit 141a.Namely, the 2nd shielded signal IN2M that is generated by the 2nd shielded signal generative circuit 143b generates as the basis take the 1st shielding input signal IN12 that takes out from comparator C M_M2, but the signal that generates is prepared in order to the noise that shielding is superimposed upon the signal that takes out from comparator C M1.
Flip-flop FF is in order to return to and to prepare from the identical state of the transmission signal Sin of electronic-controlled installation 110 outputs.Herein " recovery " refer to roughly return to form, the position of original signal.That is, transmit signal Sin and implement signal and process for power consumption at input side circuit 120 and transformer circuit 130 being reduced and reducing pulse duration, but as having prepared flip-flop FF in order to the restore circuit that finally returns to the signal of state originally.
What signalization Ps inputed to flip-flop FF arranges terminal S.Thus, flip-flop FF is set to arrange state.Reset signal Pr inputs to the replacement terminal R of flip-flop FF.Thus, flip-flop FF is set to Reset Status.
Be taken out to lead-out terminal 150 from the output signal Sout of flip-flop FF output.The output signal Sout that is taken out to lead-out terminal 150 for example disconnects in order to the connection of controlling not shown IGBT (Insulated Gate Bipolar Transistor, insulated gate bipolar transistor) and uses.
Fig. 2 A represents the internal circuit of the 1st inhibit signal generative circuit 141a shown in Figure 1, and be circuit part that it is peripheral remove and the person.That is, the 1st 140A of screened circuit section comprises the 1st inhibit signal generative circuit 141a, the 2nd shielded signal generative circuit 143b, reaches the 1st 145a of logical operation circuit section.
The 1st input signal IN11 that takes out from comparator C M1 inputs to the 1st input x1 of the NAND gate circuit 149a of a part that consists of the 1st inhibit signal generative circuit 141a, and inputs to signal delay circuit 147a.Take out from signal delay circuit 147a as inhibit signal IN1D, the inhibit signal IN1D that takes out inputs to the 2nd input x2 of NAND gate circuit 149a.
The output x3 output of NAND gate circuit 149a has been carried out the inhibit signal IN1S of the long-pending computing of negative logic to the 1st input signal IN11 and inhibit signal IN1D.
Prepare that at the 1st 145a of logical operation circuit section two inputs are arranged, to the 1st input y1 input delay signal IN1S, the 2nd input y2 is inputted the 2nd shielded signal IN2M.The 2nd shielded signal IN2M is generated by the 2nd shielded signal generative circuit 143b.Shield in the situation of input signal IN21 with identical sequential input at the 1st input signal IN11 and the 1st, with regard to the 2nd shielded signal IN2M, inhibit signal IN1S and the 2nd shielded signal IN2M have specific phase difference.
The 1st 145a of logical operation circuit section carries out negative logic and the computing of inhibit signal IN1S and the 2nd shielded signal IN2M, only when both signals are low level, at its output y3 performance high level.Thereby, the 1st commutation pulse Sa1 that takes out from the 1st pulse conversion circuit 121 is via the 1st transformer T1, comparator C M1 and CM_M1, the 1st inhibit signal generative circuit 141a, and the 1st 145a of logical operation circuit section and taking out, but inhibit signal IN1S is subject to via the 2nd pulse conversion circuit 123, the 2nd transformer T2, comparator C M_M2, and the 2nd shielded signal generative circuit 143b and the restriction of the 2nd shielded signal IN2M that generates.That is, the 2nd shielded signal IN2M be high level during, the noise composition that is superimposed upon inhibit signal IN1S conductively-closed by the 1st 145a of logical operation circuit section.
From what the signalization Ps of the 1st 145a of logical operation circuit section output inputed to flip-flop FF terminal S is set, the flip-flop FF of back segment is set.
The 2nd 140B of noise isolation circuit part shown in Fig. 2 B cooperates with the 1st 140A of screened circuit section shown in Fig. 2 A and consists of noise suicide circuit 140.
Fig. 2 B represents the inside circuit part peripheral with it of the 2nd inhibit signal generative circuit 141b.That is, the 2nd 140B of screened circuit section comprises the 2nd inhibit signal generative circuit 141b, the 1st shielded signal generative circuit 143a, reaches the 2nd 145b of logical operation circuit section.
The 2nd input signal IN22 that takes out from comparator C M2 inputs to the 1st input x1 of NAND gate circuit 149b, and the inhibit signal IN2D that takes out from signal delay circuit 147b that inputs to signal delay circuit 147b inputs to the 2nd input x2 of AND circuit 149b.
The output x3 output of AND circuit 149b has been carried out the inhibit signal IN2S of the long-pending computing of negative logic to the 2nd input signal IN22 and inhibit signal IN2D.
Prepare that at the 2nd 145b of logical operation circuit section two inputs are arranged, to the 1st input y1 input delay signal IN2S, the 2nd input y2 is inputted the 1st shielded signal IN1M.The 1st shielded signal IN1M is generated by the 1st shielded signal generative circuit 143a.Shield in the situation of input signal IN22 with identical sequential input at the 1st input signal IN12 and the 2nd, with regard to the 1st shielded signal IN1M, inhibit signal IN2S and the 1st shielded signal IN1M have specific phase difference.
The 2nd 145b of logical operation circuit section carries out negative logic and the computing of inhibit signal IN2S and the 1st shielded signal IN1M, and only when both signals are low level, shows high level in output.Thereby, the 2nd commutation pulse Sa2 that takes out from the 2nd pulse conversion circuit 123 is via the 2nd transformer T2, comparator C M2 and CM_M2, the 2nd inhibit signal generative circuit 141b, and the 2nd 145b of logical operation circuit section and taking out, but inhibit signal IN2S is subject to via the 1st pulse conversion circuit 121, the 1st transformer T1, comparator C M_M2, and the 1st shielded signal generative circuit 143a and the restriction of the 1st shielded signal IN1M that generates.That is, be between high period at the 1st shielded signal IN1M, the noise that is superimposed upon inhibit signal IN2S does not export the 2nd 145b of logical operation circuit section to.Therefore it is called noise suicide circuit.
Input to the replacement terminal R of flip-flop FF from the reset signal Pr of the output y3 of the 2nd 145b of logical operation circuit section output, flip-flop FF is reset.
As previously discussed, noise suicide circuit 140 comprises the 1st 140A of screened circuit section and the 2nd 140B of screened circuit section.
Fig. 3 schematically shows the various signals in the 1st and the 2nd 140A of screened circuit section, 140B generation shown in Fig. 2 A, Fig. 2 B.The 1st input signal IN11, the 2nd input signal IN22 input to respectively the 1st input x1 of AND circuit 149a, 149b.The 1st shielding input signal IN12, the 1st shielding input signal IN21 are for inputing to respectively the signal of the 1st shielded signal generative circuit 143a, the 2nd shielded signal generative circuit 143b.Inhibit signal IN1S, IN2S are respectively from AND circuit 149a, 149b output, and the 1st shielded signal IN1M and the 2nd shielded signal IN2M are respectively from the 1st shielded signal generative circuit 143a and the 2nd shielded signal generative circuit 143b output.
Fig. 3 represents epimere.The 1st input signal IN11, the 2nd input signal IN22, the 1st shielding input signal IN12, the 1st shielding input signal IN21 are as before, be respectively from the signal of comparator C M1, comparator C M2, comparator C M_M1, comparator C M_M2 output, its pulse duration W1 for example elects as about 5ns.The size of pulse duration W1 is suitably set according to the electric characteristics of the frequency that transmits signal Sin, pulse duration, the 1st pulse conversion circuit 121, the 2nd pulse conversion circuit 123, the 1st transformer T1, the 2nd transformer T2 for the design item.The 1st input signal IN1, the 2nd input signal IN2 have respectively rising edge along Tr1, trailing edge along Tf1.
Inhibit signal IN1D, IN2D are from the taking-up person respectively of signal delay circuit 147a, the 147b shown in Fig. 2 A, Fig. 2 B, these inhibit signals only postpone specific time of delay of Δ t1 from the 1st input signal IN11, the 2nd input signal IN22, and its pulse duration W2 is set to identical with pulse duration W1 or becomes more than it.Inhibit signal IN1D, IN2D have respectively rising edge along Tr2, trailing edge along Tf2, show rising edge and only postpone free Δ t1 than the rising edge of the 1st input signal IN1, the 2nd input signal IN2 along Tr1 along Tr2, and trailing edge only postpones the state of free Δ t2 along Tf1 than trailing edge along Tf2.In addition, Fig. 3 illustrates time Δ t2 greater than time Δ t1 for convenient mapping, but the setting of both magnitude relationship only is the design item.Thereby, can be set as also that time Δ t1 and Δ t2 are almost equal, time Δ t1 greater than Δ t2 or time Δ t1 less than Δ t2.
That is, as long as being set as the noise that is superimposed upon the 1st input signal IN11, the 2nd input signal IN22, the size of time Δ t1, Δ t2 suitably shielded.
Inhibit signal IN1S is for having carried out the signal that the logic product computing generates by AND circuit 149a to the 1st input signal IN1 and inhibit signal IN1D.Inhibit signal IN2S is for having carried out the signal that the logic product computing generates by AND circuit 149b to the 2nd input signal IN2 and inhibit signal IN2D.Therefore, inhibit signal IN1S, IN2S are in order to become respectively high level when the 1st input signal IN11, the 2nd input signal IN22 and inhibit signal IN1D, IN2D are high level, and show that such as Fig. 3 the rising sequential Tr2 that becomes at inhibit signal IN1D, IN2D is low level, be the signal of high level at the decline sequential Tf1 of the 1st input signal IN1, the 2nd input signal IN2.This pulse duration W3 is than pulse duration W1, W2 little (narrow) for example about 3ns.
The 1st shielded signal IN1M and the 2nd shielded signal IN2M are generated by the 1st shielded signal generative circuit 143a and the 2nd shielded signal generative circuit 143b as the basis take the 1st shielding input signal IN21 and the 2nd shielding input signal IN22.The pulse duration W4 of these signals for example elects 7～10ns as greater than pulse duration W1～W3.In other words, be set as this big or small mode with pulse duration W4 and adjust time Δ t1 and Δ t2.The pulse duration W4 of the 1st shielded signal IN1M, the 2nd shielded signal IN2M is set as enough sizes (width) even if so that the rising sequential Tr3 of inhibit signal IN1S, IN2S and decline sequential Tf3 have deviation also can not produce obstacle to the logic product computing.In addition, when carrying out the logic product computing by the 1st 145a of logical operation circuit section and the 2nd 145b of logical operation circuit section, object signal as the 2nd shielded signal IN2M and the 1st shielded signal IN1M, not using the 1st input signal IN11, the 2nd input signal IN22, inhibit signal IN1D, IN2D and use inhibit signal IN1S, IN2S, is to carry out the logic product computing in order not hinder by the 1st 145a of logical operation circuit section and the 2nd 145b of logical operation circuit section.
In addition, be effective section of these various signals during shown in the pulse duration W1 of various signals shown in Figure 3, W2, W3 and the W4, be that high level or low level are carried out the logic product computing according to these effective sections.In addition, effective section of various signals refers to exist the signal section of signal itself, not necessarily specifies high level, in addition, does not also specify low level.Thereby, consisting of according to circuit, the effective section of signal is high level or is low level.
If conclude Fig. 2 A, Fig. 2 B, Fig. 3, and the concept of noise suicide circuit 140 shown in Figure 4 then be as described below.That is, noise suicide circuit 140 of the present utility model is according to the signal of two the 1st input signal IN11, the 2nd input signal IN22 and generate respectively inhibit signal IN1D, IN2D.And then generate respectively the 1st shielded signal IN1M, the 2nd shielded signal IN2M according to the 2nd input signal IN22, the 1st shielding input signal IN12, the 1st shielding input signal IN21.In the 1st input signal IN11, the 2nd input signal IN22 situation with identical sequential input, so that being positioned at the mode of the useful signal section of the 1st shielded signal IN1M, the useful signal section of inhibit signal IN2S adjusts respective delay time Δ t1, Δ t2.In addition, so that being positioned at the mode of the useful signal section of the 2nd shielded signal IN2M, the useful signal section of inhibit signal IN1S adjusts respective delay time Δ t1, Δ t2.
Fig. 4 be shown schematically among Fig. 1 the transmission signal Sin that generated by electronic-controlled installation 110, with the sequential chart of the phase relation of the 1st input signal IN11, the 2nd input signal IN22 that go out from the 1st transformer T1, the 2nd transformer T2 side-draw.
Transmission signal Sin shown in Fig. 4 (a) reaches for example signal of indicating impulse shape of mapping for convenience of description, and the expression rising edge is 50% signal along Tf, duty ratio along Tr, trailing edge.
As also understanding from explanation up to now, the 1st input signal IN11 shown in Fig. 4 (b) is the signal that goes out from the 1st transformer T1 side-draw, and is adjusted into the signal of specific pulse duration W1 along Tr for detecting the rising edge that transmits signal Sin.
As also from explanation up to now, understanding, the input signal of the 2nd input signal IN22 shown in Fig. 4 (c) for going out from the 2nd transformer T2 side-draw, and be to detect the trailing edge that transmits signal Sin is adjusted into specific pulse duration along Tf signal.The pulse duration W1 of the 2nd input signal IN2 is identical with the pulse duration W1 of the 1st input signal IN1.
The 1st input signal IN11, the 2nd input signal IN22 are the rising edge that detect the to transmit signal Sin signal after along Tr and trailing edge along Tf, but at the terminal section of device for signalling of the present utility model, revert to transmission signal Sin originally take these each input signals as the basis.
In Fig. 4 (b), the signal spacing that the 1st input signal IN11 and the 1st shielding input signal IN12 are showed represents with regional P1, and the signal spacing that the 2nd shielding input signal IN21 and the 2nd input signal IN22 are showed represents with regional P2.Namely, zone P1 does not show the signal section of the 2nd shielding input signal IN21 and the 2nd input signal IN22 for showing the 1st input signal IN11 and the 1st shielding input signal IN12, regional P2 represents to show the 2nd shielding input signal IN21 and the 2nd input signal IN22 and do not show the signal section of the 1st input signal IN11 and the 1st shielding input signal IN12.
Fig. 5 represents the sequential chart of the various signals in the pith of device for signalling shown in Figure 1.
The transmission signal Sin that Fig. 5 (a) expression is generated by electronic-controlled installation 110.Transmitting signal Sin represents as keeping the signal of high level during till from moment t1 to moment t5.That is, be expressed as till from rising edge along Tr0 to trailing edge along Tf0 during be high level.
Fig. 5 (b) expression is as the signal Sa1 of the signal before and after the transformer T1.Signal Sa1 is the signal that the rising edge that detect to transmit signal Sin generates and sends via the 1st transformer T1 along Tr0 and by the 1st pulse conversion circuit 121.Signal Sa1 so via comparator C M1 or comparator C M_M1 as the first input signal IN11 or the first shielding input signal IN22 and take out.Signal Sa1 for example during moment t1～t3, is expressed as rising edge along Tr1, trailing edge along Tf1, pulse duration W1.In addition, can think that signal Sa1 is at the front and back of transformer T1 roughly equiv.
Signal Sa1 takes out as IN11 or IN12 via comparator C M1 or comparator C M_M1.At this moment, set with reference to potential vt h_A at comparator C M1, in addition, set with reference to potential vt h_B at comparator C M_M1.
Be to prepare in order to the discrimination standard signal with reference to potential vt h_A, in addition, prepare in order to carry out noise isolation with reference to potential vt h_B.At this moment, with reference to potential vt h_A with reference to the absolute value of potential vt h_B be | Vth_A|＞| Vth_B|.And then, with reference to potential vt h_B preferably for example as long as select to become with reference to the mode of the size below 99.9% of the size of potential vt h_A, more preferably as long as select in the mode that becomes the size below 95%, and then preferably as long as select in the mode that becomes below 90%.Comparator C M1 the voltage of signal Sa1 be with reference to the situation more than the potential vt h_A under, the output high level is as signal IN11.Comparator C M_M1 the voltage of signal Sa1 be with reference to the situation more than the potential vt h_B under, the output high level is as signal IN12.Arbitrary comparator all input do not reach have separately with reference to the situation of the signal of current potential under output low level.
Fig. 5 (c) expression is as the signal Sa2 of the signal before and after the transformer T2.Signal Sa2 is the signal that the trailing edge that detect to transmit signal Sin generates and sends via the 2nd transformer T2 along Tf0 and by the 2nd pulse conversion circuit 123.Signal Sa2 and then take out via comparator C M2 or comparator C M_M2.The signal Sa2 standard signal that edge Tr2, trailing edge represent along Tf2, pulse duration W1 that for example during moment t5～t7, shows to rise.
Signal Sa2 so via comparator C M2 or comparator C M_M2 as IN22 or IN12 and take out.At this moment, set with reference to potential vt h_A at comparator C M1, in addition, set with reference to potential vt h_B at comparator C M_M1.
As mentioned above, prepare in order to the discrimination standard signal with reference to potential vt h_A, in addition, prepare in order to carry out noise isolation with reference to potential vt h_B.Comparator C M2 the voltage of signal Sa2 be with reference to the situation more than the potential vt h_A under, the output high level is as signal IN2.Comparator C M_M2 the voltage of signal Sa2 be with reference to the situation more than the potential vt h_B under, the output high level is as signal IN21.Arbitrary comparator all input do not reach have separately with reference to the situation of the signal of current potential under output low level.
The inhibit signal IN1S that Fig. 5 (d) expression is taken out from the 1st delay-line circuit 141a.The 1st inhibit signal IN1S is generated by signal Sa1, but is postponed by the 1st delay-line circuit 141a, therefore as described in Figure 3 as in Fig. 5 the rising sequential of not shown inhibit signal IN1D become low level, become high level in the decline sequential of signal Sa1.This pulse duration is less than not shown inhibit signal IN1D among the pulse duration of (being narrower than) signal Sa1 and Fig. 5.
The 2nd shielded signal IN2M that Fig. 5 (e) expression is taken out from the 2nd shielded signal generative circuit 143b.The 2nd shielded signal IN2M is that t1 produces constantly at the rising edge of signal Sa2 along the identical sequential of Tr1.The 2nd shielded signal IN2M represents to make the trailing edge of signal Sa2 along the signal of Tf1 side delay.The 2nd shielded signal IN2M shifts from low level at moment t1 and is high level, and high level continues to till the moment t4, and this pulse duration W3 is set as the pulse duration W1 greater than signal Sa1, signal Sa2.
The 2nd shielded signal IN1M that Fig. 5 (f) expression is taken out from the 1st shielded signal generative circuit 143a.The 1st shielded signal IN1M is that t1 produces at the rising edge with signal Sa1 along the roughly the same sequential of Tr1.The 1st shielded signal IN1M shifts from low level at moment t1 and is high level, and high level continues to till the moment t4, and this pulse duration W3 is set as the pulse duration W1 greater than signal Sa1, signal Sa2.
The inhibit signal IN2S that Fig. 5 (g) expression is taken out from the 2nd delay-line circuit 141b.Inhibit signal IN2S is generated by signal Sa2, but is postponed by delay-line circuit 141b, therefore as described in Figure 3 as in Fig. 5 the rising sequential of not shown inhibit signal IN1D become low level, become high level in the decline sequential of signal Sa2.This pulse duration is less than not shown inhibit signal IN2D among the pulse duration of (being narrower than) signal Sa2 and Fig. 5.
Fig. 5 (h) expression signalization Ps.Signalization Ps is that high level, inhibit signal IN1S are that low level, the 2nd shielded signal IN2M export when being low level at signal Sa1.Therefore, output signalization Ps between moment t2～t3, so flip-flop FF is arranged to high level at moment t2 from low level.
Fig. 5 (i) expression reset signal Pr.Reset signal Ps is that high level, inhibit signal IN2S are that low level, the 1st shielded signal IN1M export when being low level at signal Sa2.Therefore, output reset signal Pr between moment t6～t7, flip-flop FF resets to low level at moment t6 from high level.
The output signal Sout that the output Q of Fig. 5 (j) expression flip-flop FF namely exports from lead-out terminal 150.The output Q of flip-flop FF is arranged by the signalization Ps from the 1st 145a of logical operation circuit section output, and is reset by the reset signal Pr from the 2nd 145b of logical operation circuit section output.
Fig. 6 A schematically shows with same-phase and applies the noise N1 that is superimposed upon respectively signal Sa1, signal Sa2, the state of N2.
The transmission signal Sin that Fig. 6 A (a) expression is generated by electronic-controlled installation 110.Current owing to do not generate standard signal, be always low level so transmit signal Sin.
Fig. 6 A (b) expression is superimposed upon the noise N1 of signal Sa1.Expression noise N1 rises, descends at moment t4 at moment t1.That is, expression noise N1 is superimposed upon the state among the signal Sa1 between moment t1～t3.
The noise that is superimposed upon signal Sa1 is used as the 1st input signal IN11 via comparator C M1 or comparator C M_M1 or the 1st shielding input signal IN12 takes out.At this moment, comparator CM1 is set with reference to potential vt h_A, in addition, comparator CM_M1 is set with reference to potential vt h_B.
As mentioned above, prepare in order to the discrimination standard signal with reference to potential vt h_A, in addition, prepare in order to carry out noise isolation with reference to potential vt h_B.Comparator C M1 the voltage of signal Sa1 be with reference to the situation more than the potential vt h_A under, making the 1st input signal IN11 is high level.Comparator C M_M1 the voltage of signal Sa1 be with reference to the situation more than the potential vt h_B under, making the 1st shielding input signal IN12 is high level.Arbitrary comparator all input do not reach have separately with reference to the situation of the signal of current potential under output low level.In addition, the sequential from the signal of each comparator output is identical with signal Sa1.
Fig. 6 A (c) expression is superimposed upon the noise N2 of signal Sa2.Noise N2 is as representing at the noise of the timing sequence generating identical with noise N1.That is, be illustrated between noise N2 and the noise N1 and do not produce phase difference.
The noise that is superimposed upon signal Sa2 is used as the 2nd input signal IN21 via comparator C M2 or comparator C M_M2 or the 2nd shielding input signal IN22 takes out.At this moment, comparator CM2 is set with reference to potential vt h_A, in addition, comparator CM_M2 is set with reference to potential vt h_B.
As mentioned above, prepare in order to the discrimination standard signal with reference to potential vt h_A, in addition, prepare in order to carry out noise isolation with reference to potential vt h_B.Comparator C M2 the voltage of signal Sa2 be with reference to the situation more than the potential vt h_A under, making the 2nd input signal IN21 is high level.Comparator C M_M2 the voltage of signal Sa2 be with reference to the situation more than the potential vt h_B under, making the 2nd shielding input signal IN22 is high level.Arbitrary comparator all input do not reach have separately with reference to the situation of the signal of current potential under output low level.In addition, the sequential from the signal of each comparator output is identical with signal Sa2.
Fig. 6 A (d) expression is superimposed upon from the noise N3 of the inhibit signal IN1S of the 1st inhibit signal generative circuit 141a taking-up.The 1st inhibit signal IN1S is generated by signal Sa1, but postpones at the 1st delay-line circuit 141a, therefore as described in Figure 3 as in Fig. 6 A the rising sequential of not shown inhibit signal IN1D become low level, become high level in the decline sequential of signal Sa1.This pulse duration is less than not shown inhibit signal IN1D among the pulse duration of (being narrower than) signal Sa1 and Fig. 6 A.Thereby the noise N3 that is superimposed upon inhibit signal IN1S shifts from high level at moment t3 and is low level, shifts from low level at moment t4 to be high level.
Fig. 6 A (e) expression is superimposed upon from the noise N4 of the 2nd shielded signal IN2M of the 2nd shielded signal generative circuit 143b taking-up.The 2nd shielded signal IN2M for the rising edge of signal Sa2 along identical sequential TL translation level, shift from low level at moment t1 and to be high level.In addition, shifting from high level at moment t6 is low level.The 2nd shielded signal IN2M makes the trailing edge of signal Sa2 along the signal of side delay.Thereby noise N4 becomes the noise that the trailing edge of noise N2 is postponed along side.
Fig. 6 A (f) expression is superimposed upon the noise N5 of the 1st shielded signal IN1M that is taken out to the 1st shielded signal generative circuit 143a.The 1st shielded signal IN1M shifts from high level at moment t1 and is low level, shifts from low level at moment t6 to be high level.The 1st shielded signal IN1M makes the trailing edge of the 1st input signal IN1 along the signal of side delay.Thereby noise N5 becomes the noise that the trailing edge that makes noise N1 postpones along side.
Fig. 6 A (g) expression is superimposed upon from the noise N6 of the inhibit signal IN2S of the 2nd inhibit signal generative circuit 141b taking-up.The 2nd inhibit signal IN2S is generated by signal Sa2, but postpones at signal delay circuit 147b, therefore as described in Figure 3 as in Fig. 6 A the rising sequential of not shown inhibit signal IN2D become low level, become high level in the decline sequential of signal Sa2.This pulse duration is less than not shown inhibit signal IN2D among the pulse duration of (being narrower than) signal Sa2 and Fig. 6 A.Thereby the noise N6 that is superimposed upon inhibit signal IN1S shifts from high level at moment t3 and is low level, shifts from low level at moment t4 to be high level.
The output signal Sout that the output Q of Fig. 6 A (h) expression flip-flop FF namely exports from lead-out terminal 150.The output Q of flip-flop FF output is arranged by the signalization Ps from the 1st 145a of logical operation circuit section output, and the signal of being reset by the reset signal Pr from the 2nd 145b of logical operation circuit section output.
Signalization Ps not shown among Fig. 6 A is that high level, inhibit signal IN1S are that low level, the 2nd shielded signal IN2M export when being low level at signal Sa1.That is, the noise of stack is that high level, N3 are that low level, N4 occur when being low level at noise N1.Noise N3 is to be t3～t4 constantly during low level, and noise N4 is high level in this period, therefore noise do not occur in signalization Ps.That is, owing to being shielded by noise N4, noise N1, N3 make signalization Ps keep low level.Thereby flip-flop FF is not failure to actuate owing to arranging.
Reset signal Pr not shown among Fig. 6 A is that high level, inhibit signal IN2S are that low level, the 1st shielded signal IN2M export when being low level at signal Sa2.That is, the noise of stack is that high level, N5 are that low level, N6 occur when being low level at noise N2.Noise N5 is to be t3～t4 constantly during low level, and noise N4 is high level in this period, therefore noise do not occur in signalization Ps.That is, noise N2, N6 are shielded by noise N5 and make signalization Ps keep low level.Thereby flip-flop FF is not failure to actuate owing to arranging.
At signalization Ps and reset signal Pr all not in the situation of output, namely, when being all high level or low level, the output of flip-flop FF namely becomes low level from the output signal Sout of lead-out terminal 150 outputs, therefore spread all over whole during output low level, noise is not exported, and the noise eradicating efficacy is brought into play.
Fig. 6 B is shown schematically in the state that the noise N1, the N2 that are superimposed upon respectively signal Sa1, signal Sa2 produce phase difference.In addition, the previous Fig. 6 A those shown who sets forth is that the noise N1 that is superimposed upon signal Sa1 and the noise N2 that is superimposed upon signal Sa2 are in identical timing sequence generating.Thereby the state shown in Fig. 6 B is compared with the state shown in Fig. 6 A owing to the phase difference that has noise N1 and noise N2 requires higher noise and is eliminated performance.
The transmission signal Sin that Fig. 6 B (a) expression is generated by electronic-controlled installation 110.Current, owing to do not generate standard signal, be always low level so transmit signal Sin.
Fig. 6 B (b) expression is superimposed upon the noise N1 of signal Sa1.Expression noise N1 rises, descends at moment t4 at moment t1.That is, noise N1 is superimposed upon among the signal Sa1 between moment t1～t4.
The noise that is superimposed upon signal Sa1 takes out as the 1st input signal IN11 or the 1st shielding input signal IN12 via comparator C M1 or comparator C M_M1.At this moment, comparator CM1 is set with reference to potential vt h_A, in addition, comparator CM_M1 is set with reference to potential vt h_B.
As mentioned above, prepare in order to the discrimination standard signal with reference to potential vt h_A, in addition, prepare in order to carry out noise isolation with reference to potential vt h_B.Comparator C M1 the voltage of signal Sa1 be with reference to the situation more than the potential vt h_A under, making the 1st input signal IN11 is high level.Comparator C M_M1 the voltage of signal Sa1 be with reference to the situation more than the potential vt h_B under, making the 1st shielding input signal IN12 is high level.Arbitrary comparator all input do not reach have separately with reference to the situation of the signal of current potential under output low level.In addition, the sequential from the signal of each comparator output is identical with signal Sa1.
Fig. 6 B (c) expression is superimposed upon the noise N2 of signal Sa2.The state that expression noise N2 rises at moment t3, descend at moment t6.Thereby noise N2 only postpones to have than noise N1 constantly to produce (t3-t1).
The noise that is superimposed upon signal Sa2 via comparator C M2 or comparator C M_M2 as the 2nd input signal IN21 or the 2nd shielding input signal IN22 and take out.At this moment, comparator CM2 is set with reference to potential vt h_A, in addition, comparator CM_M2 is set with reference to potential vt h_B.
As mentioned above, prepare in order to the discrimination standard signal with reference to potential vt h_A, in addition, prepare in order to carry out noise isolation with reference to potential vt h_B.Comparator C M_M2 the voltage of signal Sa2 be with reference to the situation more than the potential vt h_B under, making the 2nd shielding input signal IN22 is high level.Arbitrary comparator all input do not reach have separately with reference to the situation of the signal of current potential under output low level.In addition, the sequential from the signal of each comparator output is identical with signal Sa2.
Fig. 6 B (d) expression is superimposed upon from the noise N3 of the inhibit signal IN1S of the 1st inhibit signal generative circuit 141a taking-up.The 1st inhibit signal IN1S is generated by signal Sa1, but postpones at signal delay circuit 147a, therefore as described in Figure 3 as in Fig. 6 B the rising sequential of not shown inhibit signal IN1D become low level, become high level in the decline sequential of signal Sa1.This pulse duration is less than not shown inhibit signal IN1D among the pulse duration of (being narrower than) signal Sa1 and Fig. 6 B.Thereby the noise N3 that is superimposed upon inhibit signal IN1S shifts from high level at moment t3 and is low level, shifts from low level at moment t4 to be high level.
Fig. 6 B (e) expression is superimposed upon from the noise N4 of the 2nd shielded signal IN2M of the 2nd shielded signal generative circuit 143b taking-up.The moment t3 that noise N4 produces when the rising sequential of the noise N2 shown in Fig. 6 B (b) shifts from low level and is high level, shifts from high level at moment t8 to be low level.The 2nd shielded signal IN2M makes the trailing edge of signal Sa2 along the signal of side delay.That is, with respect to the constantly t6 that drops to of signal Sa2, the 1st shielded signal IN1M is declined to become than its slow moment t7.
Fig. 6 B (f) expression is superimposed upon the noise N5 of the 1st shielded signal IN1M that is taken out to the 1st shielded signal generative circuit 143a.Noise N5 is identical with Fig. 6 A (f) those shown, shifts from low level at moment t1 to be high level, shifts from high level at moment t6 to be low level.
Fig. 6 B (g) expression is superimposed upon from the noise N6 of the inhibit signal IN2S of the 2nd inhibit signal generative circuit 141b taking-up.The 2nd inhibit signal IN2S is generated by signal Sa2, but postpones at signal delay circuit 147b, therefore as described in Figure 3 as in Fig. 6 B the rising sequential of not shown inhibit signal IN2D become low level, become high level in the decline sequential of signal Sa2.This pulse duration is less than not shown inhibit signal IN2D among the pulse duration of (being narrower than) signal Sa2 and Fig. 6 B.Thereby the noise N6 that is superimposed upon inhibit signal IN1S shifts from high level at moment t5 and is low level, shifts from low level at moment t6 to be high level.
The output signal Sout that the output Q of Fig. 6 B (h) expression flip-flop FF namely exports from lead-out terminal 150.The output Q of flip-flop FF output is arranged by the signalization Ps from the 1st 145a of logical operation circuit section output, and the signal of being reset by the reset signal Pr from the 2nd 145b of logical operation circuit section output.
Signalization Ps not shown among Fig. 6 B is that high level, inhibit signal IN1S are that low level, the 2nd shielded signal IN2M export when being low level at signal Sa1.That is, the noise of stack is that high level, N3 are that low level, N4 occur when being low level at noise N1.Noise N3 is to be t3～t4 constantly during low level, and noise N4 is high level in this period, therefore noise do not occur in signalization Ps.That is, owing to noise N1, N3 make signalization Ps keep low level by noise N4 shielding.Thereby flip-flop FF is not failure to actuate owing to arranging.
Reset signal Pr not shown among Fig. 6 B is that high level, inhibit signal IN2S are that low level, the 2nd shielded signal IN2M export when being low level at signal Sa2.That is, the noise of stack is that high level, N5 are that low level, N6 occur when being low level at noise N2.Noise N6 is to be t5～t6 constantly during low level, and noise N5 is high level in this period, therefore noise do not occur in signalization Ps.That is, owing to noise N2, N6 make signalization Ps keep low level by noise N5 shielding.Thereby flip-flop FF is not failure to actuate owing to arranging.
At signalization Ps and reset signal Pr all not in the situation of output, namely, when being all high level or low level, the output of flip-flop FF namely becomes low level from the output signal Sout of lead-out terminal 150 outputs, therefore spread all over whole during output low level, noise is not exported, and the noise eradicating efficacy is brought into play.
Schematically show among Fig. 7 with same-phase and apply noise N1, N2 and the different situation of noise level separately that is superimposed upon respectively signal Sa1, signal Sa2.
The transmission signal Sin that Fig. 7 (a) expression is generated by electronic-controlled installation 110.Current, owing to do not generate standard signal, be always low level so transmit signal Sin.
Fig. 7 (b) expression is superimposed upon the noise N1 of signal Sa1.Noise N1 is as rising, represent moment t4 descender at moment t1.That is, expression noise N1 is superimposed upon the state among the signal Sa1 between moment t1～t3.
Fig. 7 (c) expression is superimposed upon the noise N2 of signal Sa2.Noise N2 is in the timing sequence generating identical with noise N1, but its signal strength signal intensity is the noise level difference.Among the figure, noise N2 is as less than reference voltage Vth_A, apply greater than the value of reference voltage Vth_B.Input at its noise level in the situation of each comparator, comparator C M1, CM2 output low level, comparator C M_1, comparator C M_M2 export high level.
Fig. 7 (d) expression is superimposed upon from the noise N3 of the inhibit signal IN1S of the 1st inhibit signal generative circuit 141a taking-up.The 1st inhibit signal IN1S is generated by signal Sa1, but postpones at the 1st delay-line circuit 141a, therefore as described in Figure 3 as in Fig. 7 the rising sequential of not shown inhibit signal IN1D become low level, become high level in the decline sequential of signal Sa1.This pulse duration is less than not shown inhibit signal IN1D among the pulse duration of (being narrower than) signal Sa1 and Fig. 7.Thereby the noise N3 that is superimposed upon inhibit signal IN1S shifts from high level at moment t3 and is low level, shifts from low level at moment t4 to be high level.
Fig. 7 (e) expression is superimposed upon from the noise N4 of the 2nd shielded signal IN2M of the 2nd shielded signal generative circuit 143b taking-up.Because noise N2 greater than reference voltage Vth_B, so comparator C M_M2 exports the 2nd shielding input signal IN21 as high level, inputs the 2nd shielding input signal IN21 the 2nd shielded signal generative circuit 143b as high level.The 2nd shielded signal IN2M for the rising edge of signal Sa2 along identical sequential TL translation level, shift from low level at moment t1 and to be high level.In addition, shifting from high level at moment t6 is low level.The 2nd shielded signal IN2M makes the trailing edge of signal Sa2 along the signal of side delay.Thereby noise N4 becomes the noise that the trailing edge that makes noise N2 postpones along side.
Fig. 7 (f) expression is superimposed upon the noise N5 of the 1st shielded signal IN1M that is taken out to the 1st shielded signal generative circuit 143a.The 1st shielded signal IN1M shifts from high level at moment t1 and is low level, shifts from low level at moment t6 to be high level.The 1st shielded signal IN1M makes the trailing edge of the 1st input signal IN1 along the signal of side delay.Thereby noise N5 becomes the noise that the trailing edge that makes noise N1 postpones along side.
Fig. 7 (g) expression is superimposed upon from the noise N6 of the inhibit signal IN2S of the 2nd inhibit signal generative circuit 141b taking-up.The 2nd inhibit signal IN2S is generated by signal Sa2, but the noise level of noise N2 is less than the reference voltage Vth_A of comparator C M1, therefore to the 2nd input signal IN22 output low level, thereby keeps high level at inhibit signal IN2S.
The output signal Sout that the output Q of Fig. 7 (h) expression flip-flop FF namely exports from lead-out terminal 150.The output Q of flip-flop FF output is arranged by the signalization Ps from the 1st 145a of logical operation circuit section output, and the signal of being reset by the reset signal Pr from the 2nd 145b of logical operation circuit section output.
Signalization Ps not shown among Fig. 7 is that high level, inhibit signal IN1S are that low level, the 2nd shielded signal IN2M export when being low level at signal Sa1.That is, the noise of stack is that high level, noise N3 are that low level, noise N4 occur when being low level at noise N1.Noise N3 is to be t3～t4 constantly during low level, and noise N4 is high level in this period, therefore noise do not occur in signalization Ps.That is, owing to being shielded by noise N4, noise N1, N3 make signalization Ps keep low level.Thereby flip-flop FF is not failure to actuate owing to arranging.
Reset signal Pr not shown among Fig. 7 is that high level, inhibit signal IN2S are that low level, the 1st shielded signal IN2M export when being low level at signal Sa2.That is, the noise of stack is that high level, noise N5 are that low level, noise N6 occur when being low level at noise N2.Do not exist noise N6 be low level during, noise does not appear in signalization Ps.
At signalization Ps and reset signal Pr all not in the situation of output, that is, and when being all high level or low level, the output of flip-flop FF namely becomes low level from the output signal Sout of lead-out terminal 150 outputs, therefore spread all over whole during output low level, output noise, performance noise eradicating efficacy.
As described above, Fig. 6 A is the noise suicide circuit 140 in the situation of common noise to the situation of the complete homophase of noise that is superimposed upon signal Sa1, signal Sa2 circuit operation is illustrated.Learn to be in the situation of common noise, noise suicide circuit 140 regular events.
In addition, Fig. 6 B describes the circuit operation of the noise suicide circuit 140 in the situation of the noise producing phase difference that is superimposed upon signal Sa1, signal Sa2.Even if learn in the situation that in both, produces phase difference as long as signal in scope of design, also can similarly make noise suicide circuit 140 regular events with the state shown in Fig. 6 A.
Like this, even if in the situation that produces phase deviation under the state that applies of noise N1 and noise N2, as long as this skew is in the particular range (for example phase difference 1w) of design, also shielding noise normally.In addition, in the situation that postpones from action to consider phase difference 1w is optimized with the viewpoint of anti-noise properties, do not change circuit and consist of itself, only can relatively easily implement according to the change of the combination of buffer or inverter.
If conclude, then noise suicide circuit 140 of the present utility model generates respectively the 1st and the 2nd inhibit signal take two input signals as the basis.And then take this input signal as basic the 1st and the 2nd shielded signal that generates.Adjust the respective delay time in the useful signal mode partly that be arranged in the 1st shielded signal effectively dividing of the 2nd inhibit signal.In addition, the mode that is arranged in the useful signal part of the 2nd shielded signal with the live part of the 1st inhibit signal is carried out logical operation by OR circuit negative logic circuit to the respective delay time and is processed.
And then, as of the present utility model one large feature, among Fig. 7 the circuit operation of the noise suicide circuit 140 in the different situation of the noise level of the noise that is superimposed upon signal Sa1, signal Sa2 is illustrated.The comparator that transmits each signal in order to shaping arrange respectively have standard signal transmit usefulness with reference to potential vt h_A person and the reference voltage Vth_B person who has noise and eliminate usefulness.By these values with reference to current potential of suitable selection, can the generating masking signal even if produce in the poor situation also at both noise levels of signal Sa1, Sa2, situation that therefore can be identical with noise level is shielding noise similarly.
In addition, the noise level of expression noise N2 is lower than the situation of the noise level of noise N1 in the example shown in Figure 7, even if otherwise but learn noise level at noise N1 be lower than the situation of noise level of noise N2 or noise level N1 is different from the noise level of noise level N2 and phase place is different situation namely with situation corresponding to Fig. 6 B under, formation of the present utility model is effective too.
(example 2)
Fig. 8 is the circuit diagram of the device for signalling of expression example 2 of the present utility model.In example 2, consist of comparator by hysteresis comparator.
Secondary winding T12 side at the 1st transformer T1 is connected with hysteresis comparator CM1_H.Hysteresis comparator CM1_H has the effect that makes its leading portion section and the coupling of back segment section.That is, the bad situation that produces when in order to be buffered in transformer circuit 130 directly being electrically connected with noise suicide circuit 140 is for example carried out impedance matching.In addition, hysteresis comparator CM1_H has specific sluggish width, and has two critical value voltages corresponding to described sluggish width.In addition, also can make hysteresis comparator CM1_H have enlarger or damping mechanism.In addition, the signal Sa1 that goes out at secondary winding T12 side-draw also can be sent to noise suicide circuit 140 with originally size roughly, but the amplitude of signal is both variable large, also can diminish in addition.
Secondary winding T22 side at the 2nd transformer T2 is connected with hysteresis comparator CM2_H.For the effect of hysteresis comparator CM2_H owing to identical repetition of above-mentioned hysteresis comparator CM_M1, so detailed.
Hysteresis comparator CM_H1, CM_H2 have two critical value voltages for input signal, therefore can regard as this each critical value voltage identical with above-mentioned reference voltage Vth_A and Vth_B.Thereby, such as this example, even if by comparator is replaced as hysteresis comparator, also can bring into play illustrated up to now effect of the present utility model.
In addition, hysteresis comparator has two critical value voltages in a comparator, therefore namely compares with reference to the example 1 of current potential with using two critical value voltages of two comparators preparations, and existence can reduce the advantage of the number of comparator.
In addition, described comparator C M1, CM_M1, CM2, CM_M2 also can be made of window comparator (Window Comparator).
[industrial utilizability]
Device for signalling of the present utility model comprises respectively in order to the comparator of cleanup standard signal, reaches in order to append the comparator of noise elimination function, therefore can provide a kind of device for signalling of anti-noise properties excellence, so its industrial utilizability is high.
Claims (11)
1. device for signalling is characterized in that comprising:
Transformer makes a winding separate with secondary winding direct current ground, and one time winding is interconnected on different earthing potentials from secondary winding;
The 1st comparator and the 2nd comparator are transfused to the output from the secondary winding of described transformer;
The inhibit signal generating unit is transfused to the output of described the 1st comparator; And
The shielded signal generating unit is transfused to the output of described the 2nd comparator.
2. device for signalling according to claim 1, it is characterized in that: described the 1st comparator and described the 2nd comparator comprise a hysteresis comparator or a window comparator.
3. device for signalling according to claim 1, it is characterized in that: the 1st input to described the 1st comparator is endowed the 1st with reference to current potential, and the 1st input of described the 2nd comparator is endowed the 2nd with reference to current potential.
4. device for signalling according to claim 3 is characterized in that: the described the 1st with reference to current potential greater than the described the 2nd absolute value with reference to current potential.
5. each described device for signalling in 4 according to claim 1, it is characterized in that: described transformer comprises the 1st transformer and the 2nd transformer.
6. device for signalling according to claim 5 is characterized in that comprising:
The 3rd comparator and the 4th comparator are transfused to the output from the secondary winding of described the 2nd transformer;
The inhibit signal generating unit is transfused to the output of described the 3rd comparator; And
The shielded signal generating unit is transfused to the output of described the 4th comparator.
7. each described device for signalling according to claim 5 or in 6 is characterized in that comprising:
The 1st inhibit signal makes from the output delay of the 1st comparator and is set as the 1st pulse duration;
The 1st shielded signal makes from the output delay of the 2nd comparator and is set as the large pulse duration of more described the 1st pulse duration;
The 2nd inhibit signal makes from the output delay of the 3rd comparator and is set as the 2nd pulse duration;
The 2nd shielded signal makes from the output delay of the 4th comparator and is set as the large pulse duration of more described the 2nd pulse duration;
The 1st logical operation circuit section carries out the logical operation processing to described the 1st inhibit signal and described the 2nd shielded signal; And
The 2nd logical operation circuit section carries out the logical operation processing to described the 2nd inhibit signal and described the 1st shielded signal; And
Be superimposed upon the noise of described the 1st inhibit signal and described the 2nd inhibit signal respectively by described the 2nd noise isolation signal and described the 1st noise isolation signal shielding.
8. device for signalling according to claim 7, it is characterized in that: the pulse duration of described the 1st shielded signal is greater than the pulse duration of described the 2nd inhibit signal, and the pulse duration of described the 2nd shielded signal is greater than the pulse duration of described the 1st inhibit signal.
9. each described device for signalling according to claim 7 or in 8, it is characterized in that: described the 1st logical operation circuit section and described the 2nd logical operation circuit section comprise respectively at least one in OR circuit, OR-NOT circuit, AND circuit and the NAND gate circuit.
10. each described device for signalling in 9 according to claim 7 is characterized in that: the signalization and the reset signal that are used separately as flip-flop from the signal of described the 1st logical operation circuit section and the output of described the 2nd logical operation circuit section.
11. each described device for signalling in 10 according to claim 5 is characterized in that it is pulse conversion circuit, and comprises:
The 1st pulse generate section, the rising edge that detect to transmit signal along and generate the 1st commutation pulse less than the pulse duration of described transmission signal; And
The 2nd pulse generate section, detect described pulse type the transmission signal trailing edge along and generate the 2nd commutation pulse less than the pulse duration of described transmission signal; And
In the described pulse conversion circuit,
Described the 1st commutation pulse is input to a winding side of described the 1st transformer, and described commutation pulse is sent to its secondary winding side; And
Described the 2nd commutation pulse is input to a winding side of described the 2nd transformer, and described commutation pulse is sent to its secondary winding side.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011195528A JP5793376B2 (en) | 2011-09-08 | 2011-09-08 | Signal transmission device |
| JP2011-195528 | 2011-09-08 |
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| Publication Number | Publication Date |
|---|---|
| CN202798646U true CN202798646U (en) | 2013-03-13 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201220449713.2U Expired - Lifetime CN202798646U (en) | 2011-09-08 | 2012-09-05 | Signal transmission device |
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| JP (1) | JP5793376B2 (en) |
| CN (1) | CN202798646U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105897251A (en) * | 2016-05-20 | 2016-08-24 | 西安矽源半导体有限公司 | Digital signal isolator and isolation method |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6368111B2 (en) * | 2013-06-07 | 2018-08-01 | ローム株式会社 | Signal transmission device |
| JP6418447B2 (en) * | 2014-12-25 | 2018-11-07 | パナソニックＩｐマネジメント株式会社 | Signal generator |
| JP6685192B2 (en) | 2016-07-11 | 2020-04-22 | 三菱電機株式会社 | Signal transmission device and power switching element drive device |
| CN110690888B (en) * | 2019-09-29 | 2022-10-14 | 北京中科格励微科技有限公司 | Isolator for digital signals |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3635975B2 (en) * | 1999-03-02 | 2005-04-06 | 富士電機デバイステクノロジー株式会社 | Level shift circuit |
| JP5261031B2 (en) * | 2008-06-03 | 2013-08-14 | ローム株式会社 | Buffer circuit and signal transmission device using the same |
| JP5253012B2 (en) * | 2008-06-24 | 2013-07-31 | ローム株式会社 | Power semiconductor drive circuit device and signal transmission circuit device used therefor |
-
2011
- 2011-09-08 JP JP2011195528A patent/JP5793376B2/en active Active
-
2012
- 2012-09-05 CN CN201220449713.2U patent/CN202798646U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105897251A (en) * | 2016-05-20 | 2016-08-24 | 西安矽源半导体有限公司 | Digital signal isolator and isolation method |
| CN105897251B (en) * | 2016-05-20 | 2019-01-22 | 西安矽源半导体有限公司 | A kind of digital signal isolator and its method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2013058878A (en) | 2013-03-28 |
| JP5793376B2 (en) | 2015-10-14 |
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