JP2016122968A - Signal generation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal generation device that can reduce the number of wires for an input pulse signal and generate an output pulse signal having a pulse width which is equal to or less than that of the input pulse signal.SOLUTION: An output pulse generator (510) detects eight timings from the combination of the level of one input pulse signal out of input pulse signals (INA, INB) output from isolators (IS1, IS2) and the rising and falling timings of the other input pulse signal. The output pulse generator (510) selects every two timings from the eight detected timings to select four pairs of timings, and allocates the four pairs of timings to toggle timings of output pulse signals (SH, MH, SL, ML) to generate output pulse signals (SH, MH, SL, ML).SELECTED DRAWING: Figure 6

Description

  The present disclosure relates to a signal generation device that generates an output pulse signal for controlling a switch included in a control target device.

  2. Description of the Related Art Conventionally, there is known a switch device that includes a plurality of switch circuits and a plurality of control circuits corresponding to the respective switch circuits, and each control circuit controls on / off of each switch circuit. In such a switch device, as the number of switch circuits increases, the number of control circuits also increases. Accordingly, the wiring of control lines for controlling the switch circuits becomes complicated, and the area of the wiring increases. There is a problem.

  Therefore, Patent Document 1 supplies a plurality of control circuits that individually control each of the plurality of switch circuits, and a first control signal that cyclically allocates the time of each of the plurality of control circuits to the plurality of control circuits. And a control line for supplying a second control signal for controlling the output voltages of the plurality of switch circuits to the plurality of control circuits, and the time-allocated control circuit includes the second control signal. Accordingly, a switch device that generates a pulse signal for turning on and off a corresponding switch circuit is disclosed.

JP-A-11-168368

  However, in Patent Document 1, since the time allocation of each control circuit is performed cyclically, one control circuit cannot generate a pulse signal having a shorter pulse width than the period in which its own time allocation is one order. There was a problem.

  The present disclosure provides a signal generation device that reduces the number of wires of an input pulse signal and generates an output pulse signal having a pulse width equal to or smaller than the input pulse signal.

A signal generation device according to an aspect of the present disclosure is provided.
A first for controlling the first to fourth switches of the device to be controlled using the first and second input pulse signals that are switched between the first level and a second level different from the first level. A signal generation device for generating a fourth output pulse signal,
The first and second input pulse signals have a pulse width equal to or greater than a minimum pulse width defined by an isolator,
An isolator to which the first and second input pulse signals are input;
Of the first and second input pulse signals output from the isolator, eight timings are detected from a combination of the level of one input pulse signal and the rising and falling timings of the other input pulse signal, and the detection An output pulse generator that selects any two of the eight timings and assigns them to the toggle timing of the first to fourth output pulse signals to generate the first to fourth output pulse signals With.

  According to the present disclosure, it is possible to reduce the number of wires of the input pulse signal and generate an output pulse signal having a pulse width equal to or smaller than the input pulse signal.

It is a figure which shows the structural example of the drive system to which the signal generation apparatus in this indication was applied. It is a figure which shows the structural example of the DC-DC converter controlled by the drive device of this indication. It is a figure which shows the structural example of the drive device which controls the switching element shown in FIG. It is a timing chart which shows roughly the simulation result of the drive device at the time of turning on a switching element. FIG. 5 is a timing chart schematically showing a simulation result of the driving device when the switching element is turned on when the charging time is set shorter than that in FIG. 4. It is a figure which shows the structural example of a signal generator. It is a timing chart which shows the process of an output pulse production | generation part. It is a timing chart which shows the process which an output pulse production | generation part produces | generates an output pulse signal from an input pulse signal, when a drive device employ | adopts the aspect which controls a switching element by a charging system. It is a timing chart which shows the process in which an output pulse production | generation part produces | generates an output pulse signal from an input pulse signal, when the drive device employ | adopts the aspect which controls a switching element with a clamp advance method. It is a timing chart which shows the process in which an output pulse production | generation part produces | generates an output pulse signal from an input pulse signal, when the drive device employ | adopts the aspect which controls a switching element with a clamp advance method. It is a graph which shows the experimental result performed in order to obtain | require optimal charging time according to a load state. Section (a) is a graph showing the relationship between the ringing voltage (Vds (H) .max) and the charging time, and section (b) is the relationship between the voltage change rate (dV (L) / dt) and the charging time. The section (c) is a graph showing the relationship between the switching loss (Eon) and the charging time, and the section (d) is the voltage change rate (dV (H) / dt) and the charging time. It is the graph which showed this relationship. 10 is a circuit diagram of a switch device of Patent Document 1. FIG. It is a time chart of the switch apparatus shown in FIG. It is a figure which shows the structural example of the drive system in a comparative example.

(Background to this disclosure)
In the DC-DC converter, it is desired to reduce the switching loss of the switching element. The switching element reduces switching loss by increasing the response speed of the drain-source voltage.

  However, when the response speed is increased, ringing may occur due to a resonance loop including a parasitic inductance and a parasitic capacitance on the DC-DC converter, and an excessive voltage may be applied to the switching element. For this reason, it is necessary to employ a switching element having a high withstand voltage as the switching element, resulting in an increase in the cost of the circuit. In addition, excessive radiation noise is generated with ringing, which may adversely affect other electrical devices.

  The voltage level of the control signal input to the gate of the switching element is about 5V, for example, while the voltage level handled by the DC-DC converter is very large, 300V to 500V, and the control signal is transferred to the DC-DC converter. In order to propagate well, it is necessary to electrically insulate the reference potential of both circuits. Therefore, an isolator is generally provided in the previous stage of the gate of the switching element and the previous stage of the gate of each switch constituting the driving device. Here, the isolator has a standard called common-mode rejection voltage. In order to satisfy this standard, the response speed of the switching element needs to be equal to or less than the voltage change rate determined by the common-mode rejection voltage. There is a limit to speeding up.

  Accordingly, a switching speed (hereinafter referred to as “SW speed”) in which the switching loss of the switching element is set to a certain value or less, the response speed of the switching element is set to a voltage change rate specified by the isolator, and the ringing voltage is set to a certain value or less. The switching element drive can be optimized by setting the fastest SW speed.

  However, the switching loss, the response speed, and the ringing voltage vary depending on load conditions such as a current input / output to / from the switching element, a voltage, and a device temperature. Therefore, when the DC-DC converter is actually designed, the worst SW speed that can satisfy any load state is set. For this reason, there is a case in which the actually set SW speed does not have an optimum value in a load state. In this case, the switching element cannot be driven efficiently.

  Here, the increase in SW speed can be realized, for example, by increasing the period (charge time) during which charges are injected into the gate capacitance of the switching element. Therefore, the inventor has focused on the fact that the switching element can be driven efficiently if the optimum charging time is dynamically set according to the load state.

  Next, problems of Patent Document 1 will be described.

  FIG. 13 is a circuit diagram of the switch device SS1 of Patent Document 1. FIG. 14 is a time chart of the switch device SS1. The switch device SS1 includes four switch circuits (hereinafter described as “SW1 to SW4”) and four control circuits (hereinafter referred to as “CONT1 to CONT4”) corresponding to SW1 to SW4.

  CONTi is a D flip-flop (hereinafter referred to as “D-FFi1”), a NOR circuit (hereinafter referred to as “NORi”), a D-flipflop (hereinafter referred to as “D-FFi2”). Write). Here, i is an index for specifying CONT1 to CONT4 and SW1 to SW4, and takes a value of 1 to 4.

  D-FFi1 takes in the first control signal C1 input to the D terminal at the rising edge of the clock CK. As shown in FIG. 14, the level of the first control signal C1 is set to H every four periods such that the level is H in the period P1 and the level is H in the period P5.

  Therefore, in the period P1, the D-FF 11 receives the first control signal C1 having the level H when the clock CK rises because the first control signal C1 having the level H is input to the D terminal. Thereby, the level of the output signal F1 output from the F terminal of the D-FF 11 becomes H (C141).

  In the period P2, the D-FF 11 receives the first control signal C1 having the L level when the clock CK rises because the first control signal C1 having the L level is input to the D terminal (C142). .

  In the period P2, when the clock CK rises, the D-FF 21 takes in the output signal F1 whose level is H. As a result, the level of the output signal F2 output from the F terminal of the D-FF 21 becomes H (C143).

  Thus, as the periods P1, P2, P3, and P4 progress, the levels of the output signals F1, F2, F3, and F4 are sequentially set to H (C144, C145).

  NOR1 to NOR4 respectively AND the output signals F1 to F4 and the second control signal C2 (C146). For example, in the period P2, since the level of the second control signal C2 is H and the level of the output signal F2 is H, the level of the output signal of NOR2 is H.

  Since the F-bar terminal is connected to the D terminal, the D-FFi2 inverts the level of the switch switching signal Si output from the F terminal every time the level of the T terminal is inverted. Therefore, in the period P2, the D-FF 22 sets the level of the switch switching signal S2 output to SW2 to H.

  In the period P6, the D-FF 21 takes in the output signal F2 whose level is H again in synchronization with the rising edge of the clock CK. Thereby, the level of the output signal F2 output from the F terminal of the D-FF 21 becomes H. In the period P6, the level of the second control signal C2 is H. Therefore, in the period P6, the level of the output signal of NOR2 becomes H.

  Therefore, in the period P6, the D-FF 22 sets the level of the switch switching signal S2 output to SW2 to L.

  As described above, in the switching device SS1, the number of control lines is reduced by sequentially propagating the first control signal C1 having the level H to the CONT1 to CONT4.

  However, in the switching device SS1, once the switch switching signal Si is toggled, it is necessary to wait for the output signal Fi to go one step before the next toggle. For example, the level of the switch switching signal S2 is H in the period P2 in synchronization with the rise of the output signal F2, but it takes four periods until the output signal F2 rises next, so the period P6 arrives. Until the level cannot be L. Therefore, if the pulse width of the clock CK is ½ of one period, the minimum pulse width of the switch switching signal S2 is 8 × (pulse width of the clock CK).

  That is, when the number of the switches SWi is n and the pulse width of the clock CK is CK, the minimum pulse width that the switch device SS1 can output to the switch SWi is CK × 2n.

  Here, in FIG. 13, a configuration is assumed in which an isolator is provided in front of the input terminal of the first control signal C1. The minimum possible propagation time is determined by the specification of the isolator, and the isolator cannot transmit a pulse smaller than that. Therefore, in the configuration in which the switching device SS1 is provided with an isolator, the minimum pulse width of the first control signal C1 cannot be made smaller than the minimum pulse width determined by the specifications of the isolator. In the switching device SS1, the minimum pulse width of the switch switching signal Si needs to be CK × 2n. Therefore, when the minimum pulse width determined by the isolator is P_IS, in the configuration in which the isolator is provided in the switch device SS1, the minimum pulse width of the switch switching signal Si is P_IS × 2n.

  With this, the minimum pulse width of the switch switching signal Si cannot be made shorter than the minimum propagation time determined by the isolator. Therefore, when the switching device SS1 is applied to the driving device 300 shown in FIG. 3, the charging time of the switching element to be controlled by the driving device 300 cannot be set to a time shorter than the minimum propagation time determined by the isolator. Therefore, the switching device SS1 is not suitable for a driving device that dynamically changes the charging time of the switching element according to the load state.

  The present disclosure has been made in view of the above problems, and provides a signal generation device that reduces the number of wires of an input pulse signal and generates an output pulse signal having a pulse width equal to or smaller than the input pulse signal.

(1) A signal generation device according to an aspect of the present disclosure includes:
A first for controlling the first to fourth switches of the device to be controlled using the first and second input pulse signals that are switched between the first level and a second level different from the first level. A signal generation device for generating a fourth output pulse signal,
The first and second input pulse signals have a pulse width equal to or greater than a minimum pulse width defined by an isolator,
An isolator to which the first and second input pulse signals are input;
Of the first and second input pulse signals output from the isolator, eight timings are detected from a combination of the level of one input pulse signal and the rising and falling timings of the other input pulse signal, and the detection An output pulse generator that selects any two of the eight timings and assigns them to the toggle timing of the first to fourth output pulse signals to generate the first to fourth output pulse signals With.

  In this aspect, since the first and second input pulse signals are switched between the first and second levels, there are four rising or falling timings of the first and second input pulse signals. Therefore, 4 × 2 = 8 ways by combining the levels (two ways) of the other input pulse signal with the rising or falling timing of one of the first and second input pulse signals. Can be detected.

  Then, two timings are selected from the eight timings according to a predetermined logic and assigned to the toggle timings of the first to fourth output pulse signals. Thereby, an output pulse signal having a pulse width equal to or smaller than the minimum pulse width of the first and second input pulse signals is obtained. Therefore, first to fourth output pulse signals having a pulse width equal to or smaller than the minimum pulse width defined by the isolator are obtained.

  Further, in this aspect, since the first to fourth output pulse signals are generated from the first and second input pulse signals, the number of wires of the input pulse signal is only two, and the number of wires can be reduced. Also, since only two input pulse signals are required, the number of isolators is two, and the number of isolators can be reduced.

  In this aspect, the toggle timing of the output pulse signal is determined by a combination of the rising or falling timing of one input pulse signal and the level of the other input pulse signal. For this reason, it is possible to prevent a plurality of output pulse signals from rising or falling at the rising or falling timing of one input pulse signal.

(2) In the above aspect,
The device to be controlled is a drive device that drives a switching element including a control terminal,
The driving device includes a first terminal and a second terminal, and the second terminal includes a coil connected to the control terminal,
The first switch is connected between a first potential line for applying a first potential and the first terminal, and is turned on to turn on the switching element.
The second switch is connected between the first potential line and the second terminal, and is turned on to clamp the control terminal of the turned-on switching element at the first potential,
The third switch is connected between a second potential line that applies a second potential lower than the first potential and the first terminal, and is turned on to turn off the switching element.
The fourth switch is connected between the second potential line and the second terminal, and may be turned on to clamp the control terminal of the turned-off switching element at the second potential.

  In this aspect, it is possible to generate the first to fourth output pulse signals for controlling the first to fourth switches included in the driving device.

(3) In the above aspect,
The first switch has an on-time adjusted according to a load state of the switching element,
The output pulse generation unit determines a rising timing of one input pulse signal of the first and second input pulse signals, and toggles one of the output pulse signals of the first to fourth output pulse signals. May be selected as the other toggle timing of the one output pulse signal.

  In this aspect, when the rising timing of one input pulse signal is selected as the toggle timing of one output pulse signal, the falling timing of the other input pulse signal is selected as the other toggle timing of this output pulse signal. The Therefore, an output pulse signal having a pulse width shorter than the minimum pulse width of the input pulse signal can be obtained. By adjusting the ON time of the first switch using this output pulse signal, the ON time of the first switch can be set to a time shorter than the minimum pulse width defined by the isolator, and the ON time of the first switch can be set. The adjustment range increases. As a result, it is possible to generate an output pulse signal suitable for control of a driving device that employs a control method (charging method described later) that dynamically sets the ON time of the first switch according to the load state.

(4) In the above aspect,
The output pulse generator is
The timing at which the first input pulse signal rises when the second input pulse signal is at the first level is selected as the rise timing of the first output pulse signal, and the first input pulse signal is the first level. A timing at which the second input pulse signal falls in the case of a level is selected as a fall timing of the first output pulse signal;
The timing at which the first input pulse signal falls when the second input pulse signal is at the second level is selected as the rise timing of the second output pulse signal, and the second input pulse signal is the first level. In the case of two levels, the timing when the first input pulse signal rises is selected as the fall timing of the second output pulse signal,
The timing at which the second input pulse signal rises when the first input pulse signal is at the first level is selected as the rise timing of the third output pulse signal, and the second input pulse signal is the first level. In the case of level, the timing at which the first input pulse signal falls is selected as the fall timing of the third output pulse signal,
The timing when the second input pulse signal falls when the first input pulse signal is at the second level is selected as the rise timing of the fourth output pulse signal, and the first input pulse signal is the first level. The timing at which the second input pulse signal rises in the case of two levels may be selected as the fall timing of the fourth output pulse signal.

  In this aspect, it is possible to generate the first to fourth output pulse signals suitable for the control of the driving device that employs the control method that dynamically sets the ON time of the first switch.

(5) In the above aspect,
The second switch is turned on before the first switch is turned off when the switching element is turned on, and an on time is adjusted according to a level of a signal output from the switching element,
The output pulse generator is
The timing at which the second input pulse signal falls when the first input pulse signal is at the second level is selected as the rise timing of the first output pulse signal, and the first input pulse signal is the first level. Selecting the timing at which the second input pulse signal rises in the case of 1 level as the fall timing of the first output pulse signal;
The timing at which the first input pulse signal rises when the second input pulse signal is at the second level is selected as the rise timing of the second output pulse signal, and the second input pulse signal is the first level. In the case of level, the timing at which the first input pulse signal falls is selected as the fall timing of the second output pulse signal,
The timing at which the first input pulse signal rises when the second input pulse signal is at the first level is selected as the rise timing of the third output pulse signal, and the second input pulse signal is the second level. In the case of level, the timing at which the first input pulse signal falls is selected as the fall timing of the third output pulse signal,
The timing at which the second input pulse signal falls when the first input pulse signal is at the first level is selected as the rise timing of the fourth output pulse signal, and the first input pulse signal is the first level. The timing at which the second input pulse signal rises in the case of two levels may be selected as the fall timing of the fourth output pulse signal.

  In this aspect, it is possible to generate an output pulse signal suitable for a drive device that employs a control method (clamp advance method described later) in which the second switch is turned on before the first switch is turned off.

(6) In the above aspect,
The fourth switch is turned off after the first switch is turned on when the switching element is turned on, and an on time is adjusted according to a level of a signal output from the switching element,
The output pulse generator is
The timing at which the second input pulse signal rises when the first input pulse signal is at the second level is selected as the rise timing of the first output pulse signal, and the first input pulse signal is the first level. A timing at which the second input pulse signal falls in the case of a level is selected as a fall timing of the first output pulse signal;
The timing when the first input pulse signal falls when the second input pulse signal is at the second level is selected as the rise timing of the second output pulse signal, and the first input pulse signal is the first level. Selecting the timing at which the second input pulse signal rises in the case of 1 level as the falling timing of the second output pulse signal;
The timing at which the first input pulse signal rises when the second input pulse signal is at the second level is selected as the rise timing of the third output pulse signal, and the second input pulse signal is the first level. In the case of level, the timing at which the first input pulse signal falls is selected as the fall timing of the third output pulse signal,
The timing at which the second input pulse signal falls when the first input pulse signal is at the second level is selected as the rise timing of the fourth output pulse signal, and the second input pulse signal is the second level. The timing at which the first input pulse signal rises in the case of 1 level may be selected as the fall timing of the fourth output pulse signal.

  In this aspect, it is possible to generate an output pulse signal suitable for a drive device that employs a control method (precharge method described later) in which the fourth switch is turned off after the first switch is turned on.

(Embodiment)
FIG. 1 is a diagram illustrating a configuration example of a drive system 100 to which a signal generation device 500 according to the present disclosure is applied. The drive system 100 controls a single-phase inverter in which four switching elements (not shown) are connected by a full bridge.

  The drive system 100 includes an input pulse generation unit 200, four drive devices 300, and four signal generation devices 500.

  Four driving devices 300 are provided corresponding to the four switching elements of the single-phase inverter, and control the corresponding switching elements.

  The driving device 300 includes four switches SW1 to SW4 and a coil L1. Details of the driving device 300 will be described later.

  Four signal generation devices 500 are provided corresponding to the four drive devices 300. The signal generation device 500 includes two isolators IS and an output pulse generation unit 510. Here, since there are four signal generators 500, the total number of isolators IS is eight.

  The input pulse generation unit 200 includes, for example, an FPGA (Field Programmable Gate Array) or CPLD (Complex Programmable Logic Device), and generates two input pulse signals (first and second input pulse signals). The first and second input pulse signals are signals whose voltage level is switched between H (high level) and L (low level).

  The input pulse generator 200 is connected to each of the isolators IS through a signal line Ln1. Of the two isolators IS provided in the signal generating device 500, one isolator IS receives a first input pulse signal, and the other isolator IS receives a second input pulse signal.

  The output pulse generator 510 is composed of, for example, a logic circuit, and inputs the first and second input pulse signals via the isolator IS. The signal generation device 500 performs a predetermined logical operation on the input first and second input pulse signals to generate four output pulse signals (first to fourth output pulse signals), and corresponding driving. Output to the switches SW1 to SW4 of the apparatus 300. The first to fourth output pulse signals are signals whose voltage levels are switched between H and L, respectively.

  The first to fourth output pulse signals are input to the control terminals of the switches SW1 to SW4, respectively, and control the on / off of the switches SW1 to SW4. Details of the process in which the signal generation device 500 generates the first to fourth output pulse signals will be described later.

  FIG. 15 is a diagram illustrating a configuration example of a drive system 100x in a comparative example. The drive system 100x controls a single-phase inverter in which four switching elements are connected by a full bridge. The drive system 100x includes four drive devices 300 corresponding to the four switching elements.

  Four isolators IS are provided in front of the control terminals of the four switches SW1 to SW4 provided in the driving device 300.

  The input pulse generator 200 generates an input pulse signal for controlling on / off of the switches SW <b> 1 to SW <b> 4 of the driving device 300. Here, since there are a total of 16 switches, the input pulse generator 200 generates a total of 16 input pulse signals.

  As described above, in the drive system 100x of the comparative example, four types of input pulse signals are necessary for one switching element constituting the inverter, and thus there are 16 signal lines Ln1 that connect the input pulse generator 200 and the isolator IS. Necessary. Further, since an isolator IS is provided for each of the switches SW1 to SW4, a total of 16 isolators IS are required. Therefore, the drive system 100x of the comparative example has a problem that the number of signal lines Ln1 and isolators IS increases.

  On the other hand, the drive system 100 of FIG. 1 includes an output pulse generation unit 510 that generates four output pulse signals from two input pulse signals. Therefore, the input pulse generator 200 only needs to generate two input pulse signals. As a result, the number of isolators IS included in one signal generation device 500 is two, and the number of signal lines Ln1 that supply an input pulse signal to one signal generation device 500 is two. That is, in the drive system 100, the total number of isolators IS is 2 × 4 = 8, and the total number of signal lines Ln1 is 2 × 4 = 8. Therefore, the drive system 100 can reduce the number of wirings.

  Next, the case where the drive system 100 in FIG. 1 controls the DC-DC converter will be described as an example.

  FIG. 2 is a diagram illustrating a configuration example of the DC-DC converter 400 controlled by the drive device 300 of the present disclosure. In the DC-DC converter 400 of FIG. 2, the number of switching elements Q11 and Q12 is two, and thus the number of drive devices 300 that constitute the drive system 100 is two.

  The DC-DC converter 400 includes a reactor L11, an input smoothing capacitor C11, a low-side switching element Q11, a high-side switching element Q12, and an output smoothing capacitor C12. Switching elements Q11 and Q12 are driven by driving devices 300 and 300, respectively.

  First, the boosting operation will be described. When the driving device 300 performs on / off control of the low-side switching element Q11, the energy of the input power supply E11 moves to the smoothing capacitor C12 via the reactor L11. The voltage of the smoothing capacitor C12 is boosted with respect to the voltage of the input power supply E11. The boosted voltage is converted into an AC voltage by the inverter 30 and the motor 40 is driven by the AC voltage.

  Next, the step-down operation will be described. The AC power generated by the motor 40 is converted into DC power by the inverter 30, and the DC power is stored in the smoothing capacitor C12. When the driving device 300 performs on / off control of the high-side switching element Q12, the energy stored in the smoothing capacitor C12 moves to the input power source E11 via the reactor L11. The voltage of the input power supply E11 is stepped down with respect to the voltage of the smoothing capacitor C12.

  The driving devices 300 and 300 supply driving signals to the gates of the switching elements Q11 and Q12. The switching elements Q11 and Q12 are turned on and off by, for example, PWM control.

  FIG. 3 is a diagram illustrating a configuration example of the driving device 300 that controls the switching elements Q11 and Q12 illustrated in FIG. In FIG. 3, the driving device 300 controls the switching element Q11 of FIG.

  The driving device 300 and the signal generation device 500 may be mounted on the same substrate or may be mounted on separate substrates.

  The driving device 300 includes a power source E1, a resonance circuit unit 310, and a clamp unit 320. The resonant circuit unit 310 includes a coil L1 and a recovery unit. The recovery unit includes a switch SW1 (an example of a first switch), a switch SW2 (an example of a third switch), a diode D1, and a diode D2. The clamp unit 320 includes a switch SW3 (an example of a second switch), a switch SW4 (an example of a fourth switch), a diode D3, a diode D4, a resistor R1, and a resistor R2.

  A first potential line W1 is connected to the positive electrode of the power source E1. The first potential line W1 applies the first potential Vcc. The second potential line W2 is connected to the negative electrode of the power source E1. The second potential line W2 provides the second potential Vss. The first potential Vcc is higher than the second potential Vss.

  An input terminal Lt1 (an example of a first terminal) of the coil L1 of the resonance circuit unit 310 is connected to the first potential line W1 via the switch SW1. The input terminal Lt1 of the coil L1 is connected to the second potential line W2 via the switch SW2.

  The output side terminal Lt2 (an example of the second terminal) of the coil L1 is connected to the gate (an example of the control terminal) of the switching element Q11. The source of the switching element Q11 is connected to the negative electrode of the power source E1 by the second potential line W2. Therefore, the second potential Vss and the source potential of the switching element Q11 are common. With this connection, the coil L1 and the gate-source capacitance Ciss of the switching element Q11 constitute an LC series resonance circuit.

  In the present disclosure, the first potential line W1 may be a current path having the first potential Vcc, and may not be a wiring. Similarly, the second potential line W2 may be a current path having the second potential Vss, and may not be a wiring. For example, the current path that is not a wiring may be a current path formed by connecting the terminals of the circuit elements.

  The power supply E1 applies the first potential Vcc or the second potential Vss to the gate of the switching element Q11. For example, the power supply E1 fixes the gate potential of the switching element Q11 to the same potential as the first potential Vcc when the switching element Q11 is in the on state. Further, the power source E1 fixes the gate potential of the switching element Q11 to the same potential as the second potential Vss when the switching element Q11 is in the OFF state. In other words, the power source E1 applies a fixed voltage between the gate and the source of the switching element Q11 in a stable state after the switching of the switching element Q11 is completed.

  In the example shown in FIG. 3, the second potential Vss and the source of the switching element Q11 are at the same potential. Therefore, when the gate potential of the switching element Q11 is fixed at the first potential Vcc, the gate voltage (Vgs11) with the source of the switching element Q11 as a reference is equal to Vcc−Vss, that is, the voltage of the power supply E1. When the gate potential of the switching element Q11 is fixed to the second potential Vss, the gate voltage (Vgs11) based on the source of the switching element Q11 is 0V.

  Note that in this disclosure, “A and B are the same potential” and “A potential reaches B potential” means that, for example, between the potential of A and the potential of B This includes the case where a small potential difference derived from the on-resistance and the parasitic resistance of the electric circuit element occurs. The power source E1 may be arranged outside the driving device 300.

  The switch SW1 is provided between the first potential line W1 and the input side terminal Lt1 of the coil L1. The switch SW2 is provided between the second potential line W2 and the input side terminal Lt1 of the coil L1. In the example of FIG. 3, the switch SW1 is a P-channel type MOSFET, and the switch SW2 is an N-channel type MOSFET. A parasitic diode having a forward direction from the drain to the source is formed in the P-channel MOSFET. A parasitic diode having a forward direction from the source to the drain is formed in the N-channel MOSFET. Note that the switches SW1 and SW2 may be other switching elements such as bipolar transistors and relays, for example.

  The diode D1 is provided in the reverse direction between the first potential line W1 and the input side terminal Lt1 of the coil L1. The reverse direction is a direction in which current flows from the first potential Vcc side toward the second potential Vss side, with the cathode connected to the higher potential side and the anode connected to the lower potential side. . That is, the diode D1 is connected with a reverse bias between the first potential Vcc and the input side terminal Lt1 of the coil L1.

  The diode D2 is provided in the reverse direction between the second potential line W2 and the input side terminal Lt1 of the coil L1. That is, the diode D2 is connected with a reverse bias between the second potential Vss and the input side terminal Lt1 of the coil L1. The cathode of the diode D1 is connected to the first potential line W1. The anode of the diode D2 is connected to the second potential line W2. The diode D1 and the diode D2 may be, for example, a Schottky barrier diode.

  A series circuit of the switch SW3 and the resistor R1 is provided between the first potential line W1 and the output side terminal Lt2 of the coil L1. A series circuit of the switch SW4 and the resistor R2 is provided between the second potential line W2 and the output side terminal Lt2 of the coil L1. In the example of FIG. 1, the switch SW3 is a P-channel type MOSFET, and the switch SW4 is an N-channel type MOSFET.

  The diode D3 is provided in the reverse direction between the first potential line W1 and the output side terminal Lt2 of the coil L1. That is, the diode D3 is connected with a reverse bias between the first potential Vcc and the output side terminal Lt2 of the coil L1. The diode D4 is provided in the reverse direction between the second potential line W2 and the output side terminal Lt2 of the coil L1. That is, the diode D4 is connected with the reverse bias between the second potential Vss and the output side terminal Lt2 of the coil L1. The diode D3 and the diode D4 may be, for example, a Schottky barrier diode.

  The driving device 300 includes a bridge circuit including a coil L1, four switches SW1 to SW4, and four diodes D1 to D4. The switch SW3 and the diode D3 are connected in parallel. When the switch SW3 is in the ON state, when the gate potential of the switching element Q11 becomes higher than the first potential Vcc, current is drawn from the gate of the switching element Q11 through the diode D3. When the gate potential of the switching element Q11 becomes lower than the first potential Vcc, a current is supplied to the gate of the switching element Q11 via the switch SW3. Thus, when the switch SW3 is in the ON state, the gate potential of the switching element Q11 is clamped to the first potential Vcc.

  The switch SW4 and the diode D4 are connected in parallel. When the gate potential of the switching element Q11 becomes higher than the second potential Vss when the switch SW4 is in an on state, current is drawn from the gate of the switching element Q11 via the switch SW4. When the gate potential of the switching element Q11 becomes lower than the second potential Vss, a current is supplied to the gate of the switching element Q11 via the diode D4. Thus, when the switch SW4 is in the ON state, the gate potential of the switching element Q11 is clamped to the second potential Vss.

  The signal generation device 500 controls the switch SW1, the switch SW2, the switch SW3, and the switch SW4. Specifically, the signal generation device 500 inputs the first to fourth output pulse signals to the control terminals (gates in FIG. 1) of the switches SW1 to SW4, and turns on and off the switches SW1 to SW4. As a result, the gate-source voltage Vgs11 rises, and a gate current Ig11 is generated and supplied to the gate of the switching element Q11.

  When the switching element Q11 is turned on, first, the signal generating device 500 turns on the switch SW1. As a result, the capacitor Ciss between the gate (control terminal) and the source (reference terminal) of the switching element Q11 starts to be charged by the current supplied from the first potential line W1 that applies the first potential Vcc, and the coil L1 is charged. Energy is stored. Thereafter, the signal generation device 500 turns off the switch SW1. Then, a closed loop is formed by the coil L1, the capacitance Ciss of the switching element Q11, and the diode D2. And the capacity | capacitance Ciss of the switching element Q11 is further charged with the energy accumulate | stored in the coil L1.

  On the other hand, when turning off the switching element Q11, the signal generating device 500 first turns on the switch SW2. As a result, the capacitance Ciss of the switching element Q11 starts to be discharged, and the discharged energy is accumulated in the coil L1. Thereafter, the signal generation device 500 turns off the switch SW2. Then, the energy remaining in the coil C1 and the capacitance Ciss of the switching element Q11 is regenerated to the power source E1 via the diode D1.

  In the driving device 300 for driving the switching elements Q11 and Q12 as shown in FIG. 2, it is desired to reduce the switching loss in the switching elements Q11 and Q12. As the switching elements Q11 and Q12, for example, a voltage control type switching element such as a metal oxide semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT) is used.

  Switching elements Q11 and Q12 include a control terminal, a first conduction terminal, and a second conduction terminal. For example, when the switching elements Q11 and Q12 are MOSFETs, the control terminal is a gate, one of the first conduction terminal and the second conduction terminal is a source, and the other is a drain. For example, when the switching elements Q11 and Q12 are IGBTs, the control terminal is a gate, one of the first conduction terminal and the second conduction terminal is a collector, and the other is an emitter.

  One of the first conduction terminal and the second conduction terminal serves as a reference terminal serving as a reference for the voltage of the control terminal. The voltage-controlled switching element has a capacitance formed equivalently between the control terminal and the reference terminal.

  In the following description, the switching elements Q11 and Q12 are MOSFETs, the control terminal is a gate, the first conduction terminal is a source, the second conduction terminal is a drain, the source is a reference terminal, An example having a capacitor Ciss in between will be described. However, as described above, IGBTs can also be used as the switching elements Q11 and Q12.

  Next, the operation when the driving apparatus 300 shown in FIG. 3 controls the DC-DC converter 400 shown in FIG. 2 will be described.

  FIG. 4 is a timing chart schematically showing a simulation result of the driving device 300 when the switching element Q11 is turned on. In FIG. 4, section (a) is a timing chart of the DC-DC converter 400, where the vertical axis indicates voltage, current, and power, and the horizontal axis indicates time. Section (b) is a timing chart of the driving apparatus 300, where the vertical axis indicates voltage and current, and the horizontal axis indicates time. In FIG. 4, the charging time TA is set to 65 ns.

  During a charging time TA from time tm1 to time tm2, the switch SW1 is turned on. As a result, the gate current Ig11 is supplied from the first potential line W1 to the gate of the switching element Q11, the gate-source voltage Vgs11 of the switching element Q11 gradually increases, and the capacitor Ciss is charged. As a result, the drain-source current Ids11 of the switching element Q11 begins to increase, and the drain-source voltage Vds11 of the switching element Q11 begins to decrease.

  At time tm3, the voltage Vgs11 exceeds the threshold value. Thereby, the drain-source voltage Vds12 (FIG. 2) of the switching element Q12 starts to rise.

  At time tm4, the voltage Vds11 completely falls, the voltage Vds12 completely rises, and the current Ids11 completely rises.

  The waveform of the voltage Vds12 after the time tm4 should be essentially flat, but as shown in the section (a), the waveform of the voltage Vds has a wave. The undulation of this waveform is ringing, and the ringing voltage Vds (H). max is defined by the peak value of the voltage Vds12.

  Eon11 indicates a switching loss of the switching element Q11, starts to increase slightly before time tm3, reaches a peak at time tm3, and falls at time tm4.

  At time tm5, the switch SW3 is turned on. As a result, the voltage Vgs of the switching element Q11 is clamped at the first potential Vcc.

  FIG. 5 is a timing chart schematically showing a simulation result of the driving device 300 when turning on the switching element Q11 when the charging time TA is set longer than that in FIG. The section (a) of FIG. 5 is a timing chart of the DC-DC converter 400, where the vertical axis indicates voltage, current, and power, and the horizontal axis indicates time. Section (b) is a timing chart of the driving apparatus 300, where the vertical axis indicates voltage and current, and the horizontal axis indicates time. In FIG. 4, the charging time TA is set to 80 ns.

  The outline of the control in the timing chart of FIG. 5 is the same as FIG. 4, but in FIG. 5, the charging time TA is set longer than that in FIG. 4, and the SW speed is high. Therefore, in FIG. 5, the width of the waveform of the switching loss Eon11 is narrowed, and the switching loss Eon11 is reduced. In FIG. 5, the ringing voltage Vds (H). max is slightly higher. Further, in FIG. 5, with the increase in SW speed, the voltage change rates of the voltages Vds12 and Vds11 are higher than in FIG.

  Returning to FIG. 2, parasitic inductances Lp1 and Lp2 are generated in the negative connection line W11 and the positive connection line W12 between the DC-DC converter 400 and the inverter 30, respectively. Further, parasitic capacitances Cp1 and Cp2 are generated between the drain and source of the switching elements Q11 and Q12, respectively.

  If the SW speed of the switching elements Q11 and Q12 is increased and the response speed of the voltage between the drain and source of the switching elements Q11 and Q12 is increased, the switching loss can be reduced.

  However, when the SW speed of the switching elements Q11 and Q12 is increased, the following problem occurs. For example, consider the case where the switching element Q11 is turned on. In this case, the switching element Q11 is on and the switching element Q12 is off. Therefore, a resonance loop of the switching element Q11, the parasitic inductance Lp1, the inverter 30, the parasitic inductance Lp2, and the parasitic capacitance Cp2 is formed.

  As a result, the ringing voltage Vds (H) .H is applied across the parasitic capacitance Cp2 of the switching element Q12 that is turned off. max (the peak voltage of Vds12) is generated. Ringing voltage Vds (H). When max is increased, it is necessary to increase the breakdown voltage of the switching elements Q11 and Q12, leading to an increase in size and cost of the switching elements Q11 and Q12.

  In addition, since the present disclosure includes the isolator IS, the voltage change rate between the drain and the source of the switching elements Q11 and Q12 needs to be equal to or less than the voltage change rate specified by the common mode rejection voltage of the isolator IS.

  Therefore, a condition that the ringing voltage is set to a predetermined value or less, a condition that the voltage change rate between the drain and the source is set to a voltage change rate that is defined by the common mode rejection voltage of the isolator IS, and a condition that the switching loss is set to a predetermined loss or less The switching loss can be optimized by setting the fastest SW speed among the SW speeds satisfying all of the above.

  However, the ringing voltage, the drain-source voltage change rate, and the switching loss vary depending on load conditions such as current and voltage input to and output from the switching elements Q11 and Q12.

  Therefore, in the present disclosure, the fastest SW speed among SW speeds corresponding to a load state that satisfies the ringing voltage condition, the voltage change rate condition, and the switching loss condition is obtained in advance, and a setting table (not shown) is obtained. ). In the present disclosure, the load state is monitored, the SW speed corresponding to the monitored load state is read from the setting table, and the SW speed is changed for each pulse.

  Here, since the SW speed increases as the charging time TA increases, the charging time TA can be adopted as the SW speed. Further, as the load state, the input current Iin to the DC-DC converter 400, the output current Iout from the DC-DC converter 400, or the output voltage Vout from the DC-DC converter 400 can be adopted. The input current Iin can be monitored by connecting a current sensor in series with the reactor L11. Further, the output current Iout can be monitored by providing a current sensor in the connection line W12. The output voltage Vout can be monitored by providing a voltage sensor in parallel with the smoothing capacitor C12.

  For example, when the input current Iin is adopted as the load state, the setting table includes all of the input current Iin and the ringing voltage condition, voltage change rate condition, and switching loss condition for each input current Iin. Among the satisfied SW speeds, the charging time TA for realizing the fastest SW speed is stored in association with each other. The setting table is stored in the input pulse generation unit 200 shown in FIG. 1, and control for changing the SW speed according to the load state is performed by the input pulse generation unit 200.

  Returning to FIG. 1, since an isolator IS is provided in the present disclosure, the first and second input pulse signals must have a pulse width greater than or equal to the minimum pulse width defined by the isolator IS.

  Therefore, the pulse width of the output pulse signal applied to the switches SW1 to SW4 cannot be less than the minimum pulse width defined by the isolator IS. Therefore, as described above, when the control for changing the charging time TA according to the load state is adopted, the charging time TA cannot be made equal to or less than the minimum pulse width defined by the isolator IS. In this case, the degree of freedom in adjusting the charging time TA is lowered, and there is a possibility that the optimum charging time TA cannot be set according to the load state.

  Therefore, in the drive system 100 of the present disclosure, the signal generation device 500 is provided in order to make the pulse width of the output pulse signal equal to or less than the minimum pulse width defined by the isolator IS.

(Configuration of signal generation device 500)
Details of the signal generation device 500 will be described below. FIG. 6 is a diagram illustrating a configuration example of the signal generation device 500.

  FIG. 6 shows a signal generation device 500 of the drive device 300 corresponding to the switching element Q11 shown in FIG. 6 generates first to fourth output pulse signals for on / off control of the switches SW1 to SW4 of the driving device 300 shown in FIG.

  In the following description, the first input pulse signal is described as the input pulse signal INA, and the second input pulse signal is described as the input pulse signal INB. The first output pulse signal output to the switch SW1 is output pulse signal SH, the third output pulse signal output to the switch SW3 is output pulse signal MH, and the second output pulse signal output to the switch SW2 is output pulse. The signal SL and the fourth output pulse signal output to the switch SW4 will be described as the output pulse signal ML.

  The signal generation device 500 includes isolators IS1 and IS2 to which input pulse signals INA and INB are input, and an output pulse generation unit 510.

  The output pulse generator 510 has eight timings based on the combination of the level of one input pulse signal and the rising and falling timings of the other input pulse signal among the input pulse signals INA and INB output from the isolators IS1 and IS2. Is detected. Then, the output pulse generator 510 selects two timings from the detected eight timings and assigns them to the toggle timings of the output pulse signals SH, MH, SL, ML, and outputs the output pulse signals SH, MH, SL and ML are generated.

  The output pulse generator 510 includes two differentiators (DIVs) 521 and 522 corresponding to the input pulse signals INA and INB, a logic circuit 530 provided on the output side of the differentiator 521, and an output side of the logic circuit 530. And four flip-flops 541, 542, 543, and 544 corresponding to the output pulse signals SH, MH, SL, and ML, and an oscillator 550. Hereinafter, when the isolators IS1 and IS2 are not distinguished from each other, the isolators IS are represented as isolators IS. When the differentiators 521 and 522 are not distinguished from each other, the differentiators 520 are represented.

  The isolator IS is composed of, for example, a photocoupler, electrically isolates the input pulse generation unit 200 from the driving device 300 and the DC-DC converter 400, and extracts only the signal components of the input pulse signals INA and INB. Thereby, the voltage levels of the input pulse signals INA and INB are adjusted to the voltage level of the DC-DC converter.

  The isolator IS1 outputs the input pulse signal INA to the differentiator 521 and also outputs it to the logic circuit 530. The isolator IS2 outputs the input pulse signal INB to the differentiator 522 and outputs it to the logic circuit 530.

  Differentiators 521 and 522 detect edges indicating the rising or falling timing of the input pulse signals INA and INB.

  Specifically, the differentiator 521 detects an edge indicating the rising edge of the input pulse signal INA, outputs an edge pulse (hereinafter referred to as “PED_A”) to the logic circuit 530, and the input pulse signal INA. , And an edge pulse (hereinafter referred to as “NED_A”) is output to the logic circuit 530. Similarly to the differentiator 521, the differentiator 522 also has an edge pulse indicating the rising edge of the input pulse signal INB (hereinafter referred to as “PED_B”) and an edge pulse indicating the falling edge of the input pulse signal INB (hereinafter referred to as “NED_B”). Output to the logic circuit 530.

  The logic circuit 530 generates a toggle pulse indicating the toggle timing of the output pulse signals SH to ML based on the level of one input pulse signal of the input pulse signals INA and INB and the rising and falling timings of the other input pulse signal. Generated and output to the flip-flop 540.

  Here, toggle pulses input to the J and K terminals of the flip-flop 541 are represented as SH_J and SH_K, toggle pulses input to the J and K terminals of the flip-flop 542 are represented as MH_J and MH_K, and J and K of the flip-flop 543 are represented. Toggle pulses input to the terminals are denoted as SL_J and SL_K, and toggle pulses input to the J and K terminals of the flip-flop 544 are denoted as ML_J and ML_K.

  The logic circuit 530 sets the levels of the toggle pulses SH_J and SH_K to H and L when the output pulse signal SH is raised, and sets the levels of the toggle pulses SH_J and SH_K to L and H when the output pulse signal SH is lowered.

  The logic circuit 530 sets the levels of the toggle pulses MH_J and MH_K to H and L when the output pulse signal MH is raised, and sets the levels of the toggle pulses MH_J and MH_K to L and H when the output pulse signal MH is lowered.

  The logic circuit 530 sets the levels of the toggle pulses SL_J and SL_K to H and L when the output pulse signal SL is raised, and sets the levels of the toggle pulses SL_J and SL_K to L and H when the output pulse signal SL is lowered.

  The logic circuit 530 sets the levels of the toggle pulses ML_J and ML_K to H and L when the output pulse signal ML is raised, and sets the levels of the toggle pulses ML_J and ML_K to L and H when the output pulse signal ML is lowered.

  The flip-flops 541, 542, 543, and 544 output output pulse signals SH, MH, SL, and ML.

  Here, the flip-flop 540 raises the output pulse signal when the clock CLK falls when the levels of the J and K terminals are H and L, and the clock when the level of the J and K terminals is L and H. When CLK falls, the output pulse signal falls. Note that the flip-flop 540 may raise and lower the output pulse signal in synchronization with the rise of the clock CLK instead of the fall.

  The oscillator 550 outputs a clock CLK to the flip-flop 540. Here, it is assumed that the cycle of the clock CLK is significantly smaller than the pulse width of PED_A to PED_B.

  FIG. 7 is a timing chart showing processing of the output pulse generator 510. In FIG. 7, section (a) shows the waveforms of input pulse signals INA and INB, section (b) shows the waveforms of PED_A to NED_B, and section (c) shows the output pulse signal SH output from logic circuit 530. Toggle pulses SH_J and SH_K for determining the toggle timing are shown, and section (d) shows the waveform of the output pulse signal SH.

  Each waveform shown in FIG. 7 fluctuates at two levels: a high level (hereinafter described as “H”) and a low level (hereinafter described as “L”).

  Hereinafter, the generation of PED_A to NED_B means that the levels of PED_A to NED_B are set to H. The generation of the toggle pulses SH_J and SH_K means that the levels of the toggle pulses SH_J and SH_K are set to H.

  Referring to section (a), input pulse signal INA is a periodic signal in which pulses PS1 and PS2 are repeated, and input pulse signal INB is a periodic signal in which pulses PS3 and PS4 are repeated. In this example, the rise timing (time t1) of the pulse PS3 is earlier than the rise timing (time t2) of the pulse PS1, the fall timing of the pulse PS3 (time t3), and the fall timing of the pulse PS1 (time t4). Is set faster than. In this example, the rising timing (time t5) of the pulse PS2 is earlier than the rising timing (time t6) of the pulse PS4, the falling timing of the pulse PS2 (time t7), and the falling timing (time of the pulse PS4) It is set faster than t8). In this example, the pulse widths of the pulses PS1 to PS4 are set to the same value.

  Referring to section (b), at time t1, differentiator 522 detects the rising edge of input pulse signal INB and outputs PED_B to logic circuit 530.

  At time t2, the differentiator 521 detects the rising edge of the input pulse signal INA and outputs PED_A to the logic circuit 530.

  At time t3, the differentiator 522 detects the falling edge of the input pulse signal INB and outputs NED_B to the logic circuit 530.

  At time t4, the differentiator 521 detects the falling edge of the input pulse signal INA and outputs NED_A to the logic circuit 530.

  Thereafter, as shown at times t5 to t8, PED_A and PED_B are output to the logic circuit 530 in response to rising of the input pulse signals INA and INB, and NED_A and NED_B are in logic in response to the falling of the input pulse signals INA and INB. It is output to the circuit 530.

  Referring to section (c), at time t2, logic circuit 530 sets PED_A = H, INB = H, and the logical product of both signals to H, so that the level of toggle pulse SH_J is set to H, and J of flip-flop 541 Input to the terminal. At this time, since NED_B = L, the toggle pulse SH_K having the level L is input to the K terminal of the flip-flop 541. In this state, when the clock CLK from the oscillator 550 falls, the flip-flop 541 raises the output pulse signal SH because the level of the J terminal is H and the level of the K terminal is L.

  At time t3, the logic circuit 530 sets NED_B = H, INA = H, and the logical product of both signals to H, so that the level of the toggle pulse SH_K is set to H and input to the K terminal of the flip-flop 541. At this time, since PED_A = L, the toggle pulse SH_J having the level L is input to the J terminal of the flip-flop 541. When the clock CLK is lowered from the oscillator 550 in this state, the flip-flop 541 causes the output pulse signal SH to fall because the level of the J terminal is L and the level of the K terminal is H.

  As a result, an output pulse signal SH having a pulse width that rises at time t2 and falls at time t3 is generated (section (d)).

  Here, the output pulse signal SH rises at the timing when the input pulse signal INA rises (time t2), and falls at the timing when the input pulse signal INB falls (time t3). Therefore, the pulse width SH_W of the output pulse signal SH can be made shorter than the pulse widths INA_W and INB_W of INA and INB. Thereby, an output pulse signal SH having a pulse width equal to or smaller than the minimum pulse width defined by the isolator IS can be generated.

  As described above, in the present disclosure, the input pulse signals INA and INB are out of phase, and therefore the input pulse signals INA and INB have four rising or falling timings. The input pulse signals INA and INB have two levels of H and L. Therefore, 4 × 2 = 8 kinds of toggle timings can be detected by combining the rising or falling timing (4 kinds) of one input pulse signal with the level (2 kinds) of the other input pulse signal.

  A maximum of 8 × 7 = 56 output pulse signals can be generated by combining any two of the eight toggle timings.

  Therefore, in the present disclosure, desired four output pulse signals are selected in advance from 56 output pulse signals. Then, a logic that can obtain four output pulse signals selected in advance from the rising or falling timing of one input pulse signal and the level of the other input pulse signal is assembled in advance in the logic circuit 530. Let it be implemented. Thereby, an output pulse signal having a desired pulse width is obtained.

  In the present disclosure, the level of the output pulse signal is inverted at the falling timing of the clock CLK. Therefore, for example, in the section (a) of FIG. 7, the difference between the rising timing of the input pulse signal INA and the falling timing of the input pulse signal INB is set to be equal to the cycle of the clock CLK, and the duty of the clock CLK is set. If the ratio is 50%, the minimum pulse width of the output pulse signal can be set to be equal to the cycle of the clock CLK. Therefore, the present disclosure can significantly reduce the minimum pulse width of the output pulse signal as compared with Patent Document 1.

  Furthermore, in the present disclosure, the rising or falling timing of the output pulse signal is determined by a combination of the rising or falling timing of one input pulse signal and the level of the other input pulse signal. For this reason, it is possible to prevent a plurality of output pulse signals from rising or falling at the rising or falling timing of one input pulse signal.

(Charging method)
Next, a specific example of processing in which the output pulse generation unit 510 generates the output pulse signals SH to ML will be described. FIG. 8 shows timing when the output pulse generator 510 generates the output pulse signals SH to ML from the input pulse signals INA and INB when the driving device 300 adopts a mode in which the switching device Q11 is controlled by the charging method. It is a chart. The charging method is a method of adjusting the SW speed by adjusting the charging time TA.

  In the example of FIG. 8, the input pulse signal INA is a periodic signal in which pulses PS81 and PS82 are repeated, and the input pulse signal INB is a periodic signal in which pulses PS83 and PS84 are repeated. In this example, the rising timing (time t1) of the pulse PS83 is earlier than the rising timing (time t2) of the pulse PS81, and the falling timing (time t3) of the pulse PS83 is the falling timing (time t4) of the pulse PS81. Is set faster than. Further, in this example, the rising timing (time t5) of the pulse PS82 is earlier than the rising timing (time t6) of the pulse PS84, and the falling timing (time t7) of the pulse PS82 is the falling timing (time) of the pulse PS84. It is set faster than t8).

(Generation of output pulse signal SH)
When the logic circuit 530 detects the rising timing of the input pulse signal INA when the level of the input pulse signal INB is H (time t2), the logic circuit 530 selects this timing as the rising timing of the output pulse signal SH. Then, the logic circuit 530 sets the levels of the toggle pulses SH_J and SH_K to H and L. As a result, the output pulse signal SH rises.

  Further, when the logic circuit 530 detects the timing when the input pulse signal INB falls when the level of the input pulse signal INA is H (time t3), the logic circuit 530 selects this timing as the falling timing of the output pulse signal SH. Then, the logic circuit 530 sets the levels of the toggle pulses SH_J and SH_K to L and H. As a result, the output pulse signal SH falls.

(Generation of output pulse signal MH)
When the logic circuit 530 detects the timing when the input pulse signal INA falls when the level of the input pulse signal INB is L (time t4), the logic circuit 530 selects this timing as the rising timing of the output pulse signal MH. Then, the logic circuit 530 sets the levels of the toggle pulses MH_J and MH_K to H and L. As a result, the output pulse signal MH rises.

  Further, when the logic circuit 530 detects the rising timing of the input pulse signal INA when the level of the input pulse signal INB is L (time t5), the logic circuit 530 selects this timing as the falling timing of the output pulse signal MH. Then, the logic circuit 530 sets the levels of the toggle pulses MH_J and MH_K to L and H. As a result, the output pulse signal MH falls.

(Generation of output pulse signal SL)
When the logic circuit 530 detects the rising timing of the input pulse signal INB when the level of the input pulse signal INA is H (time t6), the logic circuit 530 selects this timing as the rising timing of the output pulse signal SL. Then, the logic circuit 530 sets the levels of the toggle pulses SL_J and SL_K to H and L. Thereby, the output pulse signal SL rises.

  Further, when the logic circuit 530 detects the timing when the input pulse signal INA falls when the level of the input pulse signal INB is H (time t7), the logic circuit 530 selects this timing as the falling timing of the output pulse signal SL. Then, the logic circuit 530 sets the levels of the toggle pulses SL_J and SL_K to L and H. As a result, the output pulse signal SL falls.

(Generation of output pulse signal ML)
When the logic circuit 530 detects the timing when the input pulse signal INB falls when the level of the input pulse signal INA is L (time t8), the logic circuit 530 selects this timing as the rising timing of the output pulse signal ML. Then, the logic circuit 530 sets the levels of the toggle pulses ML_J and ML_K to H and L. Thereby, the output pulse signal ML rises.

  In addition, when the logic circuit 530 detects the rising timing of the input pulse signal INB when the level of the input pulse signal INA is L (time t1), the logic circuit 530 selects this timing as the falling timing of the output pulse signal ML. Then, the logic circuit 530 sets the levels of the toggle pulses ML_J and ML_K to L and H. As a result, the output pulse signal ML falls.

  The output pulse signal SH has the rising timing set to the rising timing of the input pulse signal INA, but the falling timing is set to the falling timing of the input pulse signal INB.

  Similarly, the rising timing of the output pulse signal SL is set to the rising timing of the input pulse signal INB, but the falling timing is set to the falling timing of the input pulse signal INA.

  Therefore, the pulse widths of the output pulse signals SH and SL can be made equal to or smaller than the pulse width of the input pulse signals INA and INB. Thereby, the charging time TA can be set with a pulse width equal to or smaller than the minimum pulse width defined by the isolator IS.

  Next, the operation of the driving apparatus 300 when the charging method is adopted will be briefly described with reference to FIG. 3 as appropriate and using the timing chart of FIG. In the initial state, the switching element Q11 is turned off. At time t1, the output pulse signal ML falls, the switch SW4 is turned off, and the process of clamping the gate of the switching element Q11 at the second potential VSS is completed.

  At time t2, in order to turn on the switching element Q11, the output pulse signal SH is raised, the switch SW1 is turned on, and charging of the gate-source capacitor Ciss is started.

  At time t3, the output pulse signal SH falls, the switch SW1 is turned off, and charging of the capacitor Ciss is completed. The SW speed is adjusted by adjusting the charging time TA from time t2 to time t3.

  At time t4, the output pulse signal MH is raised, the switch SW3 is turned on, and the process of clamping the gate of the switching element Q11 at the first potential Vcc is started.

  At time t5, the output pulse signal MH falls, the switch SW3 is turned off, and the process of clamping the gate of the switching element Q11 at the first potential Vcc is completed.

  At time t6, in order to turn off the switching element Q11, the output pulse signal SL is raised, the switch SW2 is turned on, and the discharge of the capacitor Ciss is started.

  At time t7, the output pulse signal SL falls, the switch SW2 is turned off, and the discharge of the capacitor Ciss is completed. Here, the period from time t6 to t7 is the discharge time. During the discharge time, the switch SW2 is turned on, and charges are extracted from the capacitor Ciss.

  At time t8, the output pulse signal ML is raised, and the process of clamping the gate of the switching element Q11 at the second potential Vss is started.

  The above operation is repeated, and the switching element Q11 is on / off controlled. In the charging method, the SW speed can be adjusted by adjusting the charging time TA and the discharging time.

  In FIG. 9, the phase difference and the pulse width of the input pulse signals INA and INB are determined in advance so that the desired charging time TA and discharging time can be obtained.

  The driving device 300 may adjust the SW speed of the switching element Q11 using a method other than the charging method. As other methods, there are a clamp advance method and a precharge method.

(Clamp advance method)
The clamp forward method is a method in which the switch SW3 is turned on before the switch SW1 is turned off when the switching element Q11 is turned on. In the clamp forward method, the SW speed is adjusted by adjusting the forward time during which the switches SW1 and SW3 are on.

  In the example of FIG. 9, the input pulse signal INA is a periodic signal in which pulses PS91 and PS92 are repeated, and the input pulse signal INB is a periodic signal in which pulses PS93 and PS94 are repeated. In this example, the rising and falling timings (time t1, t2) of the pulse PS93 are set faster than the rising timing (time t3) of the pulse PS91. The falling timing (time t5) of the pulse PS91 is set later than the rising timing (time t4) of the pulse PS94. In this example, the rising timing (time t6) of the pulse PS92 is set faster than the falling timing (time t7) of the pulse PS94.

  FIG. 9 shows a process in which the output pulse generator 510 generates the output pulse signals SH to ML from the input pulse signals INA and INB when the driving device 300 adopts a mode in which the switching element Q11 is controlled by the clamp advance method. It is a timing chart.

(Generation of output pulse signal SH)
When the logic circuit 530 detects the timing when the input pulse signal INB falls when the level of the input pulse signal INA is L (time t2), the logic circuit 530 selects this timing as the rising timing of the output pulse signal SH. Then, the logic circuit 530 sets the levels of the toggle pulses SH_J and SH_K to H and L. As a result, the output pulse signal SH rises.

  In addition, when the logic circuit 530 detects the rising timing of the input pulse signal INB when the level of the input pulse signal INA is H (time t4), the logic circuit 530 selects this timing as the falling timing of the output pulse signal SH. Then, the logic circuit 530 sets the levels of the toggle pulses SH_J and SH_K to L and H. As a result, the output pulse signal SH falls.

(Generation of output pulse signal MH)
When the logic circuit 530 detects the rising timing of the input pulse signal INA when the level of the input pulse signal INB is L (time t3), the logic circuit 530 selects this timing as the rising timing of the output pulse signal MH. Then, the logic circuit 530 sets the levels of the toggle pulses MH_J and MH_K to H and L. As a result, the output pulse signal MH rises.

  Further, when the logic circuit 530 detects the timing when the input pulse signal INA falls when the level of the input pulse signal INB is H (time t5), the logic circuit 530 selects this timing as the falling timing of the output pulse signal MH. Then, the logic circuit 530 sets the levels of the toggle pulses MH_J and MH_K to L and H. As a result, the output pulse signal MH falls.

(Generation of output pulse signal SL)
When the logic circuit 530 detects the rising timing of the input pulse signal INA when the level of the input pulse signal INB is H (time t6), the logic circuit 530 selects this timing as the rising timing of the output pulse signal SL. Then, the logic circuit 530 sets the levels of the toggle pulses SL_J and SL_K to H and L. Thereby, the output pulse signal SL rises.

  Further, when the logic circuit 530 detects the timing when the input pulse signal INA falls when the level of the input pulse signal INB is L (time t8), the logic circuit 530 selects this timing as the falling timing of the output pulse signal SL. Then, the logic circuit 530 sets the levels of the toggle pulses SL_J and SL_K to L and H. As a result, the output pulse signal SL falls.

(Generation of output pulse signal ML)
When the logic circuit 530 detects the timing when the input pulse signal INB falls when the level of the input pulse signal INA is H (time t7), the logic circuit 530 selects this timing as the rising timing of the output pulse signal ML. Then, the logic circuit 530 sets the levels of the toggle pulses ML_J and ML_K to H and L. Thereby, the output pulse signal ML rises.

  In addition, when the logic circuit 530 detects the rising timing of the input pulse signal INB when the level of the input pulse signal INA is L (time t1), the logic circuit 530 selects this timing as the falling timing of the output pulse signal ML. Then, the logic circuit 530 sets the levels of the toggle pulses ML_J and ML_K to L and H. As a result, the output pulse signal ML falls.

  In the example of FIG. 9, the output pulse signals SH to ML are set to rise or fall timings of the same input pulse signal.

  Therefore, the minimum pulse width of the output pulse signals SH to ML cannot be made shorter than the minimum pulse width of the input pulse signals INA and INB. However, when it is considered that the input pulse signals INA and INB correspond to the first control signal C1 of Patent Document 1, in Patent Document 1, the period in which the first control signal C1 is one order is an output pulse signal (switch switching signal). Si) is the minimum pulse width. On the other hand, in the present disclosure, the minimum pulse width of the input pulse signals INA and INB can be set to the minimum pulse width of the output pulse signals SH to ML as they are. Therefore, the minimum pulse width of the output pulse signals SH to ML can be shortened compared to Patent Document 1.

  Next, with reference to FIG. 3 as appropriate, the operation of the driving device 300 in the case of adopting the forward clamping method will be briefly described with reference to the timing chart of FIG. The difference from FIG. 8 is that in FIG. 8, the output pulse signal MH is raised after the output pulse signal SH is lowered (time t3 to t4), but in FIG. 9, the output pulse signal SH is The output pulse signal MH is raised before the signal is lowered (time t3 to t4). Here, the period from time t3 to t4 is described as forward time TB.

  In FIG. 8, the output pulse signal ML is raised after the output pulse signal SL is lowered (time t7 to t8). In FIG. 9, before the output pulse signal SL is lowered. The output pulse signal ML is raised (time t7 to t8). Here, the period from time t7 to t8 also corresponds to the advance time.

  In the advance time TB, since the switches SW1 and SW3 are turned on, the charging speed of the gate capacitance Ciss is increased, and the SW speed is increased accordingly. Further, since the switches SW2 and SW4 are on during the advance time from time t7 to time t8, the charge discharging rate from the gate capacitance Ciss is increased, and the SW rate is increased accordingly.

  In FIG. 9, the phase difference and pulse width of the input pulse signals INA and INB are determined in advance so that a desired advance time TB can be obtained.

  Further, similarly to the configuration of FIG. 8, the SW speed can be controlled more variously by controlling the period (t2 to t3) in which only SH is on.

(Precharge method)
The precharge method is a method in which the switch SW4 is turned off after the switch SW1 is turned on when the switching element Q11 is turned on. In the precharge method, the SW speed is adjusted by adjusting the precharge time in which the switches SW1 and SW4 are on.

  FIG. 10 shows a process in which the output pulse generator 510 generates the output pulse signals SH to ML from the input pulse signals INA and INB when the driving device 300 adopts a mode in which the switching element Q11 is controlled by the precharge method. It is a timing chart.

  In the example of FIG. 10, the input pulse signal INA is a periodic signal in which pulses PS101 and PS102 are repeated, and the input pulse signal INB is a periodic signal in which pulses PS103 and PS104 are repeated. In this example, the rising timing (time t1) of the pulse PS103 is earlier than the rising timing (time t2) of the pulse PS101, and the falling timing (time t3) of the pulse PS103 is the falling timing (time t4) of the pulse PS101. Is set faster than. In this example, the rise timing (time t5) of the pulse PS102 is earlier than the rise timing (time t6) of the pulse PS104, and the fall timing (time t7) of the pulse PS102 is the fall timing (time t7) of the pulse PS104. It is set faster than t8).

(Generation of output pulse signal SH)
When the logic circuit 530 detects the rising timing of the input pulse signal INB when the level of the input pulse signal INA is L (time t1), the logic circuit 530 selects this timing as the rising timing of the output pulse signal SH. Then, the logic circuit 530 sets the levels of the toggle pulses SH_J and SH_K to H and L. As a result, the output pulse signal SH rises.

  Further, when the logic circuit 530 detects the timing when the input pulse signal INB falls when the level of the input pulse signal INA is H (time t3), the logic circuit 530 selects this timing as the falling timing of the output pulse signal SH. Then, the logic circuit 530 sets the levels of the toggle pulses SH_J and SH_K to L and H. As a result, the output pulse signal SH falls.

(Generation of output pulse signal MH)
When the logic circuit 530 detects the timing when the input pulse signal INA falls when the level of the input pulse signal INB is L (time t4), the logic circuit 530 selects this timing as the rising timing of the output pulse signal MH. Then, the logic circuit 530 sets the levels of the toggle pulses MH_J and MH_K to H and L. As a result, the output pulse signal MH rises.

  Further, when the logic circuit 530 detects the timing when the input pulse signal INB rises when the level of the input pulse signal INA is H (time t6), the logic circuit 530 selects this timing as the falling timing of the output pulse signal MH. Then, the logic circuit 530 sets the levels of the toggle pulses MH_J and MH_K to L and H. As a result, the output pulse signal MH falls.

(Generation of output pulse signal SL)
When the logic circuit 530 detects the rising timing of the input pulse signal INA when the level of the input pulse signal INB is L (time t5), the logic circuit 530 selects this timing as the rising timing of the output pulse signal SL. Then, the logic circuit 530 sets the levels of the toggle pulses SL_J and SL_K to H and L. Thereby, the output pulse signal SL rises.

  Further, when the logic circuit 530 detects the timing when the input pulse signal INA falls when the level of the input pulse signal INB is H (time t7), the logic circuit 530 selects this timing as the falling timing of the output pulse signal SL. Then, the logic circuit 530 sets the levels of the toggle pulses SL_J and SL_K to L and H. As a result, the output pulse signal SL falls.

(Generation of output pulse signal ML)
When the logic circuit 530 detects the timing when the input pulse signal INB falls when the level of the input pulse signal INA is L (time t8), the logic circuit 530 selects this timing as the rising timing of the output pulse signal ML. Then, the logic circuit 530 sets the levels of the toggle pulses ML_J and ML_K to H and L. Thereby, the output pulse signal ML rises.

  In addition, when the logic circuit 530 detects the timing when the input pulse signal INA rises when the level of the input pulse signal INB is H (time t2), the logic circuit 530 selects this timing as the falling timing of the output pulse signal ML. Then, the logic circuit 530 sets the levels of the toggle pulses ML_J and ML_K to L and H. As a result, the output pulse signal ML falls.

  In the example of FIG. 10, the output pulse signals SH and SL with shorter pulse widths are set to rise and fall timings of the same input pulse signal.

  Therefore, in FIG. 10, the minimum pulse width of the output pulse signals SH to ML cannot be made shorter than the minimum pulse width of the input pulse signals INA and INB. However, for the same reason as in FIG. The minimum pulse width of the output pulse signals SH to ML can be shortened.

  Next, the operation of the driving device 300 when the precharge method is adopted will be briefly described with reference to FIG. 3 as appropriate and using the timing chart of FIG. 8 is different from FIG. 8 in that the output pulse signal SH is raised after the output pulse signal ML is lowered (time t1 to t2), but in FIG. 10, the output pulse signal SH is different from that in FIG. Is raised, the output pulse signal ML is lowered (time t1 to t2). Here, the period from time t1 to t2 is described as precharge time TC.

  In FIG. 8, the output pulse signal SL is raised after the output pulse signal MH is lowered (time t5 to t6). In FIG. 10, after the output pulse signal SL is raised. The output pulse signal MH is lowered (time t5 to t6).

  In the precharge time TC, since the switches SW1 and SW4 are turned on, the switch SW1 can be turned on while the energy is charged in the coil L1, and the charging speed of the gate capacitance Ciss is increased accordingly. SW speed is increased.

  In FIG. 10, the phase difference and pulse width of the input pulse signals INA and INB are determined in advance so that a desired precharge time TC is obtained.

  Further, as in the configuration of FIGS. 8 and 9, the time during which only SH is on (t2 to t3) and the time during which all switches are off (t3 to t4) are also controlled. SW speed can be controlled.

  Next, the optimum driving of the switching element according to the load state will be described.

  FIG. 11 is a graph showing a result of an experiment performed for obtaining an optimum charging time according to a load state. In the example of FIG. 11, an input current Iin or an output current Iout (hereinafter referred to as current ID) output from the DC-DC converter 400 is adopted as the load state. FIG. 11 shows experimental results when the DC-DC converter 400 and the driving device 300 shown in FIGS. 2 and 3 are used. In FIG. 11, the driving device 300 is driven by a charging method. Therefore, the charging time indicates the on time of the switch SW1.

  The graph in the left column in FIG. 11 shows the experimental results when the charging time is set to 65 ns, 70 ns, 75 ns, 80 ns, and 85 ns.

  Moreover, the graph of the right column in FIG. 11 has shown the experimental result when a charging time is set to 65 ns and a charging time is set to the optimal value. In the graph in the right column of FIG. 11, the experiment result of the optimum value is plotted with a triangle mark and the experiment result of 65 ns is plotted with a diamond mark for each current ID. Here, the optimum value is a charging time in which the peak voltage (Vds (H) .max: ringing voltage) between the drain and source of the switching element Q12 can be set to 330 V or less, and the maximum charging time is adopted. Is done.

  In FIG. 11, section (a) is a graph showing the relationship between the ringing voltage (Vds (H) .max) and the current ID according to the charging time, the vertical axis shows the ringing voltage, and the horizontal axis shows the current. ID is shown.

  Section (b) is a graph showing the relationship between the switching loss (Eon) and the current ID according to the charging time, the vertical axis shows the loss, and the horizontal axis shows the current ID.

  Section (c) is a graph showing the relationship between the voltage change rate (dV (L) / dt) of the drain-source voltage V (L) of the switching element Q11 and the current ID according to the charging time, The vertical axis represents the voltage change rate, and the horizontal axis represents the current ID.

  Section (d) is a graph showing the relationship between the voltage ID (dV (H) / dt) of the voltage V (H) between the drain and source of the switching element Q12 and the current ID according to the charging time. The vertical axis represents the voltage change rate, and the horizontal axis represents the current ID.

  As shown in the left column of section (a), it can be seen that the ringing voltage (Vds (H) .max) increases as the charging time increases. Therefore, in the graph in the left column of section (a), in each current ID, the experimental results of 65 ns, 70 ns, 75 ns, 80 ns, and 85 ns are plotted with rhombus marks in order from the lowest voltage side.

  Here, the condition that the ringing voltage (Vds (H) .max) is set to 330 V or less is imposed, and the charging time for which the ringing voltage can be set to 330 V or less is 65 ns in all current IDs. Therefore, in a method that employs a configuration that does not change the charging time according to the load state (hereinafter referred to as “method of comparative example”), 65 ns is set as the charging time. This makes it impossible to set an optimal charging time according to the current ID. For example, when the current ID is 20 A, the charging time is set to 65 ns in the method of the comparative example even though the ringing voltage (Vds (H) .max) is 330 V or less even if the charging time is set to 80 ns. Therefore, the optimum value is not set.

  Therefore, in the method of the present embodiment (hereinafter referred to as “proposed method”), as shown in the right column of section (a), the ringing voltage (Vds (H) .max) is set for each current ID. The maximum charging time is set out of the charging time that can be 330V or less. As a result, the charging time is optimized.

  As shown in the left column of section (b), it can be seen that the switching loss increases as the charging time decreases. Therefore, in the graph in the left column of section (b), the experimental results of 85 ns, 80 ns, 75 ns, 70 ns, and 65 ns are plotted with rhombus marks in order from the lowest switching loss in each current ID.

  In the right column of section (b), the switching loss for each current ID when the optimum value of the charging time set in section (a) is adopted is plotted with a triangular mark. In this case, the switching loss of the proposed method is lower than that of the comparative example in the total current ID, and the switching loss is improved by 18% when the current ID is 20A.

  As shown in the left column of section (c), the voltage change rate (dV (L) / dt) increases as the charging time increases, as does the ringing voltage (Vds (H) .max). I understand. Therefore, in the graph in the left column of section (c), in each current ID, the voltage change rate (dV (L) / dt) has a diamond shape of the experimental results of 65 ns, 70 ns, 75 ns, 80 ns, and 85 ns in order from the lowest. It is plotted with the mark.

  In the right column of section (c), the voltage change rate (dV (L) / dt) for each current ID when the optimum value of the charging time set in section (a) is adopted is plotted with a triangle mark. Yes. In this case, the voltage change rate (dV (L) / dt) is higher in the proposed method than in the comparative example in all current IDs.

  As shown in the left column of section (d), the voltage change rate (dV (H) / dt) increases as the charging time increases, as does the ringing voltage (Vds (H) .max). I understand. Therefore, in the graph in the left column of section (d), the voltage change rate (dV (H) / dt) for each current ID has a diamond shape of the experimental results of 65 ns, 70 ns, 75 ns, 80 ns, and 85 ns in order from the lowest. It is plotted with the mark.

  In the right column of section (d), the voltage change rate (dV (H) / dt) for each current ID when the optimum value of the charging time set in section (a) is adopted is plotted with a triangle mark. Yes. In this case, the voltage change rate (dV (L) / dt) is higher in the proposed method than in the comparative example in all current IDs.

  In FIG. 12, section (a) is a graph showing the relationship between ringing voltage (Vds (H) .max) and charging time, and section (b) shows voltage change rate (dV (L) / dt) and charging. It is the graph which showed the relationship with time, the section (c) is the graph which showed the relationship between switching loss (Eon) and charging time, and the section (d) is a voltage change rate (dV (H) / dt). It is the graph which showed the relationship between charging time.

  As shown in sections (a), (b), (d), the ringing voltage (Vds (H) .max), the voltage change rate (dV (L) / dt), and the voltage change rate (dV (H) / While dt) increases with increasing charging time, switching loss (Eon) decreases with increasing charging time, as shown in section (c). This is because the ringing voltage (Vds (H) .max), voltage change rate (dV (L) / dt), and voltage change rate (dV (H) / dt) increase as the SW speed increases. However, the switching loss (Eon) has a characteristic of decreasing as the SW speed increases.

  In the present disclosure, as indicated by the triangular mark in section (b) of FIG. 11, the charging time that satisfies the condition that the ringing voltage (Vds (H) .max) is 330 V or less for each current ID. Among these, the maximum charging time is obtained in advance and stored in the setting table.

  In this case, the input pulse generation unit 200 monitors the current ID, and reads the charging time corresponding to the current value of the monitored current ID from the setting table. The input pulse generation unit 200 stores waveform data of the input pulse signals INA and INB corresponding to the charging time in advance. Therefore, in the example of the right column in section (a) of FIG. 11, the input pulse generation unit 200 sets 80 ns as the charging time if the current value of the monitored current ID is 20 A, and the input pulse corresponding to 80 ns. The signals INA and INB are output to the driving device 300.

  Here, the optimal charging time for each current ID is set under the condition that the ringing voltage (Vds (H) .max) is set to 330 V or less, but the present disclosure is not limited to this. For example, the ringing voltage (Vds (H) .max) is set to a predetermined voltage or less, the switching loss is set to a predetermined loss or less, the voltage change rate (dV (L) / dt) is set to a predetermined change rate or less, and the voltage change rate Among the charging times that can satisfy at least one of the conditions of setting (dV (H) / dt) to a predetermined rate of change, the maximum charging time for each current ID is stored in the setting table. It may be left.

  In the above description, the optimal charging time is stored in the setting table in accordance with each current ID. However, if the driving device 300 adopts the clamp advance method, the charging time is replaced with the above charging time. The advance time (TB in FIG. 9) that can satisfy at least one of the four conditions, and the maximum advance time for each current ID may be stored in the setting table. Alternatively, both the charging time and the advance time for each current ID may be stored in the setting table.

  Further, if the driving device 300 adopts a precharge method, it is a precharge time (TC in FIG. 10) that can satisfy at least one of the above four conditions, and a current ID. The maximum precharge time for each may be stored in the setting table. Alternatively, the precharge time, the charge time, and the advance time for each current ID may be stored in the setting table.

  The present disclosure is useful for the technical field of power devices such as DC-DC converters.

INA, INB Input pulse signal IS, IS1, IS2 Isolator L1 Coil Q11, Q12 Switching element SH, MH, SL, ML Output pulse signal 100 Drive system 200 Input pulse generator 300 Driver 500 Signal generator 510 Output pulse generator 520 , 521, 522 Differentiator 530 Logic circuit 540, 541, 542, 543, 544 Flip-flop 550 Oscillator

Claims (6)

A first for controlling the first to fourth switches of the device to be controlled using the first and second input pulse signals that are switched between the first level and a second level different from the first level. A signal generation device for generating a fourth output pulse signal,
The first and second input pulse signals have a pulse width equal to or greater than a minimum pulse width defined by an isolator,
An isolator to which the first and second input pulse signals are input;
Of the first and second input pulse signals output from the isolator, eight timings are detected from a combination of the level of one input pulse signal and the rising and falling timings of the other input pulse signal, and the detection An output pulse generator that selects any two of the eight timings and assigns them to the toggle timing of the first to fourth output pulse signals to generate the first to fourth output pulse signals A signal generation device comprising: The device to be controlled is a drive device that drives a switching element including a control terminal,
The driving device includes a first terminal and a second terminal, and the second terminal includes a coil connected to the control terminal,
The first switch is connected between a first potential line for applying a first potential and the first terminal, and is turned on to turn on the switching element.
The second switch is connected between the first potential line and the second terminal, and is turned on to clamp the control terminal of the turned-on switching element at the first potential,
The third switch is connected between a second potential line that applies a second potential lower than the first potential and the first terminal, and is turned on to turn off the switching element.
The fourth switch is connected between the second potential line and the second terminal, and is turned on to clamp the control terminal of the turned-off switching element at the second potential. The signal generation device described in 1. The first switch has an on-time adjusted according to a load state of the switching element,
The output pulse generation unit determines a rising timing of one input pulse signal of the first and second input pulse signals, and toggles one of the output pulse signals of the first to fourth output pulse signals. The signal generation device according to claim 2, wherein when the second input pulse signal is selected, the falling timing of the other input pulse signal is selected as the other toggle timing of the one output pulse signal. The output pulse generator is
The timing at which the first input pulse signal rises when the second input pulse signal is at the first level is selected as the rise timing of the first output pulse signal, and the first input pulse signal is the first level. A timing at which the second input pulse signal falls in the case of a level is selected as a fall timing of the first output pulse signal;
The timing at which the first input pulse signal falls when the second input pulse signal is at the second level is selected as the rise timing of the second output pulse signal, and the second input pulse signal is the first level. In the case of two levels, the timing when the first input pulse signal rises is selected as the fall timing of the second output pulse signal,
The timing at which the second input pulse signal rises when the first input pulse signal is at the first level is selected as the rise timing of the third output pulse signal, and the second input pulse signal is the first level. In the case of level, the timing at which the first input pulse signal falls is selected as the fall timing of the third output pulse signal,
The timing when the second input pulse signal falls when the first input pulse signal is at the second level is selected as the rise timing of the fourth output pulse signal, and the first input pulse signal is the first level. 4. The signal generation device according to claim 3, wherein a timing at which the second input pulse signal rises in the case of two levels is selected as a fall timing of the fourth output pulse signal. The second switch is turned on before the first switch is turned off when the switching element is turned on, and an on time is adjusted according to a level of a signal output from the switching element,
The output pulse generator is
The timing at which the second input pulse signal falls when the first input pulse signal is at the second level is selected as the rise timing of the first output pulse signal, and the first input pulse signal is the first level. Selecting the timing at which the second input pulse signal rises in the case of 1 level as the fall timing of the first output pulse signal;
The timing at which the first input pulse signal rises when the second input pulse signal is at the second level is selected as the rise timing of the second output pulse signal, and the second input pulse signal is the first level. In the case of level, the timing at which the first input pulse signal falls is selected as the fall timing of the second output pulse signal,
The timing at which the first input pulse signal rises when the second input pulse signal is at the first level is selected as the rise timing of the third output pulse signal, and the second input pulse signal is the second level. In the case of level, the timing at which the first input pulse signal falls is selected as the fall timing of the third output pulse signal,
The timing at which the second input pulse signal falls when the first input pulse signal is at the first level is selected as the rise timing of the fourth output pulse signal, and the first input pulse signal is the first level. 3. The signal generation device according to claim 2, wherein a timing at which the second input pulse signal rises when the level is two is selected as a fall timing of the fourth output pulse signal. The fourth switch is turned off after the first switch is turned on when the switching element is turned on, and an on time is adjusted according to a level of a signal output from the switching element,
The output pulse generator is
The timing at which the second input pulse signal rises when the first input pulse signal is at the second level is selected as the rise timing of the first output pulse signal, and the first input pulse signal is the first level. A timing at which the second input pulse signal falls in the case of a level is selected as a fall timing of the first output pulse signal;
The timing when the first input pulse signal falls when the second input pulse signal is at the second level is selected as the rise timing of the second output pulse signal, and the first input pulse signal is the first level. Selecting the timing at which the second input pulse signal rises in the case of 1 level as the falling timing of the second output pulse signal;
The timing at which the first input pulse signal rises when the second input pulse signal is at the second level is selected as the rise timing of the third output pulse signal, and the second input pulse signal is the first level. In the case of level, the timing at which the first input pulse signal falls is selected as the fall timing of the third output pulse signal,
The timing at which the second input pulse signal falls when the first input pulse signal is at the second level is selected as the rise timing of the fourth output pulse signal, and the second input pulse signal is the second level. 3. The signal generation device according to claim 2, wherein a timing at which the first input pulse signal rises when the level is 1 is selected as a fall timing of the fourth output pulse signal.

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