JP2013058606A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device which inhibits short circuits between conductive wires after the multiple conductive wires, electrically connecting a substrate with a semiconductor chip, are fixed.SOLUTION: After a first resin material RS is applied, connection pads PD1 and electrode pads PD2 are wire bonded by conductive wires WR. After the process that the wire bonding is performed, the first resin material RS is solidified. A substrate SUB and a semiconductor chip CHP are sealed by supplying and hardening a second resin material MRS. In the process that the wire bonding is performed, the multiple conductive wires WR in the first resin material RS do not contact with each other. A temperature that the first resin material RS is softened is higher than process temperatures in processes conducted after the process where the second resin material MRS is supplied and hardened to form the sealing.

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device by wire bonding a semiconductor chip and a substrate.

  Semiconductor devices (packages) having a configuration in which semiconductor chips are mounted on a substrate and these are covered with a mold resin are widely distributed. In many of such semiconductor devices, a mounted semiconductor chip or the like and a substrate or a lead frame are electrically connected by a process called wire bonding. In wire bonding, a semiconductor chip to be mounted and a substrate or a lead frame are electrically connected by a conductive wire. For example, a plurality of pads for electrical connection with the semiconductor chip and the substrate are arranged on the main surfaces of the substrate and the semiconductor chip, respectively, and the substrate and the semiconductor chip are electrically connected by a plurality of wires. .

  In particular, in the step of injecting mold resin after wire bonding, a plurality of wires may be deformed or flowed (displaced) by an external force applied to the wire by the inflowing mold resin. As a result, for example, when adjacent wires come into contact with each other, a short circuit is likely to occur between the wires. Further, as the miniaturization of the semiconductor device progresses, the semiconductor chip is further reduced in size and highly integrated, so that there is a problem that a short circuit between wires sometimes occurs during the wire bonding process.

  In order to solve the above problems, for example, in Japanese Patent Application Laid-Open No. 2008-251929 (Patent Document 1), a liquid resin is filled in a region sandwiched between adjacent metal wires of a plurality of stacked semiconductor elements, and the liquid state The resin is cured and the metal wire is fixed. Specifically, the liquid resin fills the region between the adjacent metal wires in the plan view and in the height (thickness) direction from above the uppermost metal wire, and the adjacent metal wires are filled with the liquid resin. It is applied so as to be bonded with a sandwich. Thereafter, the metal wire is fixed by heating and curing the liquid resin.

  Further, for example, in Japanese Patent Application Laid-Open No. 2011-35334 (Patent Document 2), in order to simultaneously realize improvement in material filling, suppression of wire flow (displacement), and improvement in heat dissipation of a package, filler is filled around the wire. After filling a material with a small amount and curing, a package is formed by using a material with a large amount of filler as a mold resin.

  Furthermore, for example, in Japanese Patent Application Laid-Open No. 2011-18797 (Patent Document 3), after an insulating layer having thermoplasticity is applied on a semiconductor chip before the wire bonding step, the electrode pads of the semiconductor chip and the wiring board are formed. The connection pad is connected by a conductive wire. Specifically, a plurality of conductive wires are connected to the respective electrode pads and connection pads by thermocompression bonding. At this time, since heat is generated in the conductive wire, when the thermoplastic insulating layer comes into contact with the wire, the portion of the insulating layer in contact with the heat of the wire is softened, and the wire is embedded in the insulating layer. The wire is fixed to the thermoplastic insulating layer because it hardens when the wire bonding is completed and the insulating layer cools.

JP 2008-251929 A JP 2011-35334 A JP 2011-18797 A

  In the manufacturing methods disclosed in Japanese Patent Application Laid-Open Nos. 2008-251929 and 2011-35334, the liquid resin or the filling material is applied after the wire bonding. There is a possibility that the wire is deformed or flows (displaces) when flowing in. In other words, when these materials are introduced after wire bonding, even if the wires are fixed after application of the material, there is a possibility that a phenomenon may occur that causes the adjacent wires to be short-circuited at the time of the introduction. .

  In the manufacturing method disclosed in Japanese Patent Application Laid-Open No. 2011-18797, a fixing material (insulating layer) is formed before wire bonding, and this material has thermoplasticity. For this reason, even if the wire is fixed by curing the fixing material, in the subsequent process, if heat sufficient to be heated above the temperature at which the fixing material softens is applied, The material may soften again. On the other hand, semiconductor devices are often subjected to heat. For example, in a reflow process when a completed semiconductor device (package) is soldered and mounted on a substrate (mounting substrate) of a product operated by the semiconductor device, the entire mounting substrate or the semiconductor device itself may generate heat. . If the semiconductor device receives heat in the subsequent processes as described above and is heated to a temperature higher than the temperature at which the thermoplastic insulating layer is softened, the thermoplastic insulating layer may be softened. If the thermoplastic insulating layer is softened, the wire once fixed to the thermoplastic insulating layer may be deformed or flowed. At this time, if vibration is further applied to the semiconductor device, the wires may come into contact with each other to cause a short circuit. That is, if the manufacturing method disclosed in Japanese Patent Application Laid-Open No. 2011-18797 is used, the heat generated by the semiconductor device itself is transmitted to the wire even after the product is completed, and the thermoplastic insulating layer that fixes the wire is formed. If the wire is softened by heat, adjacent wires may come into contact with each other and cause a short circuit.

  The present invention has been made in view of the above problems. An object of the present invention is to provide a method of manufacturing a semiconductor device capable of suppressing a short circuit between conductive wires after a plurality of conductive wires that electrically connect a substrate and a semiconductor chip are fixed. It is.

A manufacturing method of a semiconductor device according to an embodiment of the present invention includes the following steps.
First, a substrate having a first main surface and having a connection pad disposed on the first main surface, and a second main surface having a second main surface disposed above the first main surface A semiconductor chip on which electrode pads are arranged is prepared. The first resin material is applied to at least a part of a region sandwiched between the connection pad and the electrode pad in plan view. After the first resin material is applied, the connection pad and the electrode pad are wire-bonded with a conductive wire. After the wire bonding step, the first resin material is solidified. The second resin material is supplied and cured so as to cover above the substrate and the semiconductor chip. In the wire bonding step, at least a part of at least one conductive wire is disposed inside the first resin material, and the plurality of conductive wires do not contact each other. The temperature at which the first resin material is softened is higher than the processing temperature in the steps after the step of sealing by supplying and curing the second resin material.

  According to the manufacturing method of the present embodiment, after the first resin material is applied, wire bonding is performed so that the plurality of conductive wires do not contact each other in each region including the inside of the first resin material, After the wire bonding is performed, the first resin material is solidified. The first resin material is not softened by supplying and curing the second resin material. Therefore, after the step of solidifying the first resin material, that is, when sealing with the second resin material, for example, the state in which the conductive wires inside the first resin material are not in contact with each other is maintained. Thus, a short circuit between the conductive wires is suppressed.

(A) It is a schematic plan view which shows the whole aspect except the mold resin of the semiconductor device which concerns on Embodiment 1 of this invention. (B) It is a schematic side view which shows the whole aspect of the semiconductor device shown to FIG. 1 (A). (A) It is a schematic plan view which shows the whole aspect remove | excluding gel-like resin from the semiconductor device of FIG. (B) It is a schematic side view which shows the aspect of the whole semiconductor device shown to FIG. 2 (A). It is a schematic sectional drawing containing mold resin in the part which follows the III-III line of FIG. It is a schematic sectional drawing containing mold resin in the part which follows the IV-IV line of FIG. 5 is a schematic cross-sectional view showing a mode after a die-bonding process of the method for manufacturing a semiconductor device having the configuration of the first embodiment. FIG. It is a schematic sectional drawing which shows the aspect after the process of apply | coating the 1st resin material (gel resin) of the manufacturing method of the semiconductor device which has the structure of Embodiment 1. 7 is a schematic cross-sectional view showing a mode after the wire bonding step of the method for manufacturing a semiconductor device having the configuration of the first embodiment. FIG. 5 is a schematic cross-sectional view showing a mode after a molding step of the method for manufacturing a semiconductor device having the configuration of the first embodiment. FIG. It is a schematic plan view which shows the whole aspect except the mold resin of the semiconductor device which concerns on a comparative example. (A) It is a schematic plan view which shows the whole aspect except the mold resin of the semiconductor device which concerns on Embodiment 2 of this invention. (B) It is a schematic side view which shows the aspect of the whole semiconductor device shown to FIG. 10 (A). (A) It is a schematic plan view which shows the whole aspect except gel-like resin from the semiconductor device of FIG. (B) It is a schematic side view which shows the aspect of the whole semiconductor device shown to FIG. 11 (A). It is a schematic sectional drawing containing mold resin in the part which follows the XII-XII line | wire of FIG. It is a schematic sectional drawing containing mold resin in the part which follows the XIII-XIII line | wire of FIG. FIG. 10 is a schematic cross-sectional view showing a mode after a die-bonding process in a method for manufacturing a semiconductor device having the configuration of the second embodiment. It is a schematic sectional drawing which shows the aspect after the process of apply | coating the 1st resin material (gel resin) of the manufacturing method of the semiconductor device which has the structure of Embodiment 2. FIG. 10 is a schematic cross-sectional view showing a mode after the first step of wire bonding in the method for manufacturing a semiconductor device having the configuration of the second embodiment. FIG. 10 is a schematic cross-sectional view showing a mode after the second step of wire bonding in the method for manufacturing a semiconductor device having the configuration of the second embodiment. FIG. 10 is a schematic cross-sectional view showing a mode after a molding step of the method for manufacturing a semiconductor device having the configuration of the second embodiment. FIG. 6 is a schematic diagram showing an aspect in which a cured film is formed on a gel-like resin in the vicinity of a conductive wire by the manufacturing method of Embodiment 3. It is a schematic plan view which shows the whole aspect except the mold resin of the 1st example of the semiconductor device which concerns on Embodiment 4 of this invention. It is a schematic plan view which shows the whole aspect except the mold resin of the 2nd example of the semiconductor device which concerns on Embodiment 4 of this invention. It is an expansion schematic sectional drawing which shows the area | region where the electroconductive wire especially extends of the 1st example of the semiconductor device which concerns on Embodiment 5 of this invention. It is an expansion schematic sectional drawing which shows the area | region where the conductive wire especially extends of the 2nd example of the semiconductor device which concerns on Embodiment 5 of this invention. It is an expansion schematic sectional drawing which shows the area | region where the electroconductive wire especially extends of the 3rd example of the semiconductor device which concerns on Embodiment 5 of this invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
1A and 1B, a semiconductor device DEV in the present embodiment includes a substrate SUB and a semiconductor chip CHP arranged on one main surface (first main surface) of the substrate SUB. And have. The substrate SUB is arranged as a circuit substrate for mounting elements.

  The substrate SUB is preferably an insulating substrate (for example, a resin substrate, a ceramic substrate, a glass substrate) or a semiconductor substrate on which the semiconductor chip CHP can be mounted on one main surface. More specifically, the substrate SUB can be a printed wiring board using glass-epoxy resin or BT (bismaleimide / triazine) resin. Alternatively, the substrate SUB may be a member having a configuration having both a portion on which an element can be mounted and a portion functioning as a circuit, such as a lead frame.

  A plurality of finger portions PD1 (connection pads) are disposed on one main surface of the substrate SUB. The finger part PD1 is a terminal for electrically connecting the semiconductor device DEV to an external circuit board.

  The semiconductor chip CHP has a configuration in which, for example, a circuit including a transistor not shown in FIG. 1 is formed on one main surface (second main surface) of a main body made of, for example, silicon single crystal. The semiconductor chip CHP has, for example, a rectangular planar shape. A plurality of pad portions PD2 (electrode pads) are arranged on one main surface of the semiconductor chip CHP. Pad portion PD2 is a terminal electrically connected to, for example, a circuit including a transistor formed on one main surface of semiconductor chip CHP.

  The plurality of finger portions PD1 and the pad portions PD2 are arranged, for example, along the rectangular planar shape of the semiconductor chip CHP, that is, along the extending direction of the outer periphery of the semiconductor chip CHP, for example. Each of the plurality of finger portions PD1 of the substrate SUB and each of the plurality of pad portions PD2 of the semiconductor chip CHP are electrically connected by a conductive wire WR. The conductive wire WR has a function of transmitting an electric signal of a circuit such as a transistor formed in the semiconductor chip CHP to the outside of the semiconductor chip CHP and further to the outside of the semiconductor device DEV. The conductive wire WR has a low electric resistance and can efficiently transmit an electric signal, and has high workability and high connection strength, for example, gold. The conductive wire WR electrically connects each of the plurality of finger portions PD1 and each of the plurality of pad portions PD2 with each other in a one-to-one relationship, whereby a circuit formed on the semiconductor chip CHP and the semiconductor chip CHP ( A circuit connected to the outside of the semiconductor device DEV) is electrically connected with high efficiency.

  Gel resin RS (first resin material) is disposed in a region sandwiched between finger portion PD1 and pad portion PD2 in plan view. That is, the gel-like resin RS is a resin material disposed between the finger part PD1 and the pad part PD2 in plan view. In FIGS. 1A and 1B, the gel-like resin RS is disposed in almost the entire region sandwiched between the finger portions PD1 and the pad portions PD2 in the direction in which the outer periphery of the semiconductor chip CHP extends. That is, regarding the direction in which the individual conductive wires WR connecting the individual finger portions PD1 and the pad portions PD2 extend, the gel-like resin RS is not disposed over the entire length of the conductive wires WR. The gel-like resin RS is disposed in almost the entire region sandwiched between the finger part PD1 and the pad part PD2 with respect to the direction intersecting with the extending direction.

  That is, the gel-like resin RS may be disposed in at least a part of a region sandwiched between the finger part PD1 and the pad part PD2 in plan view. Here, it is particularly preferable that the gel-like resin RS is disposed so as to fill a region between the plurality of adjacent conductive wires WR at least in a region where the plurality of adjacent conductive wires WR easily come into contact with each other. When the gel-like resin RS embeds at least a part of the plurality of conductive wires WR, the plurality of conductive wires WR are embedded so as not to contact each other inside the gel-like resin RS. Therefore, for example, the gel-like resin RS is disposed so as to fill the region between the plurality of adjacent conductive wires WR only in the region where the plurality of adjacent conductive wires WR are easily in contact with each other. In this region, the gel-like resin RS may not be disposed (even if the region is sandwiched between the finger portion PD1 and the pad portion PD2). That is, it is only necessary that at least a part of at least one conductive wire WR be disposed (embedded) inside the gel-like resin RS. For example, the cured gel-like resin RS may be arranged so as to be embedded in only one conductive wire WR.

  Since FIGS. 1A and 1B are a plan view and a side view of the entire semiconductor device DEV, a part of the region is hidden behind the gel-like resin RS and cannot be seen. 2A and 2B are a plan view and a side view of the semiconductor device DEV (in this embodiment similar to FIGS. 1A and 1B), respectively, but the gel-like resin RS is shown. 1A and 1B are shown in FIG. 1A and FIG. 1B in which the region hidden behind the gel-like resin RS is not visible.

  Referring to FIGS. 3 and 4, mold resin MRS (second resin material) is arranged so as to cover the upper side of the configuration shown in FIG. 1 (on the main surface on which finger portions PD1 and pad portions PD2 are arranged). Is done. The mold resin MRS covers the substrate SUB, the semiconductor chip CHP, the gel resin RS, and the conductive wire WR that are exposed in the plan view of FIG. 1A, and is arranged so as to be embedded in the mold resin MRS. The That is, the substrate SUB, the semiconductor chip CHP, the conductive wire WR, and the like constituting the semiconductor device DEV are protected from external stress, moisture, and contaminants by the mold resin MRS.

  Even in the state sealed with the mold resin MRS, the solidified gel-like resin RS fills a region sandwiched between a plurality of adjacent conductive wires WR (so that the conductive wires WR are embedded). Be placed. For this reason, any conductive wire WR is arrange | positioned, without contacting with another conductive wire WR.

  As mold resin MRS, for example, an epoxy resin made of so-called dissolved silica is preferably used. In this case, the mold resin MRS is a so-called thermosetting resin. The gel-like resin RS is preferably non-conductive, for example, a so-called thermosetting resin such as an epoxy resin, and the same resin as the mold resin MRS may be used.

  That is, when the gel resin RS is a thermosetting resin, the gel resin RS has a property of being irreversibly cured by heating. Therefore, in this case, once the gel-like resin RS is cured, even if very high heat is applied thereafter, or even if no heat is applied, the gel-like resin RS is not easily softened and maintains a high hardness state.

  However, the gel-like resin RS may be a so-called thermoplastic resin that may be softened by heating. However, regardless of whether the gel-like resin RS is a thermosetting resin or a thermoplastic resin, in this embodiment, the temperature at which the gel-like resin RS once softened is softened by the mold resin MRS. It is preferable that the temperature is higher than the processing temperature when the entire semiconductor device DEV is sealed by being placed and cured at a desired position on the SUB and the semiconductor chip CHP. Alternatively, in the present embodiment, the temperature at which the once solidified gel-like resin RS is softened is higher than the processing temperature at the time of actual use, for example, when soldering and mounting the completed semiconductor device DEV on a mounting board or the like. It is preferable. In summary, in the present embodiment, the temperature at which the gel-like resin RS softens is higher than the processing temperature in each step after sealing with the mold resin MRS, including, for example, a mounting step after the completion of the semiconductor device DEV. Is also expensive.

  Here, the processing temperature is, for example, the temperature of the structure in the process of forming the semiconductor device DEV when the sealing process is performed in the molding resin MRS sealing process. For example, in the mounting process, the heating temperature of the structure when soldering for mounting is the processing temperature.

  The temperature at which the gel-like resin RS softens is the heating temperature of the gel-like resin RS when the hardness of the once-cured gel-like resin RS starts to decrease. Here, softening not only means that the hardness is lowered, but also means that it is melted and liquefied. The temperature at which the mold resin MRS is cured is the temperature of the mold resin MRS when the hardness of the mold resin MRS starts to increase. Here, the term “curing (solidification)” not only means that the hardness is increased and becomes solid, but also includes the meaning that it is solidified by cooling, for example.

  When the gel-like resin RS is a thermosetting resin, the gel-like resin RS is hardly softened even by heating as described above. Therefore, the temperature to be heated to soften the gel-like resin RS is very high. . For this reason, even if the material constituting the mold resin MRS is the same as or different from the material constituting the gel resin RS, the softening temperature of the gel resin RS is usually higher than the temperature at which the mold resin MRS is solidified. Become.

  On the other hand, when the gel-like resin RS is a thermoplastic resin, the gel-like resin RS is softened by heating. Therefore, after the gel-like resin RS is once cured, the heating temperature when the hardness starts to decrease is the mold resin. It is necessary to select a material constituting the mold resin MRS so as to be higher than the temperature at which the MRS is solidified. If the material composing the mold resin MRS is the same as the material composing the gel resin RS, the gel resin RS is a thermoplastic resin, so that the softening temperature thereof is higher than the curing temperature of the mold resin MRS. . However, when the materials constituting the two are different, it is preferable to select an appropriate material so that the temperature at which the gel-like resin RS softens becomes higher than the processing temperature when the mold resin MRS is cured. In this case, the temperature at which the gel-like resin RS is heated when sealing with the mold resin MRS is lower than the temperature at which the gel-like resin RS is softened, so that the fixed gel-like resin RS is softened. The possibility of doing is reduced.

  Next, a method for manufacturing the semiconductor device DEV of the present embodiment shown in FIGS. 1 to 4 will be described with reference to FIGS. 5 to 8, the finger part PD1 and the pad part PD2 are not shown.

  Referring to FIG. 5, first, a substrate SUB in which a plurality of finger portions PD1 are formed as described above, and a semiconductor chip CHP in which circuits such as a plurality of pad portions PD2 and transistors are formed are prepared. For the finger part PD1, for example, electrolytic Ni (nickel) -Au (gold) or Cu (copper) is preferably used. For example, Al (aluminum) is preferably used for the pad portion PD2.

  Next, a process called so-called die bonding is performed in which the semiconductor chip CHP is mounted and bonded onto one main surface (first main surface) of the substrate SUB where the finger portions PD1 are formed. For die bonding, it is preferable to use an adhesive made of, for example, a silver paste containing Ag (silver) or an epoxy-acrylic-polyimide resin paste.

  Referring to FIG. 6, gel-like resin RS is applied to at least a part of a region sandwiched between finger portion PD1 and pad portion PD2 in plan view. The gel-like resin RS is preferably applied in a gel-like manner (not solidified). Further, the gel-like resin RS is preferably applied preferentially in a region where a plurality of conductive wires WR (see FIGS. 1 to 4) connected by wire bonding easily contact each other, particularly in a subsequent process. .

  At this time, as described above, the gel resin RS, whether it is a thermosetting resin or a thermoplastic resin, is a mold resin MRS (FIG. 3, FIG. 3) used later in the process of sealing the entire semiconductor device DEV. 4) is preferably selected such that its softening temperature is higher than the temperature at which it is fed and cured.

  Referring to FIG. 7, after gel-like resin RS is applied to a desired place as shown in FIG. 6, each of a plurality of finger portions PD1 and a plurality of pad portions PD2 are formed using a normal wire bonding technique. Each is processed so as to be electrically connected to each other in a one-to-one relationship by the conductive wire WR. At this time, the (at least one) conductive wire WR is preferably arranged so that at least a part of the conductive wire WR is embedded in the gel-like resin RS, and the plurality of conductive wires WR are not in contact with each other. It is preferable to be connected to.

  Specifically, first, for example, one end portion of the conductive wire WR is brought into contact with the finger portion PD1, and heat, a load, and an ultrasonic wave are applied to melt the metal material of the conductive wire WR and the finger portion PD1. By this process, the conductive wire WR and the finger part PD1 are welded. Next, the other end portion of the conductive wire WR extending from the welded finger portion PD1 is brought into contact with the pad portion PD2, and heat, a load, and an ultrasonic wave are applied, so that the metal of the conductive wire WR and the pad portion PD2 is applied. Melt the material. By this process, the conductive wire WR and the pad portion PD2 are welded. Finally, the conductive wire WR is torn off from the portion where the conductive wire WR and the pad portion PD2 are welded. Through the above procedure, the finger part PD1 and the pad part PD2 facing the finger part PD1 in plan view are electrically connected by the conductive wire WR.

  After the conductive wire WR is bonded, the gel resin RS is solidified. Specifically, for example, when the gel resin RS is a thermosetting resin, the gel resin RS is heated. Conversely, for example, when the gel-like resin RS is a thermoplastic resin, the gel-like resin RS is cooled. When the gel resin RS is solidified, the state in which the plurality of conductive wires WR are arranged so as not to contact each other in the gel resin RS is maintained.

  Referring to FIG. 8, the structure in which the semiconductor chip CHP is mounted on the substrate SUB formed by the steps up to FIG. 7 and both are electrically connected by the conductive wire WR is sealed with the mold resin MRS. Stopped. That is, the substrate SUB, the semiconductor chip CHP, the conductive wire WR and the like are embedded in the mold resin MRS from above, and the mold resin MRS is solidified. As described above, in the present embodiment, after wire bonding is performed, sealing is performed with the mold resin MRS.

  Specifically, for example, a pelletized mold resin MRS (second resin material) is placed inside the mold in a state where the structure formed by the steps up to FIG. 7 is put into the mold. Is supplied to be poured. In this way, the mold resin MRS is disposed so as to cover the substrate SUB, the semiconductor chip CHP, and the like, and to embed the structure including the substrate SUB and the semiconductor chip CHP. In this state, for example, when the mold resin MRS is a so-called thermosetting resin, the mold resin MRS is cured by being heated. The temperature for heating the mold resin MRS at this time is adjusted to be lower than the temperature at which the gel resin RS is softened.

  Thereafter, the structure of FIG. 8 sealed with the mold resin MRS is taken out of the mold, thereby forming the semiconductor device DEV having the mode shown in FIGS. 3 to 4, for example.

Next, the effect of this Embodiment is demonstrated.
Referring to FIG. 9, the semiconductor device DEV of the comparative example has a configuration basically similar to that of the present embodiment in plan view, but the gel-like resin RS is not disposed. Further, in the semiconductor device DEV of the comparative example of FIG. 9, the mold resin MRS is disposed, but the illustration is omitted as in, for example, FIG.

  In the manufacturing method of the semiconductor device DEV of the comparative example, the gel-like resin RS is applied after the step of FIG. 5 in the present embodiment (preparation of the substrate SUB and the semiconductor chip CHP and other members and die bonding), for example. Instead, wire bonding shown in FIG. 7 is performed, and then sealed with a mold resin MRS shown in FIG. In the above points, the manufacturing method of the semiconductor device DEV of the comparative example is different from the manufacturing method of the semiconductor device DEV of the present embodiment.

  As in the comparative example, when the gel resin RS is not disposed, if the mold resin MRS is supplied immediately after the conductive wire WR is bonded, the mold resin MRS becomes conductive when the mold resin MRS flows. An external force may be applied to the wire WR. Then, due to the external force, the plurality of conductive wires WR may be deformed or flowed (displaced) in the lateral direction. As a result, as shown by a circled region in FIG. 9, for example, when adjacent conductive wires WR come into contact with each other, a short circuit is likely to occur between the conductive wires WR. Further, the conductive wire WR may be bent or fallen in the vicinity of the finger portion PD1 or the pad portion PD2 to which the conductive wire WR is connected by the external force, so that the conductive wire WR can be disconnected as shown in FIG. There is sex.

  Therefore, in the present embodiment, in at least a part of a region sandwiched between the finger part PD1 and the pad part PD2 in plan view (particularly, a region where at least a plurality of adjacent conductive wires WR easily come into contact with each other) Gel resin RS is arranged so as to fill a region between adjacent conductive wires WR. This gel-like resin RS is supplied to a desired position before the conductive wire WR is connected. Thereafter, wire bonding with the conductive wire WR is performed so as to be embedded in the gel-like resin RS and not to contact each other. Thereafter, the gel-like resin RS is cured, and the whole is sealed with the mold resin MRS.

  In this way, if at least the conductive wires WR embedded in the gel-like resin RS are arranged so as not to contact each other, the solidified gel-like resin RS is fixed so as not to contact each other. Is done.

  Here, sealing with the mold resin MRS is performed in a later step. If the temperature at which the gel-like resin RS is softened is higher than the processing temperature in sealing the mold resin MRS, in the sealing step of the mold resin MRS. Further, the solidified gel-like resin RS maintains the state in which the internal conductive wire WR is fixed. For this reason, the state where the conductive wires WR inside the gel-like resin RS are fixed so as not to contact each other is also maintained. Similarly, in the subsequent process of sealing with the mold resin MRS, for example, when the semiconductor device DEV is completed and soldered and mounted on a mounting board (when the semiconductor device DEV is actually used), the processing temperature in the solder mounting If the temperature at which the gel-like resin RS softens is higher, the state where the gel-like resin RS is fixed is maintained also in this process. For this reason, the state where the conductive wires WR inside the gel-like resin RS are fixed so as not to contact each other is also maintained.

  Therefore, in the present embodiment, the gel-like resin RS once solidified is not softened during the process (including the actual use after the semiconductor device DEV is completed) after the solidification of the gel-like resin RS. For this reason, when the gel-like resin RS is softened, the conductive wire WR that has been fixed to the gel-like resin RS is deformed so that it flows, or a plurality of conductive wires WR are caused by the deformation. Generation | occurrence | production of malfunctions, such as a short circuit, can be suppressed.

  In the present embodiment, a plurality of bonding conductive materials are embedded in the gel-like resin RS previously applied as described above, particularly in an area where a plurality of adjacent conductive wires WR are easily in contact with each other. It is preferable that the wire WR is disposed. However, for the regions other than the region where the plurality of conductive wires WR are easily in contact with each other as described above, for example, the gel-like resin RS may not be supplied as in the comparative example of FIG. Wire bonding may be performed by a procedure in which the gel-like resin RS is supplied and solidified after wire bonding.

(Embodiment 2)
The present embodiment is different from the first embodiment in the configuration of the semiconductor device DEV. Hereinafter, the configuration of the present embodiment will be described with reference to FIGS.

  Referring to FIGS. 10A and 10B, semiconductor device DEV in the present embodiment has the same general configuration as semiconductor device DEV in the first embodiment. However, in the semiconductor device DEV of the present embodiment, the semiconductor chip CHPb (another semiconductor chip) is stacked on one main surface of the semiconductor chip CHPa. Thus, in the present embodiment, if the semiconductor chip CHPa in FIG. 10 is considered as the semiconductor chip CHP in FIG. 1, at least one other semiconductor chip is stacked (arranged) on the semiconductor chip CHP in the first embodiment. ) In FIG. 10, only a single semiconductor chip CHPb is stacked on the semiconductor chip CHPa, but it may have a configuration in which two or more semiconductor chips are stacked.

  The semiconductor chip CHPa in FIG. 10 corresponds to, for example, the semiconductor chip CHP in FIG. That is, in the present embodiment, another semiconductor chip CHPb is arranged on one main surface of the semiconductor chip CHP of the first embodiment. In FIG. 10, the semiconductor chip CHPb has a smaller area in plan view than the semiconductor chip CHPa.

  The semiconductor chip CHPa and the semiconductor chip CHPb have the same configuration as the semiconductor chip CHP. That is, the semiconductor chip CHPb has a configuration in which, for example, a circuit including a transistor not shown in FIG. 10 is formed on one main surface (third main surface) of a main body made of, for example, silicon single crystal. . A plurality of pad portions PD2a are formed on one main surface of the semiconductor chip CHPa, and a plurality of pad portions PD2b (other electrode pads) are formed on one main surface of the semiconductor chip CHPb. A plurality of finger portions PD1a and PD1b are arranged on one main surface of the substrate SUB. In FIG. 10, the plurality of finger portions PD1a and PD1b and the pad portions PD2a and PSD2b are all arranged along the extending direction of the outer periphery of the semiconductor chips CHPa and CHPb, and the finger portion PD1a is arranged in the finger portion PD1b. It is arranged at a position closer to the semiconductor chips CHPa and CHPb. On the contrary, the finger part PD1a may be arranged at a position farther from the semiconductor chips CHPa and CHPb than the finger part PD1b. The finger portions PD1a and PD1b have the same functions as the finger portion PD1 in the first embodiment, and the pad portions PD2a and PD2b have the same functions as the pad portion PD2 in the first embodiment.

  The conductive wire WR1 electrically connects each of the plurality of finger portions PD1a and each of the plurality of pad portions PD2a in a one-to-one relationship. The conductive wire WR2 electrically connects each of the plurality of finger portions PD1b and each of the plurality of pad portions PD2b in a one-to-one relationship. Therefore, conductive wires WR1 and WR2 have the same function as conductive wire WR in the first embodiment.

  The gel-like resin RS is disposed in at least a part of a region sandwiched between the finger portions PD1a and PD1b and the pad portions PD2a and PD2b in plan view. Similar to the first embodiment, the gel-like resin RS may be arranged limited to a region where a plurality of adjacent conductive wires WR are particularly easily in contact with each other.

  Also in the semiconductor device DEV of the present embodiment, similarly to the semiconductor device DEV of the first embodiment, any of the conductive wires WR1 and WR2 are arranged without contacting the other conductive wires WR1 and WR2. In particular, the conductive wires WR1 and WR2 embedded in the gel-like resin RS are arranged so as not to contact with the adjacent conductive wires WR1 and WR2 inside the gel-like resin RS.

  11 to 13 correspond to FIGS. 2 to 4 in the first embodiment, respectively. Although only the conductive wire WR2 actually appears in the cross section of FIG. 12, the conductive wire WR1 disposed in the vicinity of the conductive wire WR2 is also illustrated.

  The configuration of the present embodiment shown in FIGS. 10 to 13 is different from the configuration of the first embodiment shown in FIGS. 1 to 4 in the above points. In other respects, the configuration of FIGS. Since the configuration is the same as that of the first embodiment shown in FIG. 4, the same elements are denoted by the same reference numerals and the description thereof is not repeated.

  Next, a method for manufacturing the semiconductor device DEV of the present embodiment shown in FIGS. 10 to 13 will be described with reference to FIGS. Note that the finger portions PD1a and PD1b and the pad portions PD2a and PD2b are not shown in FIGS.

  Referring to FIG. 14, first, a substrate SUB on which a plurality of finger portions PD1a and PD1b are formed as described above, a semiconductor chip CHPa on which circuits such as a plurality of pad portions PD2a and transistors are formed, and a plurality of pad portions PD2b. A semiconductor chip CHPb on which a circuit such as a transistor is formed is prepared.

  Next, the semiconductor chip CHPa is mounted on one main surface (first main surface) of the substrate SUB where the finger portions PD1a are formed, and the two are bonded together. In addition, the semiconductor chip CHPb is bonded to the semiconductor chip CHPa by mounting the semiconductor chip CHPb on one main surface (second main surface) of the semiconductor chip CHPa on which the pad portion PD2a is formed and performing die bonding. To do.

  Referring to FIG. 15, gel-like resin RS is applied to at least a part of a region sandwiched between finger portions PD1a and PD1b and pad portions PD2a and PD2b in plan view. That is, for example, as in the first embodiment, in addition to the region sandwiched between the finger portion PD1a and the pad portion PD2a, the gel resin RS is applied to the region sandwiched between the finger portion PD1b and the pad portion PD2b (additional coating). ) However, in practice, the gel-like resin RS may be simultaneously applied to a region sandwiched between the finger portion PD1a and the pad portion PD2a and a region sandwiched between the finger portion PD1b and the pad portion PD2b.

  Referring to FIG. 16, after gel-like resin RS is applied to a desired location as shown in FIG. 15, each of a plurality of finger portions PD1a and a plurality of pad portions PD2a are formed using a normal wire bonding technique. Each is processed so as to be electrically connected to each other in a one-to-one relationship by the conductive wire WR1. At this time, it is preferable that the conductive wire WR1 is disposed so that a part of the conductive wire WR1 is embedded in the gel-like resin RS, and in particular, in the gel-like resin RS, the plurality of conductive wires WR are mutually connected. It is preferable that they are connected so as not to contact each other.

  Referring to FIG. 17, after gel-like resin RS is applied to a desired location as shown in FIG. 15, each of the plurality of finger portions PD <b> 1 b is Each of the plurality of pad portions PD2b is processed so as to be electrically connected to each other on a one-to-one basis by the conductive wire WR2. At this time, at least a part of at least one conductive wire WR1 and / or conductive wire WR2 is a gel-like resin RS and / or finger portion PD1b and pad portion PD2b in a region sandwiched between the finger portion PD1a and the pad portion PD2a. It arrange | positions so that it may be embedded inside the gel-like resin RS of the area | region pinched | interposed. For example, a part of only one conductive wire WR1 and a part of only one conductive wire WR2 may be embedded in the gel-like resin RS.

  In the steps of FIGS. 16 and 17, not only the conductive wires WR1 and the conductive wires WR2 but also the conductive wires WR1 and WR1, for example, so that the conductive wires WR1 and WR2 do not contact each other. Bonding is preferably performed in such a manner that WR2 is embedded in the gel-like resin RS.

  After the conductive wires WR1 and WR2 are bonded, the gel resin RS is solidified. Specifically, as in the first embodiment, for example, when the gel resin RS is a thermosetting resin, the gel resin RS is heated. Conversely, for example, when the gel-like resin RS is a thermoplastic resin, the gel-like resin RS is cooled. When the gel resin RS is solidified, the state in which the plurality of conductive wires WR1 and WR2 are arranged so as not to contact each other in the gel resin RS is maintained. .

  Referring to FIG. 18, similarly to the process of FIG. 8, the structure formed by the processes up to FIG. 17 is sealed with mold resin MRS. Thus, also in this embodiment, after wire bonding is performed and the gel-like resin RS is solidified, it is sealed with the mold resin MRS.

  Also in the present embodiment, as in the first embodiment, the temperature for heating the mold resin MRS is adjusted to be lower than the temperature at which the gel-like resin RS softens. Also in the present embodiment, basically, as in the first embodiment, the temperature at which the gel-like resin RS is softened includes, for example, a mounting process after the completion of the semiconductor device DEV and the like after sealing with the mold resin MRS. It is higher than the processing temperature in the process.

  Thereafter, the structure shown in FIG. 18 sealed with the mold resin MRS is taken out from the mold, thereby forming the semiconductor device DEV having the modes shown in FIGS. 12 to 13, for example.

Next, the effect of this Embodiment is demonstrated.
Even in the case where two or more semiconductor chips are stacked on one main surface of the substrate SUB as in the present embodiment, as in the first embodiment, the pad portion of each semiconductor chip and the substrate After the conductive wires WR1 and WR2 that electrically connect the finger portions of the SUB are fixed by the gel-like resin RS, the molding resin MRS is sealed, and the temperature at which the gel-like resin RS is softened is the mold resin MRS. It is preferable that it is higher than the processing temperature in each subsequent process including the sealing process. In this way, as in the first embodiment, the conductive wires WR1 and WR2, which are once fixed at the desired positions by the gel-like resin RS, are deformed or flow due to the softness of the gel-like resin RS. As a result, it is possible to suppress problems such as short circuits.

  The second embodiment of the present invention is different from the first embodiment of the present invention only in each point described above. That is, the configuration, conditions, procedures, effects, and the like not described above for the second embodiment of the present invention are all the same as those of the first embodiment of the present invention.

(Embodiment 3)
The present embodiment is the same as the first and second embodiments in the configuration of the semiconductor device DEV. However, the manufacturing method has the following differences from the first and second embodiments.

  Referring to FIG. 19, for example, in the wire bonding process shown in FIGS. 7, 16, and 17, conductive wires WR, WR 1, WR 2 are arranged so as to be embedded inside gel-like resin RS. Thereafter, the conductive wires WR, WR1, and WR2 are bonded. This is the same as in the first and second embodiments. However, in the present embodiment, the gel-like resin RS in which the conductive wires WR, WR1, WR2 are embedded is cured by using heat generated in the conductive wires WR, WR1, WR2 during the bonding. . That is, the manufacturing method of the present embodiment is particularly effective when the gel-like resin RS is a so-called thermosetting resin.

  In the present embodiment, for example, when the conductive wires WR1 and WR2 in FIG. 19 generate heat during bonding, the gel-like resin RS that exists in the vicinity of the conductive wires WR1 and WR2 and is in direct contact with the conductive wires WR1 and WR2 is used. Is cured. The gel-like resin RS cured at this time forms a cured film F1 around the conductive wires WR1 and WR2.

  As described above, in the present embodiment, the gel-like resin RS is solidified by the heat generated by the conductive wire simultaneously with the wire bonding of the conductive wire. That is, in the present invention, the gel-like resin RS may be solidified after the wire bonding step as in the first and second embodiments, or at the same time as the wire bonding step as in the present embodiment. May be solidified. In summary, in the present invention, the gel-like resin RS is preferably solidified after the wire bonding step.

  The configuration of the present embodiment shown in FIG. 19 is different from the configurations of the first and second embodiments in the above points, and is otherwise the same as the configurations of the first and second embodiments. Therefore, the same elements are denoted by the same reference numerals and the description thereof is not repeated.

Next, the effect of this Embodiment is demonstrated.
In the present embodiment, adjacent conductive wires in the gel-like resin RS are in contact with each other by the cured film F1 formed around the conductive wire in the gel-like resin RS by the heat of the conductive wire. Is suppressed.

  The gel-like resin RS is not cured by the heat of the conductive wire in the region other than the vicinity of the conductive wire, and maintains the state at the time of application (for example, a gel shape). For this reason, for example, after bonding one conductive wire to be embedded in the gel-like resin RS, another conductive wire is arranged and bonded to be further embedded in the gel-like resin RS in another step. be able to. Thus, according to the present embodiment, it is possible to provide a high-quality semiconductor device DEV with high efficiency (no short circuit between conductive wires) without reducing the work efficiency of the wire bonding process.

  Further, for example, even when the distance between the conductive wire WR1 and the conductive wire WR2 adjacent in the vertical direction in FIG. 19 is very short, the cured film F1 is formed around each of the conductive wire WR1 and the conductive wire WR2. Is formed. For this reason, generation | occurrence | production of malfunctions, such as the electroconductive wire WR1 and electroconductive wire WR2 with a very short distance mutually contacting in the gel-like resin RS, can be suppressed reliably.

  The third embodiment of the present invention differs from the first and second embodiments of the present invention only in the points described above. That is, the configuration, conditions, procedures, effects, and the like not described above for the third embodiment of the present invention are all the same as those of the first and second embodiments of the present invention.

(Embodiment 4)
The present embodiment is an application example of the configuration of the first to third embodiments.

  Referring to FIG. 20, the semiconductor device DEV in the first example of the present embodiment has a substrate SUB and semiconductor chips CHPa, CHPb, and CHPc arranged above one main surface of the substrate SUB. Yes.

  The semiconductor chip CHPa has a rectangular planar shape with a relatively small aspect ratio, and the semiconductor chips CHPb and CHPc have a rectangular planar shape with a relatively large aspect ratio. The semiconductor chips CHPa and CHPc are directly and independently arranged on one main surface of the substrate SUB, but the semiconductor chip CHPb is stacked on one main surface of the semiconductor chip CHPa. As described above, when the semiconductor device DEV of FIG. 20 focuses only on the semiconductor chip, the semiconductor device CDEV is further added to the semiconductor device DEV of FIG. 10 (the semiconductor chip CHPa and the semiconductor chip CHPb are stacked on the substrate SUB). It is the composition which has.

  A plurality of pad portions PD2a are formed on the main surface of the semiconductor chip CHPa, a plurality of pad portions PD2b are formed on the main surface of the semiconductor chip CHPb, and a plurality of pad portions PD2c are formed on the main surface of the semiconductor chip CHPc. Has been. Further, on one main surface of the substrate SUB, a finger portion PD1 is formed in a region facing the left outer peripheral surface S1 in a plan view of the semiconductor chip CHPa, and a finger portion PD1a is formed in a region facing the lower outer peripheral surface S3. Finger portions PD1, PD1c, and PD1d are formed in regions where PD1b faces the upper outer peripheral surface S4. These pad portions and finger portions both extend on the left outer peripheral surface S1, the right outer peripheral surface S2, the lower outer peripheral surface S3, and the upper outer peripheral surface S4 in plan view of the semiconductor chip CHPa. A plurality are arranged along the direction. Any of the above finger portions has the same function as that of the finger portion PD1 in the first embodiment, and any of the above pad portions has the same function as the pad portion PD2 in the first embodiment.

  In the region facing the left outer peripheral surface S1, each of the plurality of finger portions PD1 and each of the plurality of pad portions PD2a are electrically connected to each other by the conductive wire WR1 in a one-to-one relationship. In the region facing the right outer peripheral surface S2, each of the plurality of pad portions PD2a and each of the plurality of pad portions PD2c are electrically connected to each other by the conductive wire WR2 in a one-to-one relationship. In the region facing the lower outer circumferential surface S3, each of the plurality of finger portions PD1a and each of the plurality of pad portions PD2a are in a one-to-one relationship with each other by the conductive wires WR3a, and each of the plurality of finger portions PD1b. Are electrically connected to each other by a conductive wire WR3b in a one-to-one relationship with each other. In the region facing the upper outer peripheral surface S4, on the left side of the figure, each of the plurality of finger portions PD1 and each of the plurality of pad portions PD2a are in a one-to-one relationship with each other by the conductive wire WR4. Connected to. Further, on the right side of the figure in the region facing the upper outer peripheral surface S4, each of the plurality of finger portions PD1c and each of the plurality of pad portions PD2a are in a one-to-one relationship with each other by the conductive wires WR4c. Each finger portion PD1d and each of the plurality of pad portions PD2a are electrically connected to each other by a conductive wire WR4d in a one-to-one relationship. Each of these conductive wires has the same function as the conductive wire WR in the first embodiment.

  The gel-like resin RS is disposed so as to embed a part of the plurality of conductive wires in a region facing the right outer peripheral surface S2, the lower outer peripheral surface S3, and the upper outer peripheral surface S4. The plurality of conductive wires are all arranged so as not to contact each other. The gel-like resin RS is not arranged in a region facing the left outer peripheral surface S1 in FIG. This is because the plurality of conductive wires WR1 arranged in the region facing the left outer peripheral surface S1 in FIG. 20 is unlikely to contact each other.

  That is, it is preferable that the gel-like resin is applied for the purpose of fixing the conductive wires in a region where the plurality of conductive wires are likely to contact each other. In addition, in the region where the possibility of contact is particularly high, the gel resin is applied before the wire bonding step described in the first to third embodiments, and after the wire bonding step. It is preferable to use a production method in which RS is solidified.

  For example, in the region where the conductive wires connected to the semiconductor chip CHPa and the semiconductor chip CHPb stacked on each other extend like the region facing the outer peripheral surface S3 in the lower part of FIG. 20, the conductive wire WR3a and the conductive wire WR are electrically conductive. In order to suppress contact with the conductive wire WR3b, the gel-like resin RS is preferably solidified by the manufacturing method of each of the above embodiments.

  Further, in the region facing the outer peripheral surface S2 on the right side of FIG. 20, particularly in the region where the conductive wire WR2 extends from the vicinity of the corner in the plan view of the semiconductor chip CHPa, the gel shape is obtained by the manufacturing method of each of the above embodiments. It is preferable that the resin RS is solidified. Conductive wire WR2 extending from the vicinity of the corner (that is, the end of outer peripheral surface S2) in plan view of semiconductor chip CHPa is longer than conductive wire WR2 extending from the vicinity of the central portion of outer peripheral surface S2. The long conductive wires are particularly likely to come into contact with other conductive wires by being deformed and displaced in response to an external force in the process of pouring the mold resin MRS (see FIGS. 8 and 18). For this reason, it is preferable that a particularly long conductive wire is fixed to the gel-like resin RS solidified by the manufacturing method of each of the above embodiments. In this way, it is possible to suppress problems such as a short circuit caused by deformation and displacement of a long conductive wire.

  Therefore, for example, as described above, only the conductive wires connected to the pad portions (electrode pads) arranged at the corners in plan view of the semiconductor chip are solidified by the manufacturing method of each of the above embodiments. You may have the aspect fixed to resin RS. Referring to FIG. 21, the semiconductor device DEV of the second example of the present embodiment has a gel-like resin only on a part of the region facing the outer peripheral surface S2 and extending from the corner of the semiconductor chip CHPa to the conductive wire WR2. RS is arranged and is not arranged in other areas. The gel resin RS in the semiconductor device DEV in FIG. 21 is formed by the same manufacturing method as in the first embodiment. In FIG. 21, the gel-like resin RS is disposed only on the conductive wire WR2 extending from the corner of the semiconductor chip CHPa, but only (at least a part of) the conductive wire extending from the corner of the semiconductor chips CHPb and CHPc. May be arranged so as to be embedded in the gel-like resin RS.

  The configuration of the semiconductor device DEV in FIG. 21 is different from the configuration of the semiconductor device DEV in FIG. 20 in the above points, and is otherwise the same as the configuration of the semiconductor device DEV shown in FIG. The same elements are denoted by the same reference numerals and the description thereof will not be repeated.

  As described above, at least one of the conductive wires that are particularly likely to come into contact with each other may be disposed so as to be in contact with the solidified gel-like resin RS. Although not shown, for example, only a part of a region where conductive wires WR3a and WR3b extend (from mutually stacked semiconductor chips CHPa and CHPb) facing outer peripheral surface S3 is manufactured by the same manufacturing method as in the second embodiment. Gel-like resin RS may be formed. Also in this case, at least one of the conductive wires that are particularly likely to come into contact with each other, in particular, the region that is particularly likely to come into contact with others may be arranged so as to be embedded in the solidified gel-like resin RS.

(Embodiment 5)
The present embodiment has an additional configuration with respect to the first to third embodiments in the configuration of the semiconductor device DEV, and the manufacturing method of the semiconductor device DEV has an additional configuration with respect to the first to third embodiments. It has a configuration.

  Referring to FIG. 22, the semiconductor device DEV in the first example of the present embodiment includes a substrate SUB and three semiconductors of a semiconductor chip CHPa, a semiconductor chip CHPb, and a semiconductor chip CHPd on one main surface of the substrate SUB. The chips are stacked in this order. As described above, in the present embodiment, in FIG. 22, the semiconductor chip CHPd is further stacked (arranged) on the semiconductor chip CHPa and the semiconductor chip CHPb in the second embodiment (see FIG. 10). Yes. A plurality of pad portions PD2d are formed on one main surface of the semiconductor chip CHPd. A plurality of finger portions PD1a, PD1b, and PD1d are arranged on one main surface of the substrate SUB. The conductive wire WR3 electrically connects the finger part PD1d and the pad part PD2d.

  In FIG. 22, the conductive wires WR1 and WR2 have a structure in which a part thereof is embedded in the gel-like resin RS by the manufacturing method of the second embodiment. In the present embodiment, the conductive wire WR3 is wire bonded so as to be in contact with the upper surface of the solidified gel-like resin RS.

  That is, in the configuration of FIG. 22, for example, after the gel-like resin RS is applied, the conductive wires WR1 and WR2 are bonded, and after the gel-like resin RS is solidified, the conductive wire WR3 is additionally solidified. Bonding is performed so as to contact the upper surface of the resin RS. In other words, the conductive wire WR3 is arranged such that a part of the conductive wires WR1 and WR2 is embedded in the gel-like resin RS and the gel-like resin RS is solidified, and then the upper surface of the gel-like resin RS is turned. Therefore, although the conductive wire WR3 is not fixed to the solidified gel resin RS, it is supported by the gel resin RS by contacting the upper surface of the gel resin RS.

  In FIG. 22, both the conductive wire WR1 and the conductive wire WR2 are embedded in the gel resin RS, but only one of them may be embedded in the gel resin RS. For example, referring to FIG. 23, in the semiconductor device DEV in the second example of the present embodiment, the gel-like resin RS is only part of the conductive wire WR1 as compared with the semiconductor device DEV in the first example of FIG. After the gel resin RS is solidified, additional wire bonding is performed so that the conductive wire WR2 is in contact with the upper surface of the gel resin RS. Further, the conductive wire WR3 extends without being in contact with the gel-like resin RS and other conductive wires.

  For example, when the conductive wire WR1 and the conductive wire WR2 are highly likely to be short-circuited with each other and the conductive wire WR3 is unlikely to be short-circuited with the others, the configuration illustrated in FIG.

  The configuration of the semiconductor device DEV of FIG. 23 is different from the configuration of the semiconductor device DEV of FIG. 22 in the above points, and is otherwise the same as the configuration of the semiconductor device DEV shown in FIG. The same elements are denoted by the same reference numerals and the description thereof will not be repeated.

  Referring to FIG. 24, the semiconductor device DEV according to the third example of the present embodiment has a substrate SUB and a semiconductor chip CHPa and a semiconductor chip CHPb stacked in this order on one main surface of the substrate SUB. The configuration is the same as that of the second embodiment (FIG. 10). That is, FIG. 24 is substantially the same as the configuration excluding the semiconductor chip CHPd and the conductive wire WR3 of the semiconductor device DEV of FIG. In this case, the conductive wire WR2 may be additionally wire-bonded so as to be in contact with the upper surface of the gel-like resin RS solidified after a part of the conductive wire WR1 is embedded.

  The configuration of the present embodiment shown in FIG. 22 to FIG. 24 is different from the configuration of the first to fourth embodiments in the above points, and in other points, the configuration of the first to fourth embodiments. Since it is the same, the same code | symbol is attached | subjected about the same element and the description is not repeated.

Next, the effect of this Embodiment is demonstrated.
Although the conductive wire that is additionally wire-bonded in this embodiment is not fixed to the gel-like resin RS, it is supported by the upper surface of the gel-like resin RS, so that the conductive wire is not in contact with the gel-like resin RS, for example. The possibility of causing a short circuit due to deformation or displacement is reduced as compared to a conductive wire that does not.

  Further, by performing wire bonding so that it is placed on the upper surface of the solidified gel-like resin RS as in the present embodiment, the gel-like resin RS is fixed or supported, for example, like the conductive wire WR3 of FIG. Compared to the conductive wire WR3 having a loop (trajectory) floating in the air, control of the shape of the trajectory becomes easier.

  The fifth embodiment of the present invention is different from the first to fourth embodiments of the present invention only in the points described above. That is, the configuration, conditions, procedures, effects, and the like that have not been described above for Embodiment 5 of the present invention are all the same as those of Embodiments 1 to 4 of the present invention.

(Embodiment 6)
In the first to fifth embodiments, a semiconductor chip is mounted on the substrate SUB. However, instead of the semiconductor chip, for example, a structure in which a semiconductor chip and an interposer are combined may be mounted on the substrate SUB, or a structure in which a semiconductor chip and a system substrate are combined may be mounted. Good. Alternatively, a structure in which the interposer and the system board are combined may be mounted on the board SUB. Here, the interposer means, for example, a relay board provided with wiring, and the system board means a board on which an integrated circuit in which a resistor, a capacitor, a semiconductor element and the like are combined is mounted.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims. Further, the shape of each conductive wire and the shape of the gel-like resin RS in each of the above drawings are not limited thereto, and can be any shape.

  The present invention can be applied particularly advantageously in a method of manufacturing a semiconductor device having a configuration in which bonding is performed with a conductive wire and sealing is performed with resin.

  CHP, CHPa, CHPb, CHPc, CHPd semiconductor chip, DEV semiconductor device, F1 cured film, MRS mold resin, PD1, PD1a, PD1b, PD1c, PD1d finger part, PD2, PD2a, PD2b, PD2c, PD2d pad part, RS gel Resin, S1 left outer peripheral surface, S2 right outer peripheral surface, S3 lower outer peripheral surface, S4 outer peripheral surface, SUB substrate, WR, WR1, WR2, WR3, WR3a, WR3b, WR4, WR4c, WR4d conductive wire .

Claims (6)

A substrate having a first main surface and having a connection pad disposed on the first main surface, and a second main surface disposed above the first main surface and having the second main surface Preparing a semiconductor chip having electrode pads disposed on the main surface;
Applying a first resin material to at least a part of a region sandwiched between the connection pad and the electrode pad in plan view;
After the step of applying the first resin material, a step of wire bonding the connection pad and the electrode pad with a conductive wire;
After the wire bonding step, the step of solidifying the first resin material;
A step of sealing by supplying and curing a second resin material so as to cover the upper portion of the substrate and the semiconductor chip,
In the wire bonding step, at least a part of the at least one conductive wire is disposed inside the first resin material, and the plurality of conductive wires do not contact each other,
The method for manufacturing a semiconductor device, wherein the temperature at which the first resin material is softened is higher than the processing temperature in the steps after the step of sealing by supplying and curing the second resin material. The semiconductor chip has a rectangular planar shape,
2. The manufacturing of a semiconductor device according to claim 1, wherein at least a part of the conductive wire connected to the electrode pad disposed at a corner of the semiconductor chip is disposed inside the first resin material. Method. Disposing at least one other semiconductor chip having a third main surface and having another electrode pad disposed on the third main surface above the second main surface of the semiconductor chip. When,
A step of additionally applying the first resin material to at least a part of a region sandwiched between the connection pad and the other electrode pad in plan view;
After the step of additionally applying the first resin material, a step of wire bonding the connection pad and the other electrode pad with the conductive wire;
A step of solidifying the first resin material applied in the step of additionally applying the first resin material after the step of wire bonding the connection pad and the other electrode pad;
In the sealing step, after the step of solidifying the first resin material applied in the additional applying step, the second resin material is supplied and cured so as to cover the upper side of the other semiconductor chip. Made by
In the step of wire bonding the connection pad and the other electrode pad, the plurality of conductive wires do not contact each other,
The temperature at which the first resin material applied in the step of additionally applying the first resin material is softened is the processing temperature in the steps after the step of sealing by supplying and curing the second resin material. The method for manufacturing a semiconductor device according to claim 1, wherein the method is higher. The other semiconductor chip has a rectangular planar shape,
The at least one part of the said conductive wire connected with the said other electrode pad arrange | positioned at a corner | angular part among said another semiconductor chip is arrange | positioned inside the said 1st resin material. A method for manufacturing a semiconductor device.   The solidifying step is performed by curing the first resin material around the conductive wire using heat generated in the conductive wire in the wire bonding step. A method for manufacturing a semiconductor device according to any one of the above.   6. The method according to claim 1, further comprising, after the solidifying step, a step of additionally wire-bonding the conductive wire disposed so as to be in contact with the upper surface of the solidified first resin material. Semiconductor device manufacturing method.

Images