JP2013045856A - Printed circuit board and radiation noise suppression method thereof - Google Patents

Printed circuit board and radiation noise suppression method thereof Download PDF

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JP2013045856A
JP2013045856A JP2011182077A JP2011182077A JP2013045856A JP 2013045856 A JP2013045856 A JP 2013045856A JP 2011182077 A JP2011182077 A JP 2011182077A JP 2011182077 A JP2011182077 A JP 2011182077A JP 2013045856 A JP2013045856 A JP 2013045856A
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printed circuit
circuit board
noise
impedance
radiation noise
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Hiroyuki Motoki
浩之 本木
Hideyuki Nakanishi
秀行 中西
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Aica Kogyo Co Ltd
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Abstract

PROBLEM TO BE SOLVED: To solve such a problem that although an input impedance (Z11) reduction method for suppressing power supply terminal noise or a transfer impedance (Z21) reduction method for suppressing noise propagation has been studied, the EMI countermeasure requires to suppress radiation noise of the whole system by cooperation design of the printed circuit board alone and the whole system (chip+package+board).SOLUTION: In a printed circuit board mounting an LSI, radiation noise is suppressed by controlling the transfer impedance (Z21) from the LSI terminal to the end of the printed circuit board, and evaluating the whole system including the LSI.

Description

放射ノイズの原因は(a)高速信号系コモンモード放射、(b)パッケージ・ヒートシンクなどからの放射、(c)スリット等による放射、(d)電源系共振、(e)ケーブルからの放射などであり、本発明は、これらの内(d)電源系共振から発生する放射ノイズの抑制に関し、中でも半導体集積回路(LSI)を含んだ電源供給系全体のトランスファー・インピーダンス(Z21)が低減されたプリント基板およびその放射ノイズを抑制する方法に関する。 Causes of radiation noise include (a) high-speed signal system common mode radiation, (b) radiation from packages and heat sinks, (c) radiation from slits, (d) power system resonance, (e) radiation from cables, etc. The present invention relates to (d) suppression of radiation noise generated from power supply system resonance, and in particular, printing in which the transfer impedance (Z21) of the entire power supply system including the semiconductor integrated circuit (LSI) is reduced. The present invention relates to a substrate and a method for suppressing radiation noise thereof.

従来、電源系共振から発生する放射ノイズの抑制には、コンデンサによる対策が一般的で、プリント基板単体での対策が主流であり、電源系のノイズ低減のためにはトランスファー・インピーダンス(Z21)を扱うことは少なく、コンデンサの配置方法による電圧変動の抑制、実測をベースとしたカット アンド トライの対策となっていた。   Conventionally, a countermeasure with a capacitor is generally used to suppress radiation noise generated from power system resonance, and a countermeasure with a single printed circuit board has been the mainstream, and transfer impedance (Z21) is used to reduce power system noise. It was rarely handled, and it was a countermeasure for cut-and-try based on measurement and suppression of voltage fluctuations due to the capacitor placement method.

また、半導体の動作に伴う電流量の増加により、電源端子ノイズが増加し、この電源端子ノイズがプリント基板を伝播し、不要電磁放射(EMI)の原因となっている。 Further, an increase in the amount of current accompanying the operation of the semiconductor causes an increase in power supply terminal noise. This power supply terminal noise propagates through the printed circuit board, causing unnecessary electromagnetic radiation (EMI).

特許文献1には、LSIの電源端子近傍に搭載するデカップリングコンデンサの数量をLSIごとに最適化することで、高周波電源電流を抑制し、実装スペースの削減と資材コストを削減すると共に、回路の安定動作とEMIを低減することを可能としたプリント基板の設計方法が提案されているが、これはLSI設計工程で設計が完了したLSIの出力バッファ種別などの設計情報やパターン設計工程で設計が完了した設計情報を用いるものである。 In Patent Document 1, by optimizing the number of decoupling capacitors mounted in the vicinity of the power supply terminal of the LSI for each LSI, the high frequency power supply current is suppressed, the mounting space is reduced and the material cost is reduced. A printed circuit board design method that enables stable operation and EMI reduction has been proposed. This is because design information such as LSI output buffer type, which has been designed in the LSI design process, can be designed in the pattern design process. The completed design information is used.

特開2002−73716号公報JP 2002-73716 A

これまで、電源端子ノイズ抑制を目的としたインプット・インピーダンス(Z11)低減手法やノイズ伝播抑制を目的としたトランスファー・インピーダンス(Z21)低減手法に関する検討が行われてきたが、これらは、プリント基板単体での評価であり、プリント基板単体とシステム全体(チップ+パッケージ+ボード)とでは、インピーダンス特性が異なるため、プリント基板単体ではなくLSIとボードの協調設計により、システム全体の電源ノイズを検証することで、EMI対策を実施する必要がある。   Up to now, studies have been made on the input impedance (Z11) reduction method for the purpose of suppressing power supply terminal noise and the transfer impedance (Z21) reduction method for the purpose of suppressing noise propagation. Because the impedance characteristics of the printed circuit board alone and the entire system (chip + package + board) are different, the power supply noise of the entire system should be verified by co-designing the LSI and board instead of the printed circuit board alone. Therefore, it is necessary to implement EMI countermeasures.

本発明は、LSIやパターン設計工程の設計情報が完了していない場合であっても、LSI内部のチップからプリント基板端までのトランスファー・インピーダンス(Z21)を制御することにより、LSIを含んだシステム全体での評価を行ない、放射ノイズが抑制されたプリント基板を提供しようとするものである。   The present invention is a system including an LSI by controlling the transfer impedance (Z21) from the chip inside the LSI to the end of the printed circuit board even when the design information of the LSI and the pattern design process is not completed. The overall evaluation is performed to provide a printed circuit board in which radiation noise is suppressed.

請求項1の発明は、プリント基板上のコンデンサやプリント基板の寄生成分(インダクタンスおよびキャパシタンス)による反共振(高インピーダンス点)が半導体集積回路(LSI)のノイズ周波数と一致しないように制御されたプリント基板であって、得られたプリント基板は、放射ノイズが抑制されたものになる。   According to the first aspect of the present invention, the printed circuit board is controlled so that the anti-resonance (high impedance point) due to the capacitor on the printed circuit board and the parasitic components (inductance and capacitance) of the printed circuit board does not match the noise frequency of the semiconductor integrated circuit (LSI). A printed circuit board obtained by suppressing radiation noise.

請求項2の発明は、ノイズ源となる半導体集積回路(LSI)からプリント基板端までのトランスファー・インピーダンス(Z21)の低減により、反共振(高インピーダンス点)がノイズ周波数と一致しないように制御されたプリント基板であって、得られたプリント基板は、放射ノイズが抑制されたものになる。   The invention of claim 2 is controlled so that the anti-resonance (high impedance point) does not coincide with the noise frequency by reducing the transfer impedance (Z21) from the semiconductor integrated circuit (LSI) serving as a noise source to the printed circuit board end. In the printed circuit board, the obtained printed circuit board has reduced radiation noise.

請求項3の発明は、前記トランスファー・インピーダンス(Z21)の低減が、半導体集積回路(LSI)のインピーダンスモデルと、前記プリント基板のインピーダンスモデルとを協調して設計されたプリント基板であって、得られたプリント基板は、放射ノイズが抑制されたものになる。   According to a third aspect of the present invention, there is provided a printed circuit board in which the reduction of the transfer impedance (Z21) is designed in cooperation with an impedance model of a semiconductor integrated circuit (LSI) and an impedance model of the printed circuit board. The printed circuit board thus obtained has suppressed radiation noise.

請求項4の発明は、前記協調が、コンデンサの変更によるものであることを特徴とするものであって、コンデンサを選択することによって、放射ノイズが抑制されたプリント基板となる。   The invention of claim 4 is characterized in that the cooperation is due to a change of a capacitor, and by selecting a capacitor, a printed circuit board in which radiation noise is suppressed is obtained.

請求項5の発明は、プリント基板上のコンデンサやプリント基板の寄生成分(インダクタンスおよびキャパシタンス)による反共振(高インピーダンス点)が半導体集積回路(LSI)のノイズ周波数と一致しないように制御するプリント基板の放射ノイズ抑制方法であって、得られるプリント基板は、放射ノイズが抑制されたものになる。   According to a fifth aspect of the present invention, there is provided a printed circuit board for controlling an anti-resonance (high impedance point) due to a capacitor on the printed circuit board and parasitic components (inductance and capacitance) of the printed circuit board not to coincide with a noise frequency of a semiconductor integrated circuit (LSI). In the method for suppressing radiation noise, the obtained printed circuit board has radiation noise suppressed.

請求項6の発明は、前記制御が、ノイズ源となる半導体集積回路(LSI)からプリント基板端までのトランスファー・インピーダンス(Z21)を低減させて、反共振(高インピーダンス点)とノイズ周波数とを一致させないようにするプリント基板の放射ノイズ抑制方法であって、得られるプリント基板は、放射ノイズが抑制されたものになる。 According to a sixth aspect of the present invention, the control reduces the transfer impedance (Z21) from the semiconductor integrated circuit (LSI) serving as a noise source to the printed circuit board end to reduce the anti-resonance (high impedance point) and the noise frequency. A method for suppressing radiation noise of a printed circuit board that does not match, wherein the obtained printed circuit board has radiation noise suppressed.

請求項7の発明は、半導体集積回路のインピーダンスモデルと、前記プリント基板のインピーダンスモデルとを協調させて、前記トランスファー・インピーダンス(Z21)を低減するプリント基板の放射ノイズ抑制方法であって、得られるプリント基板は、放射ノイズが抑制されたものになる。 The invention according to claim 7 is a printed circuit board radiation noise suppression method for reducing the transfer impedance (Z21) by coordinating an impedance model of a semiconductor integrated circuit and an impedance model of the printed circuit board, and is obtained. The printed circuit board has reduced radiation noise.

請求項8の発明は、前記協調が、コンデンサの変更によるものであることを特徴とするものであって、コンデンサを選択することによって、プリント基板の放射ノイズを抑制することができる。 The invention according to claim 8 is characterized in that the cooperation is based on a change of a capacitor, and by selecting the capacitor, radiation noise of the printed circuit board can be suppressed.

本発明によれば、設計情報が完了していない場合であっても、LSIからプリント基板端までのトランスファー・インピーダンス(Z21)を制御することにより、放射ノイズが低減され、さらにLSIのインピーダンスモデルと、プリント基板のインピーダンスモデルとを協調させることにより放射ノイズが低減されたプリント基板となる。   According to the present invention, even when the design information is not completed, the radiation noise is reduced by controlling the transfer impedance (Z21) from the LSI to the printed circuit board end, and the LSI impedance model By coordinating with the impedance model of the printed circuit board, a printed circuit board with reduced radiation noise is obtained.

本発明のプリント基板評価ボードの概略図である。It is the schematic of the printed circuit board evaluation board of this invention. LSIモデルボードおよびマザーボードのインピーダンスモデル解析のためのシミュレーション回路である。It is a simulation circuit for impedance model analysis of an LSI model board and a motherboard. 実施例1のマザーボードにLSIモデルボードを実装したときのプリント基板評価ボードの電流波形のFFT結果である。It is a FFT result of the current waveform of the printed circuit board evaluation board when the LSI model board is mounted on the motherboard of the first embodiment. 実施例1のZ21と放射ノイズの関係を示す測定結果である。It is a measurement result which shows the relationship between Z21 of Example 1, and radiation noise. 実施例2のZ21と放射ノイズの関係を示す測定結果である。It is a measurement result which shows the relationship between Z21 of Example 2, and radiation noise. 実施例3のZ21と放射ノイズの関係を示す測定結果である。It is a measurement result which shows the relationship between Z21 of Example 3, and radiation noise. 実施例4のZ21と放射ノイズの関係を示す測定結果である。It is a measurement result which shows the relationship between Z21 of Example 4, and radiation noise. 実施例5のZ21と放射ノイズの関係を示す測定結果である。It is a measurement result which shows the relationship between Z21 of Example 5, and radiation noise. 実施例6のZ21と放射ノイズの関係を示す測定結果である。It is a measurement result which shows the relationship between Z21 of Example 6, and radiation noise. 実施例7のZ21と放射ノイズの関係を示す測定結果である。It is a measurement result which shows the relationship between Z21 of Example 7, and radiation noise. 実施例8のZ21と放射ノイズの関係を示す測定結果である。It is a measurement result which shows the relationship between Z21 of Example 8, and radiation noise.

LSIモデルボードとマザーボードの作製
任意の電源インピーダンス特性を得るために、図1に示すように、それぞれのボードにコンデンサを実装し、両ボードの組み合わせにより、ノイズの発生し易い(し難い)評価ボードを作製した。
Fabrication of LSI model board and mother board In order to obtain arbitrary power supply impedance characteristics, as shown in Fig. 1, capacitors are mounted on each board, and the combination of both boards is likely to generate noise. A difficult evaluation board was produced.

LSIモデルボード
回路構成は水晶発振器、Shift Register、EXOR、Buffer/DriverからなるPRBS信号発生ボードで、クロック周波数は48MHzとした。評価対象をBuffer/Driverのノイズに限定するため、その他ICとは電源供給を分離し、ボードは汎用BGAパッケージをモデルとする32mm×32mmサイズの900BallのBGAとした。
The LSI model board circuit configuration is a PRBS signal generation board made up of a crystal oscillator, Shift Register, EXOR, and Buffer / Driver, and the clock frequency is 48 MHz. In order to limit the evaluation object to Buffer / Driver noise, the power supply was separated from the other ICs, and the board was a 900 mm BGA of 32 mm × 32 mm size modeled on a general purpose BGA package.

マザーボード
基板中央にLSIモデルボードが実装可能で、安定化電源から電源供給を受け、LSIモデルボード直下および基板全体の電源グラウンド間にコンデンサを実装可能とした。
Motherboard <br/> substrate center to the LSI model boards can be mounted, supplied with power from a stabilized power supply, and can be mounted a capacitor between LSI model board directly below and the entire substrate of the power supply ground.

電流プロファイル取得
電流測定用抵抗(0.05Ω)の両端の電位差を測定し、I=V/Rより電流波形を計算した。また、電流波形をFFTし、周波数データを取得した。測定にはデジタルオシロスコープ(Agilent Technologies社DSA90804A)を用いた。
Current profile acquisition The potential difference between both ends of the resistance for current measurement (0.05Ω) was measured, and the current waveform was calculated from I = V / R. Further, the current waveform was FFTed to obtain frequency data. A digital oscilloscope (Agilent Technologies DSA90804A) was used for the measurement.

電源インピーダンスシミュレーション
図2のようなシミュレーション回路において、LSIモデルボード、マザーボードのインピーダンスモデルを平面電磁界解析(Ansys社SIWave)よりSパラメータを用いて抽出し、ノイズ源IC(Buffer/Driver)の内部インピーダンスをZ11測定より算出し、LCRの集中定数としてモデル化した。なお、本形態では、ノイズ源ICの電源端子を仮のノイズ源とし、ポートを付与した。
Power supply impedance simulation In the simulation circuit as shown in FIG. 2, the impedance model of the LSI model board and the motherboard is extracted from the planar electromagnetic field analysis (Ansys SI Wave) using the S parameter, and the internal impedance of the noise source IC (Buffer / Driver) Was calculated from the Z11 measurement and modeled as the LCR lumped constant. In this embodiment, the power source terminal of the noise source IC is used as a temporary noise source and a port is provided.

基板端電圧測定
スペクトラムアナライザ(ADVANTEST社R3131A)を用いて基板端電圧を測定し、基板端4箇所の測定結果がほぼ同じであることを確認の上、代表1箇所の測定とした。
The substrate end voltage was measured using a substrate end voltage measurement spectrum analyzer (ADVANTEST R3131A), and after confirming that the measurement results at the four ends of the substrate were almost the same, the measurement was made at one representative location.

放射ノイズ測定
また、プリント基板の放射ノイズ抑制効果を測るために、小型電波暗室(外形寸法:7m×3m×3m、アンテナ〜試供体間距離:3m、アンテナ高:1m(固定))にて、放射ノイズを測定した。評価ボードはターンテーブル中央に配置し、安定化電源はテーブル下に配置し、EMC MEASUREMENT SYSTEM(東陽テクニカ社)により測定した。
Radiation noise measurement In order to measure the radiation noise suppression effect of the printed circuit board, a small anechoic chamber (external dimensions: 7 m x 3 m x 3 m, antenna-to-sample distance: 3 m, antenna height: 1 m (fixed) ) To measure the radiation noise. The evaluation board was placed at the center of the turntable, the stabilized power source was placed under the table, and measurement was performed with EMC MEASUREMENT SYSTEM (Toyo Technica).

電流プロファイルのFFT結果より、図3に示すように、クロック周波数(48MHz)の3次高調波(144MHz)までの電流成分が顕著であり、当該プリント基板は、これらの周波数での放射ノイズを抑制することが必要であり、48MHzのノイズを抑制するためには0.01μFのコンデンサが、96MHzのノイズを抑制するためには2200pFのコンデンサが、144MHzのノイズを抑制するためには1000pFのコンデンサが有効であることより、これらを組み合わせた。 From the FFT result of the current profile, as shown in FIG. 3, the current component up to the third harmonic (144 MHz) of the clock frequency (48 MHz) is significant, and the printed circuit board suppresses radiation noise at these frequencies. A 0.01 μF capacitor is required to suppress 48 MHz noise, a 2200 pF capacitor is required to suppress 96 MHz noise, and a 1000 pF capacitor is required to suppress 144 MHz noise. These were combined because of their effectiveness.

LSIモデルボード、マザーボードに実装するコンデンサを表1のようにし、放射ノイズの評価を行った。コンデンサはノイズ周波数でトランスファー・インピーダンス(Z21)が高くなる、または低くなるように選択した。 The capacitors mounted on the LSI model board and the motherboard were set as shown in Table 1, and the radiation noise was evaluated. The capacitor was selected so that the transfer impedance (Z21) was increased or decreased at the noise frequency.

Figure 2013045856
Figure 2013045856

表2にノイズ周波数毎のZ21と基板端電圧を示す。   Table 2 shows Z21 and substrate end voltage for each noise frequency.

Figure 2013045856
Figure 2013045856

Z21と基板端電圧には相関があり、クロック周波数(48MHz)とその高調波(96MHz、144MHz)が高インピーダンスとなる条件では、ノイズが大きくなり、Z21はノイズ伝播に寄与している。   There is a correlation between Z21 and the substrate end voltage. Under the condition that the clock frequency (48 MHz) and its harmonics (96 MHz, 144 MHz) have a high impedance, noise increases, and Z21 contributes to noise propagation.

また、遠方界放射ノイズ測定結果より、表3および図4から11に示すように、Z21の増減傾向と放射ノイズレベルの増減傾向は一致する。 From the far-field radiation noise measurement results, as shown in Table 3 and FIGS. 4 to 11, the increase / decrease tendency of Z21 coincides with the increase / decrease tendency of the radiation noise level.

Figure 2013045856
Figure 2013045856

プリント基板の放射ノイズを抑制するためには、LSIからプリント基板端までのトランスファー・インピーダンス(Z21)を低減し、さらにLSIのインピーダンスモデルと、プリント基板のインピーダンスモデルとを協調させることが効果的であり、得られるプリント基板は放射ノイズが低減されたプリント基板となる。 In order to suppress radiation noise from the printed circuit board, it is effective to reduce the transfer impedance (Z21) from the LSI to the printed circuit board edge, and to coordinate the LSI impedance model with the printed circuit board impedance model. The obtained printed circuit board is a printed circuit board with reduced radiation noise.

1:プリント基板、2:マザーボード、3:LSIモデルボード、4:ノイズ源、5:大容量コンデンサ、6:チョークコイル、7:外部電源、8:グラウンド、9:電源
1: printed circuit board, 2: motherboard, 3: LSI model board, 4: noise source, 5: large-capacitance capacitor, 6: choke coil, 7: external power supply, 8: ground, 9: power supply

Claims (8)

プリント基板上のコンデンサやプリント基板の寄生成分(インダクタンスおよびキャパシタンス)による反共振(高インピーダンス点)が半導体集積回路のノイズ周波数と一致しないように制御されていることを特徴とするプリント基板。 A printed circuit board characterized in that an antiresonance (high impedance point) due to a capacitor on the printed circuit board and parasitic components (inductance and capacitance) of the printed circuit board does not coincide with a noise frequency of a semiconductor integrated circuit. 前記制御が、ノイズ源となる半導体集積回路からプリント基板端までのトランスファー・インピーダンスの低減によるものであることを特徴とする請求項1記載のプリント基板。 2. The printed circuit board according to claim 1, wherein the control is performed by reducing a transfer impedance from a semiconductor integrated circuit serving as a noise source to the printed circuit board end. 前記トランスファー・インピーダンスの低減が、半導体集積回路のインピーダンスモデルと、前記プリント基板のインピーダンスモデルとを協調して設計されたものであることを特徴とする請求項2記載のプリント基板。 The printed circuit board according to claim 2, wherein the transfer impedance reduction is designed by coordinating an impedance model of a semiconductor integrated circuit and an impedance model of the printed circuit board. 前記協調が、コンデンサの変更によるものであることを特徴とする請求項3記載のプリント基板。 4. The printed circuit board according to claim 3, wherein the cooperation is by changing a capacitor. プリント基板上のコンデンサやプリント基板の寄生成分(インダクタンスおよびキャパシタンス)による反共振(高インピーダンス点)が半導体集積回路のノイズ周波数と一致しないように制御することを特徴とする放射ノイズ抑制方法。 A method for suppressing radiation noise, comprising controlling anti-resonance (high impedance point) due to a capacitor on a printed circuit board and parasitic components (inductance and capacitance) of the printed circuit board so as not to coincide with a noise frequency of a semiconductor integrated circuit. 前記制御が、ノイズ源となる半導体集積回路からプリント基板端までのトランスファー・インピーダンスを低減させて制御することを特徴とする請求項5記載の放射ノイズ抑制方法。 6. The radiation noise suppression method according to claim 5, wherein the control is performed by reducing transfer impedance from a semiconductor integrated circuit serving as a noise source to a printed circuit board end. 半導体集積回路のインピーダンスモデルと、前記プリント基板のインピーダンスモデルとを協調させて、前記トランスファー・インピーダンスを低減することを特徴とする請求項6記載の放射ノイズ抑制方法。 The radiation noise suppression method according to claim 6, wherein the transfer impedance is reduced by coordinating an impedance model of a semiconductor integrated circuit and an impedance model of the printed circuit board. 前記協調が、コンデンサの変更によるものであることを特徴とする請求項7記載の放射ノイズ抑制方法。 The radiation noise suppression method according to claim 7, wherein the cooperation is by changing a capacitor.
JP2011182077A 2011-08-24 2011-08-24 Printed circuit board and radiation noise suppression method thereof Pending JP2013045856A (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001196262A (en) * 2000-01-06 2001-07-19 Toshiba Corp Radiation noise reduction system and electronic apparatus therwith
JP2005011938A (en) * 2003-06-18 2005-01-13 Murata Mfg Co Ltd High frequency electronic circuit and structure for mounting chip-type three-terminal capacitor onto high frequency electronic circuit
JP2005031850A (en) * 2003-07-09 2005-02-03 Fujitsu Ltd Power supply noise analysis method
JP2007048879A (en) * 2005-08-09 2007-02-22 Nec Corp Electronic device
JP2007324221A (en) * 2006-05-30 2007-12-13 Toshiba Corp Printed circuit board
JP2009230694A (en) * 2008-03-25 2009-10-08 Nec Corp Design adequacy verification device, method and program regarding suppression of power source noise of electronic circuit board

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001196262A (en) * 2000-01-06 2001-07-19 Toshiba Corp Radiation noise reduction system and electronic apparatus therwith
JP2005011938A (en) * 2003-06-18 2005-01-13 Murata Mfg Co Ltd High frequency electronic circuit and structure for mounting chip-type three-terminal capacitor onto high frequency electronic circuit
JP2005031850A (en) * 2003-07-09 2005-02-03 Fujitsu Ltd Power supply noise analysis method
JP2007048879A (en) * 2005-08-09 2007-02-22 Nec Corp Electronic device
JP2007324221A (en) * 2006-05-30 2007-12-13 Toshiba Corp Printed circuit board
JP2009230694A (en) * 2008-03-25 2009-10-08 Nec Corp Design adequacy verification device, method and program regarding suppression of power source noise of electronic circuit board

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JPN7016001109; プリント基板の電源配線の設計方法 , 2010, #2-#13, アイカ工業(株)電子カンパニー基板商品開発グループ *

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