JP2013039031A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the malfunction of a power device.SOLUTION: A semiconductor device for controlling to drive a power device on a higher potential side between two power devices connected in series includes: a pulse generator circuit for generating a first and a second pulse signal respectively corresponding to level transition to a first and a second state of an input signal having a first state indicative of the conduction of the power device on the high potential side and a second state indicative of the non-conduction of the power device on the high potential side; a level shift circuit for obtaining a first and a second level-shifted pulse signal by shifting the first and the second pulse signals to the high potential side; a delay circuit for delaying the first and the second level-shifted pulse signals at least as large as the pulse widths of the first and the second pulse signals, to obtain a first and a second delayed pulse signal, respectively; and an SR-type flip-flop to which the first delayed pulse signal is input from a set input and the second delayed pulse signal is input from a reset input.

Description

  The present invention relates to a semiconductor device that drives and controls a high-potential-side power device among two power devices connected in series between a high-potential main power supply potential and a low-potential main power supply potential. The present invention relates to a semiconductor device capable of preventing malfunction.

  FIG. 14 is a circuit diagram showing a half-bridge circuit. Between the positive electrode and the negative electrode (ground potential GND) of the power supply PS, power devices 101 and 102 such as IGBT (insulated gate bipolar transistor) are connected totem pole. Further, free wheel diodes D1 and D2 are connected in reverse parallel to the power devices 101 and 102, respectively. A load (inductive load such as a motor) 103 is connected to a connection point N1 between the power device 101 and the power device 102.

  The power device 101 is a device that performs a switching operation between the reference potential and the power supply potential supplied by the power source PS with the potential at the connection point N1 with the power device 102 as a reference potential, and is called a high potential side power device. On the other hand, the power device 102 is a device that performs a switching operation between the reference potential and the potential at the connection point N1, using the ground potential as a reference potential, and is called a low potential side power device.

  The power device 101 is driven by the high potential side power device driving circuit HD, and the power device 102 is driven by the low potential side power device driving circuit LD. The high potential side power device drive circuit HD includes a positive voltage VB (high potential side floating power supply absolute voltage) of the high potential side power supply 104 and a negative voltage VS (high potential side floating power supply offset voltage) of the high potential side power supply 104. ) Are applied. Then, the high potential side power device driving circuit HD outputs the output signal HO to the gate electrode of the power device 102. The low-potential side power device drive circuit LD is not related to the present invention and will not be described.

  FIG. 15 is a circuit diagram showing a conventional semiconductor device. This semiconductor device includes a high-potential-side power device driving circuit that drives and controls a high-potential-side power device among two power devices connected in series between a high-potential main power-supply potential and a low-potential main power-supply potential. It is.

  An input signal HIN is given from an external microcomputer or the like. The input signal HIN includes “H (high potential)” (first state) indicating conduction of the high-potential side power device and “L (low potential)” (second state) indicating non-conduction of the high-potential side power device. ).

  The pulse generation circuit 11 outputs a pulsed ON signal (first pulse signal) and OFF signal (second pulse signal) in response to the level transition of the input signal HIN to “H” and “L”, respectively. generate.

  Two outputs of the pulse generation circuit 11 are connected to gate electrodes of high voltage N-channel field effect transistors (hereinafter referred to as HNMOS transistors) 12 and 13, which are level shift transistors. The ON signal is supplied to the gate electrode of the HNMOS transistor 12 and the OFF signal is supplied to the gate electrode of the HNMOS transistor 13. The drain electrodes of the HNMOS transistors 12 and 13 are connected to one ends of the resistors 14 and 15, respectively, and also connected to the inputs of the inverters 16 and 17.

  The HNMOS transistors 12 and 13, the resistors 14 and 15 and the inverters 16 and 17 constitute a level shift circuit. The level shift circuit shifts the ON signal and the OFF signal to the high potential side to obtain first and second level-shifted pulse signals, respectively.

  The SR flip-flop 19 inputs the output signals (first and second level-shifted pulse signals) of the inverters 16 and 17 from the set input S and the reset input R, respectively, via the protection circuit 18. Here, the protection circuit 18 is a filter circuit for preventing malfunction of the SR flip-flop 19 and is configured by a logic gate.

  The output Q of the SR flip-flop 19 is connected to the gate electrode of the NMOS transistor 20 and also to the input of the inverter 21, and the output of the inverter 21 is connected to the gate electrode of the NMOS transistor 22. The voltage at the connection point of the NMOS transistors 20 and 22 is output as the output signal HO on the high potential side. In this way, the power device 101 is switched by turning on and off the NMOS transistors 20 and 22 in a complementary manner.

  The other ends of the resistors 14 and 15 are connected to the drain electrode side of the NMOS transistor 20, and a voltage VB is applied thereto. Further, the source electrode of the NMOS transistor 22 is connected to the anodes of the diodes 23 and 24 and the connection point N1 in FIG. 14, and the voltage VS is applied. The cathodes of the diodes 23 and 24 are connected to the drain electrodes of the HNMOS transistors 12 and 13, respectively.

  Next, the operation of the conventional high potential side power device driving circuit will be described with reference to the timing chart shown in FIG.

  First, the pulse generation circuit 11 generates a pulsed ON signal that transitions to “H (high potential)” in response to the rising of the input signal HIN. The HNMOS transistor 12 is turned on by this ON signal. At this time, the OFF signal is “L (low potential)”, and the HNMOS transistor 13 is in the OFF state.

  As a result, a voltage drop occurs in the resistor 14 connected to the HNMOS transistor 12, and an “L” signal is input to the inverter 16. On the other hand, since no voltage drop occurs in the resistor 15 connected to the HNMOS transistor 13, the “H” signal is continuously input to the inverter 17. Therefore, the output signal of the inverter 16 becomes a pulse signal that changes to “H”, and the output signal of the inverter 17 maintains the “L” state.

  The protection circuit 18 that has received the output signals of the inverters 16 and 17 outputs a pulse signal that transitions to “L” corresponding to the output signal of the inverter 16 to the set input S of the SR flip-flop 19. . On the other hand, the protection circuit 18 outputs an “H” signal corresponding to the output signal of the inverter 17 to the reset input R of the SR flip-flop 19.

  The pulse generation circuit 11 generates a pulse-like OFF signal that transitions to “H (high potential)” in response to the falling of the input signal HIN. In this case as well, the same operation as described above is performed, and the protection circuit 18 outputs an “H” signal corresponding to the output signal of the inverter 16 to the set input S of the SR flip-flop 19. On the other hand, the protection circuit 18 outputs a pulse signal that transitions to “L” corresponding to the output signal of the inverter 17 with respect to the reset input R of the SR flip-flop 19.

  As a result, the output Q of the SR flip-flop 19 transitions to “H” when the ON signal is applied, and transitions to “L” when the OFF signal is applied. Further, the output signal HO obtained by turning on and off the NMOS transistors 20 and 22 in a complementary manner is the same signal.

  The problem here is the dv / dt transient signal generated in the line from the connection point N1 to the anodes of the diodes 23 and 24 depending on the switching state of the half-bridge power device composed of the power devices 101 and 102. .

  When a dv / dt transient signal is generated, a dv / dt current obtained by integrating the parasitic capacitance between the drain and source of the HNMOS transistors 12 and 13 and the dv / dt transient signal flows through the HNMOS transistors 12 and 13 simultaneously. As a result, an error pulse due to the dv / dt transient signal is simultaneously given instead of the ON signal and the OFF signal. In such a case, the protection circuit 18 is configured to prevent simultaneous signal input to the SR flip-flop 19 (see, for example, Patent Document 1).

Japanese Patent Laid-Open No. 9-200017

  When the output signal HO of the high potential side power device driving circuit HD is “H”, the power device 101 is turned on, and a current I1 flows as shown in FIG. After that, when the output signal HO of the high potential side power device driving circuit HD changes from “H” to “L” and the power device 101 is switched from ON to OFF, the current I2 flows in the freewheel diode D2. Become. At this time, the voltage VS temporarily becomes lower than GND due to the dv / dt transient signal and the wiring inductance, and becomes a negative voltage.

  In the conventional semiconductor device, an ON signal or an OFF signal is output simultaneously with switching of the power device 101. However, when the voltage VS becomes a negative voltage by switching the power device 101, the HNMOS transistor 12 is OFF and the HNMOS transistor 13 is unbalanced by the ON signal and OFF signal. For this reason, a difference occurs in the recovery current flowing through the parasitic diodes 25 and 26 of the HNMOS transistors 12 and 13. As a result, an incorrect output signal HO is output, causing a malfunction of the power device.

  The present invention has been made to solve the above-described problems, and an object thereof is to obtain a semiconductor device capable of preventing a malfunction of a power device.

  A semiconductor device according to the present invention is a semiconductor device that drives and controls a high-potential side power device among two power devices connected in series between a high-potential main power supply potential and a low-potential main power supply potential. In response to a level transition of the input signal having the first state indicating conduction of the high-potential side power device and the second state indicating non-conduction of the high-potential side power device to the first and second states. A pulse generation circuit for generating the first and second pulse signals, respectively, and level-shifting the first and second pulse signals to the high potential side, respectively, for the first and second level-shifted pulses, respectively. A level shift circuit for obtaining a signal, and the first and second level-shifted pulse signals are delayed by at least the pulse width of the first and second pulse signals, respectively. And obtaining a delay circuit, receiving said first delayed pulse signal from the set input, characterized in that it comprises an SR-type flip-flop for inputting the second delayed pulse signal from the reset input.

  According to the present invention, malfunction of the power device can be prevented.

1 is a circuit diagram showing a semiconductor device according to a first embodiment of the present invention. 4 is a timing chart for explaining the operation of the semiconductor device according to the first embodiment of the present invention; It is a circuit diagram which shows the semiconductor device which concerns on Embodiment 2 of this invention. 6 is a timing chart for explaining the operation of the semiconductor device according to the second embodiment of the present invention; It is a circuit diagram which shows the semiconductor device which concerns on Embodiment 3 of this invention. 6 is a timing chart for explaining the operation of the semiconductor device according to the third embodiment of the present invention; It is a circuit diagram which shows the semiconductor device which concerns on Embodiment 4 of this invention. 6 is a timing chart for explaining the operation of the semiconductor device according to the fourth embodiment of the present invention; It is a circuit diagram which shows the semiconductor device which concerns on Embodiment 5 of this invention. 10 is a timing chart for explaining the operation of the semiconductor device according to the fifth embodiment of the present invention; It is a circuit diagram which shows the semiconductor device which concerns on Embodiment 6 of this invention. It is a circuit diagram which shows the semiconductor device which concerns on Embodiment 7 of this invention. It is a circuit diagram which shows the semiconductor device which concerns on Embodiment 8 of this invention. It is a circuit diagram which shows a half-bridge circuit. It is a circuit diagram which shows the conventional semiconductor device. It is a timing chart for demonstrating operation | movement of the conventional semiconductor device.

Embodiment 1 FIG.
FIG. 1 is a circuit diagram showing a semiconductor device according to the first embodiment of the present invention. This semiconductor device includes a high-potential-side power device driving circuit that drives and controls a high-potential-side power device among two power devices connected in series between a high-potential main power-supply potential and a low-potential main power-supply potential. It is.

  An input signal HIN is given from an external microcomputer or the like. The input signal HIN includes “H (high potential)” (first state) indicating conduction of the high-potential side power device and “L (low potential)” (second state) indicating non-conduction of the high-potential side power device. ).

  The pulse generation circuit 11 outputs a pulsed ON signal (first pulse signal) and OFF signal (second pulse signal) in response to the level transition of the input signal HIN to “H” and “L”, respectively. generate.

  Two outputs of the pulse generation circuit 11 are connected to gate electrodes of high voltage N-channel field effect transistors (hereinafter referred to as HNMOS transistors) 12 and 13, which are level shift transistors. The ON signal is supplied to the gate electrode of the HNMOS transistor 12 and the OFF signal is supplied to the gate electrode of the HNMOS transistor 13. The drain electrodes of the HNMOS transistors 12 and 13 are connected to one ends of the resistors 14 and 15, respectively, and also connected to the inputs of the inverters 16 and 17.

  The HNMOS transistors 12 and 13, the resistors 14 and 15 and the inverters 16 and 17 constitute a level shift circuit. The level shift circuit shifts the ON signal and the OFF signal to the high potential side to obtain first and second level-shifted pulse signals, respectively.

  The SR flip-flop 19 inputs the output signals (first and second level-shifted pulse signals) of the inverters 16 and 17 from the set input S and the reset input R, respectively, via the protection circuit 18. Here, the protection circuit 18 is a filter circuit for preventing a malfunction of the SR flip-flop 19, and includes NAND circuits 31 to 33, inverters 34 to 38, and NOR circuits 39 and 40.

  The NOR circuit 41 receives the first and second level-shifted pulse signals and performs a NOR operation. The D-type flip-flop 42 inputs the output of the NOR circuit 41 from the clock input T, and inputs the output of the SR-type flip-flop 19 from the data input D. The NOR circuit 41 and the D-type flip-flop 42 constitute a delay circuit. This delay circuit delays the output of the SR flip-flop 19 by at least the pulse width of the ON signal and the OFF signal.

  The output Q ′ of the D-type flip-flop 42 is connected to the gate electrode of the NMOS transistor 20 and is also connected to the input of the inverter 21, and the output of the inverter 21 is connected to the gate electrode of the NMOS transistor 22. The voltage at the connection point of the NMOS transistors 20 and 22 is output as the output signal HO on the high potential side. In this way, the NMOS transistors 20 and 22 are complementarily turned on and off to switch the power device on the high potential side.

  The other ends of the resistors 14 and 15 are connected to the drain electrode side of the NMOS transistor 20, and a voltage VB is applied thereto. Further, the source electrode of the NMOS transistor 22 is connected to the anodes of the diodes 23 and 24 and the connection point N1 in FIG. 14, and the voltage VS is applied. The cathodes of the diodes 23 and 24 are connected to the drain electrodes of the HNMOS transistors 12 and 13, respectively.

  FIG. 2 is a timing chart for explaining the operation of the semiconductor device according to the first embodiment of the present invention. As shown in the figure, the output signal HO is switched after the ON signal and the OFF signal are output. Thereby, when the voltage VS is a negative voltage due to switching of the power devices, the ON signal and the OFF signal are not output. Therefore, malfunction of the power device can be prevented. Further, since the output of the SR flip-flop 19 is logically delayed, there is little element variation.

Embodiment 2. FIG.
FIG. 3 is a circuit diagram showing a semiconductor device according to the second embodiment of the present invention, and FIG. 4 is a timing chart for explaining its operation.

  The second embodiment includes a first inverter 43, a NAND circuit 44, a second inverter 45, and an OR circuit 46 as a delay circuit. Other configurations are the same as those of the first embodiment.

  The first inverter 43 inverts the first level-shifted pulse signal. The NAND circuit 44 inputs the output of the first inverter 43 and the output of the SR flip-flop 19 and performs a NAND operation. The second inverter 45 inverts the output of the NAND circuit 44. The OR circuit 46 inputs the output of the second inverter 45 and the second level-shifted pulse signal, and performs an OR operation.

  With this configuration, the same effects as those of the first embodiment are obtained. Further, the circuit scale can be made smaller than in the first embodiment.

Embodiment 3 FIG.
FIG. 5 is a circuit diagram showing a semiconductor device according to the third embodiment of the present invention, and FIG. 6 is a timing chart for explaining the operation thereof.

  In the third embodiment, a plurality of inverters 47 and 48 are provided as delay circuits. Other configurations are the same as those of the first embodiment. With this configuration, it is possible to prevent a malfunction of the power device as in the first embodiment. Further, the delay amount can be easily controlled by the number of inverter stages.

Embodiment 4 FIG.
FIG. 7 is a circuit diagram showing a semiconductor device according to the fourth embodiment of the present invention, and FIG. 8 is a timing chart for explaining the operation thereof.

  In the fourth embodiment, the delay circuit includes a constant current source 51, a capacitor 52, an inverter 53, NMOS transistors 54 to 56, and PMOS transistors 57 to 59. Other configurations are the same as those of the first embodiment.

  The constant current source 51 charges the capacitor 52. The NMOS transistors 54 to 56 and the PMOS transistors 57 to 59 which are switching elements charge and discharge the capacitor 52 according to the output of the SR flip-flop 19. The inverter 53 inverts the voltage charged in the capacitor 52 and outputs it.

  With this configuration, it is possible to prevent a malfunction of the power device as in the first embodiment. Further, the delay can be easily controlled by the current value of the constant current source 51 or the capacitance value of the capacitor 52.

Embodiment 5 FIG.
FIG. 9 is a circuit diagram showing a semiconductor device according to the fifth embodiment of the present invention. In the first to fourth embodiments, the delay circuit is provided after the SR flip-flop 19. On the other hand, in the fifth embodiment, a delay circuit is provided between the protection circuit 18 and the SR flip-flop 19. Other configurations are the same as those of the first embodiment.

  As delay circuits, inverters 61 to 64 and first and second capacitors 65 and 66 are provided. The inverters 61 and 62 are connected in series between the output LFS of the protection circuit 18 and the set input S of the SR type flip-flop 19. The inverters 63 and 64 are connected in series between the output LFR of the protection circuit 18 and the reset input R of the SR type flip-flop 19. One end of the first capacitor 65 is connected to a connection point between the inverter 61 and the inverter 62, and the first level-shifted pulse signal is applied. One end of the second capacitor 66 is connected to a connection point between the inverter 63 and the inverter 64, and the second level-shifted pulse signal is applied. A voltage VS is applied to the other ends of the first and second capacitors 65 and 66.

  The delay circuit delays the first and second level-shifted pulse signals by at least the pulse widths of the ON signal and OFF signal to obtain first and second delayed pulse signals, respectively. That is, the voltages charged in the first and second capacitors 65 and 66 are output as first and second delayed pulse signals, respectively. The SR flip-flop 19 inputs the first delayed pulse signal from the set input S, and inputs the second delayed pulse signal from the reset input R.

  The output Q of the SR flip-flop 19 is connected to the gate electrode of the NMOS transistor 20 and also to the input of the inverter 21, and the output of the inverter 21 is connected to the gate electrode of the NMOS transistor 22. The voltage at the connection point of the NMOS transistors 20 and 22 is output as the output signal HO on the high potential side. In this way, the NMOS transistors 20 and 22 are complementarily turned on and off to switch the power device on the high potential side.

  FIG. 10 is a timing chart for explaining the operation of the semiconductor device according to the fifth embodiment of the present invention. As shown in the figure, the output signal HO is switched after the ON signal and the OFF signal are output. Thereby, when the voltage VS is a negative voltage due to switching of the power devices, the ON signal and the OFF signal are not output. Therefore, malfunction of the power device can be prevented. Further, the delay amounts of the ON signal and the OFF signal can be controlled respectively. The delay amount can be easily controlled by the capacitance values of the first and second capacitors 65 and 66.

Embodiment 6 FIG.
FIG. 11 is a circuit diagram showing a semiconductor device according to the sixth embodiment of the present invention. The timing chart of this semiconductor device is the same as that of the fifth embodiment.

  In the sixth embodiment, as the delay circuit, a plurality of first inverters 71 and 72 connected in series between the output LFS of the protection circuit 18 and the set input S of the SR flip-flop 19, and the protection circuit 18 A plurality of second inverters 73 and 74 connected in series are provided between the output LFR and the reset input R of the SR flip-flop 19. Other configurations are the same as those of the fifth embodiment.

  With this configuration, the power device can be prevented from malfunctioning as in the fifth embodiment, and the delay amounts of the ON signal and the OFF signal can be controlled. Further, the delay amount can be easily controlled by the number of stages of the first and second inverters.

Embodiment 7 FIG.
FIG. 12 is a circuit diagram showing a semiconductor device according to Embodiment 7 of the present invention. The timing chart of this semiconductor device is the same as that of the fifth embodiment.

  In the seventh embodiment, first and second constant current sources 80 and 81, first and second capacitors 82 and 83, inverters 84 to 87, and NMOS transistors 88 and 89 (first transistors) are used as delay circuits. 1 and a second switching element). Other configurations are the same as those of the fifth embodiment.

  The first and second constant current sources 80 and 81 charge the first and second capacitors 82 and 83, respectively. The NMOS transistors 88 and 89 charge and discharge the first and second capacitors 82 and 83, respectively, according to the first and second level-shifted pulse signals. The inverters 86 and 87 invert the voltages charged in the first and second capacitors 82 and 83, respectively, and output the inverted signals as first and second delayed pulse signals.

  With this configuration, the power device can be prevented from malfunctioning as in the fifth embodiment, and the delay amounts of the ON signal and the OFF signal can be controlled. Further, the delay amount can be easily controlled by the current values of the first and second constant current sources 80 and 81 or the capacitance values of the first and second capacitors 82 and 83.

Embodiment 8 FIG.
FIG. 13 is a circuit diagram showing a semiconductor device according to Embodiment 8 of the present invention. The timing chart of this semiconductor device is the same as that of the fifth embodiment.

  In the seventh embodiment, first and second constant current sources 90 and 91, first and second capacitors 92 and 93, inverters 94 to 97, and NMOS transistors 98 and 99 (first circuits) are used as delay circuits. 1 and a second switching element). Other configurations are the same as those of the fifth embodiment.

  The first and second constant current sources 90 and 91 charge the first and second capacitors 92 and 93, respectively. The NMOS transistors 98 and 99 charge and discharge the first and second capacitors 92 and 93, respectively, according to the first and second level-shifted pulse signals. The inverters 96 and 97 invert the voltages charged in the first and second capacitors 92 and 93, respectively, and output them as first and second delayed pulse signals.

  With this configuration, the power device can be prevented from malfunctioning as in the fifth embodiment, and the delay amounts of the ON signal and the OFF signal can be controlled. Further, the delay amount can be easily controlled by the current values of the first and second constant current sources 90 and 91 or the capacitance values of the first and second capacitors 92 and 93.

11 Pulse generation circuit 12, 13 HNMOS transistor (level shift circuit)
14,15 Resistance (level shift circuit)
16, 17 Inverter (level shift circuit)
19 SR type flip-flop 41 NOR circuit (delay circuit)
42 D-type flip-flop (delay circuit)
43 First inverter (delay circuit)
44 NAND circuit (delay circuit)
45 Second inverter (delay circuit)
46 OR circuit (delay circuit)
47, 48 Inverter (delay circuit)
51 Constant current source (delay circuit)
52 Capacitor (delay circuit)
54-59 Switching element (delay circuit)
71, 72 First inverter (delay circuit)
73, 74 Second inverter (delay circuit)
80, 90 First constant current source (delay circuit)
81, 91 Second constant current source (delay circuit)
65, 82, 92 First capacitor (delay circuit)
66, 83, 93 Second capacitor (delay circuit)
88, 98 NMOS transistor (first switching element) (delay circuit)
89,99 NMOS transistor (second switching element) (delay circuit)

Claims (4)

A semiconductor device that drives and controls a high-potential side power device among two power devices connected in series between a high-potential main power supply potential and a low-potential main power supply potential,
Corresponding to level transition of the input signal having the first state indicating conduction of the high-potential side power device and the second state indicating non-conduction of the high-potential side power device to the first and second states A pulse generation circuit for generating first and second pulse signals,
A level shift circuit for level-shifting the first and second pulse signals to the high potential side to obtain first and second level-shifted pulse signals, respectively;
A delay circuit that delays the first and second level-shifted pulse signals by at least a pulse width of the first and second pulse signals to obtain first and second delayed pulse signals, respectively;
A semiconductor device comprising: an SR-type flip-flop that inputs the first delayed pulse signal from a set input and inputs the second delayed pulse signal from a reset input. The delay circuit includes first and second capacitors to which the first and second level-shifted pulse signals are respectively applied at one end and a reference voltage is applied to the other end.
2. The semiconductor device according to claim 1, wherein voltages charged in the first and second capacitors are output as the first and second delayed pulse signals, respectively. The delay circuit is
A plurality of first inverters for delaying the first level-shifted pulse signal;
The semiconductor device according to claim 1, further comprising a plurality of second inverters that delay the second level-shifted pulse signal. The delay circuit is
A first and a second capacitor;
First and second constant current sources for charging the first and second capacitors, respectively;
First and second switching elements for charging and discharging the first and second capacitors in response to the first and second level-shifted pulse signals, respectively.
2. The semiconductor device according to claim 1, wherein voltages charged in the first and second capacitors are output as the first and second delayed pulse signals, respectively.

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